M1521 Signal Descriptions - Acer Extensa 61X Service Manual

2.2.6 Signal Descriptions
Table 2-2

M1521 Signal Descriptions

Signal
Host Interface
A[31:29] W8, W11, U11, Y10,
A[28:26] Y9, V10, W9, W10, U9,
A[25:23] U10, V9, U5, V5, W5,
A[22:20] Y5, U6, W6, V6, Y6,
A[19:17] U7, W7, Y7, V7, V8,
A[16:14] Y8, Y12, U8, Y11, V11
A[13:11]
A[10:08]
A[07:05]
A[04:03]
BEJ[7:0] M1, L4, L3, L2, L1, K4,
K3, K2
ADSJ T5
BRDYJ M5
NAJ N5
AHOLD L5
EADSJ R5
BOFFJ P5
HITMJ T8
2-8
Pin Type
I/O
I
I
O
O
O
O
O
I
Description
Host Address Bus Lines.
functions. As inputs, along with the byte enable
signals, these serve as the address lines of the host
address bus that defines the physical area of
memory or I/O being accessed.
M1521 drives them during inquiry cycles on behalf of
PCI masters.
Byte Enables. These are the byte enable signals for
the data bus. BEJ[7] applies to the most significant
byte and BEJ[0] applies to the least significant byte.
They determine which byte of data must be written to
the memory, or are requested by the CPU. In local
memory read and line-fill cycles, these are ignored
by the M1521.
Address Strobe. The CPU or M1521 starts a new
cycle by asserting ADSJ first. The M1521 does not
precede to execute a cycle until it detects ADSJ
active.
Burst Ready. The assertion of BRDYJ means the
current transaction
terminates the cycle by receiving 1 or 4 active
BRDYJs depending on different types of cycles.
Next Address. It is asserted by the M1521 to inform
the CPU that pipelined cycles are ready for
execution.
CPU A-Hold Request Output. It serves as the input
of CPU's AHOLD pin and actively driven for inquiry
cycles.
External Address Strobe. This signal is connected to
the CPU EADSJ pin. During PCI cycles, the M1521
asserts this signal to proceed snooping.
CPU Back-Off. If BOFFJ is sampled active, CPU
floats all its buses in the next clock.
Host Cache Hit after Modified. When snooped, the
CPU asserts HITMJ to indicate that a hit to a
modified line in the data cache occurred. It is used
to prohibit another bus master from accessing the
data of this modified line in the memory until the line
is completely written-back.
A[31:3] have two
As outputs, the
is complete. The
Service Guide
CPU