M1523 Signal Descriptions - Acer Extensa 61X Service Manual

2.3.4 Signal Descriptions
Table 2-3

M1523 Signal Descriptions

Signal
Clock and Reset
PWG
CPURST
RSTDRV
OSC14M
PCI Interface
PCICLK
AD[31:0]
C/BEJ[3:0]
FRAMEJ
DEVSELJ
IRDYJ
TRDYJ
STOPJ
PAR
SERRJ
2-18
Pin Type
17 I
49 O
57 O
43 I
71 I
73-80, 83-90, I/O
100-104, 106-
109, 111-118
81, 91, 99, I/O
110
92 I/O
95 I/O
93 I/O
94 I/O
96 I/O
98 I/O
97 I
Description
Power-Good Input. This signal comes from the power
supply to indicate that power is available and stable.
CPU Reset includes cold and warm reset 3.3V signal
(connected to CPU INIT)
CPU Cold Reset. 3.3V signal (connected to CPU RESET)
14.318Mhz Clock Input. This is used for 8254 timer clock.
PCI clock for internal PCI interface.
Address and Data are multiplexed on PCI bus.
the first clock of a PCI transaction, AD[31-0] contains a
physical address. During subsequent clocks, AD[31-0]
contains data.
Bus Command and Byte Enable. During address phase,
CBEJ[3:0] define the bus command. During data phase,
CBEJ[3:0] define the byte enables.
Cycle Frame. is driven by current initiator to indicate the
beginning and duration of an access.
Device Select. . This indicates that the target device has
decoded the address as its own cycle. This pin is an
output pin when the M1523 acts as a PCI slave that has
decoded address as its own cycle including subtractive
decoding.
Initiator Ready indicates the initiator's ability to complete
the current data phase of the transaction.
Target Ready indicates the target's ability to complete the
current data phase of the transaction.
Stop indicates to the M1523 is requesting a master to stop
the current transaction.
Parity Signal. PAR is even parity and is calculated on
AD[31:0] and CBEJ[3:0]. When the M1523 acts as a PCI
master, it drives PAR one PCI clock after address phase
for a read/write transaction and one PCI clock after data
phase for a write transaction. When the M1523 acts as
target, it drives PAR one PCI clock after data phase for a
PCI master read transaction.
System Error may be pulsed active by any agent that
detects a system error condition.
sampled low, the M1523 asserts NMI to send an interrupt
to the CPU.
During
When SERRJ is
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