Status Byte Register; Table 24. 8 Bit Status Byte Register; Figure 6. Status Register Schematic - Fluke RPM4-AD Operation And Maintenance Manual

4.5.2

STATUS BYTE REGISTER

The RPM4-AD contains an 8 bit Status Byte Register that reflects the general status of the
RPM4-AD.
OPER RQS/MSS
(128) (64)
This register is affected by the RPM4-AD reply output queue, the Error Queue, the Standard
Event Status register and the Ready Event Status register.
Status Byte Register
∗ ∗
(" STB?" or " SRE n")
OPER
(128)
RQS/MSS
(64)
ESB
←←←
(32)
MAV
←←←
(16)
N/A
(8)
ERROR
←←←
(4)
N/A
(2)
RSR
←←←
(1)
The Status Byte Register can be read using the "*STB?" query, or by performing a serial poll on
the IEEE-488 bus. If you read this using a serial poll then Bit 6 is the RQS. If the "*STB?" query
is used, then bit 6 is the MSS bit. All of the other bits are common to both types of query.
Each of these status bits can cause a SRQ to occur. The Service Request Enable Register
("*SRE" program message ) determines which of these flags are able to assert the SRQ line.
This enable register has a matching set of bits that each will enable the designated bit to
cause a SRQ, except for the RQS/MSS bit(s) which cannot cause a SRQ. If you set this
register to 20 ($14 hex), an SRQ will occur if the MAV or the ERROR bit are set. The
description of these bits are given as:
OPER N/A Bit 7 (128)
RQS Requested Service Bit 6 (64)
Indicates that the SRQ line of the IEEE-488 interface has been asserted by the
RPM4-AD. This bit is cleared when a serial poll is performed on the RPM4, and
is a part of the Status Byte Register when read using a serial poll. This bit does
not apply if the COM1 port is being used.
MSS Master Summary Status Bit 6 (64)
Indicates that an event or events occurred that caused the RPM4-AD to request
service from the Host, much like the RQS bit. Unlike the RQS bit, it is READ ONLY
and can be only cleared when the event(s) that caused the service request are
cleared.
ESB Event Summary Bit 5 (32)
Indicates if an enabled bit in the Standard Event Status Register became set
(see Section 4.5.3).

Table 24. 8 bit status byte register

ESB MAV
(32) (16)
Standard Event Status Register
("∗ESR?" or "∗ESE n")
PON URQ CMD EXE
(128) (64) (32) (16)
OUTPUT
QUEUE
ERROR
QUEUE
Ready Event Status Register
("RSR?" or " RSE n")
N/A MEAS NDRY RDY
HI HI
(128)
(64) (32) (16)

Figure 6. Status register schematic

Page 109
4. REMOTE OPERATION
N/A ERROR N/A
(8) (4) (2)
DDE QYE RQC
(8) (4) (2)
N/A MEAS NRDY
LO HI HI
(8)
(4) (2)
© 2005-2007 DH Instruments, a Fluke Company
RSR
(1)
OPC
(1)
RDY
HI
(1)