Download Print this page

Renesas HD6413008F Hardware Manual

16-bit single-chip microcomputer

page of 686

/ 686
Bookmarks

Advertisement

Quick Links

Download this manual

REJ09B0395-0400

16

Rev.4.00

Revision date: Aug. 20, 2007

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and

additions. Details should always be checked by referring to the

relevant text.

Renesas 16-Bit Single-Chip Microcomputer

H8/3008

Hardware Manual

H8 Family/H8/300H Series

H8/3008 HD6413008F

HD6413008TE

HD6413008VF

HD6413008VTE

www.renesas.com

Advertisement

Need help?

Need help?

Do you have a question about the HD6413008F and is the answer not in the manual?

Questions and answers

Summary of Contents for Renesas HD6413008F

Page 1 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3008 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series H8/3008 HD6413008F HD6413008TE HD6413008VF HD6413008VTE Rev.4.00...
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 Rev.4.00 Aug. 20, 2007 Page iv of xliv REJ09B0395-0400...
Page 5 Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. http://www.renesas.com/ Rev.4.00 Aug. 20, 2007, Page v of xliv REJ09B0395-0400...
Page 6 User manual for H8/3008 Document Title Document No. H8/3008 Hardware Manual This manual H8/300H Series Software Manual REJ09B0213-0300 User manual for development tools Document Title Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual REJ10B0058-0100H H8S, H8/300 Series Simulator/Debugger User’s Manual REJ10B0211-0300 High-performance Embedded Workshop User’s Manual REJ10J1554-0100...
Page 7 Page Revision (See Manual for Details) — Company name and brand names amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. 1.1 Overview Description amended Four MCU operating modes offer a choice of bus width and address space size. The modes (modes 1 to 4) include four expanded modes.
Page 8 Item Page Revision (See Manual for Details) 9.4.1 8TCNT Count Figure amended Timing φ Figure 9.8 Count Timing for Internal Clock Internal clock Input 8TCNT input clock N − 1 8TCNT N + 1 Figure 9.9 Count Figure amended Timing for External φ...
Page 9 Item Page Revision (See Manual for Details) 9.4.3 Input Capture Figure amended Signal Timing φ Figure 9.13 Timing of Input Capture Input Input capture input Signal Input capture signal 8TCNT TCORB 9.4.4 Timing of Status Figure amended Flag Setting φ Figure 9.14 CMF Flag Setting Timing when 8TCNT...
Page 10 Item Page Revision (See Manual for Details) 9.4.5 Operation with Description amended Cascaded Connection • Channels 0 and 1: Compare Match Count When bits CKS2 to CKS0 are set to (100) in 8TCR1, Mode 8TCNT1 counts channel 0 compare match A events. Channels 0 and 1 are controlled independently.
Page 11 Item Page Revision (See Manual for Details) 9.7.2 Contention Figure amended between 8TCNT Write 8TCNT write cycle and Increment Figure 9.19 Contention between 8TCNT Write φ and Increment Address bus 8 TCNT address Internal write signal 8TCNT input clock 8TCNT 8TCNT write data 9.7.3 Contention Figure amended...
Page 12 Item Page Revision (See Manual for Details) 9.7.4 Contention Figure amended between TCOR Read TCORB read cycle and Input Capture Figure 9.21 Contention between TCOR Read φ and Input Capture Address bus TCORB address Internal read signal Input capture signal TCORB Internal data bus 9.7.5 Contention...
Page 13 Item Page Revision (See Manual for Details) 9.7.6 Contention Figure amended between TCOR Write TCOR write cycle and Input Capture Figure 9.23 Contention between TCOR Write φ and Input Capture Address bus TCOR address Internal write signal Input capture signal 8TCNT TCOR 9.7.7 Contention...
Page 14 Item Page Revision (See Manual for Details) 12.3.2 Operation in Figure amended and note added Asynchronous Mode (4) Wait for at least the interval required to transmit or receive Figure 12.4 Sample one bit, then set the TE or RE bit to 1 in SCR*. Set the RIE, Flowchart for SCI TIE, TEIE, and MPIE bits as necessary.
Page 15 Item Page Revision (See Manual for Details) 19.3 AC 481, 482 Table amended Characteristics Condition Table 19.6 Bus Timing B and C Item Symbol Min Unit Test Conditions ⎯ ⎯ Read data setup time Figure 19.7, figure 19.8 ⎯ ⎯ Read data hold time ⎯...
Page 16 All trademarks and registered trademarks are the property of their respective owners. Rev.4.00 Aug. 20, 2007 page xvi of xliv REJ09B0395-0400...
Page 17 Contents Section 1 Overview ......................Overview........................... Block Diagram ........................Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ....................... 1.3.3 Pin Assignments in Each Mode ................12 Section 2 CPU ........................17 Overview........................... 17 2.1.1 Features........................ 17 2.1.2 Differences from H8/300 CPU................18 CPU Operating Modes ......................
Page 18 2.8.7 Power-Down State ....................51 Basic Operational Timing ....................51 2.9.1 Overview......................51 2.9.2 On-Chip Memory Access Timing................ 51 2.9.3 On-Chip Supporting Module Access Timing ............52 2.9.4 Access to External Address Space ............... 53 Section 3 MCU Operating Modes ..................
Page 19 5.1.2 Block Diagram ..................... 76 5.1.3 Pin Configuration....................77 5.1.4 Register Configuration..................77 Register Descriptions ......................78 5.2.1 System Control Register (SYSCR) ..............78 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ..........79 5.2.3 IRQ Status Register (ISR)..................84 5.2.4 IRQ Enable Register (IER) ..................
Page 20 6.3.4 Chip Select Signals ....................119 6.3.5 Address Output Method..................120 Basic Bus Interface ......................122 6.4.1 Overview......................122 6.4.2 Data Size and Data Alignment................122 6.4.3 Valid Strobes......................123 6.4.4 Memory Areas ..................... 124 6.4.5 Basic Bus Control Signal Timing ................ 125 6.4.6 Wait Control ......................
Page 21 7.8.2 Register Descriptions ................... 173 Section 8 16-Bit Timer ....................... 177 Overview........................... 177 8.1.1 Features........................ 177 8.1.2 Block Diagrams ....................179 8.1.3 Pin Configuration....................182 8.1.4 Register Configuration..................183 Register Descriptions ......................184 8.2.1 Timer Start Register (TSTR)................184 8.2.2 Timer Synchro Register (TSNC) .................
Page 22 9.1.3 Pin Configuration....................246 9.1.4 Register Configuration..................247 Register Descriptions ......................248 9.2.1 Timer Counters (8TCNT) ..................248 9.2.2 Time Constant Registers A (TCORA) ..............249 9.2.3 Time Constant Registers B (TCORB) ..............250 9.2.4 Timer Control Register (8TCR)................251 9.2.5 Timer Control/Status Registers (8TCSR) ............
Page 23 10.2 Register Descriptions ......................287 10.2.1 Port A Data Direction Register (PADDR) ............287 10.2.2 Port A Data Register (PADR) ................287 10.2.3 Port B Data Direction Register (PBDDR)............288 10.2.4 Port B Data Register (PBDR) ................288 10.2.5 Next Data Register A (NDRA) ................289 10.2.6 Next Data Register B (NDRB)................
Page 24 Section 12 Serial Communication Interface ..............321 12.1 Overview........................... 321 12.1.1 Features........................ 321 12.1.2 Block Diagram..................... 323 12.1.3 Pin Configuration....................324 12.1.4 Register Configuration..................325 12.2 Register Descriptions ......................326 12.2.1 Receive Shift Register (RSR) ................326 12.2.2 Receive Data Register (RDR) ................326 12.2.3 Transmit Shift Register (TSR) ................
Page 25 13.3.5 Clock........................396 13.3.6 Transmitting and Receiving Data................. 398 13.4 Usage Notes ........................406 Section 14 A/D Converter ....................411 14.1 Overview........................... 411 14.1.1 Features........................ 411 14.1.2 Block Diagram ..................... 412 14.1.3 Pin Configuration....................413 14.1.4 Register Configuration..................414 14.2 Register Descriptions ......................415 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..........
Page 26 16.2 System Control Register (SYSCR) ................... 445 16.3 Operation .......................... 446 Section 17 Clock Pulse Generator .................. 447 17.1 Overview........................... 447 17.1.1 Block Diagram..................... 448 17.2 Oscillator Circuit....................... 449 17.2.1 Connecting a Crystal Resonator................449 17.2.2 External Clock Input.................... 451 17.3 Duty Adjustment Circuit....................
Page 27 Section 19 Electrical Characteristics ................471 19.1 Absolute Maximum Ratings ..................... 471 19.2 DC Characteristics ......................472 19.3 AC Characteristics ......................479 19.4 A/D Conversion Characteristics..................485 19.5 D/A Conversion Characteristics..................487 19.6 Operational Timing ......................488 19.6.1 Clock Timing ....................... 488 19.6.2 Control Signal Timing ..................
Page 28 Appendix G Package Dimensions .................. 630 Appendix H Comparison of H8/300H Series Product Specifications ....632 Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and H8/3007, and H8/3008 ................632 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) ..635 Rev.4.00 Aug.
Page 29 Figures Section 1 Overview Figure 1.1 Block Diagram ....................Figure 1.2 Pin Arrangement of H8/3008 (FP-100B or TFP-100B Package, Top View) ..Section 2 CPU Figure 2.1 CPU Operating Modes ..................18 Figure 2.2 Memory Map...................... 19 Figure 2.3 CPU Registers ....................20 Figure 2.4 Usage of General Registers ................
Page 30 Figure 5.3 Timing of Setting of IRQnF ................88 Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 ..........93 Figure 5.5 Interrupt Masking State Transitions (Example) ..........95 Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 ..........96 Figure 5.7 Interrupt Exception Handling Sequence.............
Page 31 Section 7 I/O Ports Figure 7.1 Port 4 Pin Configuration..................144 Figure 7.2 Port 6 Pin Configuration..................148 Figure 7.3 Port 7 Pin Configuration..................151 Figure 7.4 Port 8 Pin Configuration..................153 Figure 7.5 Port 9 Pin Configuration..................156 Figure 7.6 Port A Pin Configuration..................
Page 32 Figure 8.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ..... 224 Figure 8.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR....225 Figure 8.33 Timing of Setting of IMFA and IMFB by Compare Match ....... 226 Figure 8.34 Timing of Setting of IMFA and IMFB by Input Capture........
Page 33 Figure 9.23 Contention between TCOR Write and Input Capture......... 277 Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode........................278 Section 10 Programmable Timing Pattern Controller (TPC) Figure 10.1 TPC Block Diagram ................... 284 Figure 10.2 TPC Output Operation..................
Page 34 Figure 12.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A)..........363 Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data......364 Figure 12.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) ........365 Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data ......
Page 35 Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected) ............ 424 Figure 14.5 A/D Conversion Timing ..................426 Figure 14.6 External Trigger Input Timing ................427 Figure 14.7 Example of Analog Input Protection Circuit ............429 Figure 14.8 Analog Input Pin Equivalent Circuit ..............
Page 36 Figure 19.9 Basic Bus Cycle: Three-State Access with One Wait State ....... 494 Figure 19.10 Bus-Release Mode Timing ................. 494 Figure 19.11 TPC and I/O Port Input/Output Timing.............. 495 Figure 19.12 Timer Input/Output Timing................495 Figure 19.13 Timer External Clock Input Timing ..............496 Figure 19.14 SCI Input Clock Timing ..................
Page 37 Appendix G Package Dimensions Figure G.1 Package Dimensions (FP-100B)................. 630 Figure G.2 Package Dimensions (TFP-100B) ..............631 Rev.4.00 Aug. 20, 2007, Page xxxvii of xliv REJ09B0395-0400...
Page 38 Rev.4.00 Aug. 20, 2007 Page xxxviii of xliv REJ09B0395-0400...
Page 39 Tables Section 1 Overview Table 1.1 Features ......................Table 1.2 Comparison of H8/3008 Pin Arrangements ............Table 1.3 Pin Functions...................... Table 1.4 Pin Assignments in Each Mode (FP-100B, TFP-100B) ........12 Section 2 CPU Table 2.1 Instruction Classification..................27 Table 2.2 Instructions and Addressing Modes ..............
Page 40 Section 6 Bus Controller Table 6.1 Bus Controller Pins .................... 103 Table 6.2 Bus Controller Registers ..................104 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ........119 Table 6.4 Data Buses Used and Valid Strobes ..............124 Table 6.5 Pin States in Idle Cycle ..................
Page 41 Table 9.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register .. 257 Table 9.5 Types of 8-Bit Timer Interrupt Sources and Priority Order ....... 269 Table 9.6 8-Bit Timer Interrupt Sources................270 Table 9.7 Timer Output Priority Order................
Page 42 Section 14 A/D Converter Table 14.1 A/D Converter Pins .................... 413 Table 14.2 A/D Converter Registers ..................414 Table 14.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD) ... 415 Table 14.4 A/D Conversion Time (Single Mode) ..............426 Table 14.5 Analog Input Pin Ratings ...................
Page 43 Appendix A Instruction Set Table A.1 Instruction Set..................... 499 Table A.2 Operation Code Map (1)..................512 Table A.2 Operation Code Map (2)..................513 Table A.2 Operation Code Map (3)..................514 Table A.3 Number of States per Cycle................516 Table A.4 Number of Cycles per Instruction ..............
Page 44 Rev.4.00 Aug. 20, 2007 Page xliv of xliv REJ09B0395-0400...
Page 45 Overview The H8/3008 is a microcontroller (MCU) that integrates system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space.
Page 46 1. Overview Table 1.1 Features Feature Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers) High-speed operation •...
Page 47 1. Overview Feature Description • 16-bit timer, Three 16-bit timer channels, capable of processing up to six pulse outputs or 3 channels six pulse inputs • 16-bit timer counter (channels 0 to 2) • Two multiplexed output compare/input capture pins (channels 0 to 2) •...
Page 48 • Other features On-chip clock pulse generator Product lineup Product Type Model Package (Package Code) H8/3008 5 V operation HD6413008F 100-pin QFP (FP-100B) HD6413008TE 100-pin TQFP (TFP-100B) 3 V operation HD6413008VF 100-pin QFP (FP-100B) HD6413008VTE 100-pin TQFP (TFP-100B) Rev.4.00 Aug. 20, 2007 Page 4 of 638...
Page 49 1. Overview Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL STBY H8/300H CPU RESO Interrupt controller φ/P6 BACK/P6 BREQ/P6 WAIT/P6 Watchdog timer ADTRG/CS /IRQ (WDT) /IRQ 16-bit timer unit /IRQ...
Page 50 1. Overview Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3008 is shown in figures 1.2 and 1.3. Differences in the H8/3008 pin arrangements are shown in table 1.2. Except for the differences shown in table 1.2, the pin arrangements are the same.
Page 51 1. Overview P7 /AN A 10 P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN /DA P7 /AN /DA Top view /IRQ (FP-100B, TFP-100B) /IRQ ADTRG/CS /IRQ TCLKA/TP TCLKB/TP TCLKC/TIOCA TCLKD/TIOCB /TIOCA /TIOCB /TIOCA /TIOCB Note: * V pin in 5 V operation models, V pin in 3 V operation models.
Page 52 1. Overview 1.3.2 Pin Functions Table 1.3 summarizes the pin functions. The 5 V operation models have a V pin, and require the connection of an external capacitor. Table 1.3 Pin Functions Pin No. FP-100B Type Symbol TFP-100B Name and Function Power 1*, 35, 68 Input...
Page 53 1. Overview Pin No. FP-100B Type Symbol TFP-100B Name and Function System Input Reset input: When driven low, this pin resets the control chip. This pin must be driven low at power-up. RESO Output Reset output: Outputs the reset signal generated by the watchdog timer to external devices STBY Input...
Page 54 1. Overview Pin No. FP-100B Type Symbol TFP-100B Name and Function 16-bit timer TCLKD to 96 to 93 Input Clock input D to A: External clock inputs TCLKA TIOCA 99, 97, 95 Input/ Input capture/output compare A2 to A0: TIOCA output GRA2 to GRA0 output compare or input capture, or PWM output...
Page 55 1. Overview Pin No. FP-100B Type Symbol TFP-100B Name and Function Analog Input Power supply pin for the A/D and D/A converters. power Connect to the system power supply when not supply using the A/D and D/A converters. Input Ground pin for the A/D and D/A converters. Connect to system ground (0 V).
Page 56 1. Overview 1.3.3 Pin Assignments in Each Mode Table 1.4 lists the pin assignments in each mode. Table 1.4 Pin Assignments in Each Mode (FP-100B, TFP-100B) Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 /TMO /TMO /TMO...
Page 57 1. Overview Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 /WAIT /WAIT /WAIT /WAIT Rev.4.00 Aug. 20, 2007 Page 13 of 638 REJ09B0395-0400...
Page 58 1. Overview Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK φ φ φ φ STBY STBY STBY STBY EXTAL EXTAL EXTAL EXTAL XTAL XTAL XTAL XTAL /IRQ /IRQ /IRQ...
Page 59 1. Overview Pin No. Pin Name FP-100B TFP-100B Mode 1 Mode 2 Mode 3 Mode 4 /IRQ /ADTRG P8 /IRQ /ADTRG P8 /IRQ /ADTRG P8 /IRQ /ADTRG /TCLKA /TCLKA /TCLKA /TCLKA /TCLKB /TCLKB /TCLKB /TCLKB /TIOCA /TIOCA /TIOCA /TIOCA TCLKC TCLKC TCLKC TCLKC...
Page 60 1. Overview Rev.4.00 Aug. 20, 2007 Page 16 of 638 REJ09B0395-0400...
Page 61 2. CPU Section 2 CPU Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 62 2. CPU ⎯ 32 ÷ 16-bit register-register divide: 880 ns@25 MHz • Two CPU operating modes ⎯ Normal mode ⎯ Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H CPU has the following enhancements. •...
Page 63 2. CPU Address Space Figure 2.2 shows a simple memory map for the H8/3008. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating modes use 20-bit addressing.
Page 64 2. CPU Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend: Stack pointer...
Page 65 2. CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 66 2. CPU Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute.
Page 67 2. CPU Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise.
Page 68 2. CPU Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 69 2. CPU General Data Type Register Data Format Word data Word data Longword data Legend: ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats (2) 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory.
Page 70 2. CPU Data Type Address Data Format 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
Page 71 2. CPU Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 64 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction Types Data transfer MOV, PUSH* , POP* , MOVTPE* , MOVFPE* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU Logic operations AND, OR, XOR, NOT...
Page 72 2. CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, ⎯ Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 ⎯...
Page 73 2. CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register)* (EAd) Destination operand...
Page 74 2. CPU Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3008.
Page 75 2. CPU Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 76 2. CPU Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder Rd ÷...
Page 77 2. CPU Table 2.5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 78 2. CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 79 2. CPU Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨...
Page 80 2. CPU Table 2.8 Branching Instructions Instruction Size Function ⎯ Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨...
Page 81 2. CPU Table 2.9 System Control Instructions Instruction Size* Function ⎯ TRAPA Starts trap-instruction exception handling ⎯ Returns from an exception-handling routine ⎯ SLEEP Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 82 2. CPU Table 2.10 Block Transfer Instruction Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B @ER5+ → @ER6+, R4L − 1 → R4L repeat until R4L = 0 else next; EEPMOV.W ⎯ if R4 ≠ 0 then @ER5+ → @ER6+, R4 − 1 → R4 repeat until R4 = 0...
Page 83 2. CPU Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2.9 Instruction Formats 2.6.5...
Page 84 2. CPU Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Execution of BCLR Instruction BCLR #0, @P4DDR ; Execute BCLR instruction on DDR After Execution of BCLR Instruction Input/output Output Output Output Output Output Output Output Input...
Page 85 2. CPU Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes.
Page 86 2. CPU Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
Page 87 2. CPU Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
Page 88 2. CPU Table 2.13 Effective Address Calculation Rev.4.00 Aug. 20, 2007 Page 44 of 638 REJ09B0395-0400...
Page 89 2. CPU Rev.4.00 Aug. 20, 2007 Page 45 of 638 REJ09B0395-0400...
Page 90 2. CPU Rev.4.00 Aug. 20, 2007 Page 46 of 638 REJ09B0395-0400...
Page 91 2. CPU Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states.
Page 92 2. CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register.
Page 93 2. CPU Bus request End of bus release Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception handling source Bus-released state Sleep mode End of SLEEP instruction Interrupt source exception with SSBY = 1 handling NMI, IRQ , IRQ , or IRQ interrupt...
Page 94 2. CPU the CPU fetches a start address from the exception vector table and execution branches to that address. Figure 2.14 shows the stack after the exception-handling sequence. SP−4 SP (ER7) SP−3 SP+1 SP−2 SP+2 SP−1 SP+3 Stack area SP (ER7) SP+4 Even address...
Page 95 2. CPU The reset state can also be entered by a watchdog timer overflow. For details see section 11, Watchdog Timer. 2.8.7 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode.
Page 96 2. CPU Bus cycle T state T state φ Internal address bus Address Internal read signal Internal data bus Read data (read access) Internal write signal Internal data bus Write data (write access) Figure 2.15 On-Chip Memory Access Cycle φ Address bus Address RD HWR LWR...
Page 97 2. CPU Bus cycle T state T state T state φ Address Address bus Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 Access Cycle for On-Chip Supporting Modules φ...
Page 98 2. CPU Rev.4.00 Aug. 20, 2007 Page 54 of 638 REJ09B0395-0400...
Page 99 3. MCU Operating Modes Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection The H8/3008 has four operating modes (modes 1 to 4) that are selected by the mode pins (MD ) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode.
Page 100 3. MCU Operating Modes Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes. The H8/3008 can be used only in modes 1 to 4.
Page 101 3. MCU Operating Modes MDS0 are read-only bits. The mode pin (MD to MD ) levels are latched into these bits when MDCR is read. System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3008. SSBY STS2 STS1...
Page 102 3. MCU Operating Modes Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 18, Power-Down State.) When software standby mode is exited by an external interrupt, and a transition is made to normal operation, this bit remains set to 1.
Page 103 3. MCU Operating Modes Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as an interrupt mask bit UI bit in CCR is used as a user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Page 104 3. MCU Operating Modes Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A to A , permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
Page 105 3. MCU Operating Modes Pin Functions in Each Operating Mode The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1 Mode 2...
Page 106 3. MCU Operating Modes Memory Map in Each Operating Mode Figure 3.1 shows memory map of the H8/3008. In the expanded modes, the address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes (modes 1 and 2) and the 16-Mbyte modes (modes 3 and 4).
Page 107 3. MCU Operating Modes Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF...
Page 108 3. MCU Operating Modes Rev.4.00 Aug. 20, 2007 Page 64 of 638 REJ09B0395-0400...
Page 109 4. Exception Handling Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 110 4. Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Page 111 4. Exception Handling Table 4.2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Normal Mode Reset H'0000 to H'0003 H'0000 to H'0001 Reserved for system use H'0004 to H'0007 H'0002 to H'0003 H'0008 to H'000B H'0004 to H'0005 H'000C to H'000F H'0006 to H'0007 H'0010 to H'0013...
Page 112 4. Exception Handling Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules.
Page 113 4. Exception Handling Figure 4.2 Reset Sequence (Modes 1 and 3) Rev.4.00 Aug. 20, 2007 Page 69 of 638 REJ09B0395-0400...
Page 114 4. Exception Handling Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset exception handling vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 115 4. Exception Handling Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ), and 27 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit timer, 8-bit timer, serial communication interface (SCI), and A/D converter.
Page 116 4. Exception Handling Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. → SP−4 SP (ER7) SP−3 SP+1 SP−2 SP+2 SP−1 SP+3 SP (ER7) → SP+4 Stack area Even address Before exception handling After exception handling...
Page 117 4. Exception Handling Notes on Stack Usage When accessing word data or longword data, the H8/3008 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP:ER7) should always be kept even.
Page 118 4. Exception Handling H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFE H'FFFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP CCR contents lost Legend: CCR: Condition code register Program counter R1L: General register R1L Stack pointer Note: The diagram illustrates modes 3 and 4.
Page 119 5. Interrupt Controller Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB).
Page 120 5. Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number TEIE Interrupt controller SYSCR Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR:...
Page 121 5. Interrupt Controller 5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Abbreviation I/O Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable to IRQ External interrupt request 5 to 0 Input Maskable interrupts, falling edge or level sensing selectable 5.1.4 Register Configuration...
Page 122 5. Interrupt Controller Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here.
Page 123 5. Interrupt Controller Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 124 5. Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt...
Page 125 5. Interrupt Controller Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 126 5. Interrupt Controller Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt requests.
Page 127 5. Interrupt Controller Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. ⎯ ⎯ ⎯ ⎯ IPRB7 IPRB6 IPRB3 IPRB2 Initial value Read/Write Reserved bit Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI...
Page 128 5. Interrupt Controller Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) (Initial value) 8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority) Bits 5 and 4—Reserved: These bits can be written and read, but they do not affect interrupt priority.
Page 129 5. Interrupt Controller ⎯ ⎯ IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value ⎯ ⎯ Read/Write R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Reserved bits IRQ to IRQ flags These bits indicate IRQ to IRQ flag interrupt request status Note: Only 0 can be written, to clear flags.
Page 130 5. Interrupt Controller Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0—IRQ to IRQ Enable (IRQ5E to IRQ0E): These bits enable or disable to IRQ interrupts. Bits 5 to 0 IRQ5E to IRQ0E Description to IRQ...
Page 131 5. Interrupt Controller Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 27 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and can be used to exit software standby mode.
Page 132 5. Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Page 133 5. Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority H'001C to H'001F H'000E to H'000F ⎯ External High pins H'0030 to H'0033 H'0018 to H'0019 IPRA7 H'0034 to H0037 H'001A to H'001B IPRA6 H'0038 to H'003B...
Page 134 5. Interrupt Controller Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority IMIA2 16-bit timer H'0080 to H'0083 H'0040 to H'0041 IPRA0 High (compare match/ channel 2 input capture A2) IMIB2 H'0084 to H'0087 H'0042 to H'0043 (compare match/ input capture B2) OVI2 (overflow 2)
Page 135 5. Interrupt Controller Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority ERI0 H'00D0 to H'00D3 H'0068 to H'0069 IPRB3 High (receive error 0) channel 0 RXI0 (receive H'00D4 to H'00D7 H'006A to H'006B data full 0) TXI0 (transmit H'00D8 to H'00DB H'006C to H'006D data empty 0)
Page 136 5. Interrupt Controller Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3008 handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits.
Page 137 5. Interrupt Controller Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 Rev.4.00 Aug.
Page 138 5. Interrupt Controller • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 139 5. Interrupt Controller ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
Page 140 5. Interrupt Controller Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 Rev.4.00 Aug.
Page 141 5. Interrupt Controller 5.4.2 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Exception Handling Sequence Rev.4.00 Aug.
Page 142 5. Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip Memory...
Page 143 5. Interrupt Controller Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 144 5. Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 145 6. Bus Controller Section 6 Bus Controller Overview The H8/3008 has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 146 6. Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. to CS ABWCR ASTCR Area Internal address bus Internal signals CSCR decoder Chip select ADRCR Bus mode control signal control signals Bus size control signal Access state control signal Bus control Wait request signal...
Page 147 6. Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus...
Page 148 6. Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers Address* Name Abbreviation Initial Value H'EE020 Bus width control register ABWCR H'FF* H'EE021 Access state control register ASTCR H'FF H'EE022 Wait control register H WCRH H'FF H'EE023...
Page 149 6. Bus Controller Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits 7 to 0 ABW7 to ABW0 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas ABWCR specifies the data bus width of external memory areas.
Page 150 6. Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that does not depend on WCRH/WCRL settings.
Page 151 6. Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
Page 152 6. Bus Controller WCRL Initial value Read/Write Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Page 153 6. Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Page 154 6. Bus Controller 6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. ⎯ ⎯ ⎯ A23E A22E A21E A20E...
Page 155 6. Bus Controller Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A output from PA . In modes other than 3 and 4, this bit cannot be modified and PA has its ordinary port functions.
Page 156 6. Bus Controller BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the area division unit, selects the extended memory map, and enables or disables WAIT pin input. BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 157 6. Bus Controller Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3 and 4, and is invalid in modes 1 and 2. Bit 1 RDEA Description Area divisions are as follows: Area 0: 2 Mbytes Area 4: 1.93 Mbytes Area 1: 2 Mbytes...
Page 158 6. Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals to CS If output of a chip select signal CS to CS is enabled by a setting in this register, the to CS corresponding pin functions a chip select signal (CS ) output regardless of any other...
Page 159 6. Bus Controller 6.2.7 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADRCTL Initial value ⎯...
Page 160 6. Bus Controller Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
Page 161 6. Bus Controller H'000000 Area 0 Area 0 2 Mbytes 2 Mbytes H'1FFFFF H'200000 Area 1 Area 1 2 Mbytes 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes Area 2 H'5FFFFF 8 Mbytes H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF...
Page 162 6. Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 163 6. Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL Bus Specifications (Basic Bus Interface) ABWn ASTn Bus Width Access States Program Wait States ⎯ ⎯ ⎯ ⎯ Note: n = 0 to 7 6.3.3 Memory Interfaces As its memory interface, the H8/3008 has only a basic bus interface that allows direct connection...
Page 164 6. Bus Controller Output of CS to CS : Output of CS to CS is enabled or disabled in the chip select control register (CSCR). A reset leaves pins CS to CS in the input state. To output chip select signals CS to CS , the corresponding CSCR bits must be set to 1.
Page 165 6. Bus Controller Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H Series. Addresses are always updated between bus cycles. Address Update Mode 2: In address update mode 2, address updating is performed only in external space accesses.
Page 166 6. Bus Controller Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Page 167 6. Bus Controller In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
Page 168 6. Bus Controller Table 6.4 Data Buses Used and Valid Strobes Access Read/ Valid Upper Data Bus Lower Data Bus Area Size Write Address Strobe to D to D ⎯ 8-bit access Byte Read Valid Invalid area ⎯ Write Undetermined data 16-bit access Byte Read...
Page 169 6. Bus Controller 6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit, ) is used in accesses to these areas. The LWR three-state-access area. The upper data bus (D to D pin is always high.
Page 170 6. Bus Controller 8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit, ) is used in accesses to these areas. The LWR two-state-access area. The upper data bus (D to D pin is always high. Wait states cannot be inserted. Bus cycle φ...
Page 171 6. Bus Controller 16-Bit, Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 172 6. Bus Controller Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address) Rev.4.00 Aug.
Page 173 6. Bus Controller Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D to D Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access) Rev.4.00 Aug.
Page 174 6. Bus Controller 16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 175 6. Bus Controller Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address) Rev.4.00 Aug.
Page 176 6. Bus Controller Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D Valid to D Note: n = 7 to 0 Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) 6.4.6 Wait Control...
Page 177 6. Bus Controller Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last T or T state, another T state is inserted.
Page 178 6. Bus Controller Idle Cycle 6.5.1 Operation When the H8/3008 chip accesses external space, it can insert a 1-state idle cycle (T ) between bus cycles in the following cases: when read accesses between different areas occur consecutively, and when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which has a long output floating time, and high-speed memory, I/O interfaces, and so on.
Page 179 6. Bus Controller In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Page 180 6. Bus Controller Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ φ Address bus Address bus Simultaneous change of RD and CSn: possibility of mutual overlap (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.20 Example of Idle Cycle Operation 6.5.2 Pin States in Idle Cycle...
Page 181 6. Bus Controller Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters. The bus master can be either the CPU or an external bus master. When a bus master has the bus right it can carry out read and write operations.
Page 182 6. Bus Controller External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an external bus master. The external bus master has highest priority, and requests the bus right from the bus arbiter driving the BREQ signal low. Once the external bus master acquires the bus, it keeps the bus until the BREQ signal goes high.
Page 183 6. Bus Controller When making a transition to software standby mode, if there is contention with a bus request from an external bus master, the BACK and strobe states may be indefinite when the transition is made. When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the SLEEP instruction.
Page 184 6. Bus Controller φ Address bus BRCR address to PA to A High-impedance Figure 6.24 BRCR Write Timing BREQ Pin Input Timing 6.7.2 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes lows, the bus arbiter may operate incorrectly.
Page 185 7. I/O Ports Section 7 I/O Ports Overview The H8/3008 has six input/output ports (ports 4, 6, 8, 9, A, and B) and one input-only port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7.1.
Page 186 7. I/O Ports Expanded Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 • Port 8 DDR = 0: generic input 5-bit I/O port DDR = 1 (reset value): CS • output to P8 have input, CS schmitt inputs /IRQ output, external trigger input (ADTRG) to...
Page 187 7. I/O Ports Expanded Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Port B • TPC output (TP to TP ) and generic input/output 8-bit I/O port /TMIO TPC output (TP to TP ), 8-bit timer input and output (TMIO ), CS to CS , TMIO...
Page 188 7. I/O Ports Port 4 7.2.1 Overview Port 4 is an 8-bit input/output port which also functions as a data bus. It's pin configuration is shown in figure 7.1. The pin functions differ depending on the operating mode. In the H8/3008, when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit- access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port.
Page 189 7. I/O Ports 7.2.2 Register Descriptions Table 7.2 summarizes the registers of port 4. Table 7.2 Port 4 Registers Address* Name Abbreviation Initial Value H'EE003 Port 4 data direction register P4DDR H'00 H'FFFD3 Port 4 data register P4DR H'00 H'EE03E Port 4 input pull-up MOS control P4PCR H'00...
Page 190 7. I/O Ports Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4. When port 4 functions as an output port, the value of this register is output. When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin logic level is read.
Page 191 7. I/O Ports Table 7.3 summarizes the states of the input pull-up MOS in each operating mode. Table 7.3 Input Pull-Up MOS Transistor States (Port 4) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 1 to 4 8-bit bus mode On/off On/off 16-bit bus mode...
Page 192 7. I/O Ports Port 6 7.3.1 Overview Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock (φ) output. The port 6 pin configuration is shown in figure 7.2. See table 7.5 for the selection of the pin functions.
Page 193 7. I/O Ports Bit 7 is reserved. It is fixed at 1, and cannot be modified. ⎯ P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR Initial value ⎯ Read/Write Reserved bit Port 6 data direction 6 to 0 These bits select input or output for port 6 pins •...
Page 194 7. I/O Ports Table 7.5 Port 6 Pin Functions in Modes 1 to 4 Pin Functions and Selection Method /φ Bit PSTOP in MSTCRH selects the pin function. PSTOP φ output Pin function input Functions as LWR regardless of the setting of bit P6 LWR output Pin function Functions as HWR regardless of the setting of bit P6...
Page 195 7. I/O Ports Port 7 7.4.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 7.3 shows the pin configuration of port 7.
Page 196 7. I/O Ports Port 7 Data Register (P7DR) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value Read/Write Note: * Determined by pins P7 to P7 . When port 7 is read, the pin logic levels are always read. P7DR cannot be modified. Port 8 7.5.1 Overview...
Page 197 7. I/O Ports Port 8 pins P8 / P8 (input)/ (output) IRQ / ADTRG (input) / ADTRG (input) P8 / P8 (input)/ (output)/ P8 / P8 (input)/ (output)/ (input) Port 8 P8 / P8 (input)/ (output)/ (input) P8 / P8 (input/output)/ (input) Figure 7.4 Port 8 Pin Configuration 7.5.2...
Page 198 7. I/O Ports functions as the CS output, while CS to CS In the H8/3008, following a reset P8 are input ports. P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting.
Page 199 7. I/O Ports Table 7.8 Port 8 Pin Functions in Modes 1 to 4 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows. Pin function input output /IRQ Bit P8 DDR selects the pin function as follows ADTRG Pin function input...
Page 200 7. I/O Ports Port 9 7.6.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Page 201 7. I/O Ports 7.6.2 Register Descriptions Table 7.9 summarizes the registers of port 9. Table 7.9 Port 9 Registers Address* Name Abbreviation Initial Value H'EE008 Port 9 data direction register P9DDR H'C0 H'FFFD8 Port 9 data register P9DR H'C0 Note: * Lower 20 bits of the address in advanced mode.
Page 202 7. I/O Ports Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read.
Page 203 7. I/O Ports Table 7.10 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P9 select the pin function as follows. CKE1 ⎯ ⎯ ⎯...
Page 204 7. I/O Ports Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows. SMIF ⎯ ⎯ ⎯ Pin function input output output TxD output* Note: * Functions as the TxD output pin, but there are two states:...
Page 205 7. I/O Ports Port A 7.7.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input and output (TIOCB , TIOCA , TIOCB , TIOCA , TIOCB TIOCA , TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, clock input (TCLKD, TCLKC,...
Page 206 7. I/O Ports Port A pins Pin functions in modes 1 and 2 PA /TP /TIOCB /A PA (input/output)/TP (output)/TIOCB (input/output) PA /TP /TIOCA /A PA (input/output)/TP (output)/TIOCA (input/output) PA (input/output)/TP (output)/TIOCB (input/output) PA /TP /TIOCB /A PA (input/output)/TP (output)/TIOCA (input/output) PA /TP /TIOCA /A Port A PA /TP /TIOCB /TCLKD...
Page 207 7. I/O Ports Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When pins are used for TPC output, the corresponding PADDR bits must also be set. PA DDR PA DDR PA DDR...
Page 208 7. I/O Ports Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
Page 209 7. I/O Ports Table 7.12 Port A Pin Functions (Modes 1 and 2) Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit TIOCB PA 7 DDR select the pin function as follows. 16-bit timer channel 2 settings (1) in table below...
Page 210 7. I/O Ports Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit TIOCB DDR select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below ⎯...
Page 211 7. I/O Ports Table 7.13 Port A Pin Functions (Modes 3 and 4) Pin Functions and Selection Method Always used as A output. Pin function output Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in TIOCA BRCR, and bit PA DDR select the pin function as follows.
Page 212 7. I/O Ports Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in TIOCB BRCR, and bit PA DDR select the pin function as follows. A22E 16-bit timer ⎯...
Page 213 7. I/O Ports Table 7.14 Port A Pin Functions (Modes 1 to 4) Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to TIOCB 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit TCLKD NDER3 in NDERA, and bit PA DDR select the pin function as follows.
Page 214 7. I/O Ports Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to TIOCA 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit TCLKC NDER2 in NDERA, and bit PA DDR select the pin function as follows.
Page 215 7. I/O Ports Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, TCLKB bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit DDR select the pin function as follows.
Page 216 7. I/O Ports Port B 7.8.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TMIO , TMO , TMIO , TMO ) by the 8-bit timer, and CS to CS output.
Page 217 7. I/O Ports 7.8.2 Register Descriptions Table 7.15 summarizes the registers of port B. Table 7.15 Port B Registers Address* Name Abbreviation Initial Value H'EE00A Port B data direction register PBDDR H'00 H'FFFDA Port B data register PBDR H'00 Note: * Lower 20 bits of the address in advanced mode.
Page 218 7. I/O Ports Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read.
Page 219 7. I/O Ports Table 7.16 Port B Pin Functions (Modes 1 to 4) Pin Functions and Selection Method Bit NDER15 in NDERB and bit PB DDR select the pin function as follows. ⎯ NDER15 Pin function input output output Bit NDER14 in NDERB and bit PB DDR select the pin function as follows.
Page 220 7. I/O Ports Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB DDR select the pin function as follows. OIS3/2 and All 0 Not all 0 OS1/0 ⎯...
Page 221 8. 16-Bit Timer Section 8 16-Bit Timer Overview The H8/3008 has built-in 16-bit timer module with three 16-bit counter channels. 8.1.1 Features 16-bit timer features are listed below. • Capability to process up to 6 pulse outputs or 6 pulse inputs •...
Page 222 8. 16-Bit Timer Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently. • Output triggering of programmable timing pattern controller (TPC) Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers. Table 8.1 summarizes the 16-bit timer functions.
Page 223 8. 16-Bit Timer 8.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 8.1 is a block diagram of the 16-bit timer. IMIA0 to IMIA2 TCLKA to TCLKD Clock selector IMIB0 to IMIB2 OVI0 to OVI2 φ, φ/2, φ/4, φ/8 Control logic TIOCA to TIOCA TIOCB...
Page 224 8. 16-Bit Timer Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 IMIB0 Comparator...
Page 225 8. 16-Bit Timer Block Diagram of Channel 2: Figure 8.3 is a block diagram of channel 2 TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2 Comparator IMIB2 OVI2 Module data bus Legend: 16TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits ×...
Page 226 8. 16-Bit Timer 8.1.3 Pin Configuration Table 8.2 summarizes the 16-bit timer pins. Table 8.2 16-bit timer Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input...
Page 227 8. 16-Bit Timer 8.1.4 Register Configuration Table 8.3 summarizes the 16-bit timer registers. Table 8.3 16-bit timer Registers Abbre- Initial Channel Address* Name viation Value Common H'FFF60 Timer start register TSTR H'F8 H'FFF61 Timer synchro register TSNC H'F8 H'FFF62 Timer mode register TMDR H'98 H'FFF63...
Page 228 8. 16-Bit Timer Abbre- Initial Channel Address* Name viation Value H'FFF78 Timer control register 2 16TCR2 H'80 H'FFF79 Timer I/O control register 2 TIOR2 H'88 H'FFF7A Timer counter 2H 16TCNT2H R/W H'00 H'FFF7B Timer counter 2L 16TCNT2L R/W H'00 H'FFF7C General register A2H GRA2H H'FF...
Page 229 8. 16-Bit Timer Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2). Bit 2 STR2 Description 16TCNT2 is halted (Initial value) 16TCNT2 is counting Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1). Bit 1 STR1 Description 16TCNT1 is halted...
Page 230 8. 16-Bit Timer Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously. Bit 2 SYNC2 Description Channel 2's timer counter (16TCNT2) operates independently (Initial value) 16TCNT2 is preset and cleared independently of other channels Channel 2 operates synchronously 16TCNT2 can be synchronously preset and cleared Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously.
Page 231 8. 16-Bit Timer 8.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. ⎯ ⎯...
Page 232 8. 16-Bit Timer Counting Direction Down-Counting Up-Counting ↑ ↓ ↑ ↓ TCLKA pin High High ↑ ↓ ↑ ↓ TCLKB pin High High In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2 and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting mode operations take precedence.
Page 233 8. 16-Bit Timer When bit PWM1 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin. The output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1. Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. Bit 0 PWM0 Description...
Page 234 8. 16-Bit Timer Bit 6—Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables the interrupt requested by the IMFA2 when IMFA2 flag is set to 1. Bit 6 IMIEA2 Description IMIA2 interrupt requested by IMFA2 flag is disabled (Initial value) IMIA2 interrupt requested by IMFA2 flag is enabled Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Page 235 8. 16-Bit Timer Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1 compare match or input capture events. Bit 1 IMFA1 Description [Clearing condition] (Initial value) Read IMFA1 flag when IMFA1 = 1, then write 0 in IMFA1 flag [Setting conditions] •...
Page 236 8. 16-Bit Timer 8.2.5 Timer Interrupt Status Register B (TISRB) TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture and enables or disables GRB compare match and input capture interrupt requests. ⎯ ⎯ IMIEB2 IMIEB1 IMIEB0 IMFB2 IMFB1...
Page 237 8. 16-Bit Timer Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 when IMFB1 flag is set to 1. Bit 5 IMIEB1 Description IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value) IMIB1 interrupt requested by IMFB1 flag is enabled Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables the interrupt requested by the IMFB0 when IMFB0 flag is set to 1.
Page 238 8. 16-Bit Timer Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 Description [Clearing condition] (Initial value) Read IMFB1 flag when IMFB1 = 1, then write 0 in IMFB1 flag [Setting conditions] •...
Page 239 8. 16-Bit Timer 8.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. ⎯ ⎯ OVIE2 OVIE1 OVIE0 OVF2 OVF1 OVF0 Initial value ⎯ ⎯...
Page 240 8. 16-Bit Timer Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the OVF1 when OVF1 flag is set to 1. Bit 5 OVIE1 Description OVI1 interrupt requested by OVF1 flag is disabled (Initial value) OVI1 interrupt requested by OVF1 flag is enabled Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 when OVF0 flag is set to 1.
Page 241 8. 16-Bit Timer Bit 0—Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow. Bit 0 OVF0 Description [Clearing condition] (Initial value) Read OVF0 flag when OVF0 = 1, then write 0 in OVF0 flag [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000 8.2.7 Timer Counters (16TCNT) 16TCNT is a 16-bit counter.
Page 242 8. 16-Bit Timer The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. Each 16TCNT is initialized to H'0000 by a reset and in standby mode. 8.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers.
Page 243 8. 16-Bit Timer 8.2.9 Timer Control Registers (16TCR) 16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel. Channel Abbreviation Function 16TCR0 16TCR controls the timer counter. The 16TCRs in all channels are functionally identical. When phase counting mode is selected 16TCR1 in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 16TCR2...
Page 244 8. 16-Bit Timer Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description 16TCNT is not cleared (Initial value) 16TCNT is cleared by GRA compare match or input capture* 16TCNT is cleared by GRB compare match or input capture* Synchronous clear: 16TCNT is cleared in synchronization with other synchronized timers*...
Page 245 8. 16-Bit Timer Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 Function Internal clock: φ (Initial value) Internal clock: φ/2 Internal clock: φ/4 Internal clock: φ/8 External clock A: TCLKA input External clock B: TCLKB input...
Page 246 8. 16-Bit Timer 8.2.10 Timer I/O Control Register (TIOR) TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel. Channel Abbreviation Function TIOR0 TIOR controls the general registers. Some functions differ in PWM mode. TIOR1 TIOR2 ⎯...
Page 247 8. 16-Bit Timer Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 Bit 5 Bit 4 IOB2 IOB1 IOB0 Function GRB is an output No output at compare match (Initial value) compare register 0 output at GRB compare match* 1 output at GRB compare match*...
Page 248 8. 16-Bit Timer 8.2.11 Timer Output Level Setting Register C (TOLR) TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2. ⎯ ⎯ TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value ⎯ ⎯ Read/Write Output level setting A2 to A0, B2 to B0 These bits set the levels of the timer outputs...
Page 249 8. 16-Bit Timer Bit 3—Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB Bit 3 TOB1 Description TIOCB is 0 (Initial value) TIOCB is 1 Bit 2—Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA Bit 2 TOA1 Description...
Page 250 8. 16-Bit Timer CPU Interface 8.3.1 16-Bit Accessible Registers The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time.
Page 251 8. 16-Bit Timer On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte) On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) On-chip data bus Module Bus interface...
Page 252 8. 16-Bit Timer On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus.
Page 253 8. 16-Bit Timer On-chip data bus Module Bus interface data bus 16TCR Figure 8.11 16TCR Access (CPU Reads 16TCR) Operation 8.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter.
Page 254 8. 16-Bit Timer • Sample setup procedure for counter Figure 8.12 shows a sample procedure for setting up a counter. Counter setup Select counter clock Count operation Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter...
Page 255 8. 16-Bit Timer 5. Set the STR bit to 1 in TSTR to start the timer counter. • Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters.
Page 256 8. 16-Bit Timer 16TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 8.14 Periodic Counter Operation • 16TCNT count timing ⎯ Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Page 257 8. 16-Bit Timer φ External clock input 16TCNT input clock N − 1 16TCNT N + 1 Figure 8.16 Count Timing for External Clock Sources (when Both Edges are Detected) Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle.
Page 258 8. 16-Bit Timer • Examples of waveform output Figure 8.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change.
Page 259 8. 16-Bit Timer • Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 260 8. 16-Bit Timer • Sample setup procedure for input capture Figure 8.21 shows a sample procedure for setting up input capture. Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal.
Page 261 8. 16-Bit Timer • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 262 8. 16-Bit Timer Setup for synchronization Select synchronization Synchronous preset Synchronous clear Clearing synchronized to this channel? Write to 16TCNT Select counter clear source Select counter clear source Start counter Start counter Synchronous preset Counter clear Synchronous clear Set the SYNC bits to 1 in TSNC for the channels to be synchronized. When a value is written in 16TCNT in one of the synchronized channels, the same value is simultaneously written in 16TCNT in the other channels.
Page 263 8. 16-Bit Timer Value of 16TCNT0 to 16TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 H'0000 TIOCA TIOCA TIOCA Figure 8.25 Synchronization (Example) 8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1.
Page 264 8. 16-Bit Timer Table 8.4 PWM Output Pins and Registers Channel Output Pin 1 Output 0 Output TIOCA GRA0 GRB0 TIOCA GRA1 GRB1 TIOCA GRA2 GRB2 Sample Setup Procedure for PWM Mode: Figure 8.26 shows a sample procedure for setting up PWM mode.
Page 265 8. 16-Bit Timer Examples of PWM Mode: Figure 8.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB.
Page 266 8. 16-Bit Timer Figure 8.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%.
Page 267 8. 16-Bit Timer 8.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2.
Page 268 8. 16-Bit Timer Example of Phase Counting Mode: Figure 8.30 shows an example of operations in phase counting mode. Table 8.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 269 8. 16-Bit Timer 8.4.6 16-Bit Timer Output Timing The initial value of 16-bit timer output when a timer count operation begins can be specified arbitrarily by making a setting in TOLR. Figure 8.32 shows the timing for setting the initial value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
Page 270 8. 16-Bit Timer Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR).
Page 271 8. 16-Bit Timer Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 8.34 shows the timing. φ...
Page 272 8. 16-Bit Timer Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.35 shows the timing. φ 16TCNT Overflow signal Figure 8.35 Timing of Setting of OVF 8.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is...
Page 273 8. 16-Bit Timer 8.5.3 Interrupt Sources Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1.
Page 274 8. 16-Bit Timer Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 8.37.
Page 275 8. 16-Bit Timer Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 8.38 shows the timing in this case. 16TCNT word write cycle φ...
Page 276 8. 16-Bit Timer Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the T or T state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The byte data for which a write was not performed is not incremented, and retains its pre-write value.
Page 277 8. 16-Bit Timer Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8.40. General register write cycle φ...
Page 278 8. 16-Bit Timer Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 8.41. 16TCNT write cycle φ...
Page 279 8. 16-Bit Timer Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 8.42. General register read cycle φ...
Page 280 8. 16-Bit Timer Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 281 8. 16-Bit Timer Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8.44. General register write cycle φ...
Page 282 8. 16-Bit Timer Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the 16TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: φ...
Page 283 8. 16-Bit Timer 16-bit timer Operating Modes Table 8.7 (a) 16-bit timer Operating Modes (Channel 0) Register Settings TSNC TMDR TIOR0 16TCR0 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select ⎯ ⎯ Synchronous preset SYNC0 = 1 ⎯ ⎯...
Page 284 8. 16-Bit Timer Table 8.7 (b) 16-bit timer Operating Modes (Channel 1) Register Settings TSNC TMDR TIOR1 16TCR1 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select ⎯ ⎯ Synchronous preset SYNC1 = 1 ⎯ ⎯ ⎯ PWM mode PWM1 = 1 ⎯...
Page 285 8. 16-Bit Timer Table 8.7 (c) 16-bit timer Operating Modes (Channel 2) Register Settings TSNC TMDR TIOR2 16TCR2 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select ⎯ Synchronous preset SYNC2 = 1 ⎯ ⎯ PWM mode PWM2 = 1 ⎯...
Page 286 8. 16-Bit Timer Rev.4.00 Aug. 20, 2007 Page 242 of 638 REJ09B0395-0400...
Page 287 9. 8-Bit Timers Section 9 8-Bit Timers Overview The H8/3008 has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events.
Page 288 9. 8-Bit Timers Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources.
Page 289 9. 8-Bit Timers 9.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 9.1 shows a block diagram of 8-bit timer group 0.
Page 290 9. 8-Bit Timers 9.1.3 Pin Configuration Table 9.1 summarizes the input/output pins of the 8-bit timer module. Table 9.1 8-Bit Timer Pins Group Channel Name Abbreviation I/O Function Timer output Output Compare match output Timer clock input TCLKC Input Counter external clock input Timer input/output TMIO Compare match output/input capture input...
Page 291 9. 8-Bit Timers 9.1.4 Register Configuration Table 9.2 summarizes the registers of the 8-bit timer module. Table 9.2 8-Bit Timer Registers Channel Address* Name Abbreviation R/W Initial value H'FFF80 Timer control register 0 8TCR0 H'00 H'FFF82 Timer control/status register 0 8TCSR0 R/(W)* H'00...
Page 292 9. 8-Bit Timers Register Descriptions 9.2.1 Timer Counters (8TCNT) 8TCNT0 8TCNT1 Initial value Read/Write 8TCNT2 8TCNT3 Initial value Read/Write The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR).
Page 293 9. 8-Bit Timers 9.2.2 Time Constant Registers A (TCORA) TCORA0 to TCORA3 are 8-bit readable/writable registers. TCORA0 TCORA1 Initial value Read/Write TCORA2 TCORA3 Initial value Read/Write The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access.
Page 294 9. 8-Bit Timers 9.2.3 Time Constant Registers B (TCORB) TCORB0 TCORB1 Initial value Read/Write TCORB2 TCORB3 Initial value Read/Write TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value.
Page 295 9. 8-Bit Timers 9.2.4 Timer Control Register (8TCR) CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write 8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT clearing specification, and enables interrupt requests. 8TCR is initialized to H'00 by a reset and in standby mode.
Page 296 9. 8-Bit Timers Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT clearing source. Compare match A or B, or input capture B, can be selected as the clearing source. Bit 4 Bit 3 CCLR1 CCLR0 Description...
Page 297 9. 8-Bit Timers Bit 2 Bit 1 Bit 0 CSK2 CSK1 CSK0 Description Clock input disabled (Initial value) Internal clock, counted on falling edge of φ/8 Internal clock, counted on falling edge of φ/64 Internal clock, counted on falling edge of φ/8192 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow signal* Channel 1 (compare match count mode): Count on 8TCNT0...
Page 298 9. 8-Bit Timers 9.2.5 Timer Control/Status Registers (8TCSR) 8TCSR0 CMFB CMFA OIS3 OIS2 ADTE Initial value Read/Write R/(W)* R/(W)* R/(W)* 8TCSR2 ⎯ CMFB CMFA OIS3 OIS2 Initial value ⎯ Read/Write R/(W)* R/(W)* R/(W)* 8TCSR1, 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)*...
Page 299 9. 8-Bit Timers Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the occurrence of a TCORB compare match or input capture. Bit 7 CMFB Description [Clearing condition] (Initial value) Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] •...
Page 300 9. 8-Bit Timers Bit 4—A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D control register (ADCR), enables or disables A/D converter start requests by compare match A or an external trigger. Bit 4 TRGE* ADTE Description A/D converter start requests by compare match A or external trigger pin (ADTRG) input are disabled (Initial value)
Page 301 9. 8-Bit Timers Table 9.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register Register Timer Output Register Function Status Flag Change Capture Input Interrupt Request TCORA0 Compare match CMFA changed from 0 output CMIA0 interrupt request operation...
Page 302 9. 8-Bit Timers Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge. The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
Page 303 9. 8-Bit Timers CPU Interface 9.3.1 8-Bit Registers 8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time.
Page 304 9. 8-Bit Timers Internal data bus Module data bus interface 8TCNTH0 8TCNTL1 Figure 9.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1 Figure 9.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) Internal data bus Module data bus interface...
Page 305 9. 8-Bit Timers Operation 9.4.1 8TCNT Count Timing 8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 9.8 shows the count timing.
Page 306 9. 8-Bit Timers φ External clock input 8TCNT input clock N − 1 N + 1 8TCNT Figure 9.9 Count Timing for External Clock Input (Both-Edge Detection) 9.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Page 307 9. 8-Bit Timers Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when compare match A or B occurs, Figure 9.11 shows the timing of this operation. φ Compare match signal 8TCNT H'00 Figure 9.11 Timing of Clear by Compare Match...
Page 308 9. 8-Bit Timers φ Input capture input Input capture signal 8TCNT TCORB Figure 9.13 Timing of Input Capture Input Signal 9.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and 8TCNT values match.
Page 309 9. 8-Bit Timers φ 8TCNT TCORB Input capture signal CMFB Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 9.16 shows the timing in this case.
Page 310 9. 8-Bit Timers 16-Bit Count Mode • Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ⎯...
Page 311 9. 8-Bit Timers • TMIO pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in accordance with the lower 8-bit compare match conditions. ⎯ Setting when Input Capture Occurs • The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3 and input capture occurs.
Page 312 9. 8-Bit Timers Caution Do not set 16-bit counter mode and compare match count mode simultaneously within the same group, as the 8TCNT input clock will not be generated and the counters will not operate. 9.4.6 Input Capture Setting The 8TCNT value can be transferred to TCORB on detection of an input edge on the input capture/output compare pin (TMIO or TMIO ).
Page 313 9. 8-Bit Timers ⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO ) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings of bits OIS3 and OIS2 in 8TCSR3 are ignored.) ⎯...
Page 314 9. 8-Bit Timers Table 9.6 8-Bit Timer Interrupt Sources Channel Interrupt Source Description CMIA0 TCORA0 compare match CMIB0 TCORB0 compare match/input capture CMIA1/CMIB1 TCORA1 compare match, or TCORB1 compare match/input capture 0, 1 TOVI0/TOVI1 Counter 0 or counter 1 overflow CMIA2 TCORA2 compare match CMIB2...
Page 315 9. 8-Bit Timers 8-Bit Timer Application Example Figure 9.17 shows how the 8-bit timer module can be used to output pulses with any desired duty cycle. The settings for this example are as follows: • Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a TCORA compare match.
Page 316 9. 8-Bit Timers Usage Notes Note that the following kinds of contention can occur in 8-bit timer operation. 9.7.1 Contention between 8TCNT Write and Clear If a timer counter clear signal occurs in the T state of a 8TCNT write cycle, clearing of the counter takes priority and the write is not performed.
Page 317 9. 8-Bit Timers 9.7.2 Contention between 8TCNT Write and Increment If an increment pulse occurs in the T state of a 8TCNT write cycle, writing takes priority and 8TCNT is not incremented. Figure 9.19 shows the timing in this case. 8TCNT write cycle φ...
Page 318 9. 8-Bit Timers 9.7.3 Contention between TCOR Write and Compare Match If a compare match occurs in the T state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 9.20 shows the timing in this case. TCOR write cycle φ...
Page 319 9. 8-Bit Timers 9.7.4 Contention between TCOR Read and Input Capture If an input capture signal occurs in the T state of a TCOR read cycle, the value before input capture is read. Figure 9.21 shows the timing in this case. TCORB read cycle φ...
Page 320 9. 8-Bit Timers 9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB.
Page 321 9. 8-Bit Timers 9.7.6 Contention between TCOR Write and Input Capture If an input capture signal occurs in the T state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 9.23 shows the timing in this case. TCOR write cycle φ...
Page 322 9. 8-Bit Timers 9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) If an increment pulse occurs in the T or T state of an 8TCNT byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented.
Page 323 9. 8-Bit Timers 9.7.8 Contention between Compare Matches A and B If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 9.7.
Page 324 9. 8-Bit Timers Table 9.8 Internal Clock Switchover and 8TCNT Operation CKS1 and CKS0 Write Timing 8TCNT Operation High → high switchover* Old clock source New clock source 8TCNT clock 8TCNT N + 1 CKS bits rewritten High → low switchover* Old clock source New clock...
Page 325 9. 8-Bit Timers CKS1 and CKS0 Write Timing 8TCNT Operation Low → low switchover* Old clock source New clock source 8TCNT clock 8TCNT N + 1 N + 2 CKS bits rewritten Notes: 1. Including switchovers from the high level to the halted state, and from the halted state to the high level.
Page 326 9. 8-Bit Timers Rev.4.00 Aug. 20, 2007 Page 282 of 638 REJ09B0395-0400...
Page 327 10. Programmable Timing Pattern Controller (TPC) Section 10 Programmable Timing Pattern Controller (TPC) 10.1 Overview The H8/3008 has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 328 10. Programmable Timing Pattern Controller (TPC) 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the TPC. 16-bit timer compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2...
Page 329 10. Programmable Timing Pattern Controller (TPC) 10.1.3 Pin Configuration Table 10.1 summarizes the TPC output pins. Table 10.1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output...
Page 330 10. Programmable Timing Pattern Controller (TPC) 10.1.4 Register Configuration Table 10.2 summarizes the TPC registers. Table 10.2 TPC Registers Address* Name Abbreviation Initial Value H'EE009 Port A data direction register PADDR H'00 H'FFFD9 Port A data register PADR R/(W)* H'00 H'EE00A Port B data direction register PBDDR...
Page 331 10. Programmable Timing Pattern Controller (TPC) 10.2 Register Descriptions 10.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR...
Page 332 10. Programmable Timing Pattern Controller (TPC) 10.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR...
Page 333 10. Programmable Timing Pattern Controller (TPC) 10.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 334 10. Programmable Timing Pattern Controller (TPC) Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7.
Page 335 10. Programmable Timing Pattern Controller (TPC) 10.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 336 10. Programmable Timing Pattern Controller (TPC) Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6.
Page 337 10. Programmable Timing Pattern Controller (TPC) 10.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1...
Page 338 10. Programmable Timing Pattern Controller (TPC) 10.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9...
Page 339 10. Programmable Timing Pattern Controller (TPC) 10.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0...
Page 340 10. Programmable Timing Pattern Controller (TPC) Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP to TP Bit 7 Bit 6 G3CMS1 G3CMS0 Description TPC output group 3 (TP...
Page 341 10. Programmable Timing Pattern Controller (TPC) Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP to TP Bit 3 Bit 2 G1CMS1 G1CMS0 Description TPC output group 1 (TP...
Page 342 10. Programmable Timing Pattern Controller (TPC) 10.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. ⎯ ⎯ ⎯ ⎯ G3NOV G2NOV G1NOV G0NOV Initial value ⎯ ⎯ ⎯...
Page 343 10. Programmable Timing Pattern Controller (TPC) Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for...
Page 344 10. Programmable Timing Pattern Controller (TPC) 10.3 Operation 10.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 345 10. Programmable Timing Pattern Controller (TPC) 10.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 10.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
Page 346 10. Programmable Timing Pattern Controller (TPC) 10.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 10.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited).
Page 347 10. Programmable Timing Pattern Controller (TPC) Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 10.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
Page 348 10. Programmable Timing Pattern Controller (TPC) 10.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 10.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited).
Page 349 10. Programmable Timing Pattern Controller (TPC) Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 10.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR Non-overlap margin...
Page 350 10. Programmable Timing Pattern Controller (TPC) 10.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 351 10. Programmable Timing Pattern Controller (TPC) 10.4 Usage Notes 10.4.1 Operation of TPC Output Pins to TP are multiplexed with 16-bit timer, address bus, and other pin functions. When 16-bit timer, or address bus output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Page 352 10. Programmable Timing Pattern Controller (TPC) Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR.
Page 353 11. Watchdog Timer Section 11 Watchdog Timer 11.1 Overview The H8/3008 has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer.
Page 354 11. Watchdog Timer 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources φ/2 RSTCSR φ/32 φ/64 Reset Reset control Clock φ/128 (internal, external)
Page 355 11. Watchdog Timer 11.1.4 Register Configuration Table 11.2 summarizes the WDT registers. Table 11.2 WDT Registers Address* Write* Read Name Abbreviation Initial Value H'FFF8C H'FFF8C Timer control/status register TCSR R/(W)* H'18 H'FFF8D Timer counter TCNT H'00 H'FFF8E H'FFF8F Reset control/status register RSTCSR R/(W)* H'3F...
Page 356 11. Watchdog Timer 11.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. ⎯ ⎯ WT/IT CKS2 CKS1 CKS0 Initial value ⎯ ⎯ Read/Write R/(W) Clock select These bits select the TCNT clock source Reserved bits...
Page 357 11. Watchdog Timer Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows.
Page 358 11. Watchdog Timer 11.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. ⎯ ⎯ ⎯ ⎯...
Page 359 11. Watchdog Timer Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is no RESO pin in the versions with on-chip flash memory. Bit 6 RSTOE Description Reset signal is not output externally...
Page 360 11. Watchdog Timer Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 11.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 361 11. Watchdog Timer 11.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 11.3.1 Watchdog Timer Operation Figure 11.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR.
Page 362 11. Watchdog Timer 11.3.2 Interval Timer Operation Figure 11.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow.
Page 363 11. Watchdog Timer 11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 11.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1.
Page 364 11. Watchdog Timer 11.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 11.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 365 12. Serial Communication Interface Section 12 Serial Communication Interface 12.1 Overview The H8/3008 has a serial communication interface (SCI) with two independent channels. The two channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 366 12. Serial Communication Interface ⎯ Data length: 8 bits ⎯ Receive error detection: overrun errors • Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously.
Page 367 12. Serial Communication Interface 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the SCI. Module data bus Internal data bus φ Baud rate φ/ 4 SCMR generator φ/16 Transmit/receive φ/64 control Parity generate Clock Parity check External clock T E I T X I R X I...
Page 368 12. Serial Communication Interface 12.1.3 Pin Configuration The SCI has serial pins for each channel as listed in table 12.1. Table 12.1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output...
Page 369 12. Serial Communication Interface 12.1.4 Register Configuration The SCI has internal registers as listed in table 12.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface.
Page 370 12. Serial Communication Interface 12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 371 12. Serial Communication Interface 12.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 372 12. Serial Communication Interface 12.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator's clock source...
Page 373 12. Serial Communication Interface For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 Description Asynchronous mode (Initial value) Synchronous mode For Smart Card Interface (SMIF Bit in SCMR Set to 1): Selects GSM mode for the smart card interface.
Page 374 12. Serial Communication Interface Bit 4—Parity Mode (O/E): Specifies whether even parity or odd parity is used for parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode.
Page 375 12. Serial Communication Interface Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 12.3.3, Multiprocessor Communication.
Page 376 12. Serial Communication Interface 12.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. CKE0 MPIE TEIE CKE1 Initial value...
Page 377 12. Serial Communication Interface Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 Description Transmit-data-empty interrupt request (TXI) is disabled* (Initial value)
Page 378 12. Serial Communication Interface Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 Description Receiving disabled* (Initial value) Receiving enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 379 12. Serial Communication Interface Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2 TEIE Description Transmit-end interrupt requests (TEI) are disabled* (Initial value) Transmit-end interrupt requests (TEI) are enabled* Note:...
Page 380 12. Serial Communication Interface For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output pin.
Page 381 12. Serial Communication Interface 12.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the SCI. TEND MPBT TDRE RDRF ORER FER/ERS Initial value R/(W)∗ R/(W)∗ R/(W)∗ Read/Write R/(W)∗...
Page 382 12. Serial Communication Interface The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written.
Page 383 12. Serial Communication Interface Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] • The chip is reset or enters standby mode •...
Page 384 12. Serial Communication Interface For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4 Description Normal reception, no error signal*...
Page 385 12. Serial Communication Interface For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Bit 2 TEND Description...
Page 386 12. Serial Communication Interface Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value) Multiprocessor bit value in receive data is 1...
Page 387 12. Serial Communication Interface Table 12.3 shows examples of BRR settings in asynchronous mode. Table 12.4 shows examples of BRR settings in synchronous mode. Table 12.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) 2.097152 2.4576 Bit Rate (bit/s) Error (%) n...
Page 388 12. Serial Communication Interface φ (MHz) 6.144 7.3728 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 106 −0.44 130 −0.07 108 0.08 141 0.03 0.16 0.00 0.00 103 0.16 155 0.16 159 0.00 191 0.00 207 0.16 0.16 0.00...
Page 389 12. Serial Communication Interface φ (MHz) 14.7456 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 230 −0.08 248 −0.17 0.70 0.03 168 0.16 181 0.16 191 0.00 207 0.16 −0.43 0.16 0.00 103 0.16 168 0.16 181 0.16 191 0.00...
Page 390 12. Serial Communication Interface Table 12.4 Examples of Bit Rates and BRR Settings in Synchronous Mode φ (MHz) Rate (bit/s) n ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 124 ⎯ ⎯ 249 ⎯...
Page 391 12. Serial Communication Interface The BRR setting is calculated as follows: Asynchronous mode: φ × 10 − 1 64 × 2 × B 2n−1 Synchronous mode: φ × 10 − 1 8 × 2 × B 2n−1 Legend: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤...
Page 392 12. Serial Communication Interface Table 12.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 12.6 and 12.7 show the maximum bit rates with external clock input. Table 12.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings φ...
Page 393 12. Serial Communication Interface Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800...
Page 394 12. Serial Communication Interface Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0...
Page 395 12. Serial Communication Interface Asynchronous Mode • Data length is selectable: 7 or 8 bits • Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. •...
Page 396 12. Serial Communication Interface Table 12.8 SMR Settings and Serial Communication Formats SMR Settings SCI Communication Format Multi- Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data processor Parity Stop Bit STOP Mode Length Length Asyn- 8-bit data Absent Absent 1 bit...
Page 397 12. Serial Communication Interface 12.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible.
Page 398 12. Serial Communication Interface Table 12.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data...
Page 399 12. Serial Communication Interface Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 12.9.
Page 400 12. Serial Communication Interface Figure 12.4 shows a sample flowchart for initializing the SCI. Start of initialization Set the clock source in SCR. Clear the Clear TE and RE bits RIE, TIE, TEIE, MPIE, TE, and RE bits to to 0 in SCR 0.
Page 401 12. Serial Communication Interface • Transmitting Serial Data (Asynchronous Mode): Figure 12.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting After the TE bit is set to 1, one frame of 1s is output, then transmission is...
Page 402 12. Serial Communication Interface In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 403 12. Serial Communication Interface • Receiving Serial Data (Asynchronous Mode): Figure 12.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data input function of the RxD pin is selected automatically. Start receiving (2)(3) Receive error handling and break detection:...
Page 404 12. Serial Communication Interface Error handling ORER = 1 Overrun error handling FER = 1 Break? Framing error handling Clear RE bit to 0 in SCR PER = 1 Parity error handling Clear ORER, PER, and FER flags to 0 in SSR <End>...
Page 405 12. Serial Communication Interface In receiving, the SCI operates as follows: • The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 406 12. Serial Communication Interface Figure 12.8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt RXI interrupt handler request reads data in RDR and Framing error, ERI interrupt clears RDRF flag to 0 1 frame...
Page 407 12. Serial Communication Interface Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 12.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A...
Page 408 12. Serial Communication Interface Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: Read TDRE flag in SSR read SSR, check that the TDRE flag is 1, then write transmit data in TDR.
Page 409 12. Serial Communication Interface In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 410 12. Serial Communication Interface SCI initialization: Initialize the receive data input function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. Set MPIE bit to 1 in SCR SCI status check and ID check: Read ORER and FER flags read SSR, check that the RDRF flag in SSR...
Page 411 12. Serial Communication Interface Error handling ORER = 1 Overrun error handling FER = 1 Break? Clear RE bit to 0 in SCR Framing error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev.4.00 Aug.
Page 412 12. Serial Communication Interface Figure 12.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value RXI interrupt request RXI interrupt handler reads Not own ID, so MPIE No RXI interrupt MPB detection (multiprocessor interrupt)
Page 413 12. Serial Communication Interface 12.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible.
Page 414 12. Serial Communication Interface Transmitting and Receiving Data: • SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 415 12. Serial Communication Interface • Transmitting Serial Data (Synchronous Mode): Figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE...
Page 416 12. Serial Communication Interface In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 417 12. Serial Communication Interface • Receiving Serial Data (Synchronous Mode): Figure 12.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 418 12. Serial Communication Interface Error handling Overrun error handling Clear ORER flag to 0 in SSR <End> Figure 12.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows: • The SCI synchronizes with serial clock input or output and synchronizes internally. •...
Page 419 12. Serial Communication Interface Figure 12.19 shows an example of SCI receive operation. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt RXI interrupt handler RXI interrupt Overrun error, request reads data in RDR and...
Page 420 12. Serial Communication Interface • Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin and the read data input function of the TxD pin are selected, enabling simultaneous Start of transmitting and receiving...
Page 421 12. Serial Communication Interface 12.4 SCI Interrupts The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 12.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR.
Page 422 12. Serial Communication Interface 12.5 Usage Notes 12.5.1 Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 423 12. Serial Communication Interface Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Page 424 12. Serial Communication Interface The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). D − 0.5 (1 + F) × 100% ) − (L − 0.5) F − M = (0.5 − ..(1) Legend: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16)
Page 425 12. Serial Communication Interface Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (high- level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
Page 426 12. Serial Communication Interface • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Page 427 13. Smart Card Interface Section 13 Smart Card Interface 13.1 Overview The SCI supports an IC card (smart card) interface handling ISO/IEC7816-3 (Identification Card) character transmission as a serial communication interface expansion function. Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting.
Page 428 13. Smart Card Interface 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCMR φ φ/4 Baud rate generator φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock Legend: SCMR: Smart card mode register...
Page 429 13. Smart Card Interface 13.1.3 Pin Configuration Table 13.1 shows the smart card interface pins. Table 13.1 Smart Card Interface Pins Pin Name Abbreviation Function Serial clock pin Clock input/output Receive data pin Input Receive data input Transmit data pin Output Transmit data output 13.1.4...
Page 430 13. Smart Card Interface 13.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 13.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. ⎯...
Page 431 13. Smart Card Interface Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention cards.* The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 13.3.4, Register Settings.
Page 432 13. Smart Card Interface 13.2.2 Serial Status Register (SSR) The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND). TDRE RDRF ORER TEND MPBT Initial value Read/Write...
Page 433 13. Smart Card Interface Bits 3 to 0: These bits operate as in normal serial communication. For details see section 12.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are modified as follows. Bit 2 TEND Description Transmission is in progress [Clearing condition]...
Page 434 13. Smart Card Interface Bit 7 Description Normal smart card interface mode operation • The TEND flag is set 12.5 etu after the beginning of the start bit. • Clock output on/off control only. (Initial value) GSM mode smart card interface mode operation •...
Page 435 13. Smart Card Interface 13.3 Operation 13.3.1 Overview The main features of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame.
Page 436 13. Smart Card Interface Data line Clock line H8/3008 Px (port) chip Reset line Smart card Card-processing device Figure 13.2 Smart Card Interface Connection Diagram Note: Setting both TE and RE to 1 without connecting a smart card enables closed transmission/reception, allowing self-diagnosis to be carried out.
Page 437 13. Smart Card Interface No parity error Output from transmitting device Parity error Output from transmitting device Output from receiving Legend: device Start bit D0 to D7: Data bits Parity bit Error signal Figure 13.3 Smart Card Interface Data Format The operating sequence is as follows.
Page 438 13. Smart Card Interface 13.3.4 Register Settings Table 13.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described in this section. Table 13.3 Smart Card Interface Register Settings Register Address* Bit 7...
Page 439 13. Smart Card Interface The register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. Direct Convention (SDIR = SINV = O/E = 0) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
Page 440 13. Smart Card Interface 13.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for calculating the bit rate is shown below.
Page 441 13. Smart Card Interface The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. φ × 10 − 1 1488 ×...
Page 442 13. Smart Card Interface 13.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1.
Page 443 13. Smart Card Interface Figure 13.4 shows timing of TEND flag setting. For details, see Interrupt Operations in this section. Serial data Guard time (1) GM = 0 TEND 12.5 etu (2) GM = 1 TEND 11.0 etu Figure 13.4 Timing of TEND Flag Setting Rev.4.00 Aug.
Page 444 13. Smart Card Interface Start Initialization Start transmitting FER/ERS = 0? Error handling TEND = 1? Write transmit data in TDR, and clear TDRE flag to 0 in SSR All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit to 0 Figure 13.5 Sample Transmission Processing Flowchart Rev.4.00 Aug.
Page 445 13. Smart Card Interface (shift register) 1. Data write Data 1 2. Transfer from TDR to TSR Data 1 Data 1 Data remains in TDR Data 1 3. Serial data output Data 1 I/O signal output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the...
Page 446 13. Smart Card Interface Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 13.8 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2.
Page 447 13. Smart Card Interface If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will be requested.
Page 448 13. Smart Card Interface Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty (TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt request (TEI) is not available in smart card mode. A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR.
Page 449 13. Smart Card Interface Software standby Normal operation Normal operation 1' 2' 3' 1 2 3 Figure 13.10 Procedure for Stopping and Restarting the Clock Use the following procedure to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential.
Page 450 13. Smart Card Interface 13.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate.
Page 451 13. Smart Card Interface The receive margin can therefore be expressed as follows. Receive margin in smart card interface mode: D − 0.5 (1 + F) × 100% ) − (L − 0.5) F − M = (0.5 − Legend: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372) D: Clock duty cycle (D = 0 to 1.0)
Page 452 13. Smart Card Interface Frame n Retransmitted frame Frame n + 1 (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RDRF Figure 13.12 Retransmission in SCI Receive Mode •...
Page 453 13. Smart Card Interface Note on Block Transfer Mode Support: The smart card interface installed in the H8/3008 supports an IC card (smart card) interface with provision for ISO/IEC7816-3 T = 0 (character transmission). Therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data retransmission are not performed).
Page 454 13. Smart Card Interface Rev.4.00 Aug. 20, 2007 Page 410 of 638 REJ09B0395-0400...
Page 455 14. A/D Converter Section 14 A/D Converter 14.1 Overview The H8/3008 includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 18.6, Module Standby Function.
Page 456 14. A/D Converter 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit D/A − φ/4 Comparator Analog Control circuit multi- plexer Sample-and- φ/8 hold circuit ADTRG interrupt signal Compare match A0 ADTE 8-bit timer 8TCSR0...
Page 457 14. A/D Converter 14.1.3 Pin Configuration Table 14.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter.
Page 458 14. A/D Converter 14.1.4 Register Configuration Table 14.2 summarizes the A/D converter's registers. Table 14.2 A/D Converter Registers Address* Name Abbreviation Initial Value H'FFFE0 A/D data register A H ADDRAH H'00 H'FFFE1 A/D data register A L ADDRAL H'00 H'FFFE2 A/D data register B H ADDRBH H'00...
Page 459 14. A/D Converter 14.2 Register Descriptions 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADDRn Initial value Read/Write A/D conversion data Reserved bits 10-bit data giving an A/D conversion result Note: n = A to D The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 460 14. A/D Converter 14.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable...
Page 461 14. A/D Converter Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE Description A/D end interrupt request (ADI) is disabled (Initial value) A/D end interrupt request (ADI) is enabled Bit 5—A/D Start (ADST): Starts or stops A/D conversion.
Page 462 14. A/D Converter Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection Channel Selection Description Single Mode Scan Mode...
Page 463 14. A/D Converter Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match. Bit 7 TRGE Description Starting of A/D conversion by an external trigger or 8-bit timer (Initial value) compare match is disabled A/D conversion is started at the falling edge of the external trigger signal (ADTRG) or by an 8-bit timer compare match...
Page 464 14. A/D Converter Upper-byte read Module data bus Bus interface (H'AA) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) Lower-byte read Module data bus Bus interface (H'40) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) Note: n = A to D Figure 14.2 A/D Data Register Access Operation (Reading H'AA40) Rev.4.00 Aug.
Page 465 14. A/D Converter 14.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 466 14. A/D Converter Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev.4.00 Aug. 20, 2007 Page 422 of 638 REJ09B0395-0400...
Page 467 14. A/D Converter 14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 468 14. A/D Converter Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected) Rev.4.00 Aug. 20, 2007 Page 424 of 638 REJ09B0395-0400...
Page 469 14. A/D Converter 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D conversion timing.
Page 470 14. A/D Converter φ Address bus Write signal Input sampling timing CONV Legend: ADCSR write cycle (1): ADCSR address (2): Synchronization delay Input sampling time A/D conversion time CONV Figure 14.5 A/D Conversion Timing Table 14.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol...
Page 471 14. A/D Converter 14.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A high-to- low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Page 472 14. A/D Converter 14.6 Usage Notes When using the A/D converter, note the following points: 1. Analog Input Voltage Range During A/D conversion, the voltages input to the analog input pins AN should be in the range ≤ AN ≤ V 2.
Page 473 14. A/D Converter 100 Ω Rin * to AN 0.1 μF Notes: 1. 10 μF 0.01 µF 2. Rin: input impedance Figure 14.7 Example of Analog Input Protection Circuit Table 14.5 Analog Input Pin Ratings Item Unit ⎯ Analog input capacitance ⎯...
Page 474 14. A/D Converter 6. A/D Conversion Accuracy Definitions A/D conversion accuracy in the H8/3008 is defined as follows: ⎯ Resolution Digital output code length of A/D converter ⎯ Offset error Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 14.10) ⎯...
Page 475 14. A/D Converter Digital output Ideal A/D conversion characteristic Quantization error 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Figure 14.9 A/D Converter Accuracy Definitions (1) Rev.4.00 Aug. 20, 2007 Page 431 of 638 REJ09B0395-0400...
Page 476 14. A/D Converter Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog input Offset error voltage Figure 14.10 A/D Converter Accuracy Definitions (2) 7. Allowable Signal-Source Impedance The analog inputs of the H8/3008 are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 kΩ.
Page 477 14. A/D Converter If a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. H8/3008 Equivalent circuit of A/D converter Sensor output impedance 10 kΩ...
Page 478 14. A/D Converter Rev.4.00 Aug. 20, 2007 Page 434 of 638 REJ09B0395-0400...
Page 479 15. D/A Converter Section 15 D/A Converter 15.1 Overview The H8/3008 includes a D/A converter with two channels. 15.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 μs (with 20-pF capacitive load) •...
Page 480 15. D/A Converter 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the D/A converter. Internal Module data bus data bus 8-bit D/A Control circuit Legend: DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 DASTCR: D/A standby control register Figure 15.1 D/A Converter Block Diagram...
Page 481 15. D/A Converter 15.1.3 Pin Configuration Table 15.1 summarizes the D/A converter's input and output pins. Table 15.1 D/A Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin Input Analog power supply and reference voltage Analog ground pin Input Analog ground and reference voltage Analog output pin 0...
Page 482 15. D/A Converter 15.2 Register Descriptions 15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Initial value Read/Write The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 483 15. D/A Converter Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description analog output is disabled Channel-1 D/A conversion and DA analog output are enabled Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description...
Page 484 15. D/A Converter 15.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DASTE Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯...
Page 485 15. D/A Converter An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 15.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA becomes an output pin.
Page 486 15. D/A Converter 15.4 D/A Output Control In the H8/3008, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode.
Page 487 16. RAM Section 16 RAM 16.1 Overview The H8/3008 has high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer.
Page 488 16. RAM 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Bus interface SYSCR H'FEF20* H'FEF21* H'FEF22* H'FEF23* On-chip RAM H'FFF1E* H'FFF1F* Even addresses Odd addresses Legend: SYSCR: System control register...
Page 489 16. RAM 16.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable bit Enables or disables on-chip RAM Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM.
Page 490 16. RAM 16.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to the addresses shown in table 16.1 are directed to the on-chip RAM. In modes 1 to 4 (expanded modes), when the RAME bit is cleared to 0, the off-chip address space is accessed.
Page 491 17. Clock Pulse Generator Section 17 Clock Pulse Generator 17.1 Overview The H8/3008 has a built-in clock pulse generator (CPG) that generates the system clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (φ).
Page 492 17. Clock Pulse Generator 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the clock pulse generator. XTAL Duty Frequency Oscillator Prescalers adjustment divider circuit EXTAL Division control register Data bus φ φ/2 to φ/4096 Figure 17.1 Block Diagram of Clock Pulse Generator Rev.4.00 Aug.
Page 493 17. Clock Pulse Generator 17.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 17.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 17.2. Damping resistance Rd should be selected according to table 17.1 (1), and external capacitances and C according to table 17.1 (2).
Page 494 17. Clock Pulse Generator Table 17.1 (2) External Capacitance Values External Capacitance Value 5 V Version 3 V Version 20 < f ≤ 25 2 ≤ f ≤ 20 2 ≤ f ≤ 16 16 ≤ f ≤ 25 Frequency f (MHz) (pF) 10 to 22 Crystal Resonator: Figure 17.3 shows an equivalent circuit of the crystal resonator.
Page 495 17. Clock Pulse Generator Avoid Signal A Signal B H8/3008 XTAL EXTAL Figure 17.4 Oscillator Circuit Block Board Design Precautions 17.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 17.5.
Page 496 17. Clock Pulse Generator External Clock: The external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. Table 17.3 shows the clock timing, figure 17.6 shows the external clock input timing, and figure 17.7 shows the external clock output settling delay timing.
Page 497 17. Clock Pulse Generator × 0.7 EXTAL × 0.5 0.3 V Figure 17.6 External Clock Input Timing STBY EXTAL φ (internal or external) DEXT Figure 17.7 External Clock Output Settling Delay Timing Rev.4.00 Aug. 20, 2007 Page 453 of 638 REJ09B0395-0400...
Page 498 17. Clock Pulse Generator 17.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate φ. 17.4 Prescalers The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096). 17.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ).
Page 499 17. Clock Pulse Generator 17.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DIV1 DIV0 Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Reserved bits Divide bits 1 and 0...
Page 500 17. Clock Pulse Generator 17.5.3 Usage Notes The DIVCR setting changes the φ frequency, so note the following points. • Select a frequency division ratio that stays within the assured operation range specified for the in the AC electrical characteristics. Note that φ clock cycle time t = lower limit of the operating frequency range.
Page 501 18. Power-Down State Section 18 Power-Down State 18.1 Overview The H8/3008 has a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: •...
Page 502 18. Power-Down State Table 18.1 Power-Down State and Module Standby Function Rev.4.00 Aug. 20, 2007 Page 458 of 638 REJ09B0395-0400...
Page 503 18. Power-Down State 18.2 Register Configuration The H8/3008 has a system control register (SYSCR) that controls the power-down state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby function. Table 18.2 summarizes these registers. Table 18.2 Control Register Address* Name...
Page 504 18. Power-Down State Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description...
Page 505 18. Power-Down State 18.2.2 Module Standby Control Register H (MSTCRH) MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the SCI0, SCI1. ⎯...
Page 506 18. Power-Down State Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby. Bit 0 MSTPH0 Description SCI0 operates normally (Initial value) SCI0 is in standby state 18.2.3 Module Standby Control Register L (MSTCRL) MSTCRL is an 8-bit readable/writable register that controls the module standby function, which places individual on-chip supporting modules in the standby state.
Page 507 18. Power-Down State Bit 3—Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in standby. Bit 3 MSTPL3 Description 8-bit timer channels 0 and 1 operate normally (Initial value) 8-bit timer channels 0 and 1 are in standby state Bit 2—Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in standby.
Page 508 18. Power-Down State 18.3 Sleep Mode 18.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained.
Page 509 18. Power-Down State 18.4.2 Exit from Software Standby Mode Software standby mode can be exited by input of an external interrupt at the NMI, IRQ , IRQ , or pin, or by input at the RES or STBY pin. Exit by Interrupt: When an NMI, IRQ , IRQ , or IRQ interrupt request signal is received, the...
Page 510 18. Power-Down State Table 18.3 Clock Frequency and Waiting Time for Clock to Settle DIV1 DIV0 STS2 STS1 STS0 Waiting Time 25 MHz 20 MHz 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1MHz Unit 8192 states 0.46...
Page 511 18. Power-Down State 18.4.4 Sample Application of Software Standby Mode Figure 18.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 512 18. Power-Down State 18.5 Hardware Standby Mode 18.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, and on-chip supporting modules.
Page 513 18. Power-Down State Clock oscillator STBY Oscillator settling time Reset exception handling Figure 18.2 Hardware Standby Mode Timing 18.6 Module Standby Function 18.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (SCI1, SCI0, 16- bit timer, 8-bit timer, and A/D converter) independently in the power-down state.
Page 514 18. Power-Down State function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin, and its output may collide with external SCI transmit data. Data collision should be prevented by clearing the port DDR bit to 0 or taking other appropriate action.
Page 515 19. Electrical Characteristics Section 19 Electrical Characteristics 19.1 Absolute Maximum Ratings Table 19.1 lists the absolute maximum ratings. Table 19.1 Absolute Maximum Ratings Item Symbol Value Unit 5 V version: −0.3 to +7.0 Power supply voltage 3 V version: −0.3 to +4.6 −0.3 to V Input voltage (except for port 7) +0.3...
Page 516 19. Electrical Characteristics 19.2 DC Characteristics Table 19.2 lists the DC characteristics. Table 19.3 lists the permissible output currents. Table 19.2 DC Characteristics (1) = 5.0 V ±10%, AV = 5.0 V ±10%, V Conditions: V = 4.5 V to AV = −20°C to +75°C (regular specifications), = AV = 0 V*...
Page 517 19. Electrical Characteristics Test Item Symbol Unit Conditions ⎯ ⎯ μA Three-state Ports 4 to 6, = 0.5 V to −0.5 V leakage to A current Ports 8 to B RESO ⎯ ⎯ μA 10.0 = 0 V −I ⎯ μA Input pull-up Ports 4 and 5...
Page 518 19. Electrical Characteristics Notes: 1. Do not open the pin connections of the AV and AV pins while the A/D converter is not in use. Connect the AV and V pins to the V and connect the AV pin to the V respectively.
Page 519 19. Electrical Characteristics Table 19.2 DC Characteristics (2) Conditions: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 V to AV = −20°C to +75°C (regular specifications), = AV = 0 V* = −40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 520 19. Electrical Characteristics Test Item Symbol Unit Conditions ⎯ ⎯ μA Three-state Ports 4 to 6, = 0.5 V to −0.5 V leakage to A current Ports 8 to B RESO ⎯ ⎯ μA 10.0 = 0 V −I ⎯ μA Input pull-up Ports 4 and 5...
Page 521 19. Electrical Characteristics × 0.9 and V Also, the aforesaid current consumption values are when V min = V ≤ V max = 0.3 V under the condition of V < 3.0 V. max. (under normal operations) = 3.0 (mA) + 0.61 (mA/(MHz × V)) × V ×...
Page 522 19. Electrical Characteristics H8/3008 2 kΩ Port Darlington pair Figure 19.1 Darlington Pair Drive Circuit (Example) Rev.4.00 Aug. 20, 2007 Page 478 of 638 REJ09B0395-0400...
Page 523 19. Electrical Characteristics 19.3 AC Characteristics Clock timing parameters are listed in table 19.4, control signal timing parameters in table 19.5, and bus timing parameters in table 19.6. Timing parameters of the on-chip supporting modules are listed in table 19.7. Table 19.4 Clock Timing = −20°C to +75°C (regular specifications), T = −40°C to +85°C (wide-range...
Page 524 19. Electrical Characteristics Table 19.5 Control Signal Timing = −20°C to +75°C (regular specifications), T = −40°C to +85°C (wide-range Condition: specifications) Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = 25 MHz...
Page 525 19. Electrical Characteristics Table 19.6 Bus Timing = −20°C to +75°C (regular specifications), T = −40°C to +85°C (wide-range Condition: specifications) Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = 25 MHz...
Page 526 19. Electrical Characteristics Condition B and C Item Symbol Min Unit Test Conditions ⎯ ⎯ Write data hold time 0.5 t 0.5 t Figure 19.7, −15 −15 figure 19.8 ⎯ ⎯ Read data access time 1 2.0 t 2.0 t ACC1 −45 −45...
Page 527 19. Electrical Characteristics Table 19.7 Timing of On-Chip Supporting Modules = −20°C to +75°C (regular specifications), T = −40°C to +85°C (wide-range Condition: specifications) Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = 25 MHz...
Page 528 19. Electrical Characteristics Condition B and C Test Module Item Symbol Min Max Unit Conditions ⎯ ⎯ Input clock Asynchronous t Figure 19.14 Scyc cycle ⎯ ⎯ Synchronous ⎯ ⎯ Input clock rise time SCKr ⎯ ⎯ Input clock fall time SCKf Input clock pulse width SCKW...
Page 529 19. Electrical Characteristics 19.4 A/D Conversion Characteristics Table 19.8 lists the A/D conversion characteristics. Table 19.8 A/D Conversion Characteristics = −20°C to +75°C (regular specifications), T = −40°C to +85°C (wide-range Condition: specifications) Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV...
Page 530 19. Electrical Characteristics Condition B and C Item Unit Conversion Resolution bits time: 5.36 ⎯ ⎯ 5.36 ⎯ ⎯ μs Conversion time (single mode) 70 states ⎯ ⎯ ⎯ ⎯ Analog input capacitance φ ≤ 13 MHz ⎯ ⎯ ⎯ ⎯...
Page 531 19. Electrical Characteristics 19.5 D/A Conversion Characteristics Table 19.9 lists the D/A conversion characteristics. Table 19.9 D/A Conversion Characteristics = −20°C to +75°C (regular specifications), T = −40°C to +85°C (wide-range Condition: specifications) Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV...
Page 532 19. Electrical Characteristics 19.6 Operational Timing This section shows timing diagrams. 19.6.1 Clock Timing Clock timing is shown as follows: • Oscillator settling timing Figure 19.3 shows the oscillator settling timing. φ STBY OSC1 OSC1 Figure 19.3 Oscillator Settling Timing Rev.4.00 Aug.
Page 533 19. Electrical Characteristics 19.6.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 19.4 shows the reset input timing. • Reset output timing Figure 19.5 shows the reset output timing. • Interrupt input timing Figure 19.6 shows the interrupt input timing for NMI and IRQ to IRQ φ...
Page 534 19. Electrical Characteristics φ NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0 to 5) NMIW (j = 0 to 5) Figure 19.6 Interrupt Input Timing Rev.4.00 Aug. 20, 2007 Page 490 of 638 REJ09B0395-0400...
Page 535 19. Electrical Characteristics 19.6.3 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 19.7 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 19.8 shows the timing of the external three-state access cycle. •...
Page 536 19. Electrical Characteristics φ to A PCH1 ACC3 ACC3 PCH2 (read) ACC1 to D (read) PCH1 HWR, LWR (write) WSW1 WDS1 to D (write) , CS , and RD. Note: Specification from the earliest negation timing of A to A Figure 19.7 Basic Bus Cycle: Two-State Access Rev.4.00 Aug.
Page 537 19. Electrical Characteristics φ to A ACC4 ACC4 (read) ACC2 to D (read) WSW2 HWR, LWR (write) WDS2 to D (write) Figure 19.8 Basic Bus Cycle: Three-State Access Rev.4.00 Aug. 20, 2007 Page 493 of 638 REJ09B0395-0400...
Page 538 19. Electrical Characteristics φ to A RD (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 19.9 Basic Bus Cycle: Three-State Access with One Wait State φ BRQS BRQS BREQ BACD2 BACD1 BACK to A AS, RD, HWR, LWR Figure 19.10 Bus-Release Mode Timing Rev.4.00 Aug.
Page 539 19. Electrical Characteristics 19.6.4 TPC and I/O Port Timing Figure 19.11 shows the TPC and I/O port input/output timing. φ Port 4 to B (read) Port 4, 6, 8 to B (write) Figure 19.11 TPC and I/O Port Input/Output Timing 19.6.5 Timer Input/Output Timing 16-bit timer and 8-bit timer timing are shown below.
Page 540 19. Electrical Characteristics TCKS φ TCKS TCLKA to TCLKD TCKWL TCKWH Figure 19.13 Timer External Clock Input Timing 19.6.6 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 19.14 shows the SCI input clock timing. •...
Page 541 Appendix A Instruction Set Appendix A Instruction Set Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs)
Page 542 Appendix A Instruction Set Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 ⎯ Not affected by execution of the instruction Δ Varies depending on conditions, described in notes Rev.4.00 Aug.
Page 543 Appendix A Instruction Set Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z #xx:8 → Rd8 ⎯ ⎯ 0 ⎯ MOV.B #xx:8, Rd Rs8 → Rd8 ⎯...
Page 544 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z @aa:24 → Rd16 ⎯ ⎯ 0 ⎯ MOV.W @aa:24, Rd Rs16 → @ERd ⎯ ⎯ 0 ⎯ MOV.W Rs, @ERd Rs16 →...
Page 545 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ⎯ ⎯ 0 ⎯ SP − 2 → SP PUSH.W Rn Rn16 → @SP ⎯ ⎯ 0 ⎯ SP − 4 → SP PUSH.L ERn ERn32 →...
Page 546 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32 ⎯ ⎯ ⎯ INC.L #1, ERd ERd32+2 → ERd32 ⎯ ⎯ ⎯ INC.L #2, ERd ⎯ * * ⎯...
Page 547 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32 ÷ Rs16 → ERd32 ⎯ ⎯ (6) (7) ⎯ ⎯ DIVXU. W Rs, ERd (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷...
Page 548 Appendix A Instruction Set 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8 ⎯ ⎯ 0 ⎯ AND.B #xx:8, Rd Rd8∧Rs8 → Rd8 ⎯ ⎯ 0 ⎯ AND.B Rs, Rd Rd16∧#xx:16 →...
Page 549 Appendix A Instruction Set 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ⎯ ⎯ SHAL.B Rd ⎯ ⎯ SHAL.W Rd ⎯ ⎯ SHAL.L ERd ⎯ ⎯ SHAR.B Rd ⎯ ⎯ SHAR.W Rd ⎯...
Page 550 Appendix A Instruction Set 5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BSET #xx:3, Rd (#xx:3 of @ERd) ← 1 ⎯...
Page 551 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C ⎯ ⎯ ⎯ ⎯ ⎯ BLD #xx:3, @ERd (#xx:3 of @aa:8) → C ⎯ ⎯ ⎯ ⎯ ⎯ BLD #xx:3, @aa:8 ¬(#xx:3 of Rd8) →...
Page 552 Appendix A Instruction Set 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Condition H N Z ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BRA d:8 (BT d:8) If condition Always is true then ⎯...
Page 553 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Operation H N Z Condition ⎯ Z ∨ (N⊕V) = 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BLE d:8 If condition is true then ⎯...
Page 554 Appendix A Instruction Set 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ⎯ PC → @−SP 1 ⎯ ⎯ ⎯ ⎯ ⎯ TRAPA #x:2 14 16 CCR → @−SP <vector>...
Page 555 Appendix A Instruction Set 8. Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ⎯ if R4L ≠ 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ EEPMOV. B 8+4n* repeat @R5 → @R6 R5+1 →...
Page 556 Appendix A Instruction Set Operation Code Maps Table A.2 Operation Code Map (1) Rev.4.00 Aug. 20, 2007 Page 512 of 638 REJ09B0395-0400...
Page 557 Appendix A Instruction Set Table A.2 Operation Code Map (2) Rev.4.00 Aug. 20, 2007 Page 513 of 638 REJ09B0395-0400...
Page 558 Appendix A Instruction Set Table A.2 Operation Code Map (3) Rev.4.00 Aug. 20, 2007 Page 514 of 638 REJ09B0395-0400...
Page 559 Appendix A Instruction Set Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction.
Page 560 Appendix A Instruction Set Table A.3 Number of States per Cycle Access Conditions External Device On-Chip Sup- porting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S Stack operation...
Page 561 Appendix A Instruction Set Table A.4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS...
Page 562 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16...
Page 563 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8...
Page 564 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B 2n + 2*...
Page 565 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd...
Page 566 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOVFPE MOVFPE @aa:16, Rd* MOVTPE MOVTPE Rs, @aa:16* MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd...
Page 567 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic Normal Advanced 2 SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR...
Page 568 Appendix B Internal I/O Registers Appendix B Internal I/O Registers Address List Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE000 ⎯ ⎯...
Page 569 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE020 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller H'EE021 ASTCR...
Page 570 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE040 Reserved area (access prohibited) H'EE041 H'EE042 H'EE043 H'EE044 H'EE045 H'EE046 H'EE047...
Page 571 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE060 Reserved area (access prohibited) H'EE061 H'EE062 H'EE063 H'EE064 H'EE065 H'EE066 H'EE067...
Page 572 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE080 Reserved area (access prohibited) H'EE081 H'EE082 H'EE083 H'EE084 H'EE085 H'EE086 H'EE087...
Page 573 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE0A0 Reserved area (access prohibited) H'EE0A1 H'EE0A2 H'EE0A3 H'EE0A4 H'EE0A5 H'EE0A6 H'EE0A7...
Page 574 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE0C0 Reserved area (access prohibited) H'EE0C1 H'EE0C2 H'EE0C3 H'EE0C4 H'EE0C5 H'EE0C6 H'EE0C7...
Page 575 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE0E0 Reserved area (access prohibited) H'EE0E1 H'EE0E2 H'EE0E3 H'EE0E4 H'EE0E5 H'EE0E6 H'EE0E7...
Page 576 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF20 Reserved area (access prohibited) H'FFF21 H'FFF22 H'FFF23 H'FFF24 H'FFF25 H'FFF26 H'FFF27...
Page 577 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF40 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯...
Page 578 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name ⎯ ⎯ ⎯ ⎯ ⎯ H'FFF60 TSTR STR2 STR1 STR0 16-bit timer, (all ⎯...
Page 579 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF80 8TCR0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8-bit timer channels 0 and...
Page 580 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name ⎯ ⎯ ⎯ ⎯ H'FFFA0 TPMR G3NOV G2NOV G1NOV G0NOV TPC H'FFFA1 TPCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 H'FFFA2 NDERB...
Page 581 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFC0 Reserved area (access prohibited) H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 H'FFFC7...
Page 582 Appendix B Internal I/O Registers Data Bit Names Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFE0 ADDRAH A/D converter ⎯ ⎯ ⎯ ⎯ ⎯ ⎯...
Page 583 Appendix B Internal I/O Registers Functions Register Register Address to which Name of on-chip acronym name the register is mapped supporting module TSTR⎯Timer Start Register H'60 ITU (all channels) numbers ⎯ Initial bit ⎯ ⎯ STR4 STR3 STR2 STR1 STR0 values Initial value Names of the...
Page 584 Appendix B Internal I/O Registers P4DDR—Port 4 Data Direction Register H'EE003 Port 4 Initial value Read/Write Port 4 input/output select Generic input Generic output P6DDR—Port 6 Data Direction Register H'EE005 Port 6 ⎯ Initial value ⎯ Read/Write Port 6 input/output select Generic input Generic output P8DDR—Port 8 Data Direction Register...
Page 585 Appendix B Internal I/O Registers P9DDR—Port 9 Data Direction Register H'EE008 Port 9 ⎯ ⎯ Initial value ⎯ ⎯ Read/Write Port 9 input/output select Generic input Generic output PADDR—Port A Data Direction Register H'EE009 Port A Initial value Modes ⎯ Read/Write 3 and 4 Modes...
Page 586 Appendix B Internal I/O Registers MDCR—Mode Control Register H'EE011 System control ⎯ ⎯ ⎯ ⎯ ⎯ MDS2 MDS1 MDS0 ⎯ ⎯ ⎯ Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Mode select 2 to 0 Bit 2 Bit 1 Bit 0 Operating Mode ⎯...
Page 587 Appendix B Internal I/O Registers SYSCR—System Control Register H'EE012 System control SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable On-chip RAM is disabled On-chip RAM is enabled Software standby output port enable In software standby mode, all address bus and bus control signals are high- impedance...
Page 588 Appendix B Internal I/O Registers BRCR—Bus Release Control Register H'EE013 Bus controller ⎯ ⎯ ⎯ A23E A22E A21E A20E BRLE Modes Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 and 2 Read/Write Modes Initial value ⎯ ⎯ ⎯ ⎯...
Page 589 Appendix B Internal I/O Registers IER—IRQ Enable Register H'EE015 Interrupt Controller ⎯ ⎯ IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write to IRQ enable to IRQ interrupts are disabled to IRQ interrupts are enabled ISR—IRQ Status Register H'EE016 Interrupt Controller ⎯...
Page 590 Appendix B Internal I/O Registers IPRA—Interrupt Priority Register A H'EE018 Interrupt Controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 Priority level 0 (low priority) Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 591 Appendix B Internal I/O Registers DASTCR—D/A Standby Control Register H'EE01A ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DASTE Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write D/A standby enable D/A output is disabled in software standby mode (Initial value) D/A output is enabled in software standby mode DIVCR—Division Control Register H'EE01B...
Page 592 Appendix B Internal I/O Registers MSTCRH—Module Standby Control Register H H'EE01C System control ⎯ ⎯ ⎯ ⎯ ⎯ PSTOP MSTPH1 MSTPH0 Initial value ⎯ ⎯ ⎯ ⎯ Read/Write Module standby H1 to H0 Selection bits for placing modules in standby state. Reserved bits φ...
Page 593 Appendix B Internal I/O Registers ADRCR—Address Control Register H'EE01E Bus controller ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADRCTL Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Reserved bits Address control Selects address update mode 1 or address update mode 2.
Page 594 Appendix B Internal I/O Registers ABWCR—Bus Width Control Register H'EE020 Bus controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes Initial value 1 and 3 Modes Initial value 2 and 4 Read/Write Area 7 to 0 bus width control Bits 7 to 0 Bus Width of Access Area ABW7...
Page 595 Appendix B Internal I/O Registers WCRH—Wait Control Register H H'EE022 Bus controller Initial value Read/Write Area 4 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 5 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 596 Appendix B Internal I/O Registers WCRL—Wait Control Register L H'EE023 Bus controller Initial value Read/Write Area 0 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 1 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 597 Appendix B Internal I/O Registers BCR—Bus Control Register H'EE024 Bus controller ⎯ ⎯ ⎯ ⎯ ICIS1 ICIS0 RDEA WAITE Initial value ⎯ ⎯ ⎯ ⎯ Read/Write Wait pin enable WAIT pin wait input is disabled WAIT pin wait input is enabled Area division unit select Area divisions are as follows: Area 0: 2 Mbytes...
Page 598 Appendix B Internal I/O Registers P4PCR—Port 4 Input Pull-Up MOS Control Register H'EE03E Port 4 Initial value Read/Write Port 4 input pull-up MOS control 7 to 0 Input pull-up transistor is off Input pull-up transistor is on Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input).
Page 599 Appendix B Internal I/O Registers TSTR—Timer Start Register H'FFF60 16-bit timer (all channels) ⎯ ⎯ ⎯ ⎯ ⎯ STR2 STR1 STR0 Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Reserved bits Counter start 0 16TCNT0 is halted (Initial value) 16TCNT0 is counting Counter start 1 16TCNT1 is halted (Initial value)
Page 600 Appendix B Internal I/O Registers TSNC—Timer Synchro Register H'FFF61 16-bit timer (all channels) ⎯ ⎯ ⎯ ⎯ ⎯ SYNC2 SYNC1 SYNC0 Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Reserved bits Timer sync 0 Channel 0 timer counter (16TCNT0) operates independently (16TCNT0 presetting/clearing is independent of other channels) (Initial value)
Page 601 Appendix B Internal I/O Registers TMDR—Timer Mode Register H'FFF62 16-bit timer (all channels) ⎯ ⎯ ⎯ FDIR PWM2 PWM1 PWM0 Initial value ⎯ ⎯ ⎯ Read/Write PWM mode 0 Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode PWM mode 1 Channel 1 operates normally (Initial value)
Page 602 Appendix B Internal I/O Registers TOLR—Timer Output Level Setting Register H'FFF63 16-bit timer (all channels) ⎯ ⎯ TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value ⎯ ⎯ Read/Write Output level setting A0 TIOCA is 0 (Initial value) TIOCA is 1 Output level setting B0 TIOCB is 0...
Page 603 Appendix B Internal I/O Registers TISRA—Timer Interrupt Status Register A H'FFF64 16-bit timer (all channels) Bit: ⎯ ⎯ IMIEA2 IMIEA1 IMIEA0 IMFA2 IMFA1 IMFA0 Initial value: ⎯ ⎯ Read/Write: R/(W)* R/(W)* R/(W)* Input capture/compare match flag A0 [Clearing conditions] (Initial value) Read IMFA0 when IMFA0 = 1, then write 0 in IMFA0 [Setting conditions] •...
Page 604 Appendix B Internal I/O Registers TISRB—Timer Interrupt Status Register B H'FFF65 16-bit timer (all channels) Bit: ⎯ ⎯ IMIEB2 IMIEB1 IMIEB0 IMFB2 IMFB1 IMFB0 Initial value: ⎯ ⎯ Read/Write: R/(W)* R/(W)* R/(W)* Input capture/compare match flag B0 [Clearing condition] (Initial value) Read IMFB0 when IMFB0 = 1, then write 0 in IMFB0.
Page 605 Appendix B Internal I/O Registers TISRC—Timer Interrupt Status Register C H'FFF66 16-bit timer (all channels) Bit: ⎯ ⎯ OVIE2 OVIE1 OVIE0 OVF2 OVF1 OVF0 Initial value: ⎯ ⎯ Read/Write: R/(W)* R/(W)* R/(W)* Overflow flag 0 [Clearing condition] (Initial value) Read OVF0 when OVF0 = 1, then write 0 in OVF0. [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000.
Page 606 Appendix B Internal I/O Registers 16TCR0—Timer Control Register 0 H'FFF68 16-bit timer channel 0 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value ⎯ Read/Write Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 Description TPSC2 TPSC1 TPSC0 Internal clock : φ...
Page 607 Appendix B Internal I/O Registers TIOR0—Timer I/O Control Register 0 H'FFF69 16-bit timer channel 0 Bit: ⎯ ⎯ IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Initial value: ⎯ ⎯ Read/Write: I / O control A2 to A0 Bit 2 Bit 1 Bit 0 Description IOA2...
Page 608 Appendix B Internal I/O Registers 16TCNT0 H/L—Timer Counter 0 H/L H'FFF6A, H'FFF6B 16-bit timer channel 0 Initial value Read/Write Up-counter GRA0 H/L—General Register A0 H/L H'FFF6C, H'FFF6D 16-bit timer channel 0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H'FFF6E, H'FFF6F 16-bit timer channel 0...
Page 609 Appendix B Internal I/O Registers 16TCR1 Timer Control Register 1 H'FFF70 16-bit timer channel 1 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value ⎯ Read/Write Note: Bit functions are the same as for 16-bit timer channel 0. TIOR1—Timer I/O Control Register 1 H'FFF71 16-bit timer channel 1 ⎯...
Page 610 Appendix B Internal I/O Registers GRA1 H/L—General Register A1 H/L H'FFF74, H'FFF75 16-bit timer channel 1 Initial value Read/Write Note: Bit functions are the same as for 16-bit timer channel 0. GRB1 H/L—General Register B1 H/L H'FFF76, H'FFF77 16-bit timer channel 1 Initial value Read/Write Note: Bit functions are the same as for 16-bit timer channel 0.
Page 611 Appendix B Internal I/O Registers TIOR2—Timer I/O Control Register 2 H'FFF79 16-bit timer channel 2 ⎯ ⎯ IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Initial value ⎯ ⎯ Read/Write Note: Bit functions are the same as for 16-bit timer channel 0. 16TCNT2 H/L—Timer Counter 2 H/L H'FFF7A, H'FFF7B 16-bit timer channel 2...
Page 612 Appendix B Internal I/O Registers 8TCR0—Timer Control Register 0 H'FFF80 8-bit timer channel 0 8TCR1—Timer Control Register 1 H'FFF81 8-bit timer channel 1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 Clock input is disabled Internal clock: counted on rising edge of φ/8 Internal clock: counted on rising...
Page 613 Appendix B Internal I/O Registers 8TCSR0—Timer Control/Status Register 0 H'FFF82 8-bit timer channel 0 CMFB CMFA ADTE OIS3 OIS2 Initial value Read/Write R/(W) R/(W) R/(W) Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare...
Page 614 Appendix B Internal I/O Registers 8TCSR1—Timer Control/Status Register 1 H'FFF83 8-bit timer channel 1 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare...
Page 615 Appendix B Internal I/O Registers TCORA0—Time Constant Register A0 H'FFF84 8-bit timer channel 0 TCORA1—Time Constant Register A1 H'FFF85 8-bit timer channel 1 TCORA0 TCORA1 Initial value Read/Write TCORB0—Time Constant Register B0 H'FFF86 8-bit timer channel 0 TCORB1—Time Constant Register B1 H'FFF87 8-bit timer channel 1 TCORB0...
Page 616 Appendix B Internal I/O Registers TCSR—Timer Control/Status Register H'FFF8C ⎯ ⎯ WT/IT CKS2 CKS1 CKS0 Initial value ⎯ ⎯ Read/Write R/(W)* Clock select 2 to 0 CKS2 CKS1 CKS0 Description φ/2 φ/32 φ/64 φ/128 φ/256 φ/512 φ/2048 φ/4096 Timer enable Timer disabled: TCNT is initialized to H'00 and halted Timer enabled:...
Page 617 Appendix B Internal I/O Registers TCNT—Timer Counter H'FFF8D (read), H'FFF8C (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'FFF8F (read), H'FFF8E (write) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ WRST RSTOE Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write R/(W)* Reset output enable External output of reset signal is disabled...
Page 618 Appendix B Internal I/O Registers 8TCR2—Timer Control Register 2 H'FFF90 8-bit timer channel 2 8TCR3—Timer Control Register 3 H'FFF91 8-bit timer channel 3 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 CSK2 CSK1 CSK0 Description Clock input is disabled Internal clock: counted on rising edge...
Page 619 Appendix B Internal I/O Registers 8TCSR2—Timer Control/Status Register 2 H'FFF92 8-bit timer channel 2 8TCSR3—Timer Control/Status Register 3 H'FFF93 8-bit timer channel 3 8TCSR2 ⎯ CMFB CMFA OIS3 OIS2 Initial value ⎯ Read/Write R/(W)* R/(W)* R/(W)* 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write...
Page 620 Appendix B Internal I/O Registers TCORA2—Time Constant Register A2 H'FFF94 8-bit timer channel 2 TCORA3—Time Constant Register A3 H'FFF95 8-bit timer channel 3 TCORA2 TCORA3 Initial value Read/Write TCORB2—Time Constant Register B2 H'FFF96 8-bit timer channel 2 TCORB3—Time Constant Register B3 H'FFF97 8-bit timer channel 3 TCORB2...
Page 621 Appendix B Internal I/O Registers DADR1—D/A Data Register 1 H'FFF9D Initial value Read/Write D/A conversion data Rev.4.00 Aug. 20, 2007 Page 577 of 638 REJ09B0395-0400...
Page 622 Appendix B Internal I/O Registers DACR—D/A Control Register H'FFF9E ⎯ ⎯ ⎯ ⎯ ⎯ DAOE1 DAOE0 Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write D/A enable Bit 7 Bit 6 Bit 5 Description DAOE1 DAOE0 D/A conversion is disabled ⎯ in channels 0 and 1 D/A conversion is enabled in channel 0...
Page 623 Appendix B Internal I/O Registers TPMR—TPC Output Mode Register H'FFFA0 ⎯ ⎯ ⎯ ⎯ G3NOV G2NOV G1NOV G0NOV Initial value ⎯ ⎯ ⎯ ⎯ Read/Write Group 0 non-overlap Normal TPC output in group 0. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 0, controlled by compare match A and B in the...
Page 624 Appendix B Internal I/O Registers TPCR—TPC Output Control Register H'FFFA1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 16-Bit Timer Channel Selected as Output Trigger G0CMS1 G0CMS0 TPC output group 0 (TP...
Page 625 Appendix B Internal I/O Registers NDERB—Next Data Enable Register B H'FFFA2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 Description NDER15 to NDER8 TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB...
Page 626 Appendix B Internal I/O Registers NDRB—Next Data Register B H'FFFA4/H'FFFA6 • Same trigger for TPC output groups 2 and 3 ⎯ Address H'FFFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Store the next output data for TPC output group 3 Store the next output data for TPC output group 2 ⎯...
Page 627 Appendix B Internal I/O Registers NDRA—Next Data Register A H'FFFA5/H'FFFA7 • Same trigger for TPC output groups 0 and 1 ⎯ Address H'FFFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Store the next output data for TPC output group 1 Store the next output data for TPC output group 0 ⎯...
Page 628 Appendix B Internal I/O Registers SMR—Serial Mode Register H'FFFB0 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 Clock Source CKS1 CKS0 φ clock φ/4 clock φ/16 clock φ/64 clock Multiprocessor mode Multiprocessor function disabled Multiprocessor format selected Stop bit length One stop bit...
Page 629 Appendix B Internal I/O Registers BRR—Bit Rate Register H'FFFB1 SCI0 Initial value Read/Write Serial communication bit rate setting Rev.4.00 Aug. 20, 2007 Page 585 of 638 REJ09B0395-0400...
Page 630 Appendix B Internal I/O Registers SCR—Serial Control Register H'FFFB2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Receive enable (for serial communication interface) Receiving is Bit 1 Bit 0 disabled Description CKE1 CKE0 Receiving is Internal clock: SCK pin Asynchronous mode enabled...
Page 631 Appendix B Internal I/O Registers TDR—Transmit Data Register H'FFFB3 SCI0 Initial value Read/Write Serial transmit data Rev.4.00 Aug. 20, 2007 Page 587 of 638 REJ09B0395-0400...
Page 632 Appendix B Internal I/O Registers SSR—Serial Status Register H'FFFB4 SCI0 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor bit transfer Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 Multiprocessor bit Multiprocessor bit value in receive data is 0 Multiprocessor bit value in receive data is 1...
Page 633 Appendix B Internal I/O Registers RDR—Receive Data Register H'FFFB5 SCI0 Initial value Read/Write Serial receive data SCMR—Smart Card Mode Register H'FFFB6 SCI0 ⎯ ⎯ ⎯ ⎯ ⎯ SDIR SINV SMIF Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Smart card interface mode select Smart card interface function is disabled (Initial value) Smart card interface function is enabled...
Page 634 Appendix B Internal I/O Registers SMR—Serial Mode Register H'FFFB8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H'FFFB9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H'FFFBA SCI1...
Page 635 Appendix B Internal I/O Registers SSR—Serial Status Register H'FFFBC SCI1 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Notes: Bit functions are the same as for SCI0. * Only 0 can be written to clear the flag. RDR—Receive Data Register H'FFFBD SCI1...
Page 636 Appendix B Internal I/O Registers P6DR—Port 6 Data Register H'FFFD5 Port 6 Initial value Read/Write Data for port 6 pins P7DR—Port 7 Data Register H'FFFD6 Port 7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value Read/Write Data for port 7 pins Note: * Determined by pins P7 to P7 P8DR—Port 8 Data Register...
Page 637 Appendix B Internal I/O Registers PADR—Port A Data Register H'FFFD9 Port A Initial value Read/Write Data for port A pins PBDR—Port B Data Register H'FFFDA Port B Initial value Read/Write Data for port B pins Rev.4.00 Aug. 20, 2007 Page 593 of 638 REJ09B0395-0400...
Page 638 Appendix B Internal I/O Registers ADDRA H/L—A/D Data Register A H/L H'FFFE0, H'FFFE1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value Read/Write ADDRAH ADDRAL A/D conversion data 10-bit data giving an A/D conversion result ADDRB H/L—A/D Data Register B H/L H'FFFE2, H'FFFE3 ⎯...
Page 639 Appendix B Internal I/O Registers ADDRD H/L—A/D Data Register D H/L H'FFFE6, H'FFFE7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value Read/Write ADDRDH ADDRDL A/D conversion data 10-bit data giving an A/D conversion result ADCR—A/D Control Register H'FFFE9 ⎯ ⎯ ⎯...
Page 640 Appendix B Internal I/O Registers ADCSR—A/D Control/Status Register H'FFFE8 ADIE ADST SCAN Initial value Read/Write R/(W)* Channel select 2 to 0 Clock select Conversion time = Description Group Selection Channel Selection 134 states (maximum) CH1 CH0 Single Mode Scan Mode Conversion time = 70 states (maximum) to AN...
Page 641 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Port 4 Block Diagram 8-bit bus 16-bit bus mode mode Reset P4 PCR RP4P WP4P Hardware Reset standby Write to external address P4 DDR External bus released WP4D Reset P4 DR Read external...
Page 642 Appendix C I/O Port Block Diagrams Port 6 Block Diagrams Reset Hardware Standby P6 DDR Bus controller WP6D WAIT input Reset enable P6 DR Bus controller WAIT Legend: input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.2 (a) Port 6 Block Diagram (Pin P6 Rev.4.00 Aug.
Page 643 Appendix C I/O Port Block Diagrams Reset controller Hardware Standby P6 DDR WP6D Bus release enable Reset P6 DR BREQ input Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.2 (b) Port 6 Block Diagram (Pin P6 Rev.4.00 Aug.
Page 644 Appendix C I/O Port Block Diagrams Reset Hardware standby P6 DDR WP6D Reset P6 DR Bus controller Bus release enable BACK output Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.2 (c) Port 6 Block Diagram (Pin P6 Rev.4.00 Aug.
Page 645 Appendix C I/O Port Block Diagrams Hardware standby φ output enable φ output Legend: RP6: Read port 6 Figure C.2 (d) Port 6 Block Diagram (Pin P6 Rev.4.00 Aug. 20, 2007 Page 601 of 638 REJ09B0395-0400...
Page 646 Appendix C I/O Port Block Diagrams Port 7 Block Diagrams A/D converter Analog input Input enable Legend: Channel select signal RP7: Read port 7 Note: n = 0 to 5 Figure C.3 (a) Port 7 Block Diagram (Pins P7 to P7 A/D converter Analog input Input enable...
Page 647 Appendix C I/O Port Block Diagrams Port 8 Block Diagrams Reset P8 DDR WP8D Reset P8 DR Interrupt controller Legend: WP8D: Write to P8DDR input WP8: Write to port 8 RP8: Read port 8 Figure C.4 (a) Port 8 Block Diagram (Pin P8 Rev.4.00 Aug.
Page 648 Appendix C I/O Port Block Diagrams SSOE Software standby External bus released Reset Hardware standby Bus controller P8 DDR WP8D Reset output P8 DR Interrupt controller input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable Note: n = 1, 2...
Page 649 Appendix C I/O Port Block Diagrams Software standby SSOE External bus released Reset Hardware standby Bus controller WP8D output Reset Interrupt controller input A/D converter ADTRG input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable Figure C.4 (c) Port 8 Block Diagram (Pin P8...
Page 650 Appendix C I/O Port Block Diagrams Software standby SSOE External bus released Reset Bus controller P8 DDR Hardware standby WP8D output Reset P8 DR Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable Figure C.4 (d) Port 8 Block Diagram (Pin P8 Rev.4.00 Aug.
Page 651 Appendix C I/O Port Block Diagrams Port 9 Block Diagrams Reset Hardware standby P9 DDR WP9D Reset P9 DR Output enable Serial transmit data Guard time Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (a) Port 9 Block Diagram (Pin P9 Rev.4.00 Aug.
Page 652 Appendix C I/O Port Block Diagrams Reset Hardware standby P9 DDR WP9D Reset P9 DR Output enable Serial transmit data Guard time Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (b) Port 9 Block Diagram (Pin P9 Rev.4.00 Aug.
Page 653 Appendix C I/O Port Block Diagrams Reset Hardware standby P9 DDR WP9D Input enable Reset P9 DR Serial receive data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (c) Port 9 Block Diagram (Pin P9 Rev.4.00 Aug.
Page 654 Appendix C I/O Port Block Diagrams Reset Hardware standby WP9D Input enable Reset Serial receive data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (d) Port 9 Block Diagram (Pin P9 Rev.4.00 Aug. 20, 2007 Page 610 of 638 REJ09B0395-0400...
Page 655 Appendix C I/O Port Block Diagrams Reset Hardware standby P9 DDR WP9D Clock input Reset enable P9 DR Clock output enable Clock output Clock input Legend: Interrupt WP9D: Write to P9DDR controller WP9: Write to port 9 input RP9: Read port 9 Figure C.5 (e) Port 9 Block Diagram (Pin P9 Rev.4.00 Aug.
Page 656 Appendix C I/O Port Block Diagrams Reset Hardware standby WP9D Clock input enable Reset Clock output enable Clock output Clock input Interrupt controller input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.5 (f) Port 9 Block Diagram (Pin P9 Rev.4.00 Aug.
Page 657 Appendix C I/O Port Block Diagrams Port A Block Diagrams Reset Hardware standby PA DDR WPAD Reset output enable PA DR Next data Output trigger 16-bit timer Counter clock input Legend: WPAD: Write to PADDR 8-bit timer WPA: Write to port A RPA: Read port A Counter...
Page 658 Appendix C I/O Port Block Diagrams Reset Hardware standby PA DDR WPAD Reset output enable PA DR Next data Output trigger 16-bit timer Output enable Compare match output Input capture Counter clock Legend: input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A 8-bit timer...
Page 659 Appendix C I/O Port Block Diagrams Software standby SSOE Bus released Address output enable Modes 3 and 4 Reset Hardware standby WPAD Reset TPC output enable Next data Output trigger 16-bit timer Output enable Compare match output Input capture Legend: WPAD: Write to PADDR WPA:...
Page 660 Appendix C I/O Port Block Diagrams Port B Block Diagrams Software standby SSOE Hardware standby Reset PB DDR Bus controller WPBD CS5 output Bus released CS output enable Reset TPC output enable PB DR Next data Output trigger 8-bit timer Output enable Compare match output...
Page 661 Appendix C I/O Port Block Diagrams Software standby SSOE Hardware standby Reset Bus controller WPBD CS4 output Bus released CS output enable Reset TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output TMO2 TMO3 input Legend: WPBD: Write to PBDDR...
Page 662 Appendix C I/O Port Block Diagrams Reset Hardware standby PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.7 (c) Port B Block Diagram (Pin PB Rev.4.00 Aug.
Page 663 Appendix C I/O Port Block Diagrams Reset Hardware standby WPBD Reset TPC output enable Next data Output trigger Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.7 (d) Port B Block Diagram (Pin PB Rev.4.00 Aug.
Page 664 Appendix C I/O Port Block Diagrams Reset PB DDR Hardware standby WPBD Reset output enable PB DR Next data Output trigger Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.7 (e) Port B Block Diagram (Pin PB Rev.4.00 Aug.
Page 665 Appendix C I/O Port Block Diagrams Reset Hardware standby PB DDR WPBD Reset output enable PB DR Next data Output trigger Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.7 (f) Port B Block Diagram (Pin PB Rev.4.00 Aug.
Page 666 Appendix D Pin States Appendix D Pin States Port States in Each Mode Table D.1 Port States Hardware Standby Software Bus- Program Name Mode Reset Mode Standby Mode Released Mode Execution Mode ⎯ to A (SSOE = 0) to A (SSOE = 1) Keep ⎯...
Page 667 Appendix D Pin States Hardware Standby Software Bus- Program Name Mode Reset Mode Standby Mode Released Mode Execution Mode ⎯ to P7 Input port ⎯ ⎯ Keep I/O port ⎯ (DDR = 0) (DDR = 0) (DDR = 0) Keep Input port (DDR = 1, SSOE = 0) (DDR = 1)
Page 668 Appendix D Pin States Hardware Standby Software Bus- Program Name Mode Reset Mode Standby Mode Released Mode Execution Mode Keep 1, 2 Keep I/O port (SSOE = 0) 3, 4 (SSOE = 1) Keep ⎯ (CS output)* to PB (CS output)* (CS output)* to CS (SSOE = 0)
Page 669 Appendix D Pin States Pin States at Reset Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the input state.
Page 670 Appendix D Pin States Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the input state.
Page 671 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below.
Page 672 Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.1 H8/3008 Product Code Lineup Product Type Product Code Mark Code Package (Package Code) H8/3008 ROMless HD6413008F HD6413008F 100-pin QFP (FP-100B) HD6413008TE HD6413008TE 100-pin TQFP (TFP-100B) HD6413008VF HD6413008VF 100-pin QFP (FP-100B) HD6413008VTE...
Page 673 Appendix G Package Dimensions Appendix G Package Dimensions Figure G.1 shows the FP-100B package dimensions of the H8/3008. Figure G.2 shows the TFP- 100B package dimensions. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x14-0.50 PRQP0100KA-A FP-100B/FP-100BV 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2"...
Page 674 Appendix G Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP100-14x14-0.50 PTQP0100KA-A TFP-100B/TFP-100BV 0.5g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Terminal cross section Reference Symbol 1.00 15.8 16.0...
Page 675 Appendix H Comparison of H8/300H Series Product Specifications Appendix H Comparison of H8/300H Series Product Specifications Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and H8/3007, and H8/3008 H8/3067 Group, H8/3048 Item H8/3062 Group Group H8/3006, H8/3007 H8/3008 Operating Mode 5 16 Mbyte ROM 1 Mbyte...
Page 676 Appendix H Comparison of H8/300H Series Product Specifications H8/3067 Group, H8/3048 Item H8/3062 Group Group H8/3006, H8/3007 H8/3008 Timer functions 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit timers timers timers timers timers timers 16 bits × 3 8 bits × 4 16 bits ×...
Page 677 Appendix H Comparison of H8/300H Series Product Specifications H8/3067 Group, H8/3048 Item H8/3062 Group Group H8/3006, H8/3007 H8/3008 Number of 3 channels (H8/3067) 2 channels 3 channels 2 channels channels 2 channels (H8/3062 Group) Smart card Supported on all Supported Supported on all Supported on all interface...
Page 678 Appendix H Comparison of H8/300H Series Product Specifications Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) Table H.1 Pin Arrangement of Each Product (FP-100B, TFP-100B) On-chip-ROM Products ROMless Products H8/3006, H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3007 H8/3008 /TMO...
Page 679 Appendix H Comparison of H8/300H Series Product Specifications On-chip-ROM Products ROMless Products H8/3006, H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3007 H8/3008 Rev.4.00 Aug. 20, 2007 Page 635 of 638 REJ09B0395-0400...
Page 680 Appendix H Comparison of H8/300H Series Product Specifications On-chip-ROM Products ROMless Products H8/3006, H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3007 H8/3008 /WAIT /WAIT /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /BACK /BACK φ...
Page 681 Appendix H Comparison of H8/300H Series Product Specifications On-chip-ROM Products ROMless Products H8/3006, H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3007 H8/3008 /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ ADTRG ADTRG ADTRG ADTRG /TCLKA PA TEND TEND TEND TEND /TCLKA /TCLKA /TCLKA /TCLKA...
Page 682 Appendix H Comparison of H8/300H Series Product Specifications Rev.4.00 Aug. 20, 2007 Page 638 of 638 REJ09B0395-0400...
Page 683 Publication Date: 1st Edition, September 2000 Rev.4.00, August 20, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 684 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 686 H8/3008 Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

This manual is also suitable for:

H8/300 seriesH8/3008h seriesH8/3008H8 seriesHd6413008teHd6413008vf ... Show all