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ADLINK Technology VPX6200 User Manual

Vpx dual node blade with intel xeon w-11865mre
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VPX6200
VPX Dual Node Blade with
Intel® Xeon®
W-11865MRE
User's Manual
Manual Rev.:
Revision Date:
Part No:
Leading EDGE COMPUTING
1.0
May 3, 2024
50M-31428-1000

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Summary of Contents for ADLINK Technology VPX6200

  • Page 1 VPX6200 VPX Dual Node Blade with Intel® Xeon® W-11865MRE User’s Manual Manual Rev.: Revision Date: May 3, 2024 Part No: 50M-31428-1000 Leading EDGE COMPUTING...
  • Page 2 Leading EDGE COMPUTING Revision History Revision Release Date Description of Change(s) 2024-05 Initial release Revision History...
  • Page 3 VPX6200 Preface Copyright © 2024 ADLINK Technology Inc. This document contains proprietary information protected by copy- right. All rights are reserved. No part of this manual may be repro- duced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 4 Leading EDGE COMPUTING California Proposition 65 Warning WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox- ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause...
  • Page 5 VPX6200-RL2 RTM Board Layout........29 VPX6200 Onboard Connector Pin Assignments ....32 VPX6200 VPX Connector Pin Assignments ...... 35 VPX6200-RL1 RTM Onboard Connector Pin Assignments 78 VPX6200-RL1 RTM VPX Connector Pin Assignments ..84 3.10 VPX6200-RL1 RTM Switches..........90 Table of Contents...
  • Page 6 Leading EDGE COMPUTING 3.11 VPX6200-RL2 Onboard Connectors........92 4 Getting Started ..............93 Installing the VPX6200 to the Chassis....... 93 Installing the VPX6200-RL1 to the Chassis ....... 93 Driver Installation ............... 94 IPMC Firmware Update ............. 95 EC Firmware Update ............96 5 Utilities ................
  • Page 7 Figure 3-3: VPX6200 Status LEDs - Front Side....... 17 Figure 3-4: VPX6200 Status LEDs - Top Side ......... 19 Figure 3-5: VPX6200 Front Panel LEDs - Front Side ...... 20 Figure 3-6: VPX6200 System on Status LED ........20 Figure 3-7: VPX6200 Storage Status LED........21 Figure 3-8: VPX6200 EC Status LED ..........
  • Page 8 Leading EDGE COMPUTING This page intentionally left blank. viii List of Figures...
  • Page 9 Table 2-4: VPX6200 Power Consumption ........14 Table 3-1: VPX6200 Status LEDs - Front Side....... 17 Table 3-2: VPX6200 Status LEDs - Top Side ......... 19 Table 3-3: VPX6200 System on Status LED ........20 Table 3-4: VPX6200 Storage Status LED........21 Table 3-5: VPX6200 EC Status LED ..........
  • Page 10 Leading EDGE COMPUTING This page intentionally left blank. List of Tables...
  • Page 11 VPX6200 Introduction 1.1 Overview The VPX6200 is a 6U VPX processor blade with 11th Gen Intel® Xeon® W11865MRE processor that provides high-performance data processing. The dual node architecture is designed for redun- dancy, fulfilling the reliability requirement in mission-critical appli- cations.
  • Page 12 ,6/,5= -7$* 8$57B 56 56 &20 &20 8$57% 8$57% 7; 5; 576 &76 7; 5; 576 &76 ,30&B-7$* ,30&B'(%8* 8$57' 8$57' *3,2 *3,2 )URQW 6LGH  3RUW /(' )URQW 6LGH  3RUW /(' Figure 1-1: VPX6200 Functional Block Diagram Introduction...
  • Page 13 VPX6200 Figure 1-2: VPX6200-RL1 RTM Functional Block Diagram Introduction...
  • Page 14 Leading EDGE COMPUTING 1GBASE-T MDI NA Port 2 Dual Port RJ45 L2BTB1 1GBASE-T MDI NB Port 2 NA x 8 + NB x 8 61-7562C-2400 20 pin header Figure 1-3: VPX6200-RL2 RTM Functional Block Diagram Introduction...
  • Page 15 VPX6200 Model Number Decoder - Processor Blade VPX6200/W11865MRE/M32/S128/10GBase-KR (A) CPU Code  W1186MRE = Dual node 8-core Intel® Xeon® W11865MRE processor (B) Memory Size Code  M32 = Onboard 32GB DDR4-3200 memory (each node) (C) NVMe SSD Size Code ...
  • Page 16 Leading EDGE COMPUTING 1.5 Package Contents The VPX6200 is packaged with the following components. If any of the items on the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any prod- uct to ADLINK.
  • Page 17 • 2.0 to P5 for node A • 4x USB • 2.0 to P6 for node B • Supports USB 3.0 power (supply 0.9A) with overcurrent protection • Supports USB 2.0 power (supply 0.5A) with overcurrent protection Table 2-1: VPX6200 Blade Specifications Specifications...
  • Page 18 BIOS • Dual BIOS support Operating • Windows 10 IoT Enterprise LTSC 21H2 System • Linux (kernel 5.13 and higher) Power • 12V (VS1/VS2) Requirement • 5V (VS3) • 3.3V_AUX only • Max. 100W Table 2-1: VPX6200 Blade Specifications Specifications...
  • Page 19 Monitors CPU temperature, system temperature, Vcore and DC voltages • IPMC SmartFusion SoC provides IPMI software functions Firmware updateable (via JTAG pin header on VPX6200- RL1) • Serial Over LAN SOL port via IPMC (COM3) for node A • Management Port Management port via UART (COM3) for node B •...
  • Page 20 105,594 hours (without SSD) and 104,313 hours (with 128GB 3D TLC NVMe, according to MIL HDBK 217F Notice 2) • CE (EN555032/EN55035) ; FCC Part 15B Class A Table 2-1: VPX6200 Blade Specifications Note: Specifications are subject to change without prior notice. Specifications...
  • Page 21 • 1x DB9 from RP5 RS-232/422 for node A (COM1) • 1x DB9 from RP6 RS-232/422 for node B (COM1) • 1x 10-pin header from RP5 & RP6 RS-232/422 for node A & node B (COM2) Table 2-2: VPX6200-RL1 RTM Specifications Specifications...
  • Page 22 1x 1000BASE-T from RP5 for node A L2 board) 1x 1000BASE-T from RP6 for node B 8x GPIO to P3 for node A 8x GPIO to P4, P6 for node B Table 2-2: VPX6200-RL1 RTM Specifications Note: Specifications are subject to change without prior notice. Specifications...
  • Page 23 • 2x RJ45 (4 lanes MDI from BTB connector) • 16 LEDs ( 8 LEDs controlled by Node A EC, 8 LEDs controlled by Node B EC) Power • Power provided from VPX6200-RL1 as LED power source 3.3V Environmental • Operating Temp. -40°C to +85°C •...
  • Page 24 152.38 W 114.95 W Windows 10 x64, Max. Mode 154.35 W 135.42 W Table 2-4: VPX6200 Power Consumption Notes:  The system set to idle mode and stays idle for 10 minutes.  Run BurnInTest™ that includes CPU, memory, video and 2D/3- graphics.
  • Page 25 Node B Node A DDR4-3200 with ECC Node B DDR4-3200 Node A with ECC Node A Node B M.2 M-Key Node B Node A IPMC Node B DB-30 DB-30 Debug Debug Figure 3-1: VPX6200 Board Layout - Top View Board Interfaces...
  • Page 26 Leading EDGE COMPUTING Node B Super I/O Node A Super I/O Node A DDR4-3200 with ECC Node B DDR4-3200 with ECC Node B Node A Reset Button Reset Button Status LEDs Figure 3-2: VPX6200 Board Layout - Bottom View Board Interfaces...
  • Page 27 LED17 LED4 LED2 LED11 LED8 LED6 LED15 LED21 LED18 LED12 LED20 Figure 3-3: VPX6200 Status LEDs - Front Side Location Color Description NALED10 Green Node A System On Status NALED11 Yellow Node A SATA ACT Status NALED9 Node A EC Status...
  • Page 28 Node B SATA ACT Status NBLED16 Green Node B System On Status Table 3-1: VPX6200 Status LEDs - Front Side *IPMC WDT Status LED  LED on indicates a single board issue (either Node A or Node B has failed) ...
  • Page 29 VPX6200 LED6701 LED5401 LED5402 LED5403 LED5404 LED14401 LED13101 LED13102 LED13104 LED13103 Figure 3-4: VPX6200 Status LEDs - Top Side Location Color Description LED6701 Node A Heater status LED5401 Green Node A X710 10G Link Status LED5402 Blue Node A X710 Activity Status...
  • Page 30 Leading EDGE COMPUTING 3.2 VPX6200 Front Panel LEDs Figure 3-5: VPX6200 Front Panel LEDs - Front Side VPX6200 System on Status LED Figure 3-6: VPX6200 System on Status LED Location Color Description System on Green On/off when platform reset desserts/asserts.
  • Page 31 VPX6200 VPX6200 Storage Status LED Figure 3-7: VPX6200 Storage Status LED Location Color Description Storage Yellow Blinks when storage is active. Status Table 3-4: VPX6200 Storage Status LED VPX6200 EC Status LED Figure 3-8: VPX6200 EC Status LED Location Color...
  • Page 32 Leading EDGE COMPUTING S5 to S0 mode, PCH PMC_SLP_S3_N didn’t NO_SLP_S3 assertion. S0 mode, EC didn’t reserve BIOS alive command and indicated BIOS fail. If select Failsafe BIOS, EC will switch to the second BIOS_FAIL BIOS for 3rd boot when the module is booted for the two time in first BIOS without reserved BIOS alive command.
  • Page 33 S5 to S0 mode, The last voltage (Before NO_PCH_PG RSMRST) no work Table 3-6: EC Status LED Indication VPX6200 Port 80h Status LED Figure 3-9: VPX6200 Port 80h Status LED Location Color Description Table 3-7: VPX6200 Port 80h Status LED...
  • Page 34 Port 80h Each node has 8 LEDs (Bit 0 to Bit 7) indicating its Yellow Status Port 80h status (see BIOS manual). Table 3-7: VPX6200 Port 80h Status LED VPX6200 IPMC WDT LED Figure 3-10: VPX6200 IPMC WDT LED Location Color Description ...
  • Page 35 PWR BTN Debug 10-pin RST BTN PWR&PXE LED IPMB JTAG Node AB Node B Node A SATA SATA COM2 Figure 3-11: VPX6200-RL1 RTM Board Layout - Top View Utility Signals Switch NA_COM2 Switch NB_COM2 Switch Node B IPMB NB_COM1 BIOS...
  • Page 36 NB HDMI NA HDMI NB USB NA USB NB COM NA COM SATA SATA RJ45 RJ45 Figure 3-13: VPX6200-RL1 RTM Board Layout - Front View VPX6200-RL1 Status LEDs PWR&PXE LED Figure 3-14: VPX6200-RL1 Status LEDs Location Color Description PWRLED1 Green...
  • Page 37 PWR BTN Debug 10-pin RST BTN PWR&PXE LED IPMB JTAG Node AB Node B Node A SATA SATA COM2 Figure 3-15: VPX6200-RL1 RTM Board Layout - Top View Utility Signals Switch NA_COM2 Switch NB_COM2 Switch Node B IPMB NB_COM1 BIOS...
  • Page 38 NB HDMI NA HDMI NB USB NA USB NB COM NA COM SATA SATA RJ45 RJ45 Figure 3-17: VPX6200-RL1 RTM Board Layout - Front View VPX6200-RL1 Status LEDs PWR&PXE LED Figure 3-18: VPX6200-RL1 Status LEDs Location Color Description PWRLED1 Green...
  • Page 39 VPX6200 3.5 VPX6200-RL2 RTM Board Layout GPIO_CN1 NA GPIO NB GPIO LED Figure 3-19: VPX6200-RL2 RTM Board Layout - Top View NB 1G RJ45 NA 1G RJ45 Board to Board CONN Figure 3-20: VPX6200-RL2 RTM Board Layout - Front View...
  • Page 40 Figure 3-21: VPX6200-RL2 Status LEDs Location Color Description NA EC GPIO0 Green Node A LED function when using VPX6200 NA EC GPIO1 Green Node A LED function when using VPX6200 NA EC GPIO2 Green Node A LED function when using VPX6200...
  • Page 41 VPX6200 Location Color Description NB EC GPIO13 Yellow Node B LED function when using VPX6200 NB EC GPIO14 Yellow Node B LED function when using VPX6200 NB EC GPIO15 Yellow Node B LED function when using VPX6200 Table 3-11: VPX6200-RL2 Status LEDs...
  • Page 42 Leading EDGE COMPUTING 3.6 VPX6200 Onboard Connector Pin Assignments M.2 2242 M-Key Connector (Node A: NAM2_1; Node B: NBM2_1) Signal Signal P_+3V3 P_+3V3 PCH_PCIE20_RX_R_N PCH_PCIE20_RX_R_P PCH_PCIE20_TX_C_N P_+3V3 PCH_PCIE20_TX_C_P P_+3V3 P_+3V3 PCH_PCIE19_RX_R_N P_+3V3 PCH_PCIE19_RX_R_P PCH_PCIE19_TX_C_N PCH_PCIE19_TX_C_P PCH_PCIE18_RX_R_N PCH_PCIE18_RX_R_P PCH_PCIE18_TX_C_N DEVSLP_M2_CON PCH_PCIE18_TX_C_P...
  • Page 43 VPX6200 Signal Signal PCH_PCIE17_SATA4_TX_ M2_RST-L CLK_REQ_M2_R-L C_PCIECLK2_100M_N C_PCIECLK2_100M_P M2TYPE_PEDET P3V3 P3V3 P3V3 DB30 Debug Connector (Node A: NAECN1; Node B: NBAECN3) Pin # DB30 Signal Name Pin # DB30 Signal Name EC_DB_UART_RX1 EC_DB_UART_TX1 EC_STATUS-L CN_CB_PWROK CN_RSTBTN-L CN_PWRBTN-L EC_SMB_CLK_A EC_SMB_DAT_A DB30_GND...
  • Page 44 Leading EDGE COMPUTING DB30_SPI_CS0-L P_+3V3_SPI_A Board Interfaces...
  • Page 45 VPX6200 3.7 VPX6200 VPX Connector Pin Assignments P0 Connector Pin Assignment P_+12V_PSU P_+12V_PS P_+12V_PS P_+12V_PSU P_+12V_PSU P_+12V_PSU No PAD U_P0 U_P0 P_+12V_PSU P_+12V_PS P_+12V_PS P_+12V_PSU P_+12V_PSU P_+12V_PSU No PAD U_P0 U_P0 P_+5V_PSU_ P_+5V_PS P_+5V_PSU P_+5V_PSU_ P_+5V_PSU_ P_+5V_PSU_ No PAD U_P0...
  • Page 46 Leading EDGE COMPUTING Signal Description PU/PD Comment Primary power supply input: +12V nominal. All available P_+12V_PSU_P0 Power P_+12V_PSU_P0 pins on the connector(s) shall be used. Primary power supply input: +12V nominal. All available P_+12V_PSU_P0 Power P_+12V_PSU_P0 pins on the connector(s) shall be used. Primary power supply input: +12V nominal.
  • Page 47 PCIe Switch PEX8750 JTAG Test PEX_TMS I 3.3VA Mode Select PCIe Switch PEX8750 JTAG PEX_TRST-L Test Reset 3.3VA The VPX6200 generates 220ohm to P0_RST-L SYSREST# when it is configured 3.3VA P_+3V3_A as System Controller The state of this signal is shown in...
  • Page 48 Leading EDGE COMPUTING Signal Description PU/PD Comment The settings of the Pins allocated PU 4.7K to for system-wide geographical I 3.3VA P_+3V3_A addressing input. The settings of the Pins allocated PU 4.7K to for system-wide geographical I 3.3VA P_+3V3_A addressing input. The settings of the Pins allocated PU 4.7K to for system-wide geographical...
  • Page 49 VPX6200 P1 Connector Pin Assignment VPX6200 - P1 (Project 1 KX SKU by BOM option) *X710 FW sets to KX 1 NA_10G_RX0_L0_C_P NA_10G_RX0_L0_C_N NA_10G_TX0_L0_P NA_10G_TX0_L0_N GDiscrete1# NA_10G_RX0_L1_C_P NA_10G_RX0_L1_C_N NA_10G_TX0_L1_P NA_10G_TX0_L1_N NA_10G_RX0_L2_C_P NA_10G_RX0_L2_C_N NA_10G_TX0_L2_R_ NA_10G_TX0_L2_R_ P_+VBAT NA_10G_RX0_L3_C_P NA_10G_RX0_L3_C_N NA_10G_TX0_L3_P NA_10G_TX0_L3_N NB_10G_RX0_L0_C_P NB_10G_RX0_L0_C_N...
  • Page 50 0 Data Plane, Node B, 10GBASE-KX4 Ethernet channel NB_10G_RX1_L3_ AC coupled 10nF on 2 receive positive differential pairs I KX4 VPX6200 10GBASE-KX4 Ethernet channel Data Plane, Node B, NB_10G_RX1_L3_ 2 receive negative differential pairs I KX4 AC coupled 10nF on...
  • Page 51 Data Plane, Node B, 10GBASE-KX4 Ethernet channel NB_10G_RX0_L0_ I KX4/ AC coupled 10nF on 1 receive positive differential pairs VPX6200, co-lay for KR Data Plane, Node B, 10GBASE-KX4 Ethernet channel NB_10G_RX0_L0_ I KX4/ AC coupled 10nF on 1 receive negative differential pairs...
  • Page 52 0 10GBASE-KX4 Ethernet channel Data Plane, Node A, NA_10G_RX1_L3_ I KX4 2 receive positive differential pairs AC coupled 10nF on VPX6200 10GBASE-KX4 Ethernet channel Data Plane, Node A, NA_10G_RX1_L3_ 2 receive negative differential pairs I KX4 AC coupled 10nF on...
  • Page 53 Data Plane, Node A, 10GBASE-KX4 Ethernet channel NA_10G_RX0_L2_ I KX4/ AC coupled 10nF on 1 receive positive differential pairs VPX6200, co-lay for KR Data Plane, Node A, 10GBASE-KX4 Ethernet channel NA_10G_RX0_L2_ I KX4/ AC coupled 10nF on 1 receive negative differential pairs...
  • Page 54 I 3.3VA P_+3V3_A from backplane time Maskable Reset. Pulling this input low for a hard reset to the PU 4.7K to MASK_RESET_R-L VPX6200. This pin can also be I 3.3VA P_+3V3_A driven by the VPX6200 via the IPMC Ground Ground Ground...
  • Page 55 VPX6200 Signal Description PU/PD Comment Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground No connection Board Interfaces...
  • Page 56 Leading EDGE COMPUTING P2 Connector Pin Assignment PCIE_SW_Port PCIE_SW_Port PCIE_ SW_Port4 PCIE_SW_Port S2_PWR_EN 4_RXP16_P2 4_RXN16_P2 _TXP16_P2 4_TXN16_P2 PCIE_SW_Port PCIE_SW_Port PCIE_SW_Port PCIE_SW_Port 4_RXP17_P2 4_RXN17_P2 4_TXP17_P2 4_TXN17_P2 PCIE_SW_Port PCIE_SW_Port PCIE_SW_Port4 PCIE_SW_Port S2_PWR_OK 4_RXP18_P2 4_RXN18_P2 _TXP18_P2 4_TXN18_P2 PCIE_SW_Port PCIE_SW_Port PCIE_SW_Port PCIE_SW_Port 4_RXP19_P2 4_RXN19_P2 4_TXP19_P2 4_TXN19_P2 PCIE_SW_Port...
  • Page 57 VPX6200 Signal Description PU/PD Comment PLX8750 PCI Express port1 PCIE_SW_PORT1_ channel 9, Receive Input positive I PCIE RXP9_P2 differential pair PLX8750 PCI Express port1 PCIE_SW_PORT1_ channel 9, Receive Input negative I PCIE RXN9_P2 differential pair PLX8750 PCI Express port1 PCIE_SW_PORT1_...
  • Page 58 Leading EDGE COMPUTING Signal Description PU/PD Comment PLX8750 PCI Express port4 PCIE_SW_PORT4_ channel 17, Receive Input positive I PCIE RXP17_P2 differential pair PLX8750 PCI Express port4 PCIE_SW_PORT4_ channel 17, Receive Input I PCIE RXN17_P2 negative differential pair PLX8750 PCI Express port4 PCIE_SW_PORT4_ channel 18, Receive Input positive I PCIE...
  • Page 59 VPX6200 Signal Description PU/PD Comment PLX8750 PCI Express port4 PCIE_SW_PORT4_ channel 17, Transmit Output TXP17_P2 PCIE positive differential pair PLX8750 PCI Express port4 PCIE_SW_PORT4_ channel 17, Transmit Output TXN17_P2 PCIE negative differential pair PLX8750 PCI Express port4 PCIE_SW_PORT4_ channel 18, Transmit Output...
  • Page 60 I PCIE RXN27_P2 negative differential pair PLX8750 PCI Express port5 PCIE_SW_PORT5_ AC coupled 220nF on channel 24, Transmit Output TXP24_P2 PCIE VPX6200 positive differential pair PLX8750 PCI Express port5 PCIE_SW_PORT5_ AC coupled 220nF on channel 24, Transmit Output TXN24_P2 PCIE VPX6200...
  • Page 61 VPX6200 Signal Description PU/PD Comment Serial COM port 0 Receive Data IPMI_DEB_RX Source IPMC UART signal for IPMC debugging CMOS Serial COM port 0 Transmit Data IPMI_DEB_TX Source IPMC UART signal for IPMC debugging CMOS Input Pin: Slot 2 Power enable signals.
  • Page 62 Leading EDGE COMPUTING Signal Description PU/PD Comment Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Board Interfaces...
  • Page 63 VPX6200 P3 Connector Pin Assignment VPX6200 - P3 (Project 1 KX SKU by BOM option) NA_PCH_PCIE1 NA_PCH_PCIE1 NA_PCH_PCIE1 NA_PCH_PCIE1 NA_EC_GPIO3 3_RX_P 3_RX_N 3_C_TX_P 3_C_TX_N NA_PCH_PCIE1 NA_PCH_PCIE1 NA_PCH_PCIE1 NA_PCH_PCIE1 4_RX_P 4_RX_N 4_C_TX_P 4_C_TX_N NA_USB3_1_RX NA_USB3_1_RX NA_USB3_1_TX NA_USB3_1_TX NA_EC_GPIO1 NA_PCIE_CLK_1 NA_PCIE_CLK_1 NA_RTM_BOOT...
  • Page 64 I PCIE RXN12_P3 negative differential pair PLX8750 PCI Express port1 PCIE_SW_PORT1_ AC coupled 220nF on channel 12, Transmit Output PCIE TXP12_P3 VPX6200 positive differential pair PLX8750 PCI Express port1 PCIE_SW_PORT1_ AC coupled 220nF on channel 12, Transmit Output PCIE TXN12_P3 VPX6200...
  • Page 65 PCIE VPX6200 negative differential pair PLX8750 PCI Express port5 AC coupled 220nF on PCIE_SW_P5_R_T channel 29, Transmit Output VPX6200, KX4 no XP29 PCIE positive differential pair used, KR is P5 lane 29 AC coupled 220nF on PLX8750 PCI Express port5...
  • Page 66 PU/PD Comment PCH PCI Express port13 channel NA_PCH_PCIE14_ Node A, AC coupled 14, Transmit Output positive C_TX_P PCIE 220nF on VPX6200 differential pair PCH PCI Express port13 channel NA_PCH_PCIE14_ Node A, AC coupled 14, Transmit Output negative C_TX_N PCIE 220nF on VPX6200...
  • Page 67 VPX6200 Signal Description PU/PD Comment PU 10k to Data in to module from carrier NA_SPI_MISO I 3.3VA P_+3V3_S Source Node A board SPI BIOS flash PI_A Data out from module to carrier NA_SPI_MOSI Source Node A board SPI BIOS flash 3.3VA...
  • Page 68 Leading EDGE COMPUTING Signal Description PU/PD Comment Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground F115 Ground Ground Ground Ground Ground Ground Ground Ground Ground No Connection No Connection No Connection No Connection...
  • Page 69 VPX6200 Signal Description PU/PD Comment No Connection No Connection P4 Connector Pin Assignment VPX6200 - P4 (Project 1 KX Sku by BOM option) NB_PCH_PCIE13_RX NB_PCH_PCIE13_RX NB_PCH_PCIE13_C_ NB_PCH_PCIE13_C_ NB_EC_GPIO0 TX_P TX_N NB_PCH_PCIE14_RX NB_PCH_PCIE14_RX NB_PCH_PCIE14_C_ NB_PCH_PCIE14_C_ TX_P TX_N NB_USB3_1_RXP NB_USB3_1_RXN NB_USB3_1_TXP NB_USB3_1_TXN...
  • Page 70 For KR SKU is AC PLX8750 PCI Express port1 PCIE_SW_P1_R_T coupled 220nF on channel 13, Transmit Output XP13 PCIE VPX6200, KX4 SKU is positive differential pair not used For KR SKU is AC PLX8750 PCI Express port1 coupled 220nF on PCIE_SW_P1_R_T...
  • Page 71 NA_1GKX_RX_P3_ 1000BASE-KX Ethernet channel 3 Node A, AC coupled I KX receive negative differential pairs 4.7nF on VPX6200 NA_1GKX_RX_P3_ 1000BASE-KX Ethernet channel 3 Node A, AC coupled I KX receive positive differential pairs 4.7nF on VPX6200...
  • Page 72 NB_1GKX_RX_P3_ 1000BASE-KX Ethernet channel 3 Node B, AC coupled I KX receive negative differential pairs 4.7nF on VPX6200 1000BASE-KX Ethernet channel NB_1GKX_RX_P3_ Node B, AC coupled 3 receive positive differential I KX 4.7nF on VPX6200 pairs...
  • Page 73 PU/PD Comment NB_SATA_3_C_TX Serial ATA channel 3, Transmit Node B, AC coupled Output positive differential pair SATA 10nF on VPX6200 NB_SATA_3_C_TX Serial ATA channel 3, Transmit Node B, AC coupled Output negative differential pair SATA 10nF on VPX6200 Clock from module to carrier board...
  • Page 74 Leading EDGE COMPUTING Signal Description PU/PD Comment General Purpose Input/Output NB_EC_GPIO4 Source Node B EC signal 0 3.3VA General Purpose Input/Output NB_EC_GPIO5 Source Node B EC signal 4 3.3VA Source Node B EC, For General Purpose Input/Output KX4 SKU, KR SKU is NB_EC_GPIO6_R signal 5 3.3VA...
  • Page 75 VPX6200 Signal Description PU/PD Comment Ground Ground Ground Ground Ground Ground Ground Ground Ground No Connection No Connection No Connection No Connection No Connection No Connection Board Interfaces...
  • Page 76 Leading EDGE COMPUTING P5 Connector Pin Assignment P_+5V_NAUSBP NA_USB2P_1 NA_USB2N_1 NA_USB2P_2 NA_USB2N_2 NA_USB2P_3 NA_USB2N_3 NA_USB2P_4 NA_USB2N_4 NA_COM1_RTS NA_COM1_TXD NA_COM1_CTS NA_COM1_RXD P_+5V_NAUSBP /TXP /TXN /RXP /RXN NA_COM2_RTS NA_COM2_TXD NA_COM2_CTS NA_COM2_RXD /TXP /TXN /RXP /RXN NA_SATA_1_RX NA_SATA_1_RX NA_SATA_1_TX NA_SATA_1_TX P_+5V_NAUSBP P_P5 N_P5 P_P5 N_P5 NA_SATA_2_RX...
  • Page 77 NA_1GKX_RX_P4_ 1000BASE-KX Ethernet channel 4 Node A, AC coupled I KX receive negative differential pair 4.7nF on VPX6200 NA_1GKX_RX_P4_ 1000BASE-KX Ethernet channel 4 Node A, AC coupled I KX receive positive differential pair 4.7nF on VPX6200 NA_1GKX_TX_P4_...
  • Page 78 ±3V to ±25V negative signal (RS-422 mode) NA_SATA_1_RXP_ Serial ATA channel 1, Receive Node A, AC coupled Input positive differential pair 10nF on VPX6200 NA_SATA_1_RXN_ Serial ATA channel 1, Receive Node A, AC coupled Input negative differential pair 10nF on VPX6200...
  • Page 79 VPX6200 Signal Description PU/PD Comment NA_TMDS_DATA1_ TMDS Datal 1 negative differential Node A pair NA_TMDS_DATA1_ TMDS Datal 1 positive differential Node A pair NA_TMDS_DATA2_ TMDS Datal 2 negative differential Node A pair NA_TMDS_DATA2_ TMDS Datal 2 positive differential Node A...
  • Page 80 Leading EDGE COMPUTING Signal Description PU/PD Comment Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground F115 Ground Ground Ground Ground Ground...
  • Page 81 VPX6200 Signal Description PU/PD Comment Ground Ground No connection No connection No connection No connection No connection No connection No connection No connection No connection No connection Board Interfaces...
  • Page 82 Leading EDGE COMPUTING P6 Connector Pin Assignment P_+5V_NBUSB NB_USB2P_1 NB_USB2N_1 NB_USB2P_2 NB_USB2N_2 PWR1 NB_USB2P_3 NB_USB2N_3 NB_USB2P_4 NB_USB2N_4 NB_COM1_RT NB_COM1_TX NB_COM1_CT NB_COM1_RX P_+5V_NBUSB S/TXP D/TXN S/RXP D/RXN PWR2 NB_COM2_RT NB_COM2_TX NB_COM2_CT NB_COM2_RX S/TXP D/TXN S/RXP D/RXN NB_SATA_1_R NB_SATA_1_R NB_SATA_1_T NB_SATA_1_T P_+5V_NBUSB XP_P6 XN_P6 XP_P6...
  • Page 83 NB_1GKX_RX_P4_ 1000BASE-KX Ethernet channel 4 Node B, AC coupled I KX receive negative differential pair 4.7nF on VPX6200 NB_1GKX_RX_P4_ 1000BASE-KX Ethernet channel 4 Node B, AC coupled I KX receive positive differential pair 4.7nF on VPX6200 NB_1GKX_TX_P4_...
  • Page 84 (RS-422 mode) NB_SATA_1_RXP_ Serial ATA channel 1, Receive Node B, AC coupled I SATA Input positive differential pair 10nF on VPX6200 NB_SATA_1_RXN_ Serial ATA channel 1, Receive Node B, AC coupled I SATA Input negative differential pair 10nF on VPX6200...
  • Page 85 VPX6200 Signal Description PU/PD Comment TMDS clock positive differential NB_TMDS_CLK_P Node B pair TMDS General purpose I²C port clock I/O OD PU 2.2k o NB_HDMI_SCL_P6 Node B output/input of HDMI DDC P_+5V General purpose I²C port data I/O I/O OD PU 2.2k to...
  • Page 86 Leading EDGE COMPUTING Signal Description PU/PD Comment Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground F115 Ground Ground Ground Ground Ground Ground Ground Ground Ground No connection No connection No connection No connection No connection...
  • Page 87 VPX6200 Signal Description PU/PD Comment No connection No connection No connection No connection No connection No connection No connection No connection No connection Board Interfaces...
  • Page 88 Leading EDGE COMPUTING 3.8 VPX6200-RL1 RTM Onboard Connector Pin Assignments HDMI Connector Pin # Signal Pin # Signal TMDS Data2+ TMDS Data2 Shield TMDS Data2– TMDS Data1+ TMDS Data1 Shield TMDS Data1– TMDS Data0+ TMDS Data0 Shield TMDS Data0– TMDS Clock+ TMDS Clock Shield TMDS Clock–...
  • Page 89 VPX6200 RJ-45 Gigabit Ethernet Connectors (CN9 and CN10) Pin # 1000BASE-T BI_DA+ BI_DA- BI_DB+ BI_DC+ BI_DC- BI_DB- BI_DD+ BI_DD- USB 2.0 Pin Header for Node A Pin # Signal Name Pin # Signal Name P_+5V_NAUSBP P_+5V_NAUSBP NA_USB2_D3_N NA_USB2_D4_N NA_USB2_D3_P NA_USB2_D4_P USB 2.0 Pin Header for Node B...
  • Page 90 Leading EDGE COMPUTING SATA 7-pin Connector Pin # Signal COM DB9 Connector for Node A Signal Signal NA_COM1_PIN1 NA_COM1_PIN6 NA_COM1_RXD/RXN NA_COM1_RTS/TXP NA_COM1_TXD/TXN NA_COM1_CTS/RXP NA_COM1_PIN4 NA_COM1_PIN9 COM DB9 Connector for Node B Signal Signal NB_COM1_PIN1 NB_COM1_PIN6 NB_COM1_RXD/RXN NB_COM1_RTS/TXP NB_COM1_TXD/TXN NB_COM1_CTS/RXP NB_COM1_PIN4 NB_COM1_PIN9 Board Interfaces...
  • Page 91 VPX6200 COM2 Pin Header for Node A & B Signal Signal NA_COM2_RTS/TXP NB_COM2_RTS/TXP NA_COM2_TXD/TXN NB_COM2_TXD/TXN NA_COM2_RXD/RXN NB_COM2_RXD/RXN NA_COM2_CTS/RXP NB_COM2_CTS/RXP COM1_CH_GND VPX IPMC JTAG Debug Port Signal Signal IPMB_JTCK IPMB_JTDO P_+3V3_RTM IPMB_JTMS IPMB_JTRST-L P_+3V3_RTM IPMB_JTDI VPX PCIe Switch JTAG Debug Port...
  • Page 92 Leading EDGE COMPUTING Debug 6-pin Connector Signal Signal PEX_I2C_SCL0 IPMI_PRG_RX IPMI_PRG_TX PEX_I2C_SDA0 Debug 10-pin Connector Signal Signal S1_PWR_OK S1_PWR_EN S2_PWR_OK S3_PWR_EN S2_PWR_EN 3_PWR_OK M.2 2242 B-Key Connector for Node A & B (Node A: NAM2_1; Node B: NBM2_1) Signal Name Signal Name P_+3V3 P_+3V3...
  • Page 93 VPX6200 Signal Name Signal Name NA_PCH_PCIE14_TX_P NA_PCH_PCIE13_RX_N NA_PCH_PCIE13_RX_P NA_PCH_PCIE13_TX_N NA_PCH_PCIE13_TX_P NA_PERST-L P_+3V3_RTM P_+3V3_RTM P_+3V3_RTM Board Interfaces...
  • Page 94 Leading EDGE COMPUTING 3.9 VPX6200-RL1 RTM VPX Connector Pin Assign- ments RP0 Connector Pin Assignment VPX6200-RL1 - RP10 (Project 1 KX SKU by BOM option) No Wafer P_+12V_PSU P_+12V_PSU P_+12V_PSU P_+12V_PSU P_+12V_PSU P_+12V_PSU P_+5V_PSU P_+5V_PSU P_+5V_PSU P_+5V_PSU P_+5V_PSU P_+5V_PSU NVMRO...
  • Page 95 VPX6200 RP1 Connector Pin Assignment NA_10G_RX1_L0_P NA_10G_RX1_L0_N NA_10G_TX1_L0_P NA_10G_TX1_L0_N BP_PWRBTN-L NA_10G_RX1_L1_P NA_10G_RX1_L1_N NA_10G_TX1_L1_P NA_10G_TX1_L1_N NA_10G_RX1_L2_P NA_10G_RX1_L2_N NA_10G_TX1_L2_P NA_10G_TX1_L2_N S1_PWR_EN NA_10G_RX1_L3_P NA_10G_RX1_L3_N NA_10G_TX1_L3_P NA_10G_TX1_L3_N NB_10G_RX1_L0_P NB_10G_RX1_L0_N NB_10G_TX1_L0_P NB_10G_TX1_L0_N S1_PWR_OK NB_10G_RX1_L1_P NB_10G_RX1_L1_N NB_10G_TX1_L1_P NB_10G_TX1_L1_N NB_10G_RX1_L2_P NB_10G_RX1_L2_N NB_10G_TX1_L2_P NB_10G_TX1_L2_N MASK_RESET-L NB_10G_RX1_L3_P NB_10G_RX1_L3_N NB_10G_TX1_L3_P NB_10G_TX1_L3_N...
  • Page 96 Leading EDGE COMPUTING RP3 Connector Pin Assignment VPX6200-RL1 - RP13 (Project 1 KX SKU by BOM option) NA_PCH_PCIE13_RX_PNA_PCH_PCIE13_RX_N NA_PCH_PCIE13_TX_P NA_PCH_PCIE13_TX_N NA_EC_GPIO3 NA_PCH_PCIE14_RX_PNA_PCH_PCIE14_RX_N NA_PCH_PCIE14_TX_P NA_PCH_PCIE14_TX_N NA_USB3_1_RXP NA_USB3_1_RXN NA_USB3_1_TXP NA_USB3_1_TXN NA_EC_GPIO1 NA_PCIE_CLK_100M_PNA_PCIE_CLK_100M_N NA_RTM_BOOT# NA_EXT_NODE_RST# NA_SPI_MISO NA_SPI_CS2-L NA_SPI_MOSI NA_SPI_CLK NA_EC_GPIO2 PCIE_SW_P5_RXP28 PCIE_SW_P5_RXN28 PCIE_SW_P5_TXP28...
  • Page 97 VPX6200 RP4 Connector Pin Assignment VPX6200-RL1 - RP14 (Project 1 KX SKU by BOM option) 1 NB_PCH_PCIE13_RX_PNB_PCH_PCIE13_RX_N NB_PCH_PCIE13_TX_P NB_PCH_PCIE13_TX_N NB_EC_GPIO0 NB_PCH_PCIE14_RX_P NB_PCH_PCIE14_RX_N NB_PCH_PCIE14_TX_P NB_PCH_PCIE14_TX_N NB_USB3_1_RXP NB_USB3_1_RXN NB_USB3_1_TXP NB_USB3_1_TXN NB_EC_GPIO1 NB_PCIE_CLK_100M_P NB_PCIE_CLK_100M_N NB_EXT_NODE_RST-L NB_SPI_MISO NB_SPI_CS2-L NB_SPI_MOSI NB_SPI_CLK NB_EC_GPIO2 PCIE_SW_P1_RXP13 PCIE_SW_P1_RXN13 PCIE_SW_P1_TXP14...
  • Page 98 Leading EDGE COMPUTING RP5 Connector Pin Assignment NA_USB2P_1 NA_USB2N_1 NA_USB2P_2 NA_USB2N_2 P_+5V_NAUSBPWR1 NA_USB2P_3 NA_USB2N_3 NA_USB2P_4 NA_USB2N_4 NA_COM1_RTS/T NA_COM1_TXD/T NA_COM1_CTS/R NA_COM1_RXD/ P_+5V_NAUSBPWR2 NA_COM2_RTS/T NA_COM2_TXD/TX NA_COM2_CTS/R NA_COM2_RXD/RX NA_SATA_1_RXP NA_SATA_1_RXN NA_SATA_1_TXP NA_SATA_1_TXN P_+5V_NAUSBPWR3 NA_SATA_2_RXP NA_SATA_2_RXN NA_SATA_2_TXP NA_SATA_2_TXN NA_1G_P2_MDI0 NA_1G_P2_MDI0 NA_1G_P2_MDI1 NA_1G_P2_MDI1 P_+5V_NAUSBPWR4 NA_1G_P2_MDI2P NA_1G_P2_MDI2N NA_1G_P2_MDI3 NA_1G_P2_MDI3N 9 PCIE_SW_P1_RXP PCIE_SW_P1_RXN NA_BP_PWRBTN-...
  • Page 99 VPX6200 RP6 Connector Pin Assignment NB_USB2P_1 NB_USB2N_1 NB_USB2P_2 NB_USB2N_2 P_+5V_NBUSBPWR1 NB_USB2P_3 NB_USB2N_3 NB_USB2P_4 NB_USB2N_4 NB_COM1_RTS/ NB_COM1_TXD/T NB_COM1_CTS/RX NB_COM1_RXD/ P_+5V_NBUSBPWR2 NB_COM2_RTS/T NB_COM2_TXD/TX NB_COM2_CTS/ NB_COM2_RXD/ 5 NB_SATA_1_RXP NB_SATA_1_RXN NB_SATA_1_TXP NB_SATA_1_TXN P_+5V_NBUSBPWR3 NB_SATA_2_RXP NB_SATA_2_RXN NB_SATA_2_TXP NB_SATA_2_TXN NB_1G_P2_MDI NB_1G_P2_MDI0 NB_1G_P2_MDI1 NB_1G_P2_MDI1P P_+5V_NBUSBPWR4 NB_1G_P2_MDI2 NB_1G_P2_MDI3...
  • Page 100 Leading EDGE COMPUTING 3.10 VPX6200-RL1 RTM Switches Utility Signals Switch UT_SW1 GA Slot No. Direction Mode NVMRO Write Enable NVMRO Write Protect System Controller Non System Controller Reserved Board Interfaces...
  • Page 101 VPX6200 RS232/RS422 Termination Switch (Node A/B COM1/2) Direction Mode Add 120 ohm Termination Resistor No Termination Resistor IPMB Source Selection Switch Signal Signal IPMBA_CLK IPMB_SCL IPMBA_DAT IPMB_SDA IPMBB_CLK IPMB_SCL IPMBB_DAT IPMB_SDA BIOS Source Selection Switch 1 for Node A 2 for Node A...
  • Page 102 Leading EDGE COMPUTING 3.11 VPX6200-RL2 Onboard Connectors RJ-45 Gigabit Ethernet Connectors Pin # 1000BASE-T BI_DA+ BI_DA- BI_DB+ BI_DC+ BI_DC- BI_DB- BI_DD+ BI_DD- GPIO_CN1 Connector Signal Signal NB_EC_GPIO7 NB_EC_GPIO6 NB_EC_GPIO5 NB_EC_GPIO4 NB_EC_GPIO3 NB_EC_GPIO2 NB_EC_GPIO1 NB_EC_GPIO0 NA_EC_GPIO7 NA_EC_GPIO6 NA_EC_GPIO5 NA_EC_GPIO4 NA_EC_GPIO3 NA_EC_GPIO2...
  • Page 103 VPX6200 Getting Started This chapter describes the installation of the and VPX6200 blade and VPX6200-RL1 rear transition module. 4.1 Installing the VPX6200 to the Chassis These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.
  • Page 104 Leading EDGE COMPUTING 4.3 Driver Installation The VPX6200 drivers are available from the ADLINK website (www.adlinktech.com). ADLINK provides validated chipset, graphics and LAN drivers for Windows 10. Follow the steps below to install the drivers for Windows 10 64-bit. 1. Install the Windows operating system before installing any driver.
  • Page 105 1. Connect RTM board and Motherboard to the backboard (ex. RTM board and Motherboard are connected to the 2nd slot of backboard in VPX6200). The Microsemi JTAG cable is connected to RTM board in VPX6200. 2. Launch FlashPro and click “New Project” to create a new project.
  • Page 106 1. Prepare a bootable USB flash drive by saving F.nsh, ifu.efi and VPX6200_ADLINK_XXX.bin into an empty USB drive using a flashing tool such as Rufus. 2. Insert the USB drive to the USB port of VPX6200. 3. Power on VPX6200. 4. Enter BIOS Setup Menu and check Secure Boot Control is set to “Disable”, if not, please change it and save...
  • Page 107 VPX6200 Flashing EC Firmware using ITEDLB4-Board Follow the steps below to flash the EC firmware using ITEDLB4-Board. 1. Prepare the following:  an ITEDLB4 board  an ADLINK DB30 board  a USB A to B cable  a 30-pin x0.5_FFC cable ...
  • Page 108 5. Connect the ITEDLB4 board to a host PC, and connect the ADLINK DB30 board to the VPX6200 using an FFC cable. 6. Turn off the VPX6200, then press the DIP switch to power on the ITEDLB4 board. The host PC shall detect a “Download Board 4”...
  • Page 109 SEMA GitHub page: https://adlinktech.github.io/sema/index.html 5.2 Watchdog Timer The VPX6200’s watchdog timer (WDT) is implemented by SEMA. For detailed information on how to program the WDT, refer to the SEMA user’s manual WDT section on the SEMA GitHub page: https://adlinktech.github.io/sema/WatchDog.html#sysfs-In...
  • Page 110 Leading EDGE COMPUTING This page intentionally left blank. Utilities...
  • Page 111 VPX6200 Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.  Read these safety instructions carefully.  Keep this user’s manual for future reference.
  • Page 112 Leading EDGE COMPUTING  Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. Risk of explosion if battery is replaced with one of an incorrect type.
  • Page 113 San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com...