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ADLINK Technology cPCI-6530BLV User Manual

Performance 6u compactpci intel core i7/i5 processor blade
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cPCI-6530BL Series
Performance 6U CompactPCI®
Intel® Core™ i7/i5 Processor Blade
User's Manual
Manual Rev.:
Revision Date:
Part Number:
Leading EDGE COMPUTING
1.0
July 12, 2018
50-15100-2000

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Summary of Contents for ADLINK Technology cPCI-6530BLV

  • Page 1 cPCI-6530BL Series Performance 6U CompactPCI® Intel® Core™ i7/i5 Processor Blade User’s Manual Manual Rev.: Revision Date: July 12, 2018 Part Number: 50-15100-2000 Leading EDGE COMPUTING...
  • Page 2 Leading EDGE COMPUTING Revision History Revision Release Date Description of Change(s) July 12, 2018 Initial release Revision History...

  • Page 3: Preface

    Preface Copyright 2018 ADLINK Technology, Inc. This document contains proprietary information protected by copy- right. All rights are reserved. No part of this manual may be repro- duced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 4 Leading EDGE COMPUTING California Proposition 65 Warning WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox- ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause...

  • Page 5: Table Of Contents

    Processors................. 13 Chipset................15 PMC/XMC................16 Intel® Turbo Boost Technology ......... 16 Intel® Hyper-Threading Technology........17 Trusted Platform Module ........... 17 Battery ................18 4 Board Interfaces ............... 19 cPCI-6530BLV Board Layout..........19 cPCI-6530BL Board Layout ..........20 Table of Contents...
  • Page 6 Leading EDGE COMPUTING cPCI-6530BL Series Front Panel........21 Connector Pin Assignments..........24 Switches and Buttons ............40 5 Getting Started ..............47 CPU and Heatsink ............. 47 mSATA Module Installation..........48 2.5" SATA Drive Installation..........49 PMC/XMC Installation............53 Installing the cPCI-6530BL to the Chassis......55 6 Driver Installation..............
  • Page 7 cPCI-6530BL 8.3.14Hardware Monitor ............91 Chipset Setup ..............92 8.4.1 System Agent (SA) Configuration........93 8.4.2 PCH-IO Configuration............ 98 Boot Settings ..............101 Security Setup ..............103 Save & Exit Menu ............104 9 Checkpoints & Beep Codes .......... 107 Checkpoint Ranges ............
  • Page 8 Leading EDGE COMPUTING This page intentionally left blank. viii Table of Contents...

  • Page 9: List Of Figures

    List of Figures Figure 2-1: cPCI-6530BL Blade Functional Block Diagram ....8 Figure 4-1: cPCI-6530BLV Series Board Layout ......19 Figure 4-2: cPCI-6530BL Series Board Layout........ 20 Figure 4-3: cPCI-6530BL Series Front Panel Layout....... 21 Figure 4-4: cPCI-6530BL Series LED Labels........23 Figure 4-5: Solder-side switch and button locations ......
  • Page 10 Leading EDGE COMPUTING This page intentionally left blank. List of Figures...

  • Page 11: List Of Tables

    cPCI-6530BL List of Tables Table 2-1: cPCI-6530BL Processor Blade Specifications....5 Table 2-2: cPCI-6530BL I/O Connectivity ......... 9 Table 4-1: cPCI-6530BL Front Panel System LED Descriptions ..22 Table 4-2: USB 2.0 Pin Definition ........... 24 Table 4-3: DVI-I Connector Pin Definition........25 Table 4-4: RJ-45 GbE Pin Definitions ..........
  • Page 12 Leading EDGE COMPUTING This page intentionally left blank. List of Tables...

  • Page 13: Introduction

    Mobile Intel® QM87 Express Chipset. The cPCI-6530BL Series is a 6U CompactPCI blade in single-slot (4HP) width form factor. Front panel I/O for the cPCI-6530BLV includes 1x DVI-I, 2x GbE and 2x USB 3.0 ports, 1x USB 2.0 port, 1x RJ-45 COM port and 1x PCI/XMC slot.

  • Page 14: Features

    CPU blade in host slot One 64-bit/33,66,133MHz PMC or PCIe x8 Gen2 XMC site on cPCI-6530BLV with rear I/O; one additional PMC/XMC site on cPCI-6530BL Supports IPMI over LAN for system health monitoring...

  • Page 15: Package Contents

    The cPCI-6530BL Series Processor Blade CPU and memory specifications will differ depending on options selected Thermal module is assembled on the board RJ-45 to DB-9 COM adapter cable (cPCI-6530BLV) 2.5” SATA drive accessory pack (cPCI-6530BLV) mSATA accessory pack Rear Transition Module...
  • Page 16 Leading EDGE COMPUTING This page intentionally left blank. Introduction...

  • Page 17: Specifications

    cPCI-6530BL Specifications 2.1 cPCI-6530BL Processor Blade Specifications CompactPCI® • PICMG® 2.0 CompactPCI® Rev. 3.0 Standards • PICMG® 2.1 Hot Swap Specification Rev. 2.0 • PICMG® 2.9 System Management Rev. 1.0 • PICMG® 2.16 Packet Switching Backplane Rev. 1.0 Mechanical • Standard 6U CompactPCI® •...
  • Page 18 3.0 for cPCI-6530BLV version PMC/XMC • One 64-bit/33,66,133 MHz PMC site or PCIe x8 Gen 2 XMC site for cPCI-6530BLV version with rear I/O • Two 64-bit/33,66,133 MHz PMC sites or PCIe x8 Gen 2 XMC sites on cPCI-6530BL version Audio •...
  • Page 19 Faceplate I/O cPCI-6530BLV (4HP) • 2x 10/100/1000BASE-T Ethernet ports • 1x DVI-I port • 2x USB 3.0 ports • 1x USB 2.0 port • 1x RJ-45 serial port • 1x PMC/XMC slot cPCI-6530BL (4HP) • 2x 10/100/1000BASE-T Ethernet ports •...

  • Page 20: Block Diagrams

    Leading EDGE COMPUTING 2.2 Block Diagrams cPCI-6530BL Blade Front Panel COM1 Intel I217 Intel ECC SO-CDIMM, max. I210 USB 3.0 7-pin USB 2.0 Soldered w/ ECC, max. 16GB BIOS PCIe x1 PCIe x1 SATA1 DDR3 1600/1067MHz ® PCIe x4 Intel QM87 PCH ®...

  • Page 21: I/O Connectivity Table

    2.3 I/O Connectivity Table cPCI-6530BLV (4HP) cPCI-6530BL (4HP) Function Faceplate Onboard Faceplate Onboard Gigabit Ethernet Y x2 – Y x2 – Y (RJ-45) – – – USB 3.0 Y x2 – Y x1 – USB 2.0 Y x1 –...

  • Page 22: Power Requirements

    Leading EDGE COMPUTING 2.4 Power Requirements In order to guarantee a stable functionality of the system, it is rec- ommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage.
  • Page 23 cPCI-6530BL Power Consumption This section provides information on the power consumption of cPCI-6530BL Series when using the Intel® Core™ i7 processors with 8GB DDR3L-1600 ECC soldered memory and 8GB DDR3L-1600 socket memory module. Storage device is used with ADLINK ASD26-MLC32G-CT 32GB SATA SSD.
  • Page 24 Leading EDGE COMPUTING This page intentionally left blank. Specifications...

  • Page 25: Functional Description

    cPCI-6530BL Functional Description The following sections describe the cPCI-6530BL Series features and functions. 3.1 Processors The Mobile 5th Generation Intel® Core™ Processor Family are state of the art, 64-bit, multi-core mobile processor built on 22 nanometer process technology. Based on a new micro-architec- ture, the processor is designed for a two-chip platform.
  • Page 26 Leading EDGE COMPUTING Supported Technologies Features Core™ i7-5850EQ Core™ i5-5700EQ Intel® Virtualization Technology for Directed I/O (Intel® VT-d) Intel® Virtualization Technology (Intel® VT-x) Intel® VT-x with Extended Page Tables (EPT) Intel® Hyper-Threading Technology Intel® 64 Architecture Execute Disable Bit Intel® Turbo Boost Technology Intel®...

  • Page 27: Chipset

    cPCI-6530BL Graphics The Intel® Graphics Engine is integrated in the processor enabling substantial gains in performance and lower power con- sumption. Intel® Core™ i7-5850EQ: Intel® Iris Pro Graphics 6200 Intel® Core™ i7-5700EQ: Intel® HD Graphics 4600 DX11.2 support OpenGL 4.3 support Graphics Base Frequency: 400 MHz Graphics Max Dynamic Frequency: 1 GHz Supports Intel®...

  • Page 28: Pmc/Xmc

    Leading EDGE COMPUTING Supports Intel® Rapid Storage Technology Supports Intel® Virtualization Technology for Directed I/O Integrated Clock Controller Analog and Digital Display ports Low Pin Count (LPC) interface Firmware Hub (FWH) interface support Serial Peripheral Interface (SPI) support 3.3 PMC/XMC The cPCI-6530BL(V) models support max two PMC or XMC sites for front panel I/O expansion.

  • Page 29: Intel® Hyper-Threading Technology

    cPCI-6530BL 3.5 Intel® Hyper-Threading Technology Intel® Hyper-Threading Technology allows an execution core to function as two logical processors. While some execution resources (such as caches, execution units, and buses) are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers.

  • Page 30: Battery

    Leading EDGE COMPUTING Physical shield in the IC to protect the die from intruding or hacking by matching the data transferred on the 2 layer metal shield on the IC. If the data is not matched, the IC may be blocked. 3.7 Battery The cPCI-6530BL is equipped with a 3.0V "coin cell"...

  • Page 31: Board Interfaces

    DVI-I connector CN11 SATA board-to-board conn. COM port in RJ-45 conn. CN12/13 USB 3.0 connector Battery socket CN14 USB 2.0 connector PCe Switch PEX8624-BB50BI JN1/2/3/4 PMC connectors U23/27 Pericom PI7C9X130 U23/27 Pericom PI7C9X130 Figure 4-1: cPCI-6530BLV Series Board Layout Board Interfaces...

  • Page 32: Cpci-6530Bl Board Layout

    Leading EDGE COMPUTING 4.2 cPCI-6530BL Board Layout JN5 JN6 PCH1 JN1 JN2 JN3 JN4 CN14 CN13 CN10 CPU1 LAN1 ™ Intel® Core Processor J1-J5 CompactPCI connectors PCH1 Intel® QM87 PCH LAN1 Dual Ethernet connectors Memory socket mSATA connector CN2/3 XMC connectors CN10 SATA 7-pin connector CN13...

  • Page 33: Cpci-6530Bl Series Front Panel

    4.3 cPCI-6530BL Series Front Panel Front Panel Layout cPCI-6530BLV USB 2.0/3.0 GbE A/B Serial Port DVI USB 3.0 PMC/XMC GP LEDs Power LED Reset Button HotSwap HDD LED WDT LED cPCI-6530BL USB 2.0/3.0 GbE A/B PMC/XMC PMC/XMC GP LEDs...

  • Page 34: Table 4-1: Cpci-6530Bl Front Panel System Led Descriptions

    Leading EDGE COMPUTING System LEDs Color Condition Indication System is off Power Green/ System Power ready (PWGD) Green Post OK No Watchdog event Orange Blinking Watchdog event alert No CF/CFast/SATA HDD activity Blue Data read/write in process for CF/CFast/ Blinking SATA HDD Handles closed, system is on Fast Blink...

  • Page 35: Figure 4-4: Cpci-6530Bl Series Led Labels

    cPCI-6530BL General Purpose LEDs The eight GP LEDs on the front panel display port 80h POST codes in hexadecimal during boot up. Users can use the POST codes to identify issues during the BIOS POST process. For example, if the Bit7 > Bit0 output is “01110101”, then the port 80h output is “75h”...

  • Page 36: Connector Pin Assignments

    Leading EDGE COMPUTING 4.4 Connector Pin Assignments USB 2.0 Connectors Pin # Signal Name UV0- UV0+ Table 4-2: USB 2.0 Pin Definition USB 3.0 Connectors Pin # Signal Name USB3.0_P5VA USB2_CMAN USB2_CMAP USB3A_CMRXN USB3A_CMRXP USB3A_CMTXN USB3A_CMTXP Board Interfaces...

  • Page 37: Table 4-3: Dvi-I Connector Pin Definition

    cPCI-6530BL DVI-I Connector Pin # Signal Pin # Signal TMDS Data2- Hot Plug Detect TMDS Data2+ TMDS Data0- TMDSData0+ DDC Clock [SCL] DDC Data [SDA] Analog vertical sync TMDS Clock + TMDS Data1- TMDS Clock - TMDS Data1+ Analog Red Analog Green Analog Blue Analog Horizontal Sync...

  • Page 38: Table 4-4: Rj-45 Gbe Pin Definitions

    Leading EDGE COMPUTING RJ-45 Gigabit Ethernet Connectors 10BASE-T/ Pin # 1000BASE-T 100BASE-TX LAN_TX0+ LAN_TX0- LAN_TX1+ — LAN_TX2+ — LAN_TX2- LAN_TX1- — LAN_TX3+ — LAN_TX3- Table 4-4: RJ-45 GbE Pin Definitions Speed Activity Speed LED Activity LED Status (Green/Orange) (Yellow) Network link is not established or system powered off Link 10 Mbps...

  • Page 39: Table 4-6: Front Panel Com Pin Definitions

    cPCI-6530BL COM (RJ-45) Pin # RS-232 RS-422 RS-485 DCD# Data- RTS# — — DSR# — — — Data+ — — CTS# — — DTR#L — Table 4-6: Front Panel COM Pin Definitions COM RJ-45 to DB-9 Cable Pin # RS-232 RS-422 RS-485 DCD#...

  • Page 40: Table 4-8: Serial Ata 7-Pin Connector Pin Definition

    Leading EDGE COMPUTING Serial ATA 7-pin Connector (CN10) Pin # Signal Table 4-8: Serial ATA 7-pin Connector Pin Definition Serial ATA Connector with Power Pin # Signal Signal Power P13~P15 Table 4-9: Serial ATA Connector with power Pin Definition Board Interfaces...

  • Page 41: Table 4-10: Sata Board-To-Board Connector Pin Definition

    cPCI-6530BL SATA Board-to-Board Connector (CN11) Signal Name Pin # Pin # Signal Name +3.3V +3.3V +3.3V +3.3V +12V CFAST_CDI +12V CFAST_CDO +12V SATA_TXN0 SATA_TXP0 SATA_RXN0 SATA_RXP0 Table 4-10: SATA Board-to-Board Connector Pin Definition Board Interfaces...

  • Page 42: Table 4-11: Cfast Socket Pin Definition

    Leading EDGE COMPUTING CFast Socket (on optional DB-CFAST) Pin # Signal Name Ground SATA_TX-P SATA_TX-N Ground SATA_RX-N SATA_RX-P Ground CFast_CDI Ground Ground CFast_LED1 CFast_LED2 +3.3V +3.3V Ground Ground CFast_CDO Table 4-11: CFast Socket Pin Definition Board Interfaces...
  • Page 43 cPCI-6530BL PMC Connector (JN1/5, JN2/6, JN3/7, JN4) Pin# JN1/5 Signal JN2/6 Signal JN3/7 Signal JN4 Signal PMC_TCK +12V PIO1 -12V* PMC_TRST-L PIO2 PMC_TMS PIO3 PCIX_INTA-L NC (PMC_TDO) PCIX_CBE-L7 PIO4 PCIX_INTB-L PMC_TDI PCIX_CBE-L6 PIO5 PCIX_INTC-L PCIX_CBE-L5 PIO6 PMC_MOD-L1 PCIX_CBE-L4 PIO7 PIO8 PCIX_INTD-L PMC_VIO PIO9...

  • Page 44: Table 4-12: Pmc Connector Pin Definitions

    Leading EDGE COMPUTING Pin# JN1/5 Signal JN2/6 Signal JN3/7 Signal JN4 Signal PCIX_AD17 PCIX_CBE-L2 PIO32 PCIX_FRAME-L PIO33 PCIX_AD48 PIO34 PCIX_TRDY-L PCIX_AD47 PIO35 PCIX_IRDY-L +3.3V PCIX_AD46 PIO36 PCIX_DEVSEL-L PCIX_AD45 PIO37 PCIX_STOP-L PIO38 PCIX_PCIXCAP PCIX_PERR-L PIO39 PCIX_LOCK-L PCIX_AD44 PIO40 +3.3V PCIX_AD43 PIO41 PCIX_SERR-L PCIX_AD42 PIO42...

  • Page 45: Table 4-13: Xmc1 Connector Pin Definition

    cPCI-6530BL XMC1 Connector (CN2) Pin# PCIE_XMC1 PCIE_XMC1 PCIE_XMC1 PCIE_XMC P3V3_PSU XMC1_VPWR _RXP0 _RXN0 _RXP1 1_RXN1 XMC_TRST- PLTRST_XMC1 PCIE_XMC1 PCIE_XMC1 PCIE_XMC1 PCIE_XMC P3V3_PSU XMC1_VPWR _RXP2 _RXN2 _RXP3 1_RXN3 XMC1_TCK XMC1_RST-L PCIE_XMC1 PCIE_XMC1 PCIE_XMC1 PCIE_XMC P3V3_PSU XMC1_VPWR _RXP4 _RXN4 _RXP5 1_RXN5 XMC1_TMS P12V PCIE_XMC1 PCIE_XMC1...

  • Page 46: Table 4-14: Xmc2 Connector Pin Definition

    Leading EDGE COMPUTING XMC2 Connector (CN3) Pin# PCIE_XMC2 PCIE_XMC2 PCIE_XMC2 PCIE_XMC P3V3_PSU XMC2_VPWR _RXP0 _RXN0 _RXP1 2_RXN1 XMC_TRST- PLTRST_XMC2 PCIE_XMC2 PCIE_XMC2 PCIE_XMC2 PCIE_XMC P3V3_PSU XMC2_VPWR _RXP2 _RXN2 _RXP3 2_RXN3 XMC2_TCK XMC2_RST-L PCIE_XMC2 PCIE_XMC2 PCIE_XMC2 PCIE_XMC P3V3_PSU XMC2_VPWR _RXP4 _RXN4 _RXP5 2_RXN5 XMC2_TMS P12V...

  • Page 47: Table 4-15: Compactpci J1 Connector Pin Definition

    cPCI-6530BL CompactPCI J1 Connector CPCI_REQ64-L CPCI_ENUM-L +3.3V CPCI_AD1 CPCI_VIO CPCI_AD0 CPCI_ACK64-L GND +3.3V CPCI_AD4 CPCI_AD3 CPCI_AD2 CPCI_AD7 +3.3V CPCI_AD6 CPCI_AD5 +3.3V CPCI_AD9 CPCI_AD8 CPCI_M66EN CPCI_CBE-L0 GND CPCI_AD12 CPCI_VIO CPCI_AD11 CPCI_AD10 +3.3V CPCI_AD15 CPCI_AD14 CPCI_AD13 CPCI_SERR-L +3.3V CPCI_PAR CPCI_CBE-L1 GND +3.3V IPMCB_CLK IPMB_DAT CPCI_PERR-L GND...

  • Page 48: Table 4-16: Compactpci J2 Connector Pin Definition

    Leading EDGE COMPUTING CompactPCI J2 Connector CPCI_CLK6 CPCI_CLK5 IPMB_DAT IPMB_CLK J2_RST-L CPCI_REQ-L6 CPCI_GNT-L6 GND CPCI_DEG-L CPCI_FAL-L CPCI_REQ-L5 CPCI_GNT-L5 GND CPCI_AD35 CPCI_AD34 CPCI_AD33 CPCI_AD32 CPCI_AD38 CPCI_VIO CPCI_AD37 CPCI_AD36 CPCI_AD42 CPCI_AD41 CPCI_AD40 CPCI_AD39 CPCI_AD45 CPCI_VIO CPCI_AD44 CPCI_AD43 CPCI_AD49 CPCI_AD48 CPCI_AD47 CPCI_AD46 CPCI_AD52 CPCI_VIO CPCI_AD51 CPCI_AD50...

  • Page 49: Table 4-17: Compactpci J3 Connector Pin Definition

    cPCI-6530BL CompactPCI J3 Connector Pin Z 19 GND +12V 18 GND LAN3_TXDP0 LAN3_TXDN0 LAN3_TXDP2 LAN3_TXDN2 17 GND LAN3_TXDP1 LAN3_TXDN1 LAN3_TXDP3 LAN3_TXDN3 16 GND LAN4_TXDP0 LAN4_TXDN0 LAN4_TXDP2 LAN4_TXDN2 15 GND LAN4_TXDP1 LAN4_TXDN1 LAN4_TXDP3 LAN4_TXDN3 14 GND USB_OC45-L USB_OC6 USB_OC7 USB_OC8 USB_OC9 13 GND USB8-P USB8-N...

  • Page 50: Table 4-18: Compactpci J4 Connector Pin Definition

    Leading EDGE COMPUTING CompactPCI J4 Connector PMC IO:P1 PMC IO:N1 PMC IO:P2 PMC IO:N2 PMC IO:P3 PMC IO:N3 PMC IO:P4 PMC IO:N4 PMC IO:P5 PMC IO:N5 PMC IO:P6 PMC IO:N6 PMC IO:P7 PMC IO:N7 PMC IO:P8 PMC IO:N8 PMC IO:17 PMC IO:19 PMC IO:18 PMC IO:20...

  • Page 51: Table 4-19: Compactpci J5 Connector Pin Definition

    cPCI-6530BL CompactPCI J5 Connector 22 GND PWRLED-L LAN4_LED_ACT-L LAN3_LED_ACT-L 21 GND EDP_TX_P1 EDP_TX_N1 20 GND EDP_TX_P0 EDP_TX_N0 19 GND EDP_AUX_P EDP_AUX_N 18 GND 17 GND 16 GND EDP_HPD 15 GND SATA_RXP2 SATA_RXN2 14 GND SATA-TXP2 SATA-TXN2 13 GND LAN4_LED_100-L LAN3_LED_100-L LAN3_LED_1000-L LAN4_LED_1000-L GND 12 GND DVI_SDA_RTM DVI_SCL_RTM DVI_HPD_RTM...

  • Page 52: Switches And Buttons

    Leading EDGE COMPUTING 4.5 Switches and Buttons Solder Side SW11 SW_MOD1 SW_MOD2 SW_COMDEG1 SW_IPMCDEG1 SW_PMC1 Board Interfaces...

  • Page 53: Figure 4-5: Solder-Side Switch And Button Locations

    cPCI-6530BL Figure 4-5: Solder-side switch and button locations Component Side SW_COMPW1 SW_VIO1 Figure 4-6: Component-side switch locations Board Interfaces...
  • Page 54 Leading EDGE COMPUTING System Reset Button (SW8) The cPCI-6530BL has a system reset button on the front panel. See “cPCI-6530BL Series Front Panel” on page 21 for the but- ton location. The following switches are located on the solder side. See Fig- ure 4-4 above for their locations.
  • Page 55 cPCI-6530BL Serial Port Setting (SW7) Sets the mode of the COM port on the front panel. Mode RS-232 (default) RS-422 RS-485 PMC VIO Function (SW_VIO1) Function 3.3V (Default) ● Board Interfaces...
  • Page 56 Leading EDGE COMPUTING PMC Clock Settings (SW_PMC1) Switch SW_PMC1 allows the user to force the PCI bus to lower bandwidth and clock settings. All are set to OFF by default to support PCI-X mode up to 64-bit/133MHz maximum with the bandwidth and clock determined by the PCI device attached.
  • Page 57 cPCI-6530BL Debug Switches (SW4/9/11, SW_IPMCDEG1/SW_MOD2) Switches SW4/9/11, SW_IPMCDEG1 and SW_MOD2 are for debugging purposes and should be left in the default settings (all OFF). Debug Switch (SW_MOD1) Switch SW_MOD1 is for debugging purposes and should be left in the default settings (all OFF). On the CT-6530BL Conduction Cooled Blade, the SW_MOD1 default settings are 1 OFF, 2 ON.
  • Page 58 Leading EDGE COMPUTING COM Debug Switches (SW_COMDEG1, SW_COMPW1) Switch SW_COMDEG1 is set 1, 2 ON and 3, 4 OFF by default to set the front panel RJ-45 COM (CN7) serial port as a stan- dard RS-232 serial port. The setting can be changed to use CN7 as an IPMI debugging port.

  • Page 59: Getting Started

    cPCI-6530BL Getting Started This chapter describes the following installation procedures for the cPCI-6530BL and rear transition module: CPU and Heatsink mSATA module 2.5” SATA hard drive PMC/XMC module installation 5.1 CPU and Heatsink cPCI-6530BL Series come with heatsink pre-installed. Removal of heatsink/CPU by users is not recom- mended.

  • Page 60: Msata Module Installation

    Leading EDGE COMPUTING 5.2 mSATA Module Installation The cPCI-6530BLV provides space to install a mSATA module. Fol- low the instructions below to install a mSATA module to the cPCI-6530BL. 1. An mSATA module can be installed in the location marked as below.

  • Page 61: Sata Drive Installation

    5.3 2.5" SATA Drive Installation The cPCI-6530BLV provides space to install a 2.5” SATA drive. 1. Locate the screws and 2.5” SATA drive bracket in the accessory pack. 2. Secure the drive to the bracket by fastening the four screws provided as shown below.
  • Page 62 Leading EDGE COMPUTING 3. Find the SATA adapter board (DB-LSATA) in the acces- sory pack. Align the adapter board with the onboard SATA connector (CN11). Getting Started...
  • Page 63 cPCI-6530BL 4. Align the drive assembly as shown below and insert it into the onboard SATA connector until it is properly seated. Secure the drive assembly to the blade with two screws circled below. Getting Started...
  • Page 64 Leading EDGE COMPUTING 5. Turn the blade over and secure with two screws as marked below to complete the SATA drive installation. Getting Started...

  • Page 65: Pmc/Xmc Installation

    The cPCI-6530BL provides 2 PMC/XMC sites and the cPCI-6530BLV has 1 PMC/XMC site. The instructions below show the cPCI-6530BLV. The same procedure is used to install a sec- ond module in the cPCI-6530BL’s second PMC/XMC site. 1. The cPCI-6530BLV’s single PMC/XMC slot is shown below.
  • Page 66 Leading EDGE COMPUTING 3. Align the connectors on the PMC/XMC module to the PMC/XMC connectors on cPCI-6530BL(V) blade. Press down to secure the PMC/XMC module to the cPCI-6530BL(V). 4. Secure four screws provided by the PMC/XMC module supplier to the solder side of the cPCI-6530BL(V) blade to complete the installation of the PMC/XMC module.

  • Page 67: Installing The Cpci-6530Bl To The Chassis

    cPCI-6530BL 5.5 Installing the cPCI-6530BL to the Chassis The cPCI-6530BL may be installed in a system or peripheral slot of a 6U CompactPCI chassis. These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.
  • Page 68 Leading EDGE COMPUTING This page intentionally left blank. Getting Started...

  • Page 69: Driver Installation

    cPCI-6530BL Driver Installation The cPCI-6530BL drivers are available from the ADLINK All-In-One DVD at X:\cPCI\cPCI-6530BL\, or from the ADLINK website (http://www.adlinktech.com). ADLINK provides vali- dated drivers for Windows 7 and Windows 8. We recommend using these drivers to ensure compatibility. The VxWorks BSP can be downloaded from the cPCI-6530BL product page on the ADLINK website 6.1 cPCI-6530BL Drivers...
  • Page 70 Leading EDGE COMPUTING 8. Install the Intel® Management Engine Interface driver for Intel® AMT support by extracting and running the program in...\Chipset\Intel_Managerment_Engine_Interface _9.0.0.1209.zip. Driver Installation...

  • Page 71: Utilities

    cPCI-6530BL Utilities 7.1 Watchdog Timer This section describes the operation of the cPCI-6530BL’s watch dog timer (WDT). The primary function of the WDT is to monitor the cPCI-6530BL operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application: enabling and disabling reloading timeout value...
  • Page 72 Leading EDGE COMPUTING Sample Code #include<stdio.h> #include<dos.h> #define IT8783_ID1 0x87 #define IT8783_ID2 0x83 static unsigned int IT8783_ioPort = 0x2e; //Check index port void Enter_IT8783_Config(unsigned int flag) if(flag) IT8783_ioPort = 0x4e; switch(IT8783_ioPort) case 0x2E: //Address port = 0x2E, enter keys = 0x87, 0x01, 0x55, 0x55 outportb(0x2E, 0x87);...
  • Page 73 cPCI-6530BL outportb(IT8783_ioPort+1, 0x02); //Check chip void Get_IT8783_ID(unsigned int &ID1, unsigned int &ID2) outportb(IT8783_ioPort, 0x20); ID1 = inportb(IT8783_ioPort+1); outportb(IT8783_ioPort, 0x21); ID2 = inportb(IT8783_ioPort+1); //WDT and LED program void IT8783_3_WDTRun(unsigned int count_value, unsigned int PLEDflag) //for cPCI-6530BL unsigned long tempCount; unsigned int registerValue; outportb(IT8783_ioPort, 0x07);...
  • Page 74 Leading EDGE COMPUTING outportb(IT8783_ioPort, 0xCD); registerValue = inportb(IT8783_ioPort + 1); registerValue |= 0x01; // set GP60 is output outportb(IT8783_ioPort+1, registerValue); outportb(IT8783_ioPort, 0xf8); outportb(IT8783_ioPort+1, 0x30);// PLED mapping to GP60 outportb(IT8783_ioPort, 0xf9); registerValue = inportb(IT8783_ioPort + 1); registerValue |= 0x02; registerValue &= 0xfb; outportb(IT8783_ioPort+1, registerValue);...
  • Page 75 cPCI-6530BL tempCount++; if(tempCount > 65535) tempCount = 65535; printf("WDT timeout in %d minutes.\n", tempCount); else outportb(IT8783_ioPort, 0x72); registerValue = inportb(IT8783_ioPort+1); registerValue |= 0x80; tempCount = count_value; if(tempCount != 0) printf("WDT timeout in %d seconds.\n", tempCount); registerValue |= 0x40; //Enable WDT output through KBRST else printf("WDT is Disabled.\n");...
  • Page 76 Leading EDGE COMPUTING This page intentionally left blank. Utilities...

  • Page 77: Bios Setup Utility

    cPCI-6530BL BIOS Setup Utility The following chapter describes basic navigation for the AMI EFI BIOS setup utility. 8.1 Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: <...
  • Page 78 Leading EDGE COMPUTING Setup Menu The main BIOS setup menu is the first screen that you can navi- gate. Each main BIOS setup menu option is described in this user’s guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured.
  • Page 79 cPCI-6530BL Navigation Note: There is a hot key legend located in the right frame on most setup screens. Keyboard Commands < > The Left and Right "Arrow" keys allow you to select a setup screen. The Up and Down "Arrow" keys allow you to select a setup screen.
  • Page 80 Leading EDGE COMPUTING Hotkey Descriptions Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. The <...
  • Page 81 cPCI-6530BL conflicting settings. The < F4 > key allows you to save any changes you have made and exit Setup. Press the < F10 > key to save your changes. The following screen will appear: Press the < Enter > key to save the configuration and exit. You can also use the <...

  • Page 82: Main Setup

    Leading EDGE COMPUTING 8.2 Main Setup When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by select- ing the Main tab. There are two Main Setup options. They are described in this section.
  • Page 83 cPCI-6530BL System Time/System Date Use this option to change the system time and date. Highlight Sys- tem Time or System Date using the < Arrow > keys. Enter new val- ues using the keyboard. Press the < Tab > key or the < Arrow > keys to move between fields.

  • Page 84: Advanced Bios Setup

    Leading EDGE COMPUTING 8.3 Advanced BIOS Setup Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item.

  • Page 85: Cpu Configuration

    cPCI-6530BL 8.3.1 CPU Configuration You can use this screen to select options for the CPU Configura- tion Settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option.

  • Page 86: Trusted Computing

    Leading EDGE COMPUTING 8.3.2 Trusted Computing Trusted Computing is an industry standard to make personal com- puters more secure through a dedicated hardware chip, called a Trusted Platform Module (TPM). This option allows you to enable or disable the TPM support. Security Device Support OS will not show TPM.

  • Page 87: Pch-Fw Configuration

    cPCI-6530BL 8.3.3 PCH-FW Configuration Intel TXT(LT) Configuration You can use this screen to view ME related information. For example, ME FW Version, ME Firmware Mode, ME Firmware Type, ME Firmware SKU..etc. An example of the ME screen is shown below. BIOS Setup Utility...

  • Page 88: Intel Anti-Theft Technology Configuration

    Leading EDGE COMPUTING 8.3.4 Intel Anti-Theft Technology Configuration You can use this screen to select options for the Intel AT Configu- ration Settings. An example of the Intel AT Configuration screen is shown below. Intel Anti-Theft Technology Set this value to Enabled/Disabled. Enter Intel®...

  • Page 89: Amt Configuration

    cPCI-6530BL 8.3.5 AMT Configuration You can use this screen to select options for the AMT settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option. Intel AMT Intel AMT feature.

  • Page 90: It8783 Super Io Configuration

    Leading EDGE COMPUTING 8.3.6 IT8783 Super IO Configuration You can use this screen to select options for the serial port con- sole redirection settings. An example of the Serial Port Console Redirection screen is shown below. Serial Port 1,2,3,4,6 Configuration Set Parameters of Serial Port 1,2,3,4,6 (COM 1,2,3,4,6).

  • Page 91: Serial Port Console Redirection

    cPCI-6530BL 8.3.7 Serial Port Console Redirection You can use this screen to select options for the serial port con- sole redirection settings. Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the selected option.
  • Page 92 Leading EDGE COMPUTING Terminal Type VT100+ is the preferred terminal type for out-of-band manage- ment. Configuration options: VT100, VT100+, VT-UTF8, ANSI. Bits per second Select the bits per second you want the serial port to use for console redirection. The options are 115200, 57600, 38400, 19200, 9600.
  • Page 93 cPCI-6530BL Communication with slow devices may require more than 1 stop bit. Set this value to 1 and 2. Flow Control Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware RTS/CTS. VT-UTF8 Combo Key Support Enables VT-UTF8 combination key support for ANSI/VT100 terminals.Set this value to Enabled/Disabled.

  • Page 94: Intel Txt Information

    Leading EDGE COMPUTING 8.3.8 Intel TXT Information You can use this screen to view Intel TXT information. BIOS Setup Utility...

  • Page 95: Platform Misc Configuration

    cPCI-6530BL 8.3.9 Platform Misc Configuration DPTF Configuration DPTF Enable/Disable Intel® Dynamic Platform Thermal Framework. BIOS Setup Utility...

  • Page 96: 10Sata Configuration

    Leading EDGE COMPUTING 8.3.10 SATA Configuration You can use this screen to select options for the SATA Configura- tion Settings. An example of the SATA Configuration screen is shown below. SATA Controller(s) Enable or disable SATA device. SATA Mode Selection The SATA can be configured as a legacy IDE, RAID and AHCI mode.
  • Page 97 cPCI-6530BL Software Feature Mask Configuration RAID OROM/RST driver will refer to the SWFM configuration to enable or disable the storage features. RAID0-5 Enable or disable RAID0-5 feature. Intel Rapid Recovery Technology Enable or disable Intel Rapid Recovery Technology. OROM UI and Banner If enabled, the OROM UI is shown.
  • Page 98 Leading EDGE COMPUTING IRRT Only on eSATA If enabled, then only IRRT volumes can span internal and eSATA drives. If disabled, then any RAID volume can span internal and eSATA drives. Smart Response Technology Enable or disable Smart Response Technology. OROM UI Delay If enabled, indicates the delay of the OROM UI Splash Screen under normal status.

  • Page 99: 11Network Stack Configuration

    cPCI-6530BL 8.3.11 Network Stack Configuration Network Stack Enable/Disable UEFI Network Stack. IPv4 PXE Support Enable IPv4 PXE Boot Support. If disabled, the IPv4 PXE boot option will not be created. IPv6 PXE Support Enable IPv6 PXE Boot Support. If disabled, the IPv6 PXE boot option will not be created.

  • Page 100: 12Csm Configuration

    Leading EDGE COMPUTING 8.3.12 CSM Configuration CSM Support Enable/Disable CSM Support. GateA20 Active Upon Request: GA20 can be disabled using BIOS services. Always: do not allow disabling of GA20; this option is useful when any RT code is executed above 1MB. Option ROM Messages Set the display mode for Option ROM.
  • Page 101 cPCI-6530BL Storage Controls the execution of UEFI and Legacy PXE OpROM. Set this value to Do not launch, Legacy, UEFI. Video Controls the execution of UEFI and Legacy PXE OpROM. Set this value to Do not launch, Legacy, UEFI. Other PCI Devices Determines OpROM execution policy for devices other than Network, Storage, or Video.

  • Page 102: 13Usb Configuration

    Leading EDGE COMPUTING 8.3.13 USB Configuration You can use this screen to select options for the USB Configura- tion. Use the up and down < Arrow > keys to select an item. The screen is shown below. Legacy USB Support Enables legacy USB support.

  • Page 103: 14Hardware Monitor

    cPCI-6530BL 8.3.14 Hardware Monitor This option displays the current status of all of the monitored hard- ware devices/components such as voltages and temperatures. CPU Temperature Displays current CPU temperature. System Temperature Displays current system temperature. 3.3V Displays current system 3.3V voltage. Displays current system 5V voltage.

  • Page 104: Chipset Setup

    Leading EDGE COMPUTING 8.4 Chipset Setup Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of Chipset BIOS Setup options by highlighting it using the < Arrow > keys. The Chipset BIOS Setup screen is shown below.

  • Page 105: System Agent (Sa) Configuration

    cPCI-6530BL 8.4.1 System Agent (SA) Configuration VT-d The Intel Virtualization Technology for Directed I/O. Set this value to Enabled/Disabled. BIOS Setup Utility...
  • Page 106 Leading EDGE COMPUTING Graphics Configuration Primary Display Select which graphics device should be the primary display. Set this value to Auto, IGFX, PCI. Internal Graphics Keep IGD enabled based on the setup options. Set this value to Auto, Enabled, Disabled. BIOS Setup Utility...
  • Page 107 cPCI-6530BL DVMT Pre-Allocated Select DVMT 5.0 Pre-Allocated (fixed) graphics memory size used by the internal graphics device. Configuration options as below: DVMT Total Gfx Memory Select DVMT 5.0 total graphic memory size used by the inter- nal graphics device. Configuration options as below: Primary IGFX Boot Display Select Boot Video Device during POST VBIOS Default: auto-detect video device by vBIOS.
  • Page 108 Leading EDGE COMPUTING PEG Port Configuration PEG0 - Gen X XMC PEG (PEX8624, PCIe x8): Bus:0 Device:1 Function:0 Available options: Auto, Gen1, Gen2, Gen3 PEG1 - Gen X PMC PEG (PI7C9X130 PCIe x4): Bus:0 Device:1 Function:1 Available options: Auto, Gen1, Gen2, Gen3 PEG2 - Gen X J1/J2 PEG (PI7C9X130 PCIe x4): Bus:0 Device:1 Function:2 Available options: Auto, Gen1, Gen2, Gen3...
  • Page 109 cPCI-6530BL Memory Configuration Memory Frequency Limiter Maximum memory frequency selections in MHz. BIOS Setup Utility...

  • Page 110: Pch-Io Configuration

    Leading EDGE COMPUTING 8.4.2 PCH-IO Configuration BIOS Setup Utility...
  • Page 111 cPCI-6530BL PCI Express Configuration PCI Express Root Port 5-8 Configuration the PCI Express Root Ports 5-8 BIOS Setup Utility...
  • Page 112 Leading EDGE COMPUTING PCH Azalia Configuration Azaila Enable/Disable the Azalia device. Disabled: Azalia will be unconditionally disabled Enabled: Azalia will be unconditionally Enabled Auto: Azalia will be enabled if present, disabled otherwise. PCH LAN Controller Enable/Disable the PCH LAN Controller. High Precision Timer Enable/Disable the High Precision Event Timer.

  • Page 113: Boot Settings

    cPCI-6530BL 8.5 Boot Settings Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item.
  • Page 114 Leading EDGE COMPUTING Set Boot Priority Set Boot Option #1 ~2 boot priority. BIOS Setup Utility...

  • Page 115: Security Setup

    cPCI-6530BL 8.6 Security Setup Administrator, User Password If only the administrator's password is set, then this only limits access to setup and is only asked for when entering setup. If only the user's password is set, then this is a power on password and must be entered to boot or enter setup.

  • Page 116: Save & Exit Menu

    Leading EDGE COMPUTING 8.7 Save & Exit Menu Select the Save & Exit tab from the setup screen to enter the Save & Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the < Arrow > keys. The Save & Exit BIOS Setup screen is shown below.
  • Page 117 cPCI-6530BL Discard Changes and Exit Exit system setup without saving any changes. Save Changes and Reset Reset the system after saving the changes. Discard Changes and Reset Reset system setup without saving any changes. Save Changes Save changes done so far to any of the setup options. BIOS Setup Utility...
  • Page 118 Leading EDGE COMPUTING Discard Changes Discard changes done so far to any of the setup options. Restore Defaults Restore/Load Defaults values for all the setup options. Save as User Defaults Save the changes done so far as user defaults.. Restore User Defaults Save changes done so far to any of the setup options.

  • Page 119: Checkpoints & Beep Codes

    cPCI-6530BL Checkpoints & Beep Codes The eight GP LEDs on the front panel display port 80h POST codes in hexadecimal during boot up. Users can use the POST codes to identify issues during the BIOS POST process (see See “General Purpose LEDs” on page 23.). Below are the BIOS checkpoints and beep codes for the cPCI- 6530BL.
  • Page 120 Leading EDGE COMPUTING Status Code Description 0x02 AP initialization before microcode loading North Bridge initialization before microcode 0x03 loading South Bridge initialization before microcode 0x04 loading 0x05 OEM initialization before microcode loading 0x06 Microcode loading 0x07 AP initialization after microcode loading North Bridge initialization after microcode 0x08 loading...
  • Page 121 cPCI-6530BL Status Code Description Pre-Memory North Bridge initialization (North 0x16 Bridge module specific) Pre-Memory North Bridge initialization (North 0x17 Bridge module specific) Pre-Memory North Bridge initialization (North 0x18 Bridge module specific) 0x19 Pre-memory South Bridge initialization is started Pre-memory South Bridge initialization (South 0x1A Bridge module specific) Pre-memory South Bridge initialization (South...
  • Page 122 Leading EDGE COMPUTING Status Code Description Post-Memory North Bridge initialization (North 0x38 Bridge module specific) Post-Memory North Bridge initialization (North 0x39 Bridge module specific) Post-Memory North Bridge initialization (North 0x3A Bridge module specific) Post-Memory South Bridge initialization is 0x3B started Post-Memory South Bridge initialization (South 0x3C Bridge module specific)
  • Page 123 cPCI-6530BL Status Code Description S3 Resume Progress Codes S3 Resume is stared (S3 Resume PPI is called 0xE0 by the DXE IPL) 0xE1 S3 Boot Script execution 0xE2 Video repost 0xE3 OS S3 wake vector call 0xE4-0xE7 Reserved for future AMI progress codes S3 Resume Error Codes 0xE8 S3 Resume Failed...
  • Page 124 Leading EDGE COMPUTING PEI Beep Codes # of Beeps Description Memory not Installed Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) Recovery started DXEIPL was not found DXE Core Firmware Volume was not found Recovery failed S3 Resume failed Reset PPI is not available DXE Phase Status Code...
  • Page 125 cPCI-6530BL Status Code Description North Bridge DXE initialization (North Bridge 0x6F module specific) 0x70 South Bridge DXE initialization is started 0x71 South Bridge DXE SMM initialization is started 0x72 South Bridge devices initialization South Bridge DXE Initialization (South Bridge 0x73 module specific) South Bridge DXE Initialization (South Bridge 0x74...
  • Page 126 Leading EDGE COMPUTING Status Code Description 0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup Reserved for ASL (see ASL Status Codes 0xAA section below)
  • Page 127 cPCI-6530BL Status Code Description Some of the Architectural Protocols are not 0xD3 available 0xD4 PCI resource allocation error. Out of Resources 0xD5 No Space for Legacy Option ROM 0xD6 No Console Output Devices are found 0xD7 No Console Input Devices are found 0xD8 Invalid password Error loading Boot Option (LoadImage returned...

  • Page 128: Oem-Reserved Checkpoint Ranges

    Leading EDGE COMPUTING ACPI/ASL Checkpoints Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20...

  • Page 129: Ipmi User Guide

    cPCI-6530BL 10 IPMI User Guide 10.1 Introduction This chapter is written for those who already have a basic under- standing of the newest implementation of the baseboard manage- ment controller (BMC) of the Intelligent Platform Management Interface (IPMI) specification rev. 2.0. It also describes the OEM extension IPMI command usages which are not listed in the IPMI specification.
  • Page 130 Leading EDGE COMPUTING Description IPMI Command NetFn CMD Spec (Required by PICMG 3.0/2.9) This command returns a GUID (Globally Unique ID), also referred to as a UUID Get Device GUID 20.8 (Universally Unique IDentifier), for the management controller. (Optional/Optional) This is a broadcast version of the ‘Get Broadcast "Get Device ID’...
  • Page 131 cPCI-6530BL Description IPMI Command NetFn CMD Spec (Required by PICMG 3.0/2.9) This global command is used to retrieve the present setting for the Event Receiver Slave Address and LUN. This command Get Event Receiver 29.2 is only applicable to management controllers that act as IPMB Event Generators.
  • Page 132 Leading EDGE COMPUTING Description IPMI Command NetFn CMD Spec (Required by PICMG 3.0/2.9) This command provides the ability to disable or enable Event Message Set Sensor Event Generation for individual sensor events. 35.10 Enable The command is also used to enable or disable sensors in their entirety using the disable scanning bit.

  • Page 133: Compactpci Address Map

    cPCI-6530BL 10.3 CompactPCI Address Map Since more than one system may be installed in a single chassis, we allocate each IPMB address based on GA input as peripheral cards. The CompactPCI Peripheral Address Mapping Table is given below. CompactPCI Peripheral Address Mapping Geo.

  • Page 134: Ipmi Sensors List

    Leading EDGE COMPUTING 10.5 IPMI Sensors List Sensor Reading Value of Sensor Normal Sensor name IPMI Get Sensor Reading Number Reading Command Timeout action: 000b = no action 001b = Hard Reset BMC Watchdog 000b = Power Down 011b = Power Cycle 100b - 111b = reserved 3.3V 3.3 V...

  • Page 135: Important Safety Instructions

    cPCI-6530BL Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this user’s manual for future reference. Read the specifications section of this manual for detailed information on the operating environment of this equipment.
  • Page 136 Leading EDGE COMPUTING Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. Risk of explosion if battery is replaced with one of an incorrect type.

  • Page 137: Getting Service

    San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com...

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