GigaDevice Semiconductor GD32C10 Series User Manual

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GigaDevice Semiconductor Inc.

GD32C10x

Arm

Cortex

-M4 32-bit MCU

User Manual

Revision 1.3

( Dec. 2022 )

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Page 1 GigaDevice Semiconductor Inc. GD32C10x Cortex -M4 32-bit MCU ® ® User Manual Revision 1.3 ( Dec. 2022 )
Page 2: Table Of Contents
GD32C10x User Manual Table of Contents Table of Contents ......................2 List of Figures ......................15 List of Tables ........................ 21 1. System and memory architecture ................ 23 ARM Cortex-M4 processor ..................23 1.1. System architecture ....................24 1.2. Memory map ......................26 1.3.
Page 3 GD32C10x User Manual 2.4.5. Control register (FMC_CTL) ....................48 2.4.6. Address register (FMC_ADDR) .................... 50 2.4.7. Option byte status register (FMC_OBSTAT) ................. 50 2.4.8. Erase/Program protection register (FMC_WP) ..............51 2.4.9. Product ID register (FMC_PID)..................... 51 3. Power management unit (PMU) ................53 Overview ........................
Page 4 GD32C10x User Manual 5.3.3. Clock interrupt register (RCU_INT) ..................81 5.3.4. APB2 reset register (RCU_APB2RST) ................. 85 5.3.5. APB1 reset register (RCU_APB1RST) ................. 87 5.3.6. AHB enable register (RCU_AHBEN) ..................90 5.3.7. APB2 enable register (RCU_APB2EN) ................91 5.3.8. APB1 enable register (RCU_APB1EN) ................93 5.3.9.
Page 5 GD32C10x User Manual 7.6.5. Software interrupt event register (EXTI_SWIEV) ............... 124 7.6.6. Pending register (EXTI_PD) ....................125 8. General-purpose and alternate-function I/Os (GPIO and AFIO) ....... 126 Overview ........................126 8.1. Characteristics ......................126 8.2. Function overview ....................126 8.3. 8.3.1.
Page 6 GD32C10x User Manual 8.5.15. AFIO port configuration register 1 (AFIO_PCF1) ............... 153 8.5.16. IO compensation control register (AFIO_CPSCTL)............154 9. CRC calculation unit (CRC) ................. 155 Overview ........................155 9.1. Characteristics ......................155 9.2. Function overview ....................156 9.3. Register definition ....................157 9.4.
Page 7 GD32C10x User Manual 11.2.5. JEDEC-106 ID code ......................175 Debug hold function overview ................175 11.3. 11.3.1. Debug support for power saving mode ................175 11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN ..........176 Register definition ....................177 11.4.
Page 8 GD32C10x User Manual 12.7.9. Routine sequence register 1 (ADC_RSQ1) ................ 203 12.7.10. Routine sequence register 2 (ADC_RSQ2) ..............204 12.7.11. Routine data register (ADC_RDATA) ................204 12.7.12. Oversample control register (ADC_OVSAMPCTL) ............205 Digital-to-analog converter (DAC) ..............207 Overview ....................... 207 13.1.
Page 9 GD32C10x User Manual 14.2.4. Register definition ....................... 230 Real-time Clock (RTC) ..................232 Overview ....................... 232 15.1. Characteristics ..................... 232 15.2. Function overview ....................232 15.3. 15.3.1. RTC reset ..........................233 15.3.2. RTC reading ........................233 15.3.3. RTC configuration ....................... 233 15.3.4.
Page 10 GD32C10x User Manual 16.4.1. Overview ..........................360 16.4.2. Characteristics ........................361 16.4.3. Block diagram ........................361 16.4.4. Function overview ....................... 361 16.4.5. TIMERx registers (x=9, 10, 12, 13) ..................369 Basic timer (TIMERx, x=5, 6) ................378 16.5. 16.5.1. Overview ..........................378 16.5.2.
Page 11 GD32C10x User Manual Overview ....................... 417 18.1. Characteristics ..................... 417 18.2. Function overview ....................417 18.3. 18.3.1. SDA and SCL lines ......................418 18.3.2. Data validation ........................419 18.3.3. START and STOP signal ....................419 18.3.4. Clock synchronization ......................419 18.3.5.
Page 12 GD32C10x User Manual 19.3.8. SPI interrupts ........................461 I2S function overview ..................462 19.4. 19.4.1. I2S block diagram ....................... 462 19.4.2. I2S signal description ......................463 19.4.3. I2S audio standards ......................463 19.4.4. I2S clock ..........................471 19.4.5. Operation ..........................472 19.4.6.
Page 13 GD32C10x User Manual 21.3.6. Time-triggered communication ................... 527 21.3.7. Communication parameters ....................527 21.3.8. CAN FD operation ......................529 21.3.9. Transmitter Delay Compensation ..................530 21.3.10. Error flags ........................531 21.3.11. CAN interrupts ........................ 531 21.4. Register definition ....................534 21.4.1.
Page 14 GD32C10x User Manual 22.5.3. USB device function ......................561 22.5.4. OTG function overview ....................... 562 22.5.5. Data FIFO ........................... 563 22.5.6. Operation guide ........................566 Interrupts ......................570 22.6. Register definition ....................572 22.7. 22.7.1. Global control and status registers ..................572 22.7.2.
Page 15: List Of Figures
GD32C10x User Manual List of Figures -M4 processor ................. 24 ® Figure 1-1. The structure of the Cortex Figure 1-2. GD32C10x series system architecture ................. 26 Figure 2-1. Process of page erase operation ..................39 Figure 2-2. Process of mass erase operation ..................40 Figure 2-3.
Page 16 GD32C10x User Manual Figure 13-1. DAC block diagram ......................208 Figure 13-2. DAC LFSR algorithm ......................210 Figure 13-3. DAC triangle noise wave ....................210 Figure 14-1. Free watchdog block diagram ..................222 Figure 14-2. Window watchdog timer block diagram ................227 Figure 14-3.
Page 17 GD32C10x User Manual Figure 16-38. Output-compare under three modes ................307 Figure 16-39. EAPWM timechart ......................308 Figure 16-40. CAPWM timechart ......................308 Figure 16-41. Restart mode ........................310 Figure 16-42. Pause mode ........................310 Figure 16-43. Event mode ........................311 Figure 16-44.
Page 18 GD32C10x User Manual Figure 17-14. IrDA data modulation ....................... 399 Figure 17-15. ISO7816-3 frame format ....................400 Figure 17-16. USART interrupt mapping diagram ................403 Figure 18-1. I2C module block diagram ....................418 Figure 18-2. Data validation ........................419 Figure 18-3. START and STOP signal ....................419 Figure 18-4.
Page 19 GD32C10x User Manual Figure 19-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ....466 Figure 19-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ....466 Figure 19-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ....466 Figure 19-31. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ....467 Figure 19-32.
Page 20 GD32C10x User Manual Figure 20-3. Mode 1 read access ......................495 Figure 20-4. Mode 1 write access......................495 Figure 20-5. Mode A read access ......................496 Figure 20-6. Mode A write access ......................497 Figure 20-7. Mode 2/B read access ......................498 Figure 20-8.
Page 21: List Of Tables
GD32C10x User Manual List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix ........24 Table 1-2. Memory map of GD32C10x devices ..................27 Table 1-3. Boot modes ..........................31 Table 2-1. GD32C10x base address and size for flash memory ............35 Table 2-2.
Page 22 GD32C10x User Manual Table 16-2. Complementary outputs controlled by parameters ............257 Table 16-3. Counting direction in different quadrature decoder mode..........260 Table 16-4. Examples of slave mode ..................... 263 Table 16-5. Examples of slave mode ..................... 309 Table 16-6．Examples of slave mode ....................344 Table 17-1.
Page 23: System And Memory Architecture
GD32C10x User Manual System and memory architecture The devices of GD32C10x series are 32-bit general-purpose microcontrollers based on the ® Cortex ® -M4 processor. The ARM ® Cortex ® -M4 processor includes three AHB buses which are known as I-Code bus, D-Code bus and System bus. All memory accesses of the ®...
Page 24: System Architecture
GD32C10x User Manual ® Figure 1-1. The structure of the Cortex -M4 processor Cortex-M4 processor Cortex-M4 core Nested Interrupts and Vectored Power control Interrupt Floating Point Controller Unit(FPU) (NVIC) Wake-up Interrupt Controller (WIC) Data Flash Patch Watchpoint Breakpoint And Trace (FPB) (WDT) Serial-Wire...
Page 25 GD32C10x User Manual IBUS DBUS SBUS DMA0 DMA1 EXMC APB1 APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, ® including IBUS, DBUS, SBUS, DMA0, DMA1. IBUS is the instruction bus of the Cortex core, which is used for fetching instruction/vector from the Code region (0x0000 0000 ~ ®...
Page 26: Memory Map
GD32C10x User Manual Figure 1-2. GD32C10x series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M4 Memory Controller : 120MHz Processor Dbus Fmax:120MHz USBFS 1.2V NVIC Master AHB Peripherals Slave 8MHz GP DMA 12 chs SRAM SRAM Controller Master Slave...
Page 27: Table 1-2. Memory Map Of Gd32C10X Devices
GD32C10x User Manual ® address space. The maximum address range of the Cortex -M4 is 4-Gbyte due to its 32-bit ® bus address width. Additionally, a pre-defined memory map is provided by the Cortex processor to reduce the software complexity of repeated implementation for different device vendors.
Page 28 GD32C10x User Manual Pre-defined Address Peripherals regions 0x4002 1000 - 0x4002 13FF 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 0x4001 8000 - 0x4001 83FF Reserved...
Page 29 GD32C10x User Manual Pre-defined Address Peripherals regions 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF...
Page 30: Bit-Banding
GD32C10x User Manual Pre-defined Address Peripherals regions 0x2002 0000 - 0x2002 FFFF Reserved 0x2001 C000 - 0x2001 FFFF Reserved 0x2001 8000 - 0x2001 BFFF Reserved 0x2000 8000 - 0x2001 7FFF Reserved 0x2000 0000 - 0x2000 7FFF SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes...
Page 31: On-Chip Sram Memory
GD32C10x User Manual where:  bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.  bit_band_base is the starting address of the alias region.  byte_offset is the number of the byte in the bit-band region that contains the targeted bit. ...
Page 32: Device Electronic Signature
GD32C10x User Manual 0004 in sequence. Then, starts code execution from the base address of boot code. Due to the selected boot source, either the main flash memory (original memory space is beginning at 0x0800 0000) or the system memory (original memory space is beginning at 0x1FFF F000) is aliased in the boot memory space which begins at 0x0000 0000.
Page 33: Memory Density Information
GD32C10x User Manual Memory density information 1.4.1. Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY[15: SRAM density The value indicates the on-chip SRAM density of the device in Kbytes. Example: 0x0008 indicates 8 Kbytes.
Page 34: System Configuration Registers
GD32C10x User Manual Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID 1.5. System configuration registers Base address: 0x4002 103C Reset value: 0x0000 0000 Reserved...
Page 35: Flash Memory Controller (Fmc)
GD32C10x User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 128K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 36: Read Operations
GD32C10x User Manual Block Name Address range size(bytes) Information Block Boot Loader area 0x1FFF B000- 0x1FFF F7FF 18KB Option bytes Option bytes 0x1FFF F800 - 0x1FFF F80F Block One-time OTP bytes 0x1FFF_7000~0x1FFF_71FF 512B program Block The Information Block stores the boot loader. This block cannot be programmed or Note: erased by user.
Page 37: Unlock The Fmc_Ctl Register
GD32C10x User Manual store in current buffer. The CPU only need 32-bit or 16-bit in each read operation. So in the case of sequential code, the next data can get from current buffer without repeat fetch from flash memory. Pre-fetch buffer: The pre-fetch buffer is enabled by set the PFEN bit in the FMC_WS register.
Page 38: Page Erase
GD32C10x User Manual The OBPG bit and OBER bit in the FMC_CTL are still protected even the FMC_CTL is unlocked. The unlocking sequence consists of two write operations, which are writing 0x45670123 and 0xCDEF89AB to the FMC_OBKEY register. Then the hardware sets the OBWEN OBWEN bit in the FMC_CTL register to 1.
Page 39: Mass Erase
GD32C10x User Manual Figure 2-1. Process of page erase operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish Mass erase...
Page 40: Main Flash Programming
GD32C10x User Manual and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. Since all flash data will be modified to a value of 0xFFFF_FFFF, the mass erase operation can be implemented using a program that runs in SRAM or using the debugging tool that accesses the FMC registers directly.
Page 41 GD32C10x User Manual  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in the FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
Page 42: Otp Programming
GD32C10x User Manual 1(64-bit program to flash memory), the 2 DBUS write must double-word alignment and belong to same double-word address. Note: If the program is not write total 64bits/32bits ( by set the PGW bit in the FMC_WS ), the data is not program to the flash memory without any notice. register In these conditions, a flash operation error interrupt will be triggered by the FMC if the ERRIE bit in the FMC_CTL register is set.
Page 43: Option Bytes Erase
GD32C10x User Manual little probability of corrupt the data stored in flash memory. Option bytes Erase 2.3.8. The FMC provides an erase function which is used to initialize the option bytes block in flash. The following steps show the erase sequence. ...
Page 44: Option Bytes Description
GD32C10x User Manual Note that there programming errors may occur. The PGERR bit and PGAERR bit can be set which is similar to main flash programming. The modified option bytes only take effect after a system reset. Option bytes description 2.3.10.
Page 45: Page Erase/Program Protection
GD32C10x User Manual Address Name Description WP[30:24]: Each bit is related to 4KB flash protection. These bits totally controls the first 124KB flash protection. WP[31]: Bit 31 controls the protection of the rest flash memory. 0x1fff f80f WP_N[31:24] WP complement value bit 31 to 24 Page erase/program protection 2.3.11.
Page 46: Register Definition
GD32C10x User Manual 2.4. Register definition FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0630 This register has to be accessed by word (32-bit) Reserved Reserved DCRST ICRST DCEN ICEN Reserved PFEN Reserved WSCNT[2:0] Bits...
Page 47: Unlock Key Register (Fmc_Key)
GD32C10x User Manual 1: Pre-fetch enable Reserved Must be kept at reset value. WSCNT[2:0] Wait state counter register These bits is set and reset by software. 000: 0 wait state added 001: 1 wait state added 010: 2 wait state added 011: 3 wait state added 100 ~111:reserved Unlock key register (FMC_KEY)
Page 48: Status Register (Fmc_Stat)
GD32C10x User Manual 31:0 OBKEY[31:0] FMC_CTL option bytes operation unlock register These bits are only be written by software. Write OBKEY[31:0] with keys to unlock option bytes command in the FMC_CTL register. Status register (FMC_STAT) 2.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved...
Page 49 GD32C10x User Manual This register has to be accessed by word (32-bit) Reserved Reserved ENDIE Reserved ERRIE OBWEN Reserved START OBER OBPG Reserved Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. ENDIE End of operation interrupt enable bit This bit is set or cleared by software 0: no interrupt generated by hardware.
Page 50: Address Register (Fmc_Addr)
GD32C10x User Manual Reserved Must be kept at reset value. Main flash mass erase command bit This bit is set or cleared by software 0: no effect 1: main flash mass erase command Main flash page erase command bit This bit is set or clear by software 0: no effect 1: main flash page erase command Main flash program command bit...
Page 51: Erase/Program Protection Register (Fmc_Wp)
GD32C10x User Manual DATA[5:0] USER[7:0] OBERR Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:10 DATA[15:0] Store DATA[15:0] of option bytes block after system reset. USER[7:0] Store USER of option bytes block after system reset. Option bytes security protection code 0: no protection 1: protection OBERR...
Page 52 GD32C10x User Manual PID[15:0] Bits Field Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by software. These bits are unchanged constant after power on. These bits are one time program when the chip produced.
Page 53: Power Management Unit (Pmu)
GD32C10x User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32C10x series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve a best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 54: Backup Domain
GD32C10x User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP WKUPR BREG BKP PAD WKUPN NRST WKUPF SLEEPING Cortex-M4 FWDGT SLEEPDEEP HXTAL POR / PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K IRC48M...
Page 55: Vdd / V Dda
GD32C10x User Manual event. After entering the power saving mode for a certain amount of time, the RTC will wake up the device when the time match event occurs. The details of the RTC configuration and Real-time Clock (RTC). operation will be described in the When the backup domain is supplied by V pin is connected to V ), the following...
Page 56: Figure 3-3. Waveform Of The Lvd Threshold
GD32C10x User Manual Figure 3-2. Waveform of the POR / PDR 40mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register (PMU_CTL). The LVD is enabled by setting the LVDEN bit in the PMU_CTL register.
Page 57: Power Domain
GD32C10x User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply is implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V...
Page 58 GD32C10x User Manual wake up the system (If SEVONPEND is 1, any interrupt can wake up the system, refer to ® Cortex -M4 Technical Reference Manual). The mode costs the lowest wakeup time as no time is wasted in interrupt entry or exit. ®...
Page 59: Table 3-1. Power Saving Mode Summary
GD32C10x User Manual ® Standby mode, a power-on reset occurs and the Cortex -M4 will execute instruction code from the 0x0000 0000 address. Table 3-1. Power saving mode summary Mode Sleep Deep-sleep Standby All clocks in the 1.2V The 1.2V domain is domain are off powered off Description...
Page 60: Register Definition
GD32C10x User Manual 3.4. Register definition PMU base address: 0x4000 7000 Control register (PMU_CTL) 3.4.1. Address offset: 0x00 Reset value: 0x0000 4000 (reset after wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit) Reserved LDOVS[1:0] Reserved BKPWEN LVDT[2:0] LVDEN...
Page 61: Control And Status Register (Pmu_Cs)
GD32C10x User Manual 111: 3.1V LVDEN Low Voltage Detector Enable 0: Disable Low Voltage Detector 1: Enable Low Voltage Detector STBRST Standby Flag Reset 0: No effect 1: Reset the standby flag This bit is always read as 0. WURST Wakeup Flag Reset 0: No effect 1: Reset the wakeup flag...
Page 62 GD32C10x User Manual will trigger a wakeup event when the input is already high. Reserved Must be kept at reset value. LVDF Low Voltage Detector Status Flag 0: Low Voltage event has not occurred (V is higher than the specified LVD threshold) 1: Low Voltage event occurred (V is equal to or lower than the specified LVD...
Page 63: Backup Registers (Bkp)
GD32C10x User Manual Backup registers (BKP) 4.1. Overview The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down, they are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from Standby mode or system reset will not affect these registers.
Page 64 GD32C10x User Manual and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the value of the edge detection signal logically ANDed with the TPEN bit, is used as the input of tamper detection signal.
Page 65: Register Definition
GD32C10x User Manual 4.4. Register definition BKP base address: 0x4000 6C00 Backup data register x (BKP_DATAx) (x= 0..41) 4.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) DATA [15:0] Bits Fields...
Page 66: Tamper Pin Control Register (Bkp_Tpctl)
GD32C10x User Manual 0: RTC alarm pulse is selected as the RTC output 1: RTC second pulse is selected as the RTC output This bit is reset only by a Backup domain reset. ASOEN RTC alarm or second signal output enable 0: Disable RTC alarm or second output 1: Enable RTC alarm or second output When enabled, the TAMPER pin will output the RTC output.
Page 67: Tamper Control And Status Register (Bkp_Tpcs)
GD32C10x User Manual Tamper control and status register (BKP_TPCS) 4.4.4. Address offset: 0x34 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved TPIE Bits Fields Descriptions 15:10 Reserved Must be kept at reset value. Tamper interrupt flag 0: No tamper interrupt occurred 1: A tamper interrupt occurred...
Page 68: Reset And Clock Unit (Rcu)
GD32C10x User Manual Reset and clock unit (RCU) 5.1. Reset control unit (RCTL) Overview 5.1.1. Reset control uint includes three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 69: Clock Control Unit (Cctl)
GD32C10x User Manual Figure 5-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on in case of both supplies have been powered off previously).
Page 70: Figure 5-2. Clock Tree
GD32C10x User Manual Figure 5-2. Clock tree CK_IRC48M CK_CTC 48 MHz 48 MHz IRC48M CK48MSEL USBFS CK_USBFS Prescaler (to USBFS) 1,1.5,2,2.5 SCS[1:0] 3,3.5,4 CK_IRC8M 8 MHz CK_AHB ×2,3,4 CK_EXMC CK_PLL CK_SYS IRC8M 120 MHz max Prescaler EXMC enable 120 MHz max (to EXMC) ÷...
Page 71: Characteristics
GD32C10x User Manual RCU_CFG1 register. The RTC is clocked by LXTAL clock, IRC40K clock or HXTAL clock divided by 128 (defined which clock selected by RTCSRC bit in backup domain control register (RCU_BDCTL)). After the RTC select HXTAL clock divided by 128, the clock disappeared when the 1.2V core domain power off.
Page 72: Figure 5-4. Hxtal Clock Source In Bypass Mode
GD32C10x User Manual is set. At this point the HXTAL clock can be used directly as the system clock source or the PLL input clock. Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the Control Register RCU_CTL. During bypass mode, the signal is connected to OSCIN, and Figure 5-4.
Page 73 GD32C10x User Manual operating frequency is still not enough accurate, because the USB need the frequency must between 48MHz with 500ppm accuracy. A hardware automatic dynamic trim performed in CTC unit adjust the IRC48M to the needed frequency. Phase locked loop (PLL) There are three internal Phase Locked Loop, the PLL, PLL1 and PLL2.
Page 74: Table 5-1. Clock Output 0 Source Select
GD32C10x User Manual in the clock interrupt register (RCU_INT) is set when the IRC40K becomes stable. The IRC40K can be trimmed by TIMER4_CH3, user can get the clocks frequency, and adjust the RTC and FWDGT counter. Please refer to TIMER4CH3_IREMAP in AFIO_PCF0 register. System clock (CK_SYS) selection After the system reset, the default CK_SYS source will be IRC8M and can be switched to HXTAL or CK_PLL by changing the system clock switch bits, SCS, in the clock configuration...
Page 75: Table 5-2. 1.2V Domain Voltage Selected In Deep-Sleep Mode
GD32C10x User Manual Clock Source 0 Selection bits Clock Source 1100 CK_IRC48M 1101 CK_IRC48M/8 Voltage control The 1.2V domain voltage in Deep-sleep mode can be controlled by DSLPVS[1:0] bit in the Deep-sleep mode voltage register (RCU_DSV). Table 5-2. 1.2V domain voltage selected in deep-sleep mode DSLPVS[1:0] Deep-sleep mode voltage(V)
Page 76: Register Definition
GD32C10x User Manual 5.3. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) HXTAL HXTAL HXTALE Reserved...
Page 77 GD32C10x User Manual 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock. Reset by hardware when entering Deep-sleep or Standby mode. 0: PLL is switched off 1: PLL is switched on 23:20...
Page 78: Clock Configuration Register 0 (Rcu_Cfg0)
GD32C10x User Manual Reserved Must be kept at reset value. IRC8MSTB Internal 8MHz RC oscillator stabilization flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator enable Set and reset by software.
Page 79 GD32C10x User Manual 1000: CK_PLL1 clock selected 1001: CK_PLL2 clock divided by 2 selected 1010: CK_HXTAL clock selected 1011: CK_PLL2 clock selected 1100: CK_IRC48M clock selected 1101: CK_IRC48M clock divided by 8 selected 23:22 USBFSPSC[1:0] USBFS clock prescaler selection Bit 31 of RCU_CFG0 and these bits are written by software to control the USBFS clock prescaler value.
Page 80 GD32C10x User Manual 10110: (PLL source clock x 23) 10111: (PLL source clock x 24) 11000: (PLL source clock x 25) 11001: (PLL source clock x 26) 11010: (PLL source clock x 27) 11011: (PLL source clock x 28) 11100: (PLL source clock x 29) 11101: (PLL source clock x 30) 11110: (PLL source clock x 31) 11111: (PLL source clock x 31)
Page 81: Clock Interrupt Register (Rcu_Int)
GD32C10x User Manual 10:8 APB1PSC[2:0] APB1 prescaler selection Set and reset by software to control the APB1 clock division ratio. Caution: The CK_APB1 output frequency must not exceed 60 MHz. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected AHBPSC[3:0]...
Page 82 GD32C10x User Manual PLL2 PLL1 HXTAL IRC8M LXTAL IRC40 Reserved CKMIC STBIC STBIC STBIC STBIC STBIC STBIC STBIC K PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIF STBIE STBIE STBIE STBIE STBIE STBIE STBIE STBIF STBIF STBIF...
Page 83 GD32C10x User Manual IRC40KSTBIC IRC40K stabilization interrupt clear Write 1 by software to reset the IRC40KSTBIF flag. 0: Not reset IRC40KSTBIF flag 1: Reset IRC40KSTBIF flag Reserved Must be kept at reset value. PLL2STBIE PLL2 stabilization interrupt enable Set and reset by software to enable/disable the PLL2 stabilization interrupt. 0: Disable the PLL2 stabilization interrupt 1: Enable the PLL2 stabilization interrupt PLL1STBIE...
Page 84 GD32C10x User Manual Set by hardware when the PLL2 is stable and the PLL2STBIE bit is set. Reset when setting the PLL2STBIC bit by software. 0: No PLL2 stabilization interrupt generated 1: PLL2 stabilization interrupt generated PLL1STBIF PLL1 stabilization interrupt flag Set by hardware when the PLL1 is stable and the PLL1STBIE bit is set.
Page 85: Apb2 Reset Register (Rcu_Apb2Rst)
GD32C10x User Manual APB2 reset register (RCU_APB2RST) 5.3.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) TIMER10 TIMER9 TIMER8 Reserved Reserved USART0 TIMER7 TIMER0 ADC1 ADC0 Reserved SPI0RST Reserved PERST PDRST PCRST PBRST PARST...
Page 86 GD32C10x User Manual 1: Reset the SPI0 TIMER0RST Timer 0 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER0 ADC1RST ADC1 reset This bit is set and reset by software. 0: No reset 1: Reset the ADC1 ADC0RST ADC0 reset...
Page 87: Apb1 Reset Register (Rcu_Apb1Rst)
GD32C10x User Manual 1: Reset Alternate Function I/O APB1 reset register (RCU_APB1RST) 5.3.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) CAN1 CAN0 UART4 UART3 USART2 USART1 Reserved DACRST PMURST BKPIRST Reserved I2C1RST I2C0RST Reserved...
Page 88 GD32C10x User Manual I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C1 I2C0RST I2C0 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C0 UART4RST UART4 reset This bit is set and reset by software.
Page 89 GD32C10x User Manual 10:9 Reserved Must be kept at reset value. TIMER13RST TIMER13 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER13 TIMER12RST TIMER12 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER12 TIMER11RST...
Page 90: Ahb Enable Register (Rcu_Ahben)
GD32C10x User Manual AHB enable register (RCU_AHBEN) 5.3.6. Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved USBFS FMCSP SRAMSP Reserved Reserved EXMCEN Reserved CRCEN Reserved Reserved DMA1EN DMA0EN Bits Fields Descriptions 31:13 Reserved...
Page 91: Apb2 Enable Register (Rcu_Apb2En)
GD32C10x User Manual 0: Disabled SRAM interface clock during Sleep mode. 1: Enabled SRAM interface clock during Sleep mode DMA1EN DMA1 clock enable This bit is set and reset by software. 0: Disabled DMA1 clock 1: Enabled DMA1 clock DMA0EN DMA0 clock enable This bit is set and reset by software.
Page 92 GD32C10x User Manual USART0EN USART0 clock enable This bit is set and reset by software. 0: Disabled USART0 clock 1: Enabled USART0 clock TIMER7EN TIMER7 clock enable This bit is set and reset by software. 0: Disabled TIMER7 clock 1: Enabled TIMER7 clock SPI0EN SPI0 clock enable This bit is set and reset by software.
Page 93: Apb1 Enable Register (Rcu_Apb1En)
GD32C10x User Manual 0: Disabled GPIO port B clock 1: Enabled GPIO port B clock PAEN GPIO port A clock enable This bit is set and reset by software. 0: Disabled GPIO port A clock 1: Enabled GPIO port A clock Reserved Must be kept at reset value.
Page 94 GD32C10x User Manual 1: Enabled Backup interface clock CAN1EN CAN1 clock enable This bit is set and reset by software. 0: Disabled CAN1 clock 1: Enabled CAN1 clock CAN0EN CAN0 clock enable This bit is set and reset by software. 0: Disabled CAN0 clock 1: Enabled CAN0 clock 24:23...
Page 95 GD32C10x User Manual 1: Enabled SPI2 clock SPI1EN SPI1 clock enable This bit is set and reset by software. 0: Disabled SPI1 clock 1: Enabled SPI1 clock 13:12 Reserved Must be kept at reset value. WWDGTEN WWDGT clock enable This bit is set and reset by software. 0: Disabled WWDGT clock 1: Enabled WWDGT clock 10:9...
Page 96: Backup Domain Control Register (Rcu_Bdctl)
GD32C10x User Manual 1: Enabled TIMER3 clock TIMER2EN TIMER2 clock enable This bit is set and reset by software. 0: Disabled TIMER2 clock 1: Enabled TIMER2 clock TIMER1EN TIMER1 clock enable This bit is set and reset by software. 0: Disabled TIMER1 clock 1: Enabled TIMER1 clock Backup domain control register (RCU_BDCTL) 5.3.9.
Page 97: Reset Source/Clock Register (Rcu_Rstsck)
GD32C10x User Manual source has been selected, it cannot be changed anymore unless the Backup domain is reset. 00: No clock selected 01: CK_LXTAL selected as RTC source clock 10: CK_IRC40K selected as RTC source clock 11: (CK_HXTAL / 128) selected as RTC source clock Reserved Must be kept at reset value.
Page 98 GD32C10x User Manual Bits Fields Descriptions LPRSTF Low-power reset flag Set by hardware when Deep-sleep /standby reset generated. Reset by writing 1 to the RSTFC bit. 0: No Low-power management reset generated 1: Low-power management reset generated WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated.
Page 99: Ahb Reset Register (Rcu_Ahbrst)
GD32C10x User Manual IRC40KSTB IRC40K stabilization flag Set by hardware to indicate if the IRC40K output clock is stable and ready for use. 0: IRC40K is not stable 1: IRC40K is stable IRC40KEN IRC40K enable Set and reset by software. 0: Disable IRC40K 1: Enable IRC40K AHB reset register (RCU_AHBRST)
Page 100 GD32C10x User Manual PLL2MF[3:0] PLL1MF[3:0] PREDV1[3:0] PREDV0[3:0] Bits Fields Descriptions Reserverd Must be kept at reset value. PLLPRESEL PLL clock source selection 0: HXTAL selected as PLL source clock 1: CK_IRC48M selected as PLL source clock ADCPSC[3] Bit 4 of ADCPSC see bits 15:14 of RCU_CFG0 and bit 28 of RCU_CFG0 28:19 Reserved...
Page 101 GD32C10x User Manual 00xx: reserve 010x: reserve 0110: (PLL1 source clock x 8) 0111: (PLL1 source clock x 9) 1000 :(PLL1 source clock x 10) 1001: (PLL1 source clock x 11) 1010: (PLL1 source clock x 12) 1011: (PLL1 source clock x 13) 1100: (PLL1 source clock x 14) 1101: reserve 1110 :(PLL1 source clock x 16)
Page 102: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32C10x User Manual 0111: PREDV0 input source clock divided by 8 1000: PREDV0 input source clock divided by 9 1001: PREDV0 input source clock divided by 10 1010: PREDV0 input source clock divided by 11 1011: PREDV0 input source clock divided by 12 1100: PREDV0 input source clock divided by 13 1101: PREDV0 input source clock divided by 14 1110: PREDV0 input source clock divided by 15...
Page 103: Additional Clock Interrupt Register (Rcu_Addint)
GD32C10x User Manual Bits Fields Descriptions 31:24 IRC48MCALIB [7:0] Internal 48MHz RC oscillator calibration value register These bits are load automatically at power on. 23:18 Reserved Must be kept at reset value. IRC48MSTB Internal 48MHz RC oscillator clock stabilization flag Set by hardware to indicate if the IRC48M oscillator is stable and ready for use.
Page 104: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32C10x User Manual Write 1 by software to reset the IRC48MSTBIF flag. 0: Not reset IRC48MSTBIF flag 1: Reset IRC48MSTBIF flag 21:15 Reserved Must be kept at reset value. IRC48MSTBIE Internal 48 MHz RC oscillator stabilization Interrupt enable Set and reset by software to enable/disable the IRC48M stabilization interrupt 0: Disable the IRC48M stabilization interrupt 1: Enable the IRC48M stabilization interrupt 13:7...
Page 105: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32C10x User Manual APB1 additional enable register (RCU_ADDAPB1EN) 5.3.17. Address offset: 0xE4 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved CTCEN Reserved Reserved Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. CTCEN CTC clock enable This bit is set and reset by software.
Page 106: Clock Trim Controller (Ctc)
GD32C10x User Manual Clock trim controller (CTC) 6.1. Overview The clock trim controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trims the frequency of the IRC48M which is based on an external accurate reference signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 107: Reference Sync Pulse Generator
GD32C10x User Manual Figure 6-1. CTC overview PCLK1 APB1 BUS Register REFSEL REFPSC SWREFPUL Reserved CTC_SYNC Prescaler (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM Reference sync pulse generator 6.3.1.
Page 108: Frequency Evaluation And Automatic Trim Process
GD32C10x User Manual counter down-counts to zero, and then up-counts to 128 x CKLIM (defined in CTC_CTL1 register), and then stops until next REF sync pulse is detected. If any REF sync pulse is detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 109: Software Program Guide
GD32C10x User Manual bit in CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register is set, the TRIMVALUE in CTC_CTL0 register is not changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. When the CKOKIF in CTC_STAT register is set, an interrupt will be generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 110 GD32C10x User Manual CKLIM= ( F ÷ F ) ×0.12% ÷2 (6-2) clock The typical step size is 0.12%. Where the F is the frequency of correct clock (IRC48M), clock the F is the frequency of reference sync pulse.
Page 111: Register Definition
GD32C10x User Manual 6.4. Register definition CTC base address: 0x4000 C800 Control register 0 (CTC_CTL0) 6.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE ERRIE CKOKIE TRIM...
Page 112: Control Register 1 (Ctc_Ctl1)
GD32C10x User Manual trim counter. When this bit is set, the CTC_CTL1 register cannot be modified. 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE Expected reference (EREFIF) interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable...
Page 113: Status Register (Ctc_Stat)
GD32C10x User Manual 01: LXTAL clock selected 10: Reserved 11: Reserved. Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8 100: Reference signal divided by 16...
Page 114 GD32C10x User Manual When a reference sync pulse occurs during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value. TRIMERR Trim value error bit This bit is set by hardware when the TRIMVALUE in CTC_CTL0 register is overflow or underflow.
Page 115: Interrupt Clear Register (Ctc_Intc)
GD32C10x User Manual CTC_INTC register. 0: No Error occurs 1: An error occurs CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurs. If the CTC trim counter is greater than or equal to 3 x CKLIM and is smaller than 128 x CKLIM when a reference sync pulse is detected, this bit will be set.
Page 116 GD32C10x User Manual This bit is written by software and read as 0. Write 1 to clear ERRIF, TRIMERR, REFMISS and CKERR bits in CTC_STAT register. Writing 0 has no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register.
Page 117: Interrupt / Event Controller (Exti)
GD32C10x User Manual Interrupt / event controller (EXTI) 7.1. Overview ® Cortex -M4 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processor core. You can read the ®...
Page 118: Table 7-1. Nvic Exception Types In Cortex ® -M4
GD32C10x User Manual ® Table 7-1. NVIC exception types in Cortex Vector Exception type Priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access Programmable 0x0000_0014...
Page 119 GD32C10x User Manual Interrupt Vector Interrupt description Vector address number number DMA0 channel3 global 0x0000_0078 IRQ 14 interrupt DMA0 channel4 global 0x0000_007C IRQ 15 interrupt DMA0 channel5 global IRQ 16 0x0000_0080 interrupt DMA0 channel6 global IRQ 17 0x0000_0084 interrupt ADC0 and ADC1 global IRQ 18 0x0000_0088 interrupts...
Page 120 GD32C10x User Manual Interrupt Vector Interrupt description Vector address number number TIMER7 break interrupt and 0x0000_00EC IRQ 43 TIMER11 global interrupt TIMER7 update and 0x0000_00F0 IRQ 44 TIMER12 global interrupts TIMER7 trigger and Channel IRQ 45 commutation and TIMER13 0x0000_00F4 global interrupts TIMER7 channel capture IRQ 46...
Page 121: External Interrupt And Event Block Diagram
GD32C10x User Manual 7.4. External interrupt and event block diagram Figure 7-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~18 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 7.5. External interrupt and event function overview The EXTI contains up to 19 independent edge detectors and generates interrupts request or event to the processor.
Page 122: Table 7-3. Exti Source
GD32C10x User Manual Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in AFIO module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 123: Register Definition
GD32C10x User Manual 7.6. Register definition EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 7.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7...
Page 124: Rising Edge Trigger Enable Register (Exti_Rten)
GD32C10x User Manual Rising edge trigger enable register (EXTI_RTEN) 7.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6 RTEN5 RTEN4 RTEN3 RTEN2...
Page 125: Pending Register (Exti_Pd)
GD32C10x User Manual Reserved SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. Interrupt / event software trigger (x = 0…18) 18:0 SWIEVx 0: Deactivate the EXTIx software interrupt / event request...
Page 126: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32C10x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 8.1. Overview There are up to 80 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15 and PE0 ~ PE15 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications.
Page 127: Gpio Pin Configuration
GD32C10x User Manual don’t care Input floating Input pull-down Input pull-up 00: Reserved Push-pull 0 or 1 General purpose 01: Speed up to 10MHz Output (GPIO) Open-drain 0 or 1 10: Speed up to 2MHz 11: Speed up to 50MHz don’t care Push-pull Alternate Function...
Page 128: External Interrupt/Event Lines
GD32C10x User Manual The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen. And the data on the external pins can be captured at every APB2 clock cycle to the port input status register (GPIOx_ISTAT).
Page 129: Output Configuration
GD32C10x User Manual Output configuration 8.3.5. When GPIO pin is configured as output.  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors are disabled.  The output buffer is enabled.  Open-drain mode, the pad outputs low level when setting “0” in the output control register;while the pad holds Hi-Z state when set “1”...
Page 130: Alternate Function (Af) Configuration
GD32C10x User Manual Figure 8-4. Basic structure of Analog configuration Alternate function (AF) configuration 8.3.7. To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software. When be configured as alternate function. ...
Page 131: Gpio I/O Compensation Cell
GD32C10x User Manual the corresponding port is locked and the corresponding port configuration cannot be modified until the next reset. It is recommended to be used in the configuration of driving a power module. GPIO I/O compensation cell 8.3.9. If the I/O port output speed need more than 50MHz, it is recommended to use the compensation cell for slew rate control to reduce the I/O noise effects on the power supply.
Page 132: Adc Af Remapping
GD32C10x User Manual Table 8-3. Debug port mapping and Pin availability SWJ_CFG Pin availability JTAG-DP and SW-DP [2:0] PA13 PA14 PA15 JTAG-DP Enabled and SW-DP Enabled (Reset state) JTAG-DP Enabled and SW-DP √ Enabled but without NJTRST JTAG-DP Disabled and SW- √...
Page 133: Timer Af Remapping
GD32C10x User Manual TIMER AF remapping 8.4.5. Table 8-5. TIMERx alternate function remapping TIMERx_REMAP [1:0](x = 0，1，2) Alternate TIMERx_REMAP(x = 8，9，10，12， function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER0_ETI PA12 TIMER0_CH0 TIMER0_CH1 PE11 TIMER0_CH2 PA10 PE13 TIMER0_CH3...
Page 134: Usart Af Remapping
GD32C10x User Manual 5. TIMER2 remap available only for 64-pin, 100-pin packages. TIMER3 r emap available only for 100-pin packages. 7. TIMER8 r efer to the AF remap and debug I/O configuration register 1(AFIO_PCF1). Table 8-6. TIMER4 alternate function remapping Alternate function TIMER4CH3_IREMAP = 0 TIMER4CH3_IREMAP = 1...
Page 135: I2C0 Af Remapping
GD32C10x User Manual PD11(USART2_CTS) PD12(USART2_RTS) 1. Remap available only 100-pin packages. 2. Remap available only for 64-pin,100-pin packages. 3. Remap available only 100-pin packages. I2C0 AF remapping 8.4.7. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-8. I2C0 alternate function remapping I2C0_SCL I2C0_SDA Register...
Page 136: Can0/1 Af Remapping
GD32C10x User Manual CAN0/1 AF remapping 8.4.9. The CAN0 signals can be mapped on Port A, Port B or Port D as shown in table below. For port D, remapping is not possible in devices delivered in 64-pin packages. Table 8-10. CAN0/1 alternate function remapping Register CAN0 CAN1...
Page 137: Table 8-13. Osc Pins Configuration
GD32C10x User Manual PD0/PD1 cannot be used for external interrupt/event generation on 36--pin, 48--pin and 64- pin packages. Table 8-13. OSC pins configuration Alternate function HXTAL= ON HXTAL = OFF OSC_IN OSC_OUT...
Page 138: Register Definition
GD32C10x User Manual 8.5. Register definition GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 AFIO base address: 0x4001 0000 Port control register 0 (GPIOx_CTL0, x=A..E) 8.5.1.
Page 139 GD32C10x User Manual Refer to MD0[1:0] description. 19:18 CTL4[1:0] Port 4 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description. 17:16 MD4[1:0] Port 4 mode bits These bits are set and cleared by software. Refer to MD0[1:0] description. 15:14 CTL3[1:0] Port 3 configuration bits...
Page 140: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32C10x User Manual 00: Input mode (reset state) 01: Output mode(10MHz) 10: Output mode(2MHz) 11: Output mode(50MHz) Port control register 1 (GPIOx_CTL1, x=A..E) 8.5.2. Address offset: 0x04 Reset value: 0x4444 4444 This register has to be accessed by word (32-bit). CTL15[1:0] MD15[1:0] CTL14[1:0]...
Page 141: Port Input Status Register (Gpiox_Istat, X=A
GD32C10x User Manual 17:16 MD12[1:0] Port 12 mode bits These bits are set and cleared by software. Refer to MD0[1:0] description. 15:14 CTL11[1:0] Port 11 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description. 13:12 MD11[1:0] Port 11 mode bits These bits are set and cleared by software.
Page 142: Port Output Control Register (Gpiox_Octl, X=A
GD32C10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 ISTATy Port input status(y=0..15) These bits are set and cleared by hardware. 0: Input signal low 1: Input signal high Port output control register (GPIOx_OCTL, x=A..E) 8.5.4.
Page 143: Port Bit Clear Register (Gpiox_Bc, X=A
GD32C10x User Manual Bits Fields Descriptions 31:16 Port clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0 BOPy Port set bit y(y=0..15) These bits are set and cleared by software.
Page 144: Port Bit Speed Register (Gpiox_Spd, X=A
GD32C10x User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. Lock sequence key It can only be set by using the lock key writing sequence. And it is always readable. 0: GPIO_LOCK register and the port configuration are not locked. 1: GPIO_LOCK register is locked until the MCU reset.
Page 145: Afio Port Configuration Register 0 (Afio_Pcf0)
GD32C10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved PORT[2:0] PIN[3:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. Event output enable Set and cleared by software.When this bit is set, the Cortex EVENTOUT output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits.
Page 146 GD32C10x User Manual PD01_ TIMER3_ TIMER2_REMAP TIMER1_REMAP USART1_ USART0_ I2C0_RE SPI0_REMA CAN0_REMAP [1:0] TIMER0_REMAP [1:0] USART2_ REMAP[1:0] REMAP REMAP [1:0] [1:0] REMAP REMAP Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. TIMER1ITI1_REMAP TIMER1 internal trigger 1 remapping These bits are set and cleared by software.
Page 147 GD32C10x User Manual 1: Connect the ADC0 external signal trigger routine conversion to TIM7_TRGO. Reserved Must be kept at reset value. TIMER4CH3_IREMAP TIMER4 channel3 internal remapping This bit is set and reset by software. 0: ConnectTIMER4_CH3 to PA3. 1: Connect the IRC40K internal clock to TIMER4_CH3 input in order to calibration. PD01_REMAP Port D0/Port D1 mapping to OSC_IN/OSC_OUT This bit is set and cleared by software.
Page 148 GD32C10x User Manual TIMER0_REMAP [1:0] TIMER0 remapping These bits are set and reset by software Disable remapping function(TIMER0_ETI/PA12, TIMER0_CH0/ PA8, TIMER0_CH1/PA9, TIMER0_CH2/PA10,TIMER0_CH3/PA11, TIMER0_BKIN/PB12, TIMER0_CH0_ON/PB13, TIMER0_CH1_ON/PB14, TIMER0_CH2_ON/PB15) 01: Enable the remapping function partially(TIMER0_ETI/PA12, TIMER0_CH0/ PA8, TIMER0_CH1/PA9, TIMER0_CH2/PA10,TIMER0_CH3/PA11, TIMER0_BKIN/PA6, TIMER0_CH0_ON/PA7, TIMER0_CH1_ON/PB0, TIMER0_CH2_ON/PB1) 10: Not used 11: Enable the remapping function fully(TIMER0_ETI/PE7, TIMER0_CH0/ PE9, TIMER0_CH1/PE11, TIMER0_CH2/PE13, TIMER0_CH3/PE14, TIMER0_BKIN/PE15,...
Page 149: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32C10x User Manual EXTI sources selection register 0 (AFIO_EXTISS0) 8.5.11. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI3_SS [3:0] EXTI2_SS [3:0] EXTI1_SS [3:0] EXTI0_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 150: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32C10x User Manual Other configurations are reserved. EXTI sources selection register 1 (AFIO_EXTISS1) 8.5.12. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions 31:16...
Page 151: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32C10x User Manual 0011: PD4 pin 0100: PE4 pin Other configurations are reserved. EXTI sources selection register 2 (AFIO_EXTISS2) 8.5.13. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI11_SS [3:0] EXTI10_SS [3:0] EXTI9_SS [3:0] EXTI8_SS [3:0] Bits...
Page 152: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32C10x User Manual 0001: PB8 pin 0010: PC8 pin 0011: PD8 pin 0100: PE8 pin Other configurations are reserved. EXTI sources selection register 3 (AFIO_EXTISS3) 8.5.14. Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI15_SS [3:0] EXTI14_SS [3:0]...
Page 153: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32C10x User Manual Other configurations are reserved. EXTI12_SS[3:0] EXTI12 sources selection 0000: PA12 pin 0001: PB12 pin 0010: PC12 pin 0011: PD12 pin 0100: PE12 pin Other configurations are reserved. AFIO port configuration register 1 (AFIO_PCF1) 8.5.15. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 154: Io Compensation Control Register (Afio_Cpsctl)
GD32C10x User Manual 0: Disable the remapping function (TIMER8_CH0 on PA2 and TIMER8_CH1 on PA3) 1: Enable the remapping function (TIMER8_CH0 on PE5 and TIMER8_CH1 on PE6) Reserved Must be kept at reset value. IO compensation control register (AFIO_CPSCTL) 8.5.16. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 155: Crc Calculation Unit (Crc)
GD32C10x User Manual CRC calculation unit (CRC) 9.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 32 bit CRC code with fixed polynomial. 9.2.
Page 156: Function Overview
GD32C10x User Manual Figure 9-1. Block diagram of CRC calculation unit Data Input Input Data Register (32 bit) CRC Calculation Unit Fixed polynomial 0x4C11DB7 Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) 9.3. Function overview ...
Page 157: Register Definition
GD32C10x User Manual 9.4. Register definition CRC base address: 0x4002 3000 Data register (CRC_DATA) 9.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA [31:16] DATA [15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads.
Page 158: Control Register (Crc_Ctl)
GD32C10x User Manual These bits are unrelated with CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register will take no effect to the byte. Control register (CRC_CTL) 9.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 159: Direct Memory Access Controller (Dma)
GD32C10x User Manual Direct memory access controller (DMA) 10.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 160: Block Diagram
GD32C10x User Manual 10.3. Block diagram Figure 10-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 161: Table 10-1. Dma Transfer Operation
GD32C10x User Manual transfer operation. Table 10-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 32 bits 32 bits 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 162: Peripheral Handshake
GD32C10x User Manual Peripheral handshake 10.4.2. To ensure a well-organized and efficient data transfer, a handshake mechanism is introduced between the DMA and peripherals, including a request signal and an acknowledge signal:  Request signal asserted by peripheral to DMA controller, indicating that the peripheral is ready to transmit or receive data.
Page 163: Circular Mode
GD32C10x User Manual In the increasing mode, the next address is equal to the current address plus 1 or 2 or 4, depending on the transfer data width. Circular mode 10.4.5. Circular mode is implemented to handle continue peripheral requests (for example, ADC scan mode).
Page 164: Dma Request Mapping
GD32C10x User Manual in the DMA_INTC register, and a dedicated enable bit in the DMA_CHxCTL register. The relationship is described in Table 10-2. Interrupt events. Table 10-2. Interrupt events Flag bit Clear bit Enable bit Interrupt event DMA_INTF DMA_INTC DMA_CHxCTL Full transfer finish FTFIF FTFIFC...
Page 165: Table 10-3. Dma0 Requests For Each Channel
GD32C10x User Manual peripheral for each channel of DMA1. Figure 10-4. DMA0 request mapping Hardware priority ADC0 TIMER1_CH2 high Channel 0 TIMER3_CH0 MEMTOMEM0 SPI0_RX USART2_TX TIMER0_CH0 Channel 1 TIMER1_UP TIMER2_CH2 MEMTOMEM2 MEMTOMEM1 SPI0_TX USART2_RX TIMER0_CH1 Channel 2 TIMER2_CH3 TIMER2_UP MEMTOMEM2 SPI1/I2S1_RX USART0_TX I2C1_TX...
Page 166: Figure 10-5. Dma1 Request Mapping
GD32C10x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● ● ● ● ● ● ADC0 ADC0 ● ● ● SPI/I2S SPI0_RX SPI0_TX SPI/I2S1_RX SPI/I2S1_TX ● USART USART2_TX USART2_RX USART0_TX USART0_RX USART1_RX USART1_TX ●...
Page 167 GD32C10x User Manual...
Page 168: Register Definition
GD32C10x User Manual 10.5. Register definition DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following registers are not suitable for DMA1. Interrupt flag register (DMA_INTF) 10.5.1.
Page 169: Interrupt Flag Clear Register (Dma_Intc)
GD32C10x User Manual Interrupt flag clear register (DMA_INTC) 10.5.2. Address offset: 0x04 Reset value: 0x0000 0000 Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0...
Page 170 GD32C10x User Manual 31:15 Reserved Must be kept at reset value. Memory to memory mode Software set and cleared 0: Disable memory to memory mode 1: Enable memory to memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level...
Page 171: Channel X Counter Register (Dma_Chxcnt)
GD32C10x User Manual 1: Enable circular mode This bit can not be written when CHEN is ‘1’. Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt Software set and cleared...
Page 172: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32C10x User Manual These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and it decreases after each DMA transfer. If the register is zero, no transaction can be issued whether the channel is enabled or not.
Page 173 GD32C10x User Manual 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address. When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these bits are ignored.
Page 174: Debug (Dbg)
GD32C10x User Manual Debug (DBG) 11.1. Overview The GD32C10x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM Cortex-M4.
Page 175: Jtag Daisy Chained Structure
GD32C10x User Manual The pin assignment is as following. PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST : JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. User can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions. (NJTRST tied to 1 by hardware).
Page 176: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32C10x User Manual debugger can debug in Deep-sleep mode. When the SLP_HOLD bit in DBG control register (DBG_CTL) is set, and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode.
Page 177: Register Definition
GD32C10x User Manual 11.4. Register definition DBG base address: 0xE004 2000 ID code register (DBG_ID) 11.4.1. Address: 0xE004 2000 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits can only be read by software.
Page 178 GD32C10x User Manual 0: no effect 1: hold the TIMER 9 counter for debugging when the core is halted TIMER8_HOLD TIMER 8 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER 8 counter for debugging when the core is halted TIMER13_HOLD TIMER 13 hold bit This bit is set and reset by software.
Page 179 GD32C10x User Manual I2C1_HOLD I2C1 hold bit This bit is set and reset by software. 0: no effect 1: hold the I2C1 status to avoid SMBUS timeout for debugging when the core is halted I2C0_HOLD I2C0 hold bit This bit is set and reset by software. 0: no effect 1: hold the I2C0 status to avoid SMBUS timeout for debugging when the core is halted...
Page 180 GD32C10x User Manual TRACE_IOEN Trace pin allocation enable This bit is set and reset by software. 0: Trace pin allocation disable 1: Trace pin allocation enable Reserved Must be kept at reset value STB_HOLD Standby mode hold register This bit is set and reset by software. 0: no effect 1: In the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, a system reset generated when exiting standby mode.
Page 181: Analog-To-Digital Converter (Adc)
GD32C10x User Manual Analog-to-digital converter (ADC) 12.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit(LSB) alignment or the most significant(MSB) bit alignment.
Page 182: Pins And Internal Signals
GD32C10x User Manual  Module supply requirements: 2.4V to 3.6V, and typical power supply voltage is 3.3V.  ≤V ≤V Channel input range: V REF- REF+ 12.3. Pins and internal signals Figure 12-1. ADC module block diagram shows the ADC block diagram. Table 12-1.
Page 183: Function Overview
GD32C10x User Manual 12.4. Function overview Figure 12-1. ADC module block diagram Trig select DMA request routine sequence Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO ADC_IN15 routine data registers SAR ADC Over sampler 6~12bit （16 bits） SENSE REFINT TOVS...
Page 184: Adc Clock
GD32C10x User Manual Set RSTCLB (optional). Set CLB=1. Wait for CLB=0. ADC clock 12.4.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller. ADC clock can be divided and configured by RCU controller. ADCON enable 12.4.3.
Page 185: Figure 12-3. Continuous Operation Mode
GD32C10x User Manual set. Software procedure for single operation mode of a routine channel: Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset. Configure RSQ0 with the analog channel number. Configure ADC_SAMPTx register. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need.
Page 186: Figure 12-4. Scan Operation Mode, Continuous Disable
GD32C10x User Manual Set the SWRCST bit, or generate an external trigger for the routine sequence. Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers.
Page 187: Conversion Result Threshold Monitor Function
GD32C10x User Manual corresponding software trigger or external trigger is active, the ADC samples and converts the next n channels configured in the ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set.
Page 188: Sample Time Configuration
GD32C10x User Manual Figure 12-7. 12-bit data storage mode 6-bit resolution data storage mode is different from 12-bit/10-bit/8-bit resolution data storage mode, shown as Figure 12-8. 6-bit data storage mode. Figure 12-8. 6-bit data storage mode Sample time configuration 12.4.8. The number of CK_ADC cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers.
Page 189: Dma Request
GD32C10x User Manual ETSRC[2:0] Trigger Source Trigger Type TIMER7_TRGO Software trigger SWRCST DMA request 12.4.10. The DMA request, which is enabled by the DMA bit of ADC_CTL1 register, is used to transfer data of routine sequence for conversion of more than one channel. The ADC generates a DMA request at the end of conversion of a routine channel.
Page 190: Programmable Resolution (Dres)
GD32C10x User Manual Programmable resolution (DRES) 12.4.12. The resolution is configured by programming the DRES[1:0] bits in the ADC_OVSAMPCTL register. For applications that do not require high data accuracy, lower resolution allows faster conversion time. The DRES[1:0] bits must only be changed when the ADCON bit is reset. Lower resolution reduces the conversion time needed for the successive approximation steps as shown in Table 12-4.
Page 191: Figure 12-9. 20-Bit To 16-Bit Result Truncation
GD32C10x User Manual Figure 12-9. 20-bit to 16-bit result truncation Raw 20-bit data Shifting Truncation and rounding Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated. Figure 12-10. A numerical example with 5-bit shifting and rounding shows a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.
Page 192: Adc Sync Mode
GD32C10x User Manual 0x1FFE 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x001F 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 128x...
Page 193: Free Mode
GD32C10x User Manual Figure 12-11. ADC sync block diagram Routine Routine data registers （16 bits） channels ADC1 (slave) ADC_IN0 ADC_IN1 GPIO Routine Routine data registers （16 bits） channels ADC_IN15 SENSE REFINT Syncl mode control ADC0 EXTI11 Routine (master) trigger mux Free mode 12.5.1.
Page 194: Routine Follow-Up Fast Mode
GD32C10x User Manual 2. Two channels sampled by two ADCs at the same time should be configured with the same sampling time. Figure 12-12. Routine parallel mode on 10 channels · · · · · · ADC0 · · · ·...
Page 195: Adc Interrupts
GD32C10x User Manual after 14 ADC clock cycles, after the second 14 ADC clock cycles the ADC1 runs again. Continuous mode can’t be used in this mode, because it continuously converts the routine channel. The behavior of follow-up slow mode shows in the Figure 12-14.
Page 196: Register Definition
GD32C10x User Manual 12.7. Register definition ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 Status register (ADC_STAT) 12.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved STRC Reserved rc_w0 rc_w0 rc_w0 Bits...
Page 197 GD32C10x User Manual This register has to be accessed by word(32-bit) Reserved RWDEN Reserved SYNCM[3:0] DISNUM[2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. RWDEN Routine channel analog watchdog enable 0: Analog watchdog disable 1: Analog watchdog enable 22:20...
Page 198: Control Register 1 (Adc_Ctl1)
GD32C10x User Manual Reserved Must be kept at reset value. WDEIE Interrupt enable for WDE 0: Interrupt disable 1: Interrupt enable EOCIE Interrupt enable for EOC 0: Interrupt disable 1: Interrupt enable WDCHSEL[4:0] Analog watchdog channel select 00000: ADC channel0 00001: ADC channel1 00010: ADC channel2 00011: ADC channel 3...
Page 199 GD32C10x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TSVREN Channel 16 and 17 enable of ADC0. 0: Channel 16 and 17 of ADC0 disable 1: Channel 16 and 17 of ADC0 enable SWRCST Software start conversion of routine sequence Set 1 on this bit starts a conversion of a routine sequence if ETSRC is 111.
Page 200: Sample Time Register 0 (Adc_Sampt0)
GD32C10x User Manual 1: Initialize calibration register start ADC calibration 0: Calibration done 1: Calibration start Continuous mode 0: Continuous operation mode disable 1: Continuous operation mode enable ADCON ADC ON. The ADC will be wake up when this bit is changed from low to high and take a stabilization time.
Page 201: Sample Time Register 1 (Adc_Sampt1)
GD32C10x User Manual 010: channel sampling time is 13.5 cycles 011: channel sampling time is 28.5 cycles 100: channel sampling time is 41.5 cycles 101: channel sampling time is 55.5 cycles 110: channel sampling time is 71.5 cycles 111: channel sampling time is 239.5 cycles Sample time register 1 (ADC_SAMPT1) 12.7.5.
Page 202: Watchdog High Threshold Register (Adc_Wdht)
GD32C10x User Manual 110: channel sampling time is 71.5 cycles 111: channel sampling time is 239.5 cycles Watchdog high threshold register (ADC_WDHT) 12.7.6. Address offset: 0x24 Reset value: 0x0000 0FFF This register has to be accessed by word(32-bit) Reserved Reserved WDHT[11:0] Bits Fields...
Page 203: Routine Sequence Register 1 (Adc_Rsq1)
GD32C10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RL[3:0] RSQ15[4:1] RSQ15[0] RSQ14[4:0] RSQ13[4:0] RSQ12[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 RL[3:0] Routine sequence length. The total number of conversion in routine sequence equals to RL[3:0]+1. 19:15 RSQ15[4:0] Refer to RSQ0[4:0] description...
Page 204: Routine Sequence Register 2 (Adc_Rsq2)
GD32C10x User Manual RSQ7[4:0] Refer to RSQ0[4:0] description RSQ6[4:0] Refer to RSQ0[4:0] description Routine sequence register 2 (ADC_RSQ2) 12.7.10. Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RSQ5[4:0] RSQ4[4:0] RSQ3[4:1] RSQ3[0] RSQ2[4:0] RSQ1[4:0] RSQ0[4:0] Bits...
Page 205: Oversample Control Register (Adc_Ovsampctl)
GD32C10x User Manual Bits Fields Descriptions 31:16 ADC1RDTR[15:0] ADC1 routine channel data In sync mode, these bits contain the routine data of ADC1. These bits are only used in ADC0. 15:0 RDATA[15:0] Routine channel data These bits contain routine channel conversion value, which is read only. Oversample control register (ADC_OVSAMPCTL) 12.7.12.
Page 206 GD32C10x User Manual 0100: Shift 4 bits 0101: Shift 5 bits 0110: Shift 6 bits 0111: Shift 7 bits 1000: Shift 8 bits Other: Reserved Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress).
Page 207: Digital-To-Analog Converter (Dac)
GD32C10x User Manual Digital-to-analog converter (DAC) 13.1. Overview The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 208: Function Overview
GD32C10x User Manual description gives the pin description. Figure 13-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx TIMER5_TRGO TIMER2_TRGO TIMER6_TRGO TIMER4_TRGO TIMER1_TRGO TIMER3_TRGO EXTI_9 Buff SWTRx DAC_OUTx Control logic 12-bit 12-bit 12-bit Table 13-1. DAC I/O description Name Description Signal type Analog power supply Power...
Page 209: Dac Data Configuration
GD32C10x User Manual The output buffer, which is turned on by default, can be turned off by setting the DBOFFx bit in the DAC_CTL register. DAC data configuration 13.3.3. The 12-bit DAC holding data (DACx_DH) can be configured by writing any one of these registers (DACx_R12DH, DACx_L12DH or DACx_R8DH).
Page 210: Dac Output Calculate
GD32C10x User Manual DAC_CTL register. The amplitude of the noise can be configured by the DAC noise wave bit width (DWBWx) bits in the DAC_CTL register. LFSR noise wave mode: there is a Linear Feedback Shift Register (LFSR) in the DAC control logic, it controls the LFSR noise signal which is added to the DACx_DH value.
Page 211: Dma Function
GD32C10x User Manual DMA function 13.3.8. When the external trigger is enabled, the DMA request can be enabled by setting the DDMAENx bit of the DAC_CTL register. When an external hardware trigger (not a software trigger) occurs, a DMA request will be generated by DAC. DAC concurrent conversion 13.3.9.
Page 212: Register Definition
GD32C10x User Manual 13.4. Register definition DAC base address: 0x4000 7400 Control register (DAC_CTL) 13.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DDMAEN1 DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 Reserved DDMAEN0 DWBW0[3:0] DWM0[1:0]...
Page 213 GD32C10x User Manual 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DAC1 trigger selection These bits select the external trigger of DAC1 when DTEN1=1. 000: Timer 5 TRGO 001: Timer 2 TRGO 010: Timer 6 TRGO 011: Timer 4 TRGO 100: Timer 1 TRGO 101: Timer 3 TRGO 110: EXTI line 9...
Page 214: Software Trigger Register (Dac_Swt)
GD32C10x User Manual 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM0[1:0] DAC0 noise wave mode These bits specify the mode selection of the noise wave signal of DAC0 when external trigger of DAC0 is enabled (DTEN0=1).
Page 215: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32C10x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DAC1 software trigger, cleared by hardware. 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware. 0: Software trigger disabled 1: Software trigger enabled DAC0 12-bit right-aligned data holding register (DAC0_R12DH) 13.4.3.
Page 216: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32C10x User Manual 31:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value. DAC0 8-bit right-aligned data holding register (DAC0_R8DH) 13.4.5.
Page 217: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh)
GD32C10x User Manual DAC1 12-bit left-aligned data holding register (DAC1_L12DH) 13.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DAC1_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 DAC1_DH[11:0] DAC1 12-bit left-aligned data...
Page 218: Dac Concurrent Mode 12-Bit Left-Aligned Data Holding Register (Dacc_L12Dh)
GD32C10x User Manual This register has to be accessed by word (32-bit). Reserved DAC1_DH[11:0] Reserved DAC0_DH[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:16 DAC1_DH[11:0] DAC1 12-bit right-aligned data These bits specify the data that is to be converted by DAC1. 15:12 Reserved Must be kept at reset value.
Page 219: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32C10x User Manual DAC concurrent mode 8-bit right-aligned data holding register 13.4.11. (DACC_R8DH) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DAC1_DH[7:0] DAC0_DH[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:8 DAC1_DH[7:0] DAC1 8-bit right-aligned data...
Page 220 GD32C10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DAC1_DO[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DAC1_DO[11:0] DAC1 data output These bits, which are read only, reflect the data that is being converted by DAC1.
Page 221: Watchdog Timer (Wdgt)
GD32C10x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and high timing accuracy.
Page 222: Figure 14-1. Free Watchdog Block Diagram
GD32C10x User Manual Figure 14-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value (0x000), there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at any time.
Page 223 GD32C10x User Manual The FWDGT timeout can be more accurate by calibrating the IRC40K. Note: When after the execution of watchdog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 224: Register Definition
GD32C10x User Manual Register definition 14.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 225 GD32C10x User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until...
Page 226 GD32C10x User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
Page 227: Window Watchdog Timer (Wwdgt)
GD32C10x User Manual 14.2. Window watchdog timer (WWDGT) Overview 14.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT [6] bit has been cleared).
Page 228: Figure 14-3. Window Watchdog Timing Diagram
GD32C10x User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F (it implies that the CNT [6] bit should be set).
Page 229: Table 14-2. Min/Max Timeout Value At 60 Mhz
GD32C10x User Manual Table 14-2. Min/max timeout value at 60 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 68.2 μs 1 / 1 4.3ms 136.4 μs 1 / 2 8.6 ms 272.8μs 1 / 4 17.2 ms 545.6 μs 1 / 8...
Page 230: Register Definition
GD32C10x User Manual Register definition 14.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 231 GD32C10x User Manual reaches 0x40. It can be cleared by a hardware reset or a software reset by setting the WWDGTRST bit of the RCU module.. A write operation of ‘0’ has no effect. PSC[1:0] Prescaler. The time base of the watchdog timer counter. 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4...
Page 232: Real-Time Clock (Rtc)
GD32C10x User Manual Real-time Clock (RTC) 15.1. Overview The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The circuits in the backup domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register. That means the RTC settings and time are kept when the device resets or wakes up from Standby mode.
Page 233: Rtc Reset
GD32C10x User Manual (stored in the RTC_ALRMH/L register). Figure 15-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTC Interrupt RTCCLK RTC_Overflow SC_CLK LXTAL RTC_DIV RTC_CNT OVIF NVIC OVIE interrupt IRC40K RTC_Alarm controler Reload COMPARE ALRMIF RTC_PSC ALRMIE...
Page 234: Rtc Flag Assertion
GD32C10x User Manual configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation takes effect only when the peripheral has exited configuration mode, and it takes at least three RTCCLK cycles. The value of the LWOFF bit in the RTC_CTL register will be set to ‘1’...
Page 235 GD32C10x User Manual RTC second and overflow waveform example (RTC_PSC= 3) Figure 15-3.
Page 236: Register Definition
GD32C10x User Manual 15.4. Register definition RTC base address: 0x4000 2800 RTC interrupt enable register(RTC_INTEN) 15.4.1. Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved OVIE ALRMIE SCIE Bits Fields Descriptions Must be kept at reset value.
Page 237: Rtc Prescaler High Register (Rtc_Psch)
GD32C10x User Manual Configuration mode flag 0: Exit configuration mode 1: Enter configuration mode RSYNF Registers synchronized flag 0: Registers not yet synchronized with the APB1 clock 1: Registers synchronized with the APB1 clock OVIF Overflow interrupt flag 0: Overflow event not detected 1: Overflow event detected.
Page 238: Rtc Divider High Register (Rtc_Divh)
GD32C10x User Manual PSC[15:0] Bits Fields Descriptions RTC prescaler value low 15:0 PSC[15:0] The frequency of SC_CLK is the RTCCLK frequency divided by (PSC[19:0]+1). RTC divider high register (RTC_DIVH) 15.4.5. Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved DIV[19:16] Bits...
Page 239: Rtc Counter Low Register (Rtc_Cntl)
GD32C10x User Manual CNT[31:16] Bits Fields Descriptions RTC counter value high 15:0 CNT[31:16] RTC counter low register (RTC_CNTL) 15.4.8. Address offset: 0x1C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CNT[15:0] Bits Fields Descriptions RTC counter value low 15:0 CNT[15:0]...
Page 240: Timer
GD32C10x User Manual TIMER Table 16-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER1/2/3/4 TIMER8/11 TIMER9/10/12/13 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L2 Basic 16-bit 16-bit 16-bit 16-bit 16-bit Prescaler Counter 16-bit 16-bit 16-bit 16-bit 16-bit UP, DOWN, UP, DOWN, Count mode UP ONLY UP ONLY...
Page 241: Advanced Timer (Timerx, X=0, 7)
GD32C10x User Manual 16.1. Advanced timer (TIMERx, x=0, 7) Overview 16.1.1. The advanced timer module (TIMER0, TIMER7) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The advanced timer has a 16-bit counter that can be used as an unsigned counter.
Page 242: Block Diagram
GD32C10x User Manual Block diagram 16.1.3. Figure 16-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 16-1. Advanced timer block diagram...
Page 243: Function Overview
GD32C10x User Manual Function overview 16.1.4. Clock source configuration The advanced timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal clock CK_TIMER is selected as timer clock source which is from module RCU.
Page 244: Figure 16-3. Timing Chart Of Psc Value Change From 0 To 2
GD32C10x User Manual 0x1, 0x2 or 0x3.  SMC1== 1’b1 (external clock mode 1). External input ETI is selected as timer clock source (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 245: Figure 16-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32C10x User Manual times of overflow events. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode. Whenever, if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register, the counter value will be initialized to 0 and generates an update event.
Page 246: Figure 16-5. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32C10x User Manual Figure 16-5. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 247: Figure 16-7. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32C10x User Manual Figure 16-6. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-7.
Page 248: Figure 16-8. Center-Aligned Counter Timechart
GD32C10x User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting direction and generates an underflow event when the counter counts to 1 in the down-counting direction.
Page 249 GD32C10x User Manual Figure 16-8. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register.
Page 250: Figure 16-9. Repetition Timechart For Center-Aligned Counter
GD32C10x User Manual If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overflow.
Page 251: Figure 16-11. Repetition Timechart For Down-Counter
GD32C10x User Manual Figure 16-11. Repetition timechart for down-counter TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 252: Figure 16-12. Channel Input Capture Principle
GD32C10x User Manual Figure 16-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 253 GD32C10x User Manual Result: when you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly.
Page 254: Figure 16-13. Output-Compare Under Three Modes
GD32C10x User Manual Figure 16-13. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 255 GD32C10x User Manual Figure 16-14. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 16-15. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 256 GD32C10x User Manual CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 257: Table 16-2. Complementary Outputs Controlled By Parameters
GD32C10x User Manual Table 16-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 258: Figure 16-16. Complementary Output With Dead-Time Insertion
GD32C10x User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 259: Figure 16-17. Output Behavior In Response To A Break(The Break High Active)
GD32C10x User Manual be set both to active level when break occurs. The break sources are input break pin and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP.
Page 260: Figure 16-18. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32C10x User Manual Table 16-3. Counting direction in different quadrature counter direction is shown in decoder mode. The quadrature decoder can be regarded as an external clock with a directional selection. This means that the counter counts continuously in the interval between 0 and the counter-period value.
Page 261: Figure 16-19. Counter Behavior With Ci0Fe0 Polarity Inverted In Mode 2
GD32C10x User Manual Figure 16-19. Counter behavior with CI0FE0 polarity inverted in mode 2 CI0FE0 CI1FE1 TIMERx_CAR 16 15 17 18 CNT_REG Hall sensor function Hall sensor is generally used to control BLDC Motor; the timers can support this function. Figure 16-20.
Page 262: Figure 16-21. Hall Sensor Timing Between Two Timers
GD32C10x User Manual Figure 16-20. Hall sensor is used to BLDC motor Hall Sensor Rotor Position signals TIMER_in Input capture Driver Motor GPIO Core TIMER_out BLDC Motor Output compare PWM output Figure 16-21. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN...
Page 263: Figure 16-22. Restart Mode
GD32C10x User Manual Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC[2:0] in the TIMERx_SMCFG register. The trigger input of these modes can be selected by the TRGS [2:0] in the TIMERx_SMCFG register.
Page 264: Figure 16-23. Pause Mode
GD32C10x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection the trigger input is selection. only. low. Figure 16-23. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF TRGS[2:0]=3’b11 Exam3 Event mode ETP = 0 no polarity ETPSC = 1, divided by 2. The counter will change.
Page 265: Figure 16-25. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32C10x User Manual enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the trigger signals edge or by setting the CEN bit to 1 using software. Setting the CEN bit to 1 or a trigger from the trigger signals edge can generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 266 GD32C10x User Manual Figure 16-26. Timer0 master/slave mode timer example TIMER0 TIMER 4 TRGS Master ITI0 TRG O Pre scaler Counter mode control TIMER 1 Master TRG O ITI1 Pre scaler Counter mode control TIMER 2 Master ITI2 TRG O Pre scaler Counter mode...
Page 267: Figure 16-27. Triggering Timer0 With Enable Signal Of Timer2
GD32C10x User Manual TIMER_CK (fCNT_CLK = fTIMER_CK /3). Do as follow: 1. Configure Timer2 master mode to send its enable signal as trigger output(MMC=3’b001 in the TIMER2_CTL1 register) 2. Configure Timer0 to select the input trigger from Timer2 (TRGS=3’b010 in the TIMERx_SMCFG register).
Page 268: Figure 16-28. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32C10x User Manual Figure 16-28. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Of course, you have to enable a DMA request which will be asserted by some internal event.
Page 269: Timerx Registers (X=0, 7)
GD32C10x User Manual TIMERx registers (x=0, 7) 16.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0]...
Page 270 GD32C10x User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode.
Page 271 GD32C10x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 272 GD32C10x User Manual counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 273 GD32C10x User Manual Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 274 GD32C10x User Manual 4’b0001 4’b0010 TIMER_CK 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 275 GD32C10x User Manual edge, while the direction depends on each other. 100: Restart mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low.
Page 276 GD32C10x User Manual 0: Disabled 1: Enabled UPDEN Update DMA request enable 0: Disabled 1: Enabled BRKIE Break interrupt enable 0: Disabled 1: Enabled TRGIE Trigger interrupt enable 0: Disabled 1: Enabled CMTIE Commutation interrupt enable 0: Disabled 1: Enabled CH3IE Channel 3 capture/compare interrupt enable 0: Disabled...
Page 277 GD32C10x User Manual Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description...
Page 278 GD32C10x User Manual Refer to CH0IF description CH1IF Channel 1 capture/compare interrupt flag Refer to CH0IF description CH0IF Channel 0 capture/compare interrupt flag This flag is set by hardware and cleared by software. If channel 0 is in input mode, this flag is set when a capture event occurs. If channel 0 is in output mode, this flag is set when a compare event occurs.
Page 279 GD32C10x User Manual 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 280 GD32C10x User Manual CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 281 GD32C10x User Manual 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise.
Page 282 GD32C10x User Manual Input capture mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as output compare mode...
Page 283 GD32C10x User Manual CH0MS[1:0] Channel 0 mode selection Same as output compare mode Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0]...
Page 284 GD32C10x User Manual When this bit is set, if the ETIFP signal is detected as high level, the O2CPRE signal will be cleared. 0: Channel 2 output compare clear disable 1: Channel 2 output compare clear enable CH2COMCTL[2:0] Channel 2 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE.
Page 285 GD32C10x User Manual PWM2 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH2_O is set to the compare level independently from the result of the comparison. 0: Channel 2 output quickly compare disable. 1: Channel 2 output quickly compare enable.
Page 286 GD32C10x User Manual 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 287 GD32C10x User Manual Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description CH1NEN Channel 1 complementary output enable Refer to CH0NEN description CH1P Channel 1 capture/compare function polarity...
Page 288 GD32C10x User Manual CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel 0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT)
Page 289 GD32C10x User Manual value of this bit-filed will be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits...
Page 290 GD32C10x User Manual Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture/compare value of channel 0 When channel 0 is configured in input mode, this bit-field indicates the counter value at the last capture event.
Page 291 GD32C10x User Manual shadow register updates by every update event. Channel 2 capture/compare value register (TIMERx_CH2CV) Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture/compare value of channel 2...
Page 292 GD32C10x User Manual When channel 3 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit)
Page 293 GD32C10x User Manual is 00. Run mode “off-state” enable When POEN bit is set (Run mode), this bit can be set to enable the “off-state” for Table 16-2. the channels which has been configured in output mode. Please refer to Complementary outputs controlled by parameters.
Page 294 GD32C10x User Manual 3’b111 (32+ DTCFG[4:0]) * t DTS_CK Note: 1. t is the period of DTS_CK which is configured by CKDIV[1:0] in DTS_CK TIMERx_CTL0. 2. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000...
Page 295 GD32C10x User Manual DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address ranges from (start address) to (start address + transfer count * 4) will be accessed.
Page 296: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32C10x User Manual 16.2. General level0 timer (TIMERx, x=1, 2, 3, 4) Overview 16.2.1. The general level0 timer module (TIMER1, 2, 3, 4) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 297: Function Overview
GD32C10x User Manual Figure 16-29. General Level 0 timer block diagram Function overview 16.2.4. Clock source configuration The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).
Page 298: Figure 16-30. Timing Chart Of Internal Clock Divided By 1
GD32C10x User Manual  SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when the SMC [2:0] == 3’b000. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK.
Page 299: Figure 16-31. Timing Chart Of Psc Value Change From 0 To 2
GD32C10x User Manual selected as clock source, the trigger controller including the edge detection circuitry will generate a clock pulse on each ETI signal rising edge to clock the counter prescaler. Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 300: Figure 16-32. Timing Chart Of Up Counting Mode, Psc=0/2
GD32C10x User Manual counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Figure 16-32. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear...
Page 301: Figure 16-33. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32C10x User Manual Figure 16-33. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 302: Figure 16-34. Timing Chart Of Down Counting Mode, Psc=0/2
GD32C10x User Manual Figure 16-34. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-35.
Page 303: Figure 16-36. Timing Chart Of Center-Aligned Counting Mode
GD32C10x User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting direction and generates an underflow event when the counter counts to 1 in the down-counting mode.
Page 304 GD32C10x User Manual Figure 16-36. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Input capture and output compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 305: Figure 16-37. Channel Input Capture Principle
GD32C10x User Manual Figure 16-37. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on CH0P Filter TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 306 GD32C10x User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly.
Page 307: Figure 16-38. Output-Compare Under Three Modes
GD32C10x User Manual Figure 16-38. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 308 GD32C10x User Manual Figure 16-39. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 16-40. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 309: Table 16-5. Examples Of Slave Mode
GD32C10x User Manual CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 310: Figure 16-41. Restart Mode
GD32C10x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0]=3’b00 Exam1 Restart mode For ITI0, no polarity selector For the ITI0, no filter and The counter can be can be used. ITI0 is the prescaler can be used. clear and restart when a selection.
Page 311: Figure 16-43. Event Mode
GD32C10x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0]=3’b11 Exam3 Event mode ETP = 0 no polarity change. ETPSC = 1, divided by 2. The counter will start to ETFC = 0 , no filter count when a rising ETIF trigger input.
Page 312 GD32C10x User Manual set to 1, the TIMERx counter stops.
Page 313: Timerx Registers(X=1, 2, 3, 4)
GD32C10x User Manual TIMERx registers(x=1, 2, 3, 4) 16.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved...
Page 314 GD32C10x User Manual center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down...
Page 315 GD32C10x User Manual Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, TIMERx_CH1 and TIMERx_CH2 pins is selected as channel 0 trigger input.
Page 316 GD32C10x User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 317 GD32C10x User Manual according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level. The filtering capability configuration is as follows: EXTFC[3:0] Times SAMP...
Page 318 GD32C10x User Manual by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level. 010: Quadrature decoder mode 1.The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level.
Page 319 GD32C10x User Manual 0: Disabled 1: Enabled CH0DEN Channel 0 capture/compare DMA request enable 0: Disabled 1: Enabled UPDEN Update DMA request enable 0: Disabled 1: Enabled Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: Disabled 1: Enabled Reserved Must be kept at reset value.
Page 320 GD32C10x User Manual Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 321 GD32C10x User Manual 1: Channel 0 interrupt occurred UPIF Update interrupt flag This bit is set by hardware when an update event occurs and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 322 GD32C10x User Manual set. 0: No generate a channel 0 capture or compare event 1: Generate a channel 0 capture or compare event This bit can be set by software, and automatically cleared by hardware. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, while in down counting mode it takes the auto-reload value.
Page 323 GD32C10x User Manual 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 324 GD32C10x User Manual This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 325 GD32C10x User Manual 4’b0010 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 326 GD32C10x User Manual CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection...
Page 327 GD32C10x User Manual 111: PWM mode 1. When counting up, O2CPRE is low when the counter is smaller than TIMERx_CH2CV, and high otherwise. When counting down, O2CPRE is high when the counter is larger than TIMERx_CH2CV, and low otherwise. If configured in PWM mode, the O2CPRE level changes only when the output compare mode is adjusted from “Timing”...
Page 328 GD32C10x User Manual 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the filtering capability.
Page 329 GD32C10x User Manual This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved CH3P CH3EN Reserved CH2P CH2EN Reserved CH1P CH1EN Reserved CH0P CH0EN Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable...
Page 330 GD32C10x User Manual in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 331 GD32C10x User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter.
Page 332 GD32C10x User Manual Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture/compare value of channel1 When channel 1 is configured in input mode, this bit-field indicates the counter value at the last capture event.And this bit-field is read-only.
Page 333 GD32C10x User Manual Reserved Must be kept at reset value. Channel 2 capture/compare value register (TIMERx_CH2CV) Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture/compare value of channel 2...
Page 334 GD32C10x User Manual at the last capture event. And this bit-field is read-only. When channel 3 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000...
Page 335: General Level1 Timer (Timerx, X=8, 11)
GD32C10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 336: Function Overview
GD32C10x User Manual Figure 16-44. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter Trigger processor TIMERx_TRGO PSC_CLK Trigger Selector&Counter TIMER_CK Quadrate Decoder Output Logic CH0_O generation of outputs signals in compare, PWM,and mixed modes according to initialization, software CH1_O...
Page 337: Figure 16-45. Timing Chart Of Internal Clock Divided By 1
GD32C10x User Manual Figure 16-45. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 338: Figure 16-46. Timing Chart Of Psc Value Change From 0 To 2
GD32C10x User Manual Figure 16-46. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 339: Figure 16-47. Timing Chart Of Up Counting Mode, Psc=0/2
GD32C10x User Manual Figure 16-47. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-48.
Page 340: Figure 16-49. Channel Input Capture Principle
GD32C10x User Manual Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ...
Page 341 GD32C10x User Manual Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 342: Figure 16-50. Output-Compare Under Three Modes
GD32C10x User Manual About the CHxVAL, you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN. The timechart below show the three compare modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 16-50. Output-compare under three modes CNT_CLK ….
Page 343: Figure 16-51. Eapwm Timechart
GD32C10x User Manual mode0 (CHxCOMCTL==3’b110). And if TIMERx_CHxCV is equal to zero, the output will be always inactive under PWM mode0 (CHxCOMCTL==3’b110). Figure 16-51. EAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Figure 16-52. CAPWM timechart CHxVAL PWM MODE0 Cx OUT...
Page 344: Table 16-6．Examples Of Slave Mode
GD32C10x User Manual x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function. These include, keeping the original level by setting the CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register.
Page 345: Figure 16-53. Restart Mode
GD32C10x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 16-53. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Exam2 Pause mode CH0P==0, Filter is bypass in this TRGS[2:0]=3’b101 no inverted. Capture will be example. The counter can be CI0FE0 sensitive to the rising edge...
Page 346: Figure 16-55. Event Mode
GD32C10x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 16-55. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 347 GD32C10x User Manual Figure 16-56. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 Timers interconnection Advanced timer (TIMERx, x=0, 7) Refer to Timer debug mode When the Cortex ® -M4 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
Page 348: Timerx Registers (X=8, 11)
GD32C10x User Manual TIMERx registers (x=8, 11) 16.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved...
Page 349 GD32C10x User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 350 GD32C10x User Manual 010: ITI2 011: ITI3 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high.
Page 351 GD32C10x User Manual Reserved Must be kept at reset value. CH1IE Channel 1 capture/compare interrupt enable 0: Disabled 1: Enabled CH0IE Channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 352 GD32C10x User Manual 1: Trigger interrupt occurred. Reserved Must be kept at reset value. CH1IF Channel 1 capture/compare interrupt flag Refer to CH0IF description CH0IF Channel 0 capture/compare interrupt flag This flag is set by hardware and cleared by software. If channel 0 is in input mode, this flag is set when a capture event occurs.
Page 353 GD32C10x User Manual Refer to CH0G description CH0G Channel 0 capture or compare event generation This bit is set by software to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH0IF flag will be set, and the corresponding interrupt or DMA request will be sent if enabled.
Page 354 GD32C10x User Manual This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 355 GD32C10x User Manual PWM1 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison. 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable.
Page 356 GD32C10x User Manual 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 357 GD32C10x User Manual Refer to CH1EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0.
Page 358 GD32C10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 359 GD32C10x User Manual This bit-field specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 360: General Level2 Timer (Timerx, X=9, 10, 12, 13)
GD32C10x User Manual When channel 1 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 361: Figure 16-57. General Level2 Timer Block Diagram
GD32C10x User Manual Characteristics 16.4.2.  Total channel num: 1.  Counter width: 16 bits.  Clock source of timer: internal clock.  Counter mode: up counting only.  Programmable prescaler: 16 bits. The factor can be changed ongoing.  Each channel is user-configurable: input capture mode, output compare mode, programmable PWM mode.
Page 362: Figure 16-58. Timing Chart Of Internal Clock Divided By 1
GD32C10x User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER which is from Figure 16-58. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register...
Page 363: Figure 16-59. Timing Chart Of Psc Value Change From 0 To 2
GD32C10x User Manual Figure 16-59. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 364: Figure 16-60. Timing Chart Of Up Counting Mode, Psc=0/2
GD32C10x User Manual Figure 16-60. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-61.
Page 365: Figure 16-62. Channel Input Capture Principle
GD32C10x User Manual Input capture and output compare channels The general level2 timer has one independent channel which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ...
Page 366 GD32C10x User Manual As soon as you select one input capture source by CHxMS, you have set the channel to input mode ( CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more. Step4: Interrupt enable. (CHxIE in TIMERx_DMAINTEN) Enable the related interrupt enable; you can got the interrupt. Step5: Capture enables.
Page 367: Figure 16-63. Output-Compare Under Three Modes
GD32C10x User Manual Figure 16-63. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 368 GD32C10x User Manual Timer debug mode ® When the Cortex -M4 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
Page 369 GD32C10x User Manual TIMERx registers (x=9, 10, 12, 13) 16.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 370 GD32C10x User Manual UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 371 GD32C10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 372 GD32C10x User Manual Reserved CH0G Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CH0G Channel 0 capture or compare event generation This bit is set by software to generate a capture or compare event in channel 0, it is automatically cleared by hardware.
Page 373 GD32C10x User Manual 001: Set the channel output. O0CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output. O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV. 011: Toggle on match.
Page 374 GD32C10x User Manual 31:8 Reserved Must be kept at reset value. CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal.
Page 375 GD32C10x User Manual Reserved Reserved CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity. 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, in conjunction with CH0P, this bit is...
Page 376 GD32C10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter.
Page 377 GD32C10x User Manual Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 378: Figure 16-64. Basic Timer Block Diagram
GD32C10x User Manual Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved...
Page 379: Figure 16-65. Timing Chart Of Internal Clock Divided By 1
GD32C10x User Manual the basic timer. Figure 16-64. Basic timer block diagram Function overview 16.5.4. Clock source configuration The basic TIMER can only be clocked by the internal timer clock CK_TIMER, which is from the source named CK_TIMER in RCU The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler.
Page 380: Figure 16-66. Timing Chart Of Psc Value Change From 0 To 2
GD32C10x User Manual (TIMERx_PSC). The new written prescaler value will not take effect until the next update event. Figure 16-66. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 381: Figure 16-67. Timing Chart Of Up Counting Mode, Psc=0/2
GD32C10x User Manual Figure 16-67. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-68.
Page 382 GD32C10x User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event. Once the timer is set to operate in the single pulse mode, it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter, then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 383 GD32C10x User Manual TIMERx registers (x=5, 6) 16.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved UPDIS...
Page 384 GD32C10x User Manual The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 385 GD32C10x User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: Disabled 1: Enabled...
Page 386 GD32C10x User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and automatically cleared by hardware.
Page 387 GD32C10x User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 388 GD32C10x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 17.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK1 or PCLK2) to produce a dedicated baud rate clock for the USART transmitter and receiver.
Page 389: Table 17-1. Description Of Usart Important Pins
GD32C10x User Manual – Block mode (T=1). – Direct and inverse convention.  Multiprocessor communication. – Enter into mute mode if address match does not occur. – Wake up from mute mode by idle frame or address match detection.  Various status flags: –...
Page 390: Figure 17-1. Usart Module Block Diagram
GD32C10x User Manual Figure 17-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Block Register Receive Shift Register USART Guard Time and Prescaler nRTS Hardware Register Controller Flow nCTS Controller USART Control Registers USART Address Transmitter Transmitter clock Controller...
Page 391 GD32C10x User Manual In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame. A break frame is configured number of low bits followed by the configured number of stop bits. The transfer speed of a USART frame depends on the frequency of the UCLK, the configuration of the baud rate generator and the oversampling mode.
Page 392: Figure 17-3. Usart Transmit Procedure
GD32C10x User Manual transmission is ongoing, the TBE bit will be cleared and set soon, because the data will be transferred to the transmit shift register immediately. If a frame is transmitted and the TBE bit is asserted, the TC bit of the USART_STAT0 register will be set.
Page 393: Figure 17-4. Receiving A Frame Bit By Oversampling Method
GD32C10x User Manual After being enabled, the receiver receives a bit stream after a valid start pulse has been detected. Detection on noisy error, parity error, frame error and overrun error is performed during the reception of a frame. When a frame is received, the RBNE bit in USART_STAT0 is asserted, an interrupt is generated if the corresponding interrupt enable bit (RBNEIE) is set in the USART_CTL0 register.
Page 394: Figure 17-5. Configuration Steps When Using Dma For Usart Transmission
GD32C10x User Manual interrupt is caused by noise error, parity error, framing error or overflow error when the RBNE interrupt occurs. Use DMA for data buffer access 17.3.5. To reduce the burden of the processor, DMA can be used to access the transmitting and receiving data buffer.
Page 395: Figure 17-6. Configuration Steps When Using Dma For Usart Reception
GD32C10x User Manual and NERR) in USART_STAT0. Figure 17-6. Configuration steps when using DMA for USART reception Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal SRAM as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt...
Page 396: Figure 17-8. Hardware Flow Control
GD32C10x User Manual data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full, and can be cleared by reading the USART_DATA register. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 397: Figure 17-9. Break Frame Occurs During Idle State
GD32C10x User Manual the USART. The status bits are available in the USART_STAT0 register. If the LSB 4 bits of an address frame differ from the ADDR[3:0] bits in the USART_CTL1 register, the hardware sets the RWU bit and enters mute mode automatically. In this situation, the RBNE bit is not set.
Page 398: Figure 17-11. Example Of Usart In Synchronous Mode
GD32C10x User Manual Synchronous mode 17.3.9. The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTL1. The LMEN bit in USART_CTL1 and SCEN, HDEN, IREN bits in USART_CTL2 should be cleared in synchronous mode. The CK pin is the clock output of the synchronous USART transmitter, and can be only activated when the TEN bit is enabled.
Page 399: Figure 17-13. Irda Sir Endec Module
GD32C10x User Manual In IrDA mode, the USART transmission data frame is modulated in the SIR transmit encoder and transmitted to the infrared LED through the TX pin. The SIR receive decoder receives the modulated signal from the infrared LED through the RX pin, and puts the demodulated data frame to the USART receiver.
Page 400: Figure 17-15. Iso7816-3 Frame Format
GD32C10x User Manual manner as the normal IrDA mode. Half-duplex communication mode 17.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode.
Page 401 GD32C10x User Manual the GUAT[7:0] bits should be configured as the character guard time (CGT) in ISO7816-3 protocol minus 12. The TC status is forced reset while the guard time counter is counting up. When the counter reaches the programmed value TC is asserted high. During USART transmission, if a parity error event is detected, the smartcard may NACK the current frame by pulling down the TX pin during the last 1 bit time of the stop bits.
Page 402: Table 17-3. Usart Interrupt Requests
GD32C10x User Manual after the block length counter reaches the maximum value. An interrupt is generated if the EBIE bit in USART_CTL3 is set. The RTF bit may be set in case that an error in the block length. If DMA is used for reception, this register field must be programmed to the minimum value (0x0) before the start of the block.
Page 403: Figure 17-16. Usart Interrupt Mapping Diagram
GD32C10x User Manual All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine. Figure 17-16.
Page 404 GD32C10x User Manual 17.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Status register 0 (USART_STAT0) 17.4.1. Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 405 GD32C10x User Manual This bit is cleared when the software writes transmit data to the USART_DATA register. 0: Transmit data buffer is not empty. 1: Transmit data buffer is empty. Transmission complete This bit is set after power on. If the TBE bit has been set, this bit is set when the transmission of current data is complete.
Page 406 GD32C10x User Manual 1: The USART has detected a noise error. FERR Frame error flag This bit is set when the RX pin is detected low during the stop bits of a receive frame. An interrupt occurs if the ERRIE bit in USART_CTL2 is set. Software can clear this bit by reading the USART_STAT0 and USART_DATA registers one by one.
Page 407 GD32C10x User Manual The software must not write this register when the USART is enabled (UEN=1). This register has to be accessed by word (32-bit). Reserved INTDIV[11:0] FRADIV[3:0] Bits Fields Descriptions Must be kept at reset value. 31:16 Reserved 15:4 INTDIV[11:0] Integer part of baud-rate divider.
Page 408 GD32C10x User Manual 1: Parity check function is enabled. Parity mode 0: Even parity 1: Odd parity PERRIE Parity error interrupt enable If this bit is set, an interrupt occurs when the PERR bit in USART_STAT0 is set. 0: Parity error interrupt is disabled. 1: Parity error interrupt is enabled.
Page 409 GD32C10x User Manual 0: Receiver in active mode. 1: Receiver in mute mode. SBKCMD Send break command Software can set this bit to send a break frame. Hardware clears this bit automatically when the break frame has been transmitted. 0: Do not transmit a break frame. 1: Transmit a break frame.
Page 410 GD32C10x User Manual CK phase This bit specifies the phase of the CK pin in synchronous mode. 0: The capture edge of the LSB bit is the first edge of CK pin. 1: The capture edge of the LSB bit is the second edge of CK pin. This bit is reserved for UART3/4.
Page 411 GD32C10x User Manual CTSIE CTS interrupt enable If this bit is set, an interrupt occurs when the CTSF bit in USART_STAT0 is set. 0: CTS interrupt disabled. 1: CTS interrupt enabled. This bit is reserved for UART3/4. CTSEN CTS enable This bit enables the CTS hardware flow control function.
Page 412 GD32C10x User Manual 1: Low-power mode IREN IrDA mode enable This bit enables the IrDA mode of USART. 0: IrDA disabled 1: IrDA enabled ERRIE Error interrupt enable When DMA request for reception is enabled (DENR=1), if this bit is set, an interrupt occurs when any one of the FERR, ORERR and NERR bits in USART_STAT0 is set.
Page 413 GD32C10x User Manual 00000: Reserved - never program this value. 00001: Divided by 2. 00010: Divided by 4. 11111: Divided by 62. The PSC [7:5] bits are reserved in smartcard mode. Control register 3 (USART_CTL3) 17.4.8. Address offset: 0x80 Reset value: 0x0000 0000 This register is reserved for UART3/4.
Page 414 GD32C10x User Manual 1: RX pin signal values are inverted. This bit field cannot be written when the USART is enabled (UEN=1). Reserved Must be kept at reset value. EBIE Interrupt enable bit of end of block event If this bit is set, an interrupt occurs when the EBF bit in USART_STAT1 is set. 0: End of block interrupt enabled.
Page 415 GD32C10x User Manual 31:24 BL[7:0] Block length These bits specify the block length in Smartcard T=1 reception. The value equals to the number of information characters + the length of the Epilogue Field (1-LEC/2- CRC) - 1. This value, which must be programmed only once per received block, can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field).
Page 416 GD32C10x User Manual 15:13 Reserved Must be kept at reset value. End of block flag This bit is set when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt occurs if the EBIE bit in USART_CTL3 is set.
Page 417: Figure 18-1. I2C Module Block Diagram
GD32C10x User Manual Inter-integrated circuit interface (I2C) 18.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard-mode, fast-mode and fast- mode-plus as well as CRC calculation and checking, SMBus (system management bus), PMBus (power management bus) and SAM_V (secure access and control module for...
Page 418: Table 18-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32C10x User Manual Figure 18-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 18-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 419: Figure 18-2. Data Validation
GD32C10x User Manual the FMPEN bit in I2C_FMPCFG is set. Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V Data validation 18.3.2.
Page 420: Figure 18-4. Clock Synchronization
GD32C10x User Manual transition of this clock may not change the state of the SCL line. The SCL line is therefore held LOW by the master with the longest LOW period. Masters with shorter LOW period enter a HIGH wait-state during this time. Figure 18-4.
Page 421: Figure 18-6. I2C Communication Flow With 7-Bit Address
GD32C10x User Manual to the following command on I2C bus: transmitting or receiving the desired data. Additionally, if General Call is enabled by software, the I2C slave always responds to a General Call Address (0x00). The I2C block supports both 7-bit and 10-bit address modes. An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation.
Page 422: Figure 18-9. Programming Model For Slave Transmitting (10-Bit Address Mode)
GD32C10x User Manual Programming model in slave transmitting mode As is shown in Figure 18-9. Programming model for slave transmitting (10-bit address mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing.
Page 423: Figure 18-10. Programming Model For Slave Receiving (10-Bit Address Mode)
GD32C10x User Manual Figure 18-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 424: Figure 18-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32C10x User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 18-10.
Page 425 GD32C10x User Manual Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 426 GD32C10x User Manual Figure 18-11. Programming model for master transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND...
Page 427 GD32C10x User Manual reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1. If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out.
Page 428: Figure 18-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32C10x User Manual Figure 18-12. Programming model for master receiving using Solution A (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 429: Figure 18-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32C10x User Manual If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 430 GD32C10x User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 431 GD32C10x User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
Page 432 GD32C10x User Manual related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). SMBus protocol Each message transmission on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications.
Page 433: Table 18-2. Event Status Flags
GD32C10x User Manual a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data. SMBus programming flow The programming flow for SMBus is similar to normal I2C. In order to use SMBus mode, the application should configure several SMBus specific registers, respond to some SMBus specific flags and implement the upper protocols described in SMBus specification.
Page 434: Table 18-3. Error Flags
GD32C10x User Manual SAM_V mode rxframe pin falling edge is detected SAM_V mode txframe pin rising edge is detected SAM_V mode txframe pin falling edge is detected Table 18-3. Error flags Error Name Description BERR Bus error LOSTARB Arbitration lost OUERR Over-run or under-run when SCL stretch is disabled.
Page 435 GD32C10x User Manual 18.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) 18.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved SALT...
Page 436 GD32C10x User Manual 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte. ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0.
Page 437 GD32C10x User Manual 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) 18.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE EVIE ERRIE Reserved I2CCLK[5:0] Bits...
Page 438 GD32C10x User Manual I2CCLK[5:0] should be the frequency of input APB1 clock in MHz which is at least 000000 - 000001: Not allowed 000010 - 111100: 2 MHz~60 MHz 111101 - 111111: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 439 GD32C10x User Manual Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled Transfer buffer register (I2C_DATA) 18.4.5.
Page 440 GD32C10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode) SMBTO...
Page 441 GD32C10x User Manual This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail). 0: I2C_DATA is not empty 1: I2C_DATA is empty, software can write RBNE...
Page 442 GD32C10x User Manual mode, address has been sent and receives the ACK from slave. SBSEND START signal is sent out in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA. 0: No START signal sent 1: START signal sent Transfer status register 1 (I2C_STAT1) 18.4.7.
Page 443 GD32C10x User Manual Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver. It is cleared by hardware after a STOP or a START signal or I2CEN=0 or LOSTARB=1. 0: Receiver 1: Transmitter I2CBSY...
Page 444 GD32C10x User Manual In fast speed mode or fast mode plus, if DTCY=0: =CLKC*T =2*CLKC*T high PCLK1 PCLK1 In fast speed mode or fast mode plus, if DTCY=1: =9*CLKC*T =16*CLKC*T high PCLK1 PCLK1 Note: If DTCY is 0, when PCLK1 is an integral multiple of 3, the baud rate will be more accurate.
Page 445 GD32C10x User Manual Rxframe fall flag, cleared by software by writing 0 Txframe rise flag, cleared by software by writing 0 Txframe fall flag, cleared by software by writing 0 11:10 Reserved Must be kept at reset value. Level of rxframe signal Level of txframe signal RFRIE Rxframe rise interrupt enable...
Page 446 GD32C10x User Manual Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. FMPEN Fast mode plus enable. The I2C device supports up to 1MHz when this bit is set. 0: Fast mode plus disabled 1: Fast mode plus enabled...
Page 447 GD32C10x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 19.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 448: Figure 19-1. Block Diagram Of Spi
GD32C10x User Manual 19.3. SPI function overview SPI block diagram 19.3.1. Figure 19-1. Block diagram of SPI SYSCLK Clock Generator Control Registers TxRx Control Logic MOSI TX Buffer MISO Shift Register RX Buffer SPI signal description 19.3.2. Normal configuration (Not Quad-SPI Mode) Table 19-1.
Page 449: Figure 19-2. Spi Timing Diagram In Normal Mode
GD32C10x User Manual Pin name Direction Description application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0).
Page 450: Figure 19-3. Spi Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32C10x User Manual Figure 19-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. Data length is 16 bits if FF16=1, otherwise is 8 bits.
Page 451: Table 19-4. Nss Function In Master Mode
GD32C10x User Manual fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1). NSS goes low after SPI is enabled. The application may also use a general purpose IO as NSS pin to realize more flexible NSS. Table 19-4.
Page 452 GD32C10x User Manual Mode Description Register configuration Data pin usage MSTMOD = 1 Master reception with RO = 1 MOSI: Not used unidirectional connection BDEN = 0 MISO: Reception BDOEN: Don’t care MSTMOD = 1 Master transmission with RO = 0 MOSI: Transmission bidirectional connection BDEN = 1...
Page 453: Figure 19-4. A Typical Full-Duplex Connection
GD32C10x User Manual Figure 19-4. A typical full-duplex connection Master Slave MISO MISO MOSI MOSI Figure 19-5. A typical simplex connection (Master: Receive, Slave: Transmit) Slave Master MISO MISO MOSI MOSI Figure 19-6. A typical simplex connection (Master: Transmit only, Slave: Receive) Master Slave MISO...
Page 454 GD32C10x User Manual SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 455: Figure 19-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32C10x User Manual receive buffer and RBNE (receive buffer not empty) will be set. The application should read SPI_DATA register to get the received data and this will clear the RBNE flag automatically. In MRU and MRB modes, hardware continuously sends clock signal to receive the next data frame, while in full-duplex master mode (MFD), hardware only receives the next data frame when the transmit buffer is not empty.
Page 456: Figure 19-9. Timing Diagram Of Ti Master Mode With Continuous Transfer
GD32C10x User Manual Figure 19-9. Timing diagram of TI master mode with continuous transfer sample MOSI D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] D[7] D[3] D[2] D[1] D[0] D[6] D[5] D[4] D[1] D[0] MISO D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]...
Page 457: Figure 19-11. Timing Diagram Of Nss Pulse With Continuous Transmission
GD32C10x User Manual frame format should follow the normal SPI protocol, select the first clock transition as the data capture edge. In summary, MSTMOD = 1, NSSP = 1, CKPH = 0. When NSS pulse mode is enabled, a pulse duration of at least 1 SCK clock period is inserted between two successive data frames depending on the status of internal data transmit buffer.
Page 458: Figure 19-12. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32C10x User Manual Figure 19-12. Timing diagram of quad write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D1[6] D0[6] D0[2] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD bits are both set in SPI_QCTL register.
Page 459: Figure 19-13. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32C10x User Manual Figure 19-13. Timing diagram of quad read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[0] D0[4] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7]...
Page 460 GD32C10x User Manual Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared. DMA function 19.3.6.
Page 461 GD32C10x User Manual SPI interrupts 19.3.8. Status flags  Transmit buffer empty flag (TBE) This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register. ...
Page 462: Figure 19-14. Block Diagram Of I2S
GD32C10x User Manual Table 19-6. SPI interrupt requests Interrupt Flag Description Clear method enable bit Transmit buffer empty Write SPI_DATA register. TBEIE RBNE Receive buffer not empty Read SPI_DATA register. RBNEIE Read or write SPI_STAT register, CONFERR Configuration fault error then write SPI_CTL0 register.
Page 463: Figure 19-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32C10x User Manual I2S signal description 19.4.2. There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
Page 464: Figure 19-16. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32C10x User Manual Figure 19-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation the transmission of to or from the SPI_DATA register is needed to complete a frame.
Page 465: Figure 19-21. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32C10x User Manual transmission mode, if a 24-bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits D[23:8]. And the second one should be a 16- bit data, the higher 8 bits of this 16-bit data should be D[7:0] and the lower 8 bits can be any value.
Page 466: Figure 19-25. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32C10x User Manual Figure 19-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 19-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 467: Figure 19-31. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32C10x User Manual than the data length, the valid data is aligned to LSB for LSB justified standard while the valid data is aligned to MSB for MSB justified standard. The timing diagrams for the cases that the channel length is greater than the data length are shown below. Figure 19-31.
Page 468: Figure 19-35. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32C10x User Manual PCM standard For PCM standard, I2S_WS and I2S_SD are updated on the rising edge of I2S_CK, and the I2S_WS signal indicates frame synchronization information. Both the short frame synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register.
Page 469: Figure 19-40. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32C10x User Manual (DTLEN=01, CHLEN=1, CKPL=0) Figure 19-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 19-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 16-bit data 16-bit 0 Figure 19-42.
Page 470: Figure 19-45. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32C10x User Manual (DTLEN=00, CHLEN=0, CKPL=1) Figure 19-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 19-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 13 bits 32 bits Figure 19-47.
Page 471: Figure 19-51. Block Diagram Of I2S Clock Generator
GD32C10x User Manual Figure 19-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) I2S clock 19.4.4. Figure 19-51. Block diagram of I2S clock generator The block diagram of I2S clock generator is shown as Figure 19-51. Block diagram of I2S clock generator.
Page 472: Table 19-8. Audio Sampling Frequency Calculation Formulas
GD32C10x User Manual Table 19-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Formula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) Operation 19.4.5.
Page 473: Figure 19-52. I2S Initialization Sequence
GD32C10x User Manual Figure 19-52. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 474 GD32C10x User Manual and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmit buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 475: Figure 19-53. I2S Master Reception Disabling Sequence
GD32C10x User Manual Figure 19-53. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTDSEL ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTDSEL !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 476 GD32C10x User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 477: Table 19-10. I2S Interrupt
GD32C10x User Manual Error flags There are three error flags:  Transmission underrun error flag (TXURERR) This situation occurs when the transmit buffer is empty if the valid SCK signal starts in slave transmission mode.  Reception overrun error flag (RXORERR) This situation occurs when the receive buffer is full and a newly incoming data has been completely received.
Page 478 GD32C10x User Manual 19.5. Register definition SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 Control register 0 (SPI_CTL0) 19.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode.
Page 479 GD32C10x User Manual register. In receive-only mode, set this bit after the second last data is received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only mode When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN...
Page 480 GD32C10x User Manual 1: CLK pin is pulled high when SPI is idle CKPH Clock phase selection 0: Capture the first data at the first clock transition 1: Capture the first data at the second clock transition Control register 1 (SPI_CTL1) 19.5.2.
Page 481 GD32C10x User Manual DMATEN Transmit buffer DMA enable 0: Disable transmit buffer DMA 1: Enable transmit buffer DMA, when the TBE bit in SPI_STAT is set, there will be a DMA request on corresponding DMA channel. DMAREN Receive buffer DMA enable 0: Disable receive buffer DMA 1: Enable receive buffer DMA, when the RBNE bit in SPI_STAT is set, there will be a DMA request on corresponding DMA channel.
Page 482 GD32C10x User Manual followed by a read access to the SPI_STAT register. CONFERR SPI Configuration error 0: No configuration fault occurs. 1: Configuration fault occurred. (In master mode, the NSS pin is pulled low in NSS hardware mode or SWNSS bit is low in NSS software mode.) This bit is set by hardware and cleared by a read or write operation on the SPI_STAT register followed by a write access to the SPI_CTL0 register.
Page 483 GD32C10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register The hardware has two buffers, including transmit buffer and receive buffer. Write data to SPI_DATA will save the data to transmit buffer and read data from SPI_DATA will get the data from receive buffer.
Page 484 GD32C10x User Manual RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the received bytes and saves them in RCRC register. If the data frame format is set to 8- bit data, CRC calculation is based on CRC8 standard, and saves the value in RCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in RCRC[15:0].
Page 485 GD32C10x User Manual This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset register is set. I2S control register (SPI_I2SCTL) 19.5.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PCMSMO Reserved...
Page 486 GD32C10x User Manual Reserved Must be kept at reset value. I2SSTD[1:0] I2S standard selection 00: I2S Phillips standard 01: MSB justified standard 10: LSB justified standard 11: PCM standard These bits should be configured when I2S is disabled. These bits are not used in SPI mode. CKPL Idle state clock polarity 0: The idle state of I2S_CK is low level...
Page 487 GD32C10x User Manual 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: I2S_MCK output is disabled 1: I2S_MCK output is enabled This bit should be configured when I2S is disabled. This bit is not used in SPI mode. Odd factor for the prescaler 0: Real divider value is DIV * 2 1: Real divider value is DIV * 2 + 1...
Page 488 GD32C10x User Manual This bit is only available in SPI0. Quad-SPI mode enable QMOD 0: SPI is in single wire mode 1: SPI is in Quad-SPI mode This bit should only be configured when SPI is not busy (TRANS bit cleared). This bit is only available in SPI0.
Page 489 GD32C10x User Manual External memory controller (EXMC) 20.1. Overview The external memory controller EXMC, is used as a translator for CPU to access a variety of external memories. By configuring the related registers, it automatically converts AMBA memory access protocol into a specific memory access protocol, such as SRAM, PSRAM, ROM and NOR Flash.
Page 490: Figure 20-1. The Exmc Block Diagram
GD32C10x User Manual Figure 20-1. The EXMC block diagram AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NOR-Flash/PSRAM Controller NOR/PSRAM Pins Basic regulation of EXMC access 20.3.2. EXMC is the conversion interface between AHB bus and external device protocol. 32-bit of AHB read/write access can split into several consecutive 8-bit or 16-bit read/write operations respectively.
Page 491: Figure 20-2. Exmc Memory Banks
GD32C10x User Manual Figure 20-2. EXMC memory banks EXMC access space is bank0, which is 64 Mbytes, and is used for NOR and PSRAM device access. HADDR[25:0] is the byte address whereas the external memory may not be byte accessed, this will lead to address inconsistency.
Page 492: Table 20-2. Psram Non-Muxed Signal Description
GD32C10x User Manual EXMC pin Direction Mode Functional description Async/sync Input/output Data bus (non-muxed) EXMC_NE Output Async/sync Chip selection Output enable(read EXMC_NOE Output Async/sync enable) EXMC_NWE Output Async/sync Write enable EXMC_NWAIT Input Async/sync Wait input signal EXMC_NL(NADV) Output Async/sync Address valid Table 20-2.
Page 493: Table 20-4. Nor/Psram Controller Timing Parameters
GD32C10x User Manual Memory Memory Access mode transaction transaction Comments width width Use byte lanes Async EXMC_NBL[1:0] Async Async Split into 2 EXMC Async accesses Split into 2 EXMC Async accesses Sync Sync Use byte lanes Sync EXMC_NBL[1:0] Sync Sync Async Async Split into 2 EXMC...
Page 494: Table 20-5. Exmc Timing Models
GD32C10x User Manual Parameter Function Access mode Unit DSET Data setup time Async HCLK AHLD Address hold time Async(muxed) HCLK ASET Address setup time Async HCLK Table 20-5. EXMC timing models Timing Extend Write timing Read timing Mode description model mode parameter parameter...
Page 495: Figure 20-3. Mode 1 Read Access
GD32C10x User Manual Figure 20-3. Mode 1 read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NE) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 2 HCLK (ASET+1 HCLK) (DSET+1 HCLK) Figure 20-4.
Page 496: Figure 20-5. Mode A Read Access
GD32C10x User Manual Bit position Bit name Reference setting value Reserved NREN No effect Depends on memory NRTP Depends on memory, except 0x2(NOR flash) NRMUX NRBKEN EXMC_SNTCFG 31-30 Reserved 29-28 ASYNCMOD No effect 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE rising edge to 19-16 BUSLAT...
Page 497: Figure 20-6. Mode A Write Access
GD32C10x User Manual Figure 20-6. Mode A write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NE) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The difference of write timing between mode A and mode 1 is that when read and write timings are specified by the same set of timing configurations, mode A write timing configuration is independent of its read configuration.
Page 498: Figure 20-7. Mode 2/B Read Access
GD32C10x User Manual Bit position Bit name Reference setting value Time between EXMC_NE rising edge to EXMC_NE 19-16 BUSLAT falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFG(write) 31-30 Reserved...
Page 499: Figure 20-8. Mode 2 Write Access
GD32C10x User Manual Figure 20-8. Mode 2 write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NE) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET+1 HCLK) (DSET HCLK) Figure 20-9. Mode B write access Address (EXMC_A[25:0]) Chip Enable...
Page 500 GD32C10x User Manual Bit position Bit name Reference setting value Reserved NREN Depends on memory NRTP 0x2, NOR flash NRMUX NRBKEN EXMC_SNTCFG(read and write in mode 2, read in mode B) 31-30 Reserved 29-28 ASYNCMOD Mode B:0x1 27-24 DLAT No effect 23-20 CKDIV No effect...
Page 501: Figure 20-10. Mode C Read Access
GD32C10x User Manual Figure 20-10. Mode C read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NE) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 2 HCLK (ASET+1 HCLK) (DSET+1 HCLK) Figure 20-11. Mode C write access Address (EXMC_A[25:0]) Chip Enable...
Page 502 GD32C10x User Manual Bit position Bit name Reference setting value WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN Depends on memory NRTP 0x2, NOR flash NRMUX NRBKEN EXMC_SNTCFG 31-30 Reserved 29-28 ASYNCMOD Mode C: 0x2 27-24 DLAT 23-20...
Page 503: Figure 20-12. Mode D Read Access
GD32C10x User Manual Figure 20-12. Mode D read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NE) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 2 HCLK (ASET+1 HCLK) (AHLD+1 HCLK) (DSET+1 HCLK) Figure 20-13.
Page 504 GD32C10x User Manual Bit position Bit name Reference setting value Reserved NREN Depends on memory Depends on memory NRTP Depends on memory NRMUX NRBKEN EXMC_SNTCFG 31-30 Reserved 29-28 ASYNCMOD Mode D: 0x3 Don’t care 27-24 DLAT 23-20 CKDIV No effect Time between EXMC_NE rising edge to 19-16 BUSLAT...
Page 505: Figure 20-14. Multiplex Mode Read Access
GD32C10x User Manual Figure 20-14. Multiplex mode read access Address Address[25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NE) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) 1 HCLK Data Mux Address[15:0] Memory Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 2 HCLK (ASET+1 HCLK) (AHLD+1 HCLK)
Page 506 GD32C10x User Manual Bit position Bit name Reference setting value Reserved NREN Depends on memory NRTP 0x2: NOR flash NRMUX NRBKEN EXMC_SNTCFG 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE rising edge to 19-16 BUSLAT EXMC_NE falling edge...
Page 507: Figure 20-16. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32C10x User Manual Figure 20-16. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NE) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1 Output Enable (EXMC_NOE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 4 HCLK 2 HCLK Data sampling point...
Page 508 GD32C10x User Manual NOR Flash latency=DLAT+2 (20-6) For specification of NOR Flash includes the EXMC_NADV cycle, their relationship should be: NOR Flash latency=DLAT+3 (20-7) 2. Data wait Users should guarantee that EXMC_NWAIT signal matches that of the external device. This signal is configured through the EXMC_SNCTL registers, it is enabled by the NRWTEN bit, and the active timing could be one data cycle before the wait state or active during the wait state by the NRWTCFG bit, and the wait signal polarity is set by the NRWTPOL bit.
Page 509: Figure 20-18. Read Timing Of Synchronous Multiplexed Burst Mode
GD32C10x User Manual Figure 20-18. Read timing of synchronous multiplexed burst mode HCLK Clock (EXMC_CLK) Address Address [25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NE) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Wait (EXMC_NWAIT) Data Memory Memory Memory Address [15:0] (EXMC_D[15:0]) Data 1 Data 2 Data 3...
Page 510: Figure 20-19. Write Timing Of Synchronous Multiplexed Burst Mode
GD32C10x User Manual Bit position Bit name Reference setting value 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1, EXMC_CLK=2HCLK Time between EXMC_NE rising edge to EXMC_NE 19-16 BUSLAT falling edge 15-8 DSET No effect AHLD No effect ASET No effect Mode SM –...
Page 511 GD32C10x User Manual Bit position Bit name Reference setting value SBRSTEN No effect Reserved NREN Depends on memory NRTP NRMUX 0x1, depends on users NRBKEN EXMC_SNTCFG(write) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1, EXMC_CLK=2HCLK Time between EXMC_NE rising edge to 19-16 BUSLAT...
Page 512 GD32C10x User Manual 20.4. Register definition EXMC base address: 0xA000 0000 SRAM/NOR Flash control registers (EXMC_SNCTL) 20.4.1. Address offset: 0x00 Reset value: 0x0000 30DB This register has to be accessed by word (32-bit). SYNCWR CPS[2:0] Reserved ASYNCW EXMODE NRWTCF NRWTPO SBRSTE NRWTEN WREN...
Page 513 GD32C10x User Manual 1: Enable NWAIT signal WREN Write enable 0: Disable writing in the bank by the EXMC, otherwise an AHB error is reported 1: Enable writing in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only work in synchronous mode 0: NWAIT signal is active one data cycle before wait state 1: NWAIT signal is active during wait state WRAPEN...
Page 514 GD32C10x User Manual SRAM/NOR Flash timing configuration registers (EXMC_SNTCFG) 20.4.2. Address offset: 0x04 Reset value: 0x0FFF FFFF This register has to be accessed by word(32-bit) Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0] DSET[7:0] AHLD[3:0] ASET[3:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:28 ASYNCMOD[1:0] Asynchronous access mode...
Page 515 GD32C10x User Manual This field is meaningful only in asynchronous access. 0x00: Reserved 0x01: Data setup time = 2 * HCLK period …… 0xFF: Data setup time = 256 * HCLK period AHLD[3:0] Address hold time This field is used to set the time of address hold phase, which is only used in mode D and multiplexed mode.
Page 516 GD32C10x User Manual 10: Mode C access 11: Mode D access 27:20 Reserved Must be kept at reset value. 19:16 WBUSLAT[3:0] Bus latency Bus latency is added at the end of each write transaction to meet the minimum time between consecutive transactions. 0x0: Bus latency = 1 * HCLK period 0x1: Bus latency = 2 * HCLK period ……...
Page 517 GD32C10x User Manual Controller area network (CAN) 21.1. Overview CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. As CAN network interface, basic extended CAN supports the CAN protocols version 2.0A, 2.0B, ISO11898-1:2015 and BOSCH CAN FD specification.
Page 518: Figure 21-1. Can Module Block Diagram
GD32C10x User Manual  Time stamp on SOF reception.  Time stamp in last two data bytes transmission. Function overview 21.3. Figure 21-1. CAN module block diagram shows the CAN block diagram. Figure 21-1. CAN module block diagram Transmit CAN0 Rx FIFO[0..1] CAN0 Tx/Rx mailbox[0..2]...
Page 519 GD32C10x User Manual Sleep working mode to normal working mode: clear IWMOD and SLPWMOD bit in CAN_CTL register. Initial working mode When the configuration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode.
Page 520: Figure 21-2. Transmission Register
GD32C10x User Manual Loopback communication mode Loopback communication mode means the transmitted messages are transferred into the Rx FIFOs, the RX pin is disconnected from the CAN network and the TX pin can still send messages to the CAN network. Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave.
Page 521: Figure 21-3. State Of Transmit Mailbox
GD32C10x User Manual If FD frame would be transmitted, always write TMDATA00 registers when mailbox 0 is used, TMDATA01 register when mailbox 1 is used and TMDATA02 register when mailbox 2 is used until the end. For example, if application wants to transmit 64 bytes data using mailbox0, it needs to write the 64 bytes data through TMDATA00 register for 16 times.
Page 522 GD32C10x User Manual Step 4: Check the transmit status. Typically, MTF and MTFNERR are set if transmission is successful. Transmission options Abort MST bit in CAN_TSTAT register can abort the transmission. If the transmit mailbox’s status is pending or scheduled, the abort of transmission can be done immediately.
Page 523: Figure 21-4. Reception Register
GD32C10x User Manual Figure 21-4. Reception register Rx FIFO Rx FIFO has three mailboxes. The reception frames are stored in the mailbox according to the arriving sequence. First arrived frame can be accessed by application firstly. The number of frames in the Rx FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.
Page 524: Figure 21-5. 32-Bit Filter
GD32C10x User Manual Steps of receiving a message Step 1: Check the number of frames in the Rx FIFO. Step 2: Read CAN_RFIFOMIx, CAN_RFIFOMPx, CAN_RFIFOMDATA0x and CAN_RFIFOMDATA1x. Step 3: Set the RFD bit in CAN_RFIFOx register. Filtering function 21.3.5. The CAN receives frames from the CAN bus. If the frame passes the filter, it is stored in the Rx FIFOs.
Page 525: Figure 21-8. 16-Bit Mask Mode Filter
GD32C10x User Manual Figure 21-8. 16-bit mask mode filter List mode The filter consists of frame identifiers. The filter can determine whether a frame will be discarded or not. When one frame arrived, the filter will check which member can match the identifier of the frame.
Page 526: Table 21-2. Filtering Index
GD32C10x User Manual be left deactivated. Filtering index Each filter number corresponds to a filtering rule. When the frame which is associated with a filter number N passes the filters, the filter index is N. It stores in the FI bits in CAN_RFIFOMPx. Filter bank has filter index once it is associated with the FIFO no matter whether the bank is active or not.
Page 527 GD32C10x User Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active bank nunber bank nunber F8DATA1[31:16]- F10DATA1[31:16]- 16bits- ID 16bits-Mask F9DATA0[15:0]- F11DATA0[15:0]- 16bits-ID 16bits-ID F9DATA0[31:16]- F11DATA0[31:16]- 16bits-Mask 16bits- ID F9DATA1[15:0]- F11DATA1[15:0]- 16bits-ID 16bits-ID F9DATA1[31:16]- F11DATA1[31:16]- 16bits-Mask 16bits- ID F12DATA0-32bits- F13DATA0-32bits- F12DATA1-32bits- F13DATA1-32bits- Mask...
Page 528: Figure 21-11. The Bit Time
GD32C10x User Manual In this mode, the data is sent only once, and if the transmission fails due to arbitration failure or bus error, the CAN bus controller does not automatically resend the data as usual. At the end of sending, the MTF bit of register CAN_TSTAT is hardware set to 1, and the sending status information can be obtained via MTFNERR, MAL, and MTE.
Page 529 GD32C10x User Manual A valid edge is defined as the first toggle in a bit time from dominant to recessive bus level before the controller sends a recessive bit. If a valid edge is detected in BS1, not in SYNC_SEG, BS1 is added up to SJW maximumly, so that the sample point is delayed.
Page 530 GD32C10x User Manual sample point when recessive reserve bit is received. When Protocol Exception Handling is disabled (PRED bit in CAN_FDCTL register is 1), it will treat a recessive reserve bit as a form error and respond with an error frame. If any recessive reserve bit occurs, set PRE bit in CAN_FDSTAT register to 1.
Page 531: Figure 21-12. Transmitter Delay Measurement
GD32C10x User Manual Figure 21-12. Transmitter Delay Measurement CANTX CANRX TDCV TDCO TDCMOD =0,TDCV>=TDCF TDCO TDCMOD SSP position TDCF TDCO TDCMOD =0,TDCV<TDCF SSP position Error flags 21.3.10. The state of CAN bus can be reflected by Transmit Error Counter (TECNT) and Receive Error Counter (RECNT) of CAN_ERR register.
Page 532 GD32C10x User Manual The interrupt sources can be classified as:  Transmit interrupt.  FIFO0 interrupt. FIFO1 interrupt.  Error and status change interrupt.  Transmit interrupt The transmit interrupt can be generated by any of the following conditions and TMEIE bit in CAN_INTEN register will be set: ...
Page 533: Table 21-3. Can Event / Interrupt Flags
GD32C10x User Manual Table 21-3. CAN Event / Interrupt The CAN bus controller interrupt conditions can refer to flags. Table 21-3. CAN Event / Interrupt flags nterrupt event nterrupt / Event flag Enable control bit Mailbox 0 transmit finished flag (MTF0) Transmit interrupt Mailbox 1 transmit finished flag (MTF1) TMEIE...
Page 534 GD32C10x User Manual Register definition 21.4. CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 Control register (CAN_CTL) 21.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit). Reserved SWRST Reserved ABOR RFOD SLPWMOD IWMOD Bits...
Page 535 GD32C10x User Manual 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission 1: Disable automatic retransmission RFOD Rx FIFO overwrite disable 0: Enable Rx FIFO overwrite when Rx FIFO is full and overwrite the FIFO with the incoming frame 1: Disable Rx FIFO overwrite when Rx FIFO is full and discard the incoming frame Tx FIFO order...
Page 536 GD32C10x User Manual Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value.
Page 537 GD32C10x User Manual IWMOD bit in CAN_CTL register. If the CAN leaves normal working mode to initial working mode, it must wait the current frame transmission or reception to be completed. This bit is cleared by hardware when the CAN leaves initial working mode after clearing IWMOD bit in CAN_CTL register.
Page 538 GD32C10x User Manual 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty. These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted at last if all mailboxes are full.
Page 539 GD32C10x User Manual transmit starts. MTFNERR1 Mailbox 1 transmit finished with no error This bit is set when the transmission finishes and no error occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardware when the transmission finishes with error.
Page 540 GD32C10x User Manual This register has to be accessed by word(32-bit). Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RFD0 Rx FIFO0 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO0. This bit is reset by hardware when the dequeuing is done.
Page 541 GD32C10x User Manual 31:6 Reserved Must be kept at reset value. RFD1 Rx FIFO1 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO1. This bit is reset by hardware when the dequeuing is done. RFO1 Rx FIFO1 overfull This bit is set by hardware when Rx FIFO1 is overfull and reset by writting 1 to this...
Page 542 GD32C10x User Manual 1: Error interrupt enabled 14:12 Reserved Must be kept at reset value. ERRNIE Error number interrupt enable 0: Error number interrupt disabled 1: Error number interrupt enabled BOIE Bus-Off interrupt enable 0: Bus-Off interrupt disabled 1: Bus-Off interrupt enabled PERRIE Passive error interrupt enable 0: Passive error interrupt disabled...
Page 543 GD32C10x User Manual Error register (CAN_ERR) 21.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). RECNT[7:0] TECNT[7:0] Reserved ERRN[2:0] Reserved BOERR PERR WERR Bits Fields Descriptions 31:24 RECNT[7:0] Receive error count defined by the CAN standard 23:16 TECNT[7:0] Transmit error count defined by the CAN standard...
Page 544 GD32C10x User Manual Reset value: 0x0123 0000 This register has to be accessed by word(32-bit). SCMOD LCMOD Reserved. SJW[4:0] Reserved BS2[2:0] BS1[3:0] Reserved BS2[4:3] BS1[6:4] BAUDPSC[9:0] Bits Fields Descriptions SCMOD Silent communication mode 0: Silent communication disabled 1: Silent communication enabled LCMOD Loopback communication mode 0: Loopback communication disabled...
Page 545 GD32C10x User Manual Reserved Reserved ESIMOD TDCMOD TDCEN NSIO PRED Reserved FDEN Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. ESIMOD Error state indicator mode 0: Always displays the node error state. Transmit the dominant bit by error active nodes and transmit the recessive bit by error passive nodes.
Page 546 GD32C10x User Manual Reserved rc_w1 Reserved TDCV[6:0] Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. Protocol exception event This bit is set by hardware when protocol exception event is detected, this bit is cleared by writting 1. 15:7 Reserved Must be kept at reset value.
Page 547 GD32C10x User Manual Date Bit timing register (CAN_DBT) 21.4.12. Address offset: 0x2C Reset value: 0x0123 0000 This register has to be accessed by word(32-bit). Reserved DSJW[2:0] Reserved DBS2[2:0] DBS1[3:0] Reserved DBAUDPSC[9:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:24 DSJW[2:0] Resynchronization jump width...
Page 548 GD32C10x User Manual SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13] The frame identifier EFID[17:13]: Extended format frame identifier 15:3 EFID[12:0] The frame identifier EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame 1: Extended format frame Frame type 0: Data frame 1: Remote frame...
Page 549 GD32C10x User Manual 0: Classical frames 1: FD frames Reserved Must be kept at reset value. Bit rate of data switch 0: Bit rate not switch 1: The bit rate shall be switched from the nominal bit rate of the arbitration phase to bit rate of data the preconfigured of the data phase...
Page 550 GD32C10x User Manual DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8 DB5[7:0] Data byte 5 DB4[7:0] Data byte 4 Rx FIFO mailbox identifier register (CAN_RFIFOMIx) (x = 0,1) 21.4.17. Address offset: 0x1B0 + 0x10 * x Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
Page 551 GD32C10x User Manual Reserved Must be kept at reset value. Rx FIFO mailbox property register (CAN_RFIFOMPx) (x = 0,1) 21.4.18. Address offset: 0x1B4 + 0x10 * x Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit). TS[15:0] FI[7:0] Reserved DLENC[3:0]...
Page 552 GD32C10x User Manual DB3[7:0] DB2[7:0] DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Rx FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x = 0,1) 21.4.20. Address offset: 0x1BC + 0x10 * x Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
Page 553 GD32C10x User Manual Reserved HBC1F[5:0] Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 HBC1F[5:0] Header bank of CAN1 filter These bits are set and cleared by software to define the first bank for CAN1 filter. Bank0 ~ Bank HBC1F-1 is used for CAN0.
Page 554 GD32C10x User Manual Reserved FS27 FS26 FS25 FS24 FS23 FS22 FS21 FS20 FS19 FS18 FS17 FS16 FS15 FS14 FS13 FS12 FS11 FS10 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 Filter scale 0: Filter x with 16-bit scale 1: Filter x with 32-bit scale Filter associated FIFO register (CAN_FAFIFO) 21.4.24.
Page 555 GD32C10x User Manual FW15 FW14 FW13 FW12 FW11 FW10 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 Filter working 0: Filter x working disable 1: Filter x working enable Filter x data y register (CAN_FxDATAy) (x = 0...27, y = 0,1) 21.4.26.
Page 556 GD32C10x User Manual Universal serial bus full-speed interface (USBFS) The USBFS is available on GD32C10x series. 22.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution for portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol).
Page 557: Figure 22-1. Usbfs Block Diagram
GD32C10x User Manual 22.3. Block diagram Figure 22-1. USBFS block diagram interrupts Register AHB Slave Device bus Host Port control Control Data UTMI FIFO Transcation USB FS Scheduler Control VBUS USB Clock USB Clock Domain 48MHz 22.4. Signal description Table 22-1. USBFS signal description I/O port Type Description...
Page 558: Figure 22-2. Connection With Host Or Device Mode
GD32C10x User Manual Connection with host or device mode Figure 22-2. Connection with host or device mode USBFS 5V Power Supply GPIO (needed in host mode) VBUS VBUS When USBFS works in host mode (FHM bit is set and FDM bit is cleared), the VBUS is 5V power supplied and detecting pin which is used for voltage detection is defined in USB protocol.
Page 559: Figure 22-3. Connection With Otg Mode
GD32C10x User Manual Figure 22-3. Connection with OTG mode USBFS 5V Power GPIO Supply VBUS VBUS USB host function 22.5.2. USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state.
Page 560 GD32C10x User Manual detected and will trigger a disconnection flag after a disconnection event. PRST bit in USBFS_HPCS register is used for USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset. This bit only takes effect when port is at connected or enabled state.
Page 561 GD32C10x User Manual queues: periodic request queue and non-periodic request queue, to perform efficient transaction schedule. A request entry in a request queue described above may represent a USB transaction request or a channel operation request. Application needs to write packet into data FIFO via AHB bus if it wants to start an OUT transaction on USB bus.
Page 562 GD32C10x User Manual A USB device will enter into suspend state if the USB bus stays at IDLE state and there is no change on data lines for 3ms. When USB device is in suspend state, most of its clocks are closed to save power.
Page 563 GD32C10x User Manual be initialized typically by the user or an application on the On-The-Go B-Device. HNP may only be implemented through the Micro-AB receptacle on a device. Since On-The-Go devices have a Micro-AB receptacle, an On-The-Go device can be a host/device by default, depending on which type of plug (Micro-A plug for host, Micro-B plug for device) is inserted.
Page 564: Figure 22-5. Host Mode Fifo Space In Sram
GD32C10x User Manual Figure 22-5. HOST mode FIFO space in USBFS_HNPTFLEN and USBFS_HPTFLEN. SRAM describes the structure of these FIFOs in SRAM. The values in the figure are in terms of 32-bit words. Figure 22-5. HOST mode FIFO space in SRAM Start: 0x00 Rx FIFO RXFD...
Page 565: Figure 22-7. Device Mode Fifo Space In Sram
GD32C10x User Manual In device mode, the data FIFO is divided into several parts: 1 Rx FIFO, and 4 Tx FIFOs (one for each IN endpoint). All the OUT endpoints share the Rx FIFO for receiving packets. The size and start offset of these data FIFOs should be configured by using USBFS_GRFLEN Figure 22-7.
Page 566 GD32C10x User Manual Operation guide 22.5.6. This section describes the advised operation guide for USBFS. Host mode Global register initialization sequence 1. Program USBFS_GAHBCS register according to application’s demand, such as the Tx FIFO’s empty threshold, etc. GINTEN bit should be kept cleared at this time. 2.
Page 567 GD32C10x User Manual 4. Set CEN bit in USBFS_HCHxCTL register to enable the channel. Channel disable sequence Software can disable the channel by setting both CEN and CDIS bits at the same time. USBFS will generate a channel disable request entry in request queue after the register setting operation.
Page 568 GD32C10x User Manual After the whole packet data is written into the FIFO, USBFS generates a Tx request entry in the corresponding request queue and decreases the TLEN field in USBFS_HCHxLEN register by the written packet’s size. 4. When the request entry reaches the top of the request queue, USBFS begins to process this request entry.
Page 569 GD32C10x User Manual packet size, etc. 2. Program USBFS_DIEPINTEN or USBFS_DOEPINTEN register. Set the desired interrupt enable bits. 3. Program USBFS_DIEPxLEN or USBFS_DOEPxLEN register. PCNT is the number of packets in a transfer and TLEN is the total bytes number of all the transmitted or received packets in a transfer.
Page 570: Table 22-2. Usbfs Global Interrupt
GD32C10x User Manual 3. When an OUT token is received, USBFS receives the data packet or response with an NAK handshake based on the status of Rx FIFO and register configuration. If the transaction is finished successfully (USBFS receives and saves the data packet into Rx FIFO successfully sends...
Page 571 GD32C10x User Manual Interrupt flag Description Operation mode NPTXFEIF Non-Periodic Tx FIFO empty interrupt flag Host Mode RXFNEIF Rx FIFO non-empty interrupt flag Host or device mode Start of frame Host or device mode OTGIF OTG interrupt flag Host or device mode MFIF Mode fault interrupt flag Host or device mode...
Page 572 GD32C10x User Manual 22.7. Register definition USBFS base address: 0x5000 0000 Global control and status registers 22.7.1. Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 573 GD32C10x User Manual protocol. Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes. 15:12 Reserved Must be kept at reset value.
Page 574 GD32C10x User Manual Note: Only accessible in device mode. SRPS SRP success flag This bit is set by the core when SRP success, and this bit is cleared when SRPREQ bit is set. 0: SRP failure 1: SRP success Note: Only accessible in device mode. Global OTG interrupt flag register (USBFS_GOTGINTF) Address offset: 0x0004 Reset value: 0x0000 0000...
Page 575 GD32C10x User Manual Set by the core when a HNP ends. Read the HNPS in USBFS_GOTGCS register to get the result of HNP. Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP.
Page 576 GD32C10x User Manual Host mode: 0: NPTXFEIF will be triggered when the non-periodic Tx FIFO is half empty. 1: NPTXFEIF will be triggered when the non-periodic Tx FIFO is completely empty. 6：1 Reserved Must be kept at reset value. GINTEN Global interrupt enable 0: Global interrupt is not enabled.
Page 577 GD32C10x User Manual 1: Host mode The application must wait at least 25ms for the change taking effect after setting the force bit. Note: Accessible in both device and host modes. 28:14 Reserved Must be kept at reset value. 13:10 UTT[3:0] USB turnaround time Turnaround time in PHY clocks.
Page 578 GD32C10x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set. Host Mode: 00000: Only non-periodic Tx FIFO is flushed. 00001: Only periodic Tx FIFO is flushed.
Page 579 GD32C10x User Manual Set by the application to reset AHB clock domain circuit. Hardware automatically clears this bit after the reset process completes. After setting this bit, application should wait until this bit is cleared before any other operation on USBFS. Note: Accessible in both device and host modes.
Page 580 GD32C10x User Manual Reserved Must be kept at reset value. PTXFEIF Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the periodic Tx FIFO is either half or completely empty. The threshold is determined by the periodic Tx FIFO empty level bit (PTXFTH) in the USBFS_GAHBCS register.
Page 581 GD32C10x User Manual IEPIF IN endpoint interrupt flag Set by USBFS when one of the IN endpoints in device mode has raised an interrupt. Software should first read USBFS_DAEPINT register to get the endpoint number, and then read the corresponding USBFS_DIEPxINTF register to get the flags of the endpoint that cause the interrupt.
Page 582 GD32C10x User Manual Note: Only accessible in device mode. NPTXFEIF Non-periodic Tx FIFO empty interrupt flag This interrupt is triggered when the non-periodic Tx FIFO is either half or completely empty. The threshold is determined by the non-periodic Tx FIFO empty level bit (TXFTH) in the USBFS_GAHBCS register.
Page 583 GD32C10x User Manual still set. This register has to be accessed by word (32-bit) Bits Fields Descriptions WKUPIE Wakeup interrupt enable 0: Disable wakeup interrupt 1: Enable wakeup interrupt Note: Accessible in both host and device modes. SESIE Session interrupt enable 0: Disable session interrupt 1: Enable session interrupt Note: Accessible in both host and device modes.
Page 584 GD32C10x User Manual Note: Only accessible in host mode. HPIE Host port interrupt enable 0: Disable host port interrupt 1: Enable host port interrupt Note: Only accessible in host mode. 23:22 Reserved Must be kept at reset value. PXNCIE Periodic transfer not complete Interrupt enable 0: Disable periodic transfer not complete interrupt 1: Enable periodic transfer not complete interrupt Note: Only accessible in host mode.
Page 585 GD32C10x User Manual Note: Only accessible in device mode. RSTIE USB reset interrupt enable 0: Disable USB reset interrupt 1: Enable USB reset interrupt Note: Only accessible in device mode. SPIE USB suspend interrupt enable 0: Disable USB suspend interrupt 1: Enable USB suspend interrupt Note: Only accessible in device mode.
Page 586 GD32C10x User Manual MFIE Mode fault interrupt enable 0: Disable mode fault interrupt 1: Enable mode fault interrupt Note: Accessible in both device and host modes. Reserved Must be kept at reset value. Global receive status read/pop registers (USBFS_GRSTATR/USBFS_GRSTATP) Address offset for Read: 0x001C Address offset for Pop: 0x0020 Reset value: 0x0000 0000 A read to the receive status read register returns the entry of the top of the Rx FIFO.
Page 587 GD32C10x User Manual 00: DATA0 10: DATA1 Others: Reserved 14:4 BCOUNT[10:0] Byte count The byte count of the received IN data packet. CNUM[3:0] Channel number The channel number to which the current received packet belongs. Device mode: Bits Fields Descriptions 31:21 Reserved Must be kept at reset value.
Page 588 GD32C10x User Manual Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RXFD[15:0] Rx FIFO depth In terms of 32-bit words 1≤RXFD≤1024 Host non-periodic Tx FIFO length register/Device IN endpoint 0 Tx FIFO length...
Page 589 GD32C10x User Manual Host Mode: Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host non-periodic Tx FIFO depth In terms of 32-bit words 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host non-periodic Tx FIFO RAM start address The start address for non-periodic Tx FIFO RAM is in terms of 32-bit words. Device Mode: Bits Fields...
Page 590 GD32C10x User Manual 30:24 NPTXRQTOP[6:0] Top entry of the non-periodic Tx request queue Entry in the non-periodic transmit request queue. Bits 30:27: Channel number Bits 26:25: – 00: IN/OUT token – 01: Zero-length OUT packet – 11: Channel halt request Bit 24: Terminate flag, indicating last entry for selected channel.
Page 591 GD32C10x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. VBUSIG VBUS ignored When this bit is set, USBFS doesn’t monitor the voltage on VBUS pin and always considers the V voltage as valid both in host mode and in device mode, then frees the V pin for other usage.
Page 592 GD32C10x User Manual Bits Fields Descriptions 31:0 CID[31:0] Core ID Software can write or read this field and uses this field as a unique ID for its application. Host periodic Tx FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600 This register has to be accessed by word (32-bit) r/rw r/rw...
Page 593 GD32C10x User Manual Device IN endpoint Tx FIFO length register (USBFS_DIEPxTFLEN) (x = 1…3, where x is the FIFO_number) Address offset: 0x0104 + (FIFO_number – 1) × 0x04 Reset value: 0x0200 0400 This register has to be accessed by word (32-bit) r/rw r/rw Bits...
Page 594 GD32C10x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CLKSEL[1:0] Clock select for USB clock 01: 48MHz clock Others: Reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the frame interval when USBFS controller is enumerating USB device. This register has to be accessed by word (32-bit) Bits Fields...
Page 595 GD32C10x User Manual Host frame information remaining register (USBFS_HFINFR) Address offset: 0x408 Reset value: 0xBB80 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clock. 15:0 FRNUM[15:0] Frame number...
Page 596 GD32C10x User Manual Bits Fields Descriptions 31:24 PTXREQT[7:0] Top entry of the periodic Tx request queue Entry in the periodic Tx request queue. Bits 30:27: Channel number Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate flag, indicating last entry for selected channel.
Page 597 GD32C10x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. HACHINT[7:0] Host all channel interrupts Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host all channels interrupt enable register (USBFS_HACHINTEN) Address offset: 0x0418 Reset value: 0x0000 0000 This register can be used by software to enable or disable a channel’s interrupt.
Page 598 GD32C10x User Manual 0: Disable channel n interrupt 1: Enable channel n interrupt Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host port control and status register (USBFS_HPCS) Address offset: 0x0440 Reset value: 0x0000 0000 This register controls the port’s behavior and also has some flags which report the status of the port.
Page 599 GD32C10x User Manual Report the current state of USB data lines. Bit 10: State of DP line Bit 11: State of DM line Reserved Must be kept at reset value. PRST Port reset Application sets this bit to start a reset signal on USB port. Application should clear this bit when it wants to stop the reset signal.
Page 600 GD32C10x User Manual 0: Device is not connected to the port 1: Device is connected to the port Host channel x control register (USBFS_HCHxCTL) (x = 0…7 where x = channel_number) Address offset: 0x0500 + (channel_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields...
Page 601 GD32C10x User Manual The transfer type of the endpoint with which this channel communicates. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Low-speed device The device that this channel communicates with is a low-speed device. Reserved Must be kept at reset value. EPDIR Endpoint direction The transfer direction of the endpoint that this channel communicates with.
Page 602 GD32C10x User Manual 31:11 Reserved Must be kept at reset value. DTER Data toggle error The IN transaction gets a data packet but the PID of this packet doesn’t match DPID bits in USBFS_HCHxLEN register. REQOVR Request queue overrun The periodic request queue is full when software starts new transfers. BBER Babble error A babble condition occurs on USB bus.
Page 603 GD32C10x User Manual This register contains the interrupt enable bits for the flags in USBFS_HCHxINTF register. If a bit in this register is set by software, the corresponding bit in USBFS_HCHxINTF register is able to trigger a channel interrupt. The bits in this register are set and cleared by software. This register has to be accessed by word (32-bit) Bits Fields...
Page 604 GD32C10x User Manual STALLIE STALL interrupt enable 0: Disable STALL interrupt 1: Enable STALL interrupt Reserved Must be kept at reset value. CHIE Channel halted interrupt enable 0: Disable channel halted interrupt 1: Enable channel halted interrupt TFIE Transfer finished interrupt enable 0: Disable transfer finished interrupt 1: Enable transfer finished interrupt Host channel x transfer length register (USBFS_HCHxLEN) (x = 0…7, where x...
Page 605 GD32C10x User Manual 01: Reserved 28:19 PCNT[9:0] Packet count The number of data packets desired to be transmitted (OUT) or received (IN) in a transfer. Software should program this field before the channel is enabled. After the transfer starts, this field is decreased automatically after each successful data packet transmission.
Page 606 GD32C10x User Manual 12:11 EOPFT[1:0] End of periodic frame time This field defines the percentage time point in a frame that the end of periodic frame (EOPF) flag should be triggered. 00: 80% of the frame time 01: 85% of the frame time 10: 90% of the frame time 11: 95% of the frame time 10:4...
Page 607 GD32C10x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. POIF Power-on initialization finished Software should set this bit to notify USBFS that the registers have been initialized after waking up from power down state. CGONAK Clear global OUT NAK Software sets this bit to clear GONS bit in this register.
Page 608 GD32C10x User Manual 0: No remote wakeup signal generated 1: Generate remote wakeup signal Device status register (USBFS_DSTAT) Address offset: 0x0808 Reset value: 0x0000 0000 This register contains status and information of the USBFS in device mode. This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 609 GD32C10x User Manual This register contains the interrupt enable bits for the USBFS_DIEPxINTF register. If a bit in this register is set by software, the corresponding bit in USBFS_DIEPxINTF register is able to trigger an endpoint interrupt in USBFS_DAEPINT register. The bits in this register are set and cleared by software.
Page 610 GD32C10x User Manual Device OUT endpoint common interrupt enable register (USBFS_DOEPINTEN) Address offset: 0x0814 Reset value: 0x0000 0000 This register contains the interrupt enable bits for the USBFS_DOEPxINTF register. If a bit in this register is set by software, the corresponding bit in USBFS_DOEPxINTF register is able to trigger an endpoint interrupt in USBFS_DAEPINT register.
Page 611 GD32C10x User Manual 0: Disable transfer finished interrupt 1: Enable transfer finished interrupt Device all endpoints interrupt register (USBFS_DAEPINT) Address offset: 0x0818 Reset value: 0x0000 0000 When an endpoint interrupt is triggered, USBFS sets corresponding bit in this register and software should read this register to get which endpoint is asserting an interrupt.
Page 612 GD32C10x User Manual This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:16 OEPIE[3:0] Out endpoint interrupt enable 0: Disable OUT endpoint n interrupt 1: Enable OUT endpoint n interrupt Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.
Page 613 GD32C10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DVBUSDT[15:0] Device V discharge time There is a discharge process after V pulsing in SRP protocol. This field defines the discharge time of V The actual discharge time is 1024 * DVBUSDT[15:0] * BUS.
Page 614 GD32C10x User Manual This register contains the enable bits for the Tx FIFO empty interrupts of IN endpoints. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. IEPTXFEIE[3:0] IN endpoint Tx FIFO empty interrupt enable bits This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to set an endpoint interrupt bit in USBFS_DAEPINT register.
Page 615 GD32C10x User Manual Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should follow the operation guide to disable or enable an endpoint.
Page 616 GD32C10x User Manual MPL[1:0] Maximum packet length This field defines the maximum packet length for a control data packet. As described in USB 2.0 protocol, there are 4 kinds of length for control transfers: 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes Device IN endpoint x control register (USBFS_DIEPxCTL) (x = 1…3, where x =...
Page 617 GD32C10x User Manual SEVENFRM Set even frame (for isochronous IN endpoints) Software sets this bit to clear EOFRM bit in this register. SD0PID Set DATA0 PID (for interrupt/bulk IN endpoints) Software sets this bit to clear DPID bit in this register. SNAK Set NAK Software sets this bit to set NAKS bit in this register.
Page 618 GD32C10x User Manual 0: Only sends data in even frames 1: Only sends data in odd frames DPID Endpoint DATA PID (for interrupt/bulk IN endpoints) There is a DATA PID toggle scheme in interrupt or bulk transfer. Set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers according to the data toggle scheme described in USB protocol.
Page 619 GD32C10x User Manual 29:28 Reserved Must be kept at reset value. SNAK Set NAK Software sets this bit to set NAKS bit in this register. CNAK Clear NAK Software sets this bit to clear NAKS bit in this register 25:22 Reserved Must be kept at reset value.
Page 620 GD32C10x User Manual Device OUT endpoint x control register (USBFS_DOEPxCTL) (x = 1…3, where x = endpoint_number) Address offset: 0x0B00 + (endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the operations of each logical OUT endpoint except OUT endpoint 0.
Page 621 GD32C10x User Manual SNAK Set NAK Software sets this bit to set NAKS bit in this register. CNAK Clear NAK Software sets this bit to clear NAKS bit in this register. 25:22 Reserved Must be kept at reset value. STALL STALL handshake Software can set this bit to send STALL handshake during an OUT transaction.
Page 622 GD32C10x User Manual These is a data PID toggle scheme in interrupt or bulk transfer. Software should set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers following the data toggle scheme described in USB protocol. 0: Data packet’s PID is DATA0 1: Data packet’s PID is DATA1 EPACT...
Page 623 GD32C10x User Manual The setting of SNAK bit in USBFS_DIEPxCTL register takes effect. This bit can be cleared either by writing 1 to it or by setting CNAK bit in USBFS_DIEPxCTL register. Reserved Must be kept at reset value. EPTXFUD Endpoint Tx FIFO underrun This flag is triggered if the Tx FIFO has no packet data to send when an IN token is received.
Page 624 GD32C10x User Manual 31:7 Reserved Must be kept at reset value. BTBSTP Back-to-back SETUP packets ( Only for control OUT endpoint) This flag is triggered when a control out endpoint has received more than 3 back- to-back setup packets. Reserved Must be kept at reset value.
Page 625 GD32C10x User Manual 20:19 PCNT[1:0] Packet count The number of data packets desired to be transmitted in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically after each successful data packet transmission. 18:7 Reserved Must be kept at reset value.
Page 626 GD32C10x User Manual 11: 3 packets 28:20 Reserved Must be kept at reset value. PCNT Packet count The number of data packets desired to receive in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically after each successful data packet reception on bus.
Page 627 GD32C10x User Manual 11: 3 packets 28:19 PCNT[9:0] Packet count The number of data packets desired to be transmitted in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically after each successful data packet transmission. 18:0 TLEN[18:0] Transfer length...
Page 628 GD32C10x User Manual Program this field before SETUP transfers. Each time a back-to-back SETUP packet is received, USBFS decreases this field by one. When this field reaches zero, the BTBSTP flag in USBFS_DOEPxINTF register will be triggered. 00: 0 packet 01: 1 packet 10: 2 packets 11: 3 packets...
Page 629 GD32C10x User Manual IN endpoint’s Tx FIFO remaining space is in terms of 32-bit words: 0: Tx FIFO is full. 1: 1 word available … n: n words available Power and clock control register (USBFS_PWRCLKCTL) 22.7.4. Address offset: 0x0E00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields...
Page 630: Table 23-1. List Of Abbreviations Used In Register
GD32C10x User Manual Appendix 23.1. List of abbreviations used in register Table 23-1. List of abbreviations used in register abbreviations for Descriptions registers read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit.
Page 631 GD32C10x User Manual 23.3. Available peripherals For availability of peripherals and their number across all MCU series types, refer to the corresponding device data datasheet.
Page 632: Table 24-1. Revision History
GD32C10x User Manual Revision history Table 24-1. Revision history Revision No. Description Date Initial Release Dec.18, 2020 1. Modify the ESI bit description of Rx FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) and the HBC1F bit description of Filter control register (CAN_FCTL) in the CAN chapter.
Page 633 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

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