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GigaDevice Semiconductor GD32L23 Series User Manual

Arm cortex-m23 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32L23x

®

®

Arm

Cortex

-M23 32-bit MCU

User Manual

Revision 1.0

( Oct 2021 )

Table of Contents

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Page 1 GigaDevice Semiconductor Inc. GD32L23x ® ® Cortex -M23 32-bit MCU User Manual Revision 1.0 ( Oct 2021 )
Page 2: Table Of Contents
GD32L23x User Manual Table of Contents Table of Contents ......................2 List of Figures ......................18 List of Tables ........................ 24 1. System and memory architecture ................ 26 ® ® 1.1. Cortex -M23 processor ................... 26 1.2. System architecture ....................27 1.3.
Page 3 GD32L23x User Manual 2.3.11. Option bytes description ....................... 54 2.3.12. Page erase / program protection ..................55 2.3.13. Security protection ........................ 56 2.3.14. LVE sequence ........................56 2.4. Register definition ..................... 57 2.4.1. Wait state register (FMC_WS) ....................57 2.4.2. Unlock key register (FMC_KEY) ...................
Page 4 GD32L23x User Manual 4.3.3. Interrupt register (RCU_INT) ....................95 4.3.4. APB2 reset register (RCU_APB2RST) ................. 98 4.3.5. APB1 reset register (RCU_APB1RST) ................. 99 4.3.6. AHB enable register (RCU_AHBEN) .................. 101 4.3.7. APB2 enable register (RCU_APB2EN) ................103 4.3.8. APB1 enable register (RCU_APB1EN) ................104 4.3.9.
Page 5 GD32L23x User Manual 6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............. 134 6.6.5. Software interrupt event register (EXTI_SWIEV) ............... 135 6.6.6. Pending register (EXTI_PD) ....................135 7. General-purpose and alternate-function I/Os (GPIO and AFIO) ....... 136 7.1. Overview ........................136 7.2.
Page 6 GD32L23x User Manual 9. True random number generator (TRNG) ............161 9.1. Overview ........................161 9.2. Characteristics ......................161 9.3. Function overview ....................161 9.3.1. Operation flow ........................162 9.3.2. Error flags ........................... 162 9.4. Register definition ....................163 9.4.1. Control register (TRNG_CTL) .....................
Page 7 GD32L23x User Manual 11.5.2. DMAMUX request generator ....................183 11.5.3. Channel configurations ....................... 183 11.5.4. Interrupt ..........................184 11.5.5. DMAMUX mapping ......................184 11.6. Register definition ....................189 11.6.1. Request multiplexer channel x configuration register (DMAMUX_RM_CHxCFG) ..... 189 11.6.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) ....... 190 11.6.3.
Page 8 GD32L23x User Manual 13.4.10. External trigger........................213 13.4.11. DMA request ........................213 13.4.12. Temperature sensor and internal reference voltage V ..........214 REFINT 13.4.13. Battery voltage monitoring ....................215 13.4.14. SLCD voltage monitoring ....................215 13.4.15. ADC interrupts ........................215 13.4.16.
Page 9 GD32L23x User Manual 14.4.4. DAC_OUT 12-bit left-aligned data holding register (OUT_L12DH) ........240 14.4.5. DAC_OUT 8-bit right-aligned data holding register (OUT_R8DH) ........241 14.4.6. DAC_OUT data output register (OUT_DO) ................ 241 14.4.7. DAC Status register 0 (DAC_STAT0) ................. 242 Watchdog timer (WDGT) .................. 243 15.1.
Page 10 GD32L23x User Manual 16.4.4. Status register (RTC_STAT) ....................276 16.4.5. Prescaler register (RTC_PSC) ................... 278 16.4.6. Wakeup timer register (RTC_WUT) ..................278 16.4.7. Alarm 0 time and date register (RTC_ALRM0TD) .............. 279 16.4.8. Alarm 1 time and date register (RTC_ALRM1TD) .............. 280 16.4.9.
Page 11 GD32L23x User Manual 18.4.1. Clock selection ........................378 18.4.2. LPTIMER enable ........................ 380 18.4.3. Prescaler ..........................380 18.4.4. Input filter ..........................381 18.4.5. External inputs high level counter ..................381 18.4.6. Start counting mode ......................382 18.4.7. External trigger mapping ..................... 383 18.4.8.
Page 12 GD32L23x User Manual 19.3.13. Auto baudrate detection ...................... 423 19.3.14. ModBus communication ..................... 424 19.3.15. Receive FIFO ........................424 19.3.16. Wakeup from Deep-sleep mode ..................425 19.3.17. USART interrupts ........................ 425 19.4. Register definition ....................427 19.4.1. Control register 0 (USART_CTL0) ..................427 19.4.2.
Page 13 GD32L23x User Manual 20.4.8. Receive data register (LPUART_RDATA) ................471 20.4.9. Transmit data register (LPUART_TDATA) ................471 20.4.10. Coherence control register (LPUART_CHC) ..............472 Inter-integrated circuit interface (I2C) ............. 473 21.1. Overview ....................... 473 21.2. Characteristics ..................... 473 21.3. Function overview ....................473 21.3.1.
Page 14 GD32L23x User Manual 22.4. SPI signal description ..................515 22.4.1. Normal configuration (Not Quad-SPI Mode) ............... 515 22.4.2. Quad-SPI configuration ...................... 516 22.5. SPI function overview ..................516 22.5.1. SPI clock timing and data format ..................516 22.5.2. RXFIFO and TXFIFO ......................518 22.5.3.
Page 15 GD32L23x User Manual 23.4. Cryptographic acceleration processor ............... 561 23.4.1. DES/TDES cryptographic acceleration processor .............. 562 23.4.2. AES cryptographic acceleration processor ................. 566 23.5. Operating modes ....................574 23.6. CAU DMA interface ....................575 23.7. CAU interrupts ...................... 576 23.8. CAU suspended mode ..................
Page 16 GD32L23x User Manual 25.4. Register definition ....................600 25.4.1. Control register (SLCD_CTL) ..................... 600 25.4.2. Configuration register (SLCD_CFG) ................... 601 25.4.3. Status flag register (SLCD_STAT) ..................603 25.4.4. Status flag clear register (SLCD_STATC) ................604 Display data registers (SLCD_DATAx) (x=0…7) ..............605 25.4.5.
Page 17 GD32L23x User Manual [0..7] 27.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in [0..7] 27.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in [0..7] 27.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x can be in [0..7] 27.7.11.
Page 18: List Of Figures
GD32L23x User Manual List of Figures ® ® Figure 1-1. The structure of the Arm Cortex -M23 processor ..........27 Figure 1-2. Series system architecture of GD32L23x series ..........29 Figure 2-1. Process of page erase operation ................48 Figure 2-2. Process of mass erase operation ................49 Figure 2-3.
Page 19 GD32L23x User Manual Figure 13-12. Data alignment of 6-bit resolution ..............212 Figure 13-13. 20-bit to 16-bit result truncation ..............216 Figure 13-14. A numerical example with 5-bit shifting and rounding ......... 217 Figure 14-1. DAC block diagram ..................... 234 Figure 14-2.
Page 20 GD32L23x User Manual Figure 17-35. Restart mode ...................... 350 Figure 17-36. Pause mode ......................350 Figure 17-37. Event mode ......................351 Figure 17-38. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 ....352 Figure 17-39. Basic timer block diagram ................367 Figure 17-40.
Page 21 GD32L23x User Manual Figure 20-2. LPUART character frame ..................450 Figure 20-3. LPUART transmit procedure ................452 Figure 20-4. Configuration step when using DMA for LPUART transmission ....454 Figure 20-5. Configuration step when using DMA for LPUART reception ......455 Figure 20-6.
Page 22 GD32L23x User Manual Figure 22-13. Timing diagram of NSS pulse with continuous transmit ......526 Figure 22-14. Timing diagram of quad write operation in Quad-SPI mode ......527 Figure 22-15. Timing diagram of quad read operation in Quad-SPI mode ......528 Figure 22-16.
Page 23 GD32L23x User Manual Figure 22-47. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ......................540 Figure 22-48. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ......................540 Figure 22-49. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ......................
Page 24: List Of Tables
GD32L23x User Manual List of Tables Table 1-1. Bus Interconnection Matrix ..................27 Table 1-2. Memory map of GD32L23x series ................30 Table1-3. Boot modes ......................... 33 Table 2-1. 256KB flash base address and size for flash memory .......... 43 Table 2-2.
Page 25 GD32L23x User Manual Table 17-3. Examples of slave mode ..................309 Table 17-4．Slave controller examples .................. 349 Table 18-1. Prescaler division ratios ..................380 Table 18-2. External trigger mapping ..................383 Table 18-3. Counting direction versus decoder signals ............388 Table 18-4.
Page 26: System And Memory Architecture
GD32L23x User Manual System and memory architecture ® The GD32L23x series are 32-bit general-purpose microcontrollers based on the Arm ® ® ® Cortex -M23 processor. The Arm Cortex -M23 processor includes AHB buses. All memory ® ® accesses of the Arm Cortex -M23 processor are executed on the AHB buses according to the different purposes and the target memory spaces.
Page 27: System Architecture
GD32L23x User Manual ® ® Figure 1-1. The structure of the Arm Cortex -M23 processor Nested Data Vectored IRQ interface Cortex-M23 Watchpoint Interrupt Processor core And Trace Controller (DWT) (NVIC) Breakpoint Processor Unit Romtable Bus Matrix Single-cycle IO Single Wire AHB Master port Debug interface...
Page 28 GD32L23x User Manual (peripheral bus) to a bus matrix that manages the arbitration between the core and the DMA. DMA bus connects the AHB master interface of the DMA to the bus matrix that manages the access of CPU and DMA to SRAMs, Flash memory and AHB/APB peripherals. There are also several slaves connected with the AHB interconnect matrix, including FMC, SRAM0, SRAM1, AHB1, AHB2.
Page 29: Memory Map
GD32L23x User Manual Figure 1-2. Series system architecture of GD32L23x series 1.1/0.9V TPIU GPIO Ports POR/PDR/ AHB2: Fma x = 64MHz A, B, C, D, F SBus SRAM ARM Cortex-M23 SRAM1(16K) Controller Processor SBus SBus SRAM : 64MHz SRAM2(16K) Controller SBus Flash 256K...
Page 30: Table 1-2. Memory Map Of Gd32L23X Series
GD32L23x User Manual ® ® Cortex -M23 processor to reduce the software complexity of repeated implementation ® ® of different device vendors. However, some regions are used by the Arm Cortex -M23 system peripherals. The following figure shows the memory map of GD32L23x series, including Code, SRAM, peripheral, and other pre-defined regions.
Page 31 GD32L23x User Manual Pre-defined ADDRESS Peripherals Regions 0x4001 5C00 - 0x4001 7BFF Reserved 0x4001 5800 - 0x4001 5BFF 0x4001 5000 - 0x4001 57FF Reserved 0x4001 4C00 - 0x4001 4FFF TIMER8 0x4001 3C00 - 0x4001 4BFF Reserved 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF Reserved...
Page 32: On-Chip Sram Memory
GD32L23x User Manual Pre-defined ADDRESS Peripherals Regions 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF 0x4000 2400 - 0x4000 27FF SLCD 0x4000 2000 - 0x4000 23FF Reserved 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF TIMER11 0x4000 1400 - 0x4000 17FF TIMER6...
Page 33: Boot Configuration
GD32L23x User Manual All of, byte, half-word (16 bits) and word (32 bits) read accesses are supported. The flash memory can be programmed word (32 bits). Each page of the flash memory can be erased individually. The whole flash memory space except information blocks can be erased at a time.
Page 34: System Configuration Registers
GD32L23x User Manual 1.6. System configuration registers SYSCFG base address: 0x4001 0000 1.6.1. System configuration register 0 (SYSCFG_CFG0) Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the BOOT1 pin after reset) This register can be accessed by word(32-bit) PB9_HC PB8_HC...
Page 35: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32L23x User Manual pin is bypassed. 15:7 Reserved Must be kept at reset value BOOT0_PD3_RMP BOOT0 and PD3 remapping bit. It controls the mapping of either BOOT0 or PD3 function on the BOOT0 pin. When BOOT0_PD3_RMP is set, the BOOT0 function is tied to 0 by hardware after reset.
Page 36: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32L23x User Manual X000: PA3 pin X001: PB3 pin X010: PC3 pin X011: PD3 pin X100: reserved X101: reserved X110: reserved X111: reserved 11:8 EXTI2_SS[3:0] EXTI 2 sources selection X000: PA2 pin X001: PB2 pin X010: PC2 pin X011: PD2 pin X100: reserved X101: reserved X110: reserved...
Page 37 GD32L23x User Manual Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 EXTI7_SS[3:0] EXTI 7 sources selection X000: PA7 pin X001: PB7 pin X010: PC7 pin X011: reserved X100: reserved X101: reserved X110: reserved...
Page 38: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32L23x User Manual X100: reserved X101: reserved X110: reserved X111: reserved 1.6.4. EXTI sources selection register 2 (SYSCFG_EXTISS2) Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by word(32-bit) Reserved EXTI11_SS [3:0] EXTI10_SS [3:0] EXTI9_SS [3:0] EXTI8_SS [3:0] Bits Fields Descriptions...
Page 39: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32L23x User Manual X011: PD9 pin X100: reserved X101: reserved X110: reserved X111: reserved EXTI8_SS[3:0] EXTI 8 sources selection X000: PA8 pin X001: PB8 pin X010: PC8 pin X011: PD8 pin X100: reserved X101: reserved X110: reserved X111: reserved 1.6.5. EXTI sources selection register 3 (SYSCFG_EXTISS3) Address offset: 0x14 Reset value: 0x0000 0000...
Page 40: Irq Latency Register (Syscfg_Cpu_Irq_Lat)
GD32L23x User Manual X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved EXTI13_SS[3:0] EXTI 13 sources selection X000: PA13 pin X001: PB13 pin X010: PC13 pin X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved EXTI12_SS[3:0] EXTI 12 sources selection X000: PA12 pin X001: PB12 pin X010: PC12 pin...
Page 41: Device Electronic Signature
GD32L23x User Manual the AHB-Lite interface. If IRQ_LATENCY is set to 0, interrupts are taken as quickly as possible. ® ® For non-zero values, the Arm Cortex -M23 processor ensures that a minimum of IRQ_LATENCY+1 hclk cycles exist between an interrupt becoming pended in the NVIC and the vector fetch for the interrupt being performed.
Page 42 GD32L23x User Manual UNIQUE_ID[31:16] UNIQUE_ID[15:0] Bits Fields Descriptions 31:0 UNIQUE_ID[31:0] Unique device ID Base address: 0x1FFF F7EC The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit) UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0...
Page 43: Flash Memory Controller (Fmc)
GD32L23x User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 256K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 44: Table 2-2. 128Kb Flash Base Address And Size For Flash Memory
GD32L23x User Manual Block Name Address range size(bytes) Page 63 0x0803 E000 - 0x0803 FFFF Information block Boot loader area 0x1FFF D000- 0x1FFF F7FF 10KB Option bytes block Option bytes 0x1FFF F800 - 0x1FFF F80F One-time program block OTP bytes 0x1FFF_7000~0x1FFF_71FF 512B Note: The information block stores the boot loader.
Page 45: Read Operations
GD32L23x User Manual Table 2-4. 32KB flash base address and size for flash memory Block Name Address range size(bytes) Page 0 0x0800 0000 - 0x0800 03FF Page 1 0x0800 0400 - 0x0800 07FF Page 2 0x0800 0800 - 0x0800 0BFF Main flash block Page 31 0x08007C00 - 0x0800 7FFF...
Page 46: Unlock The Fmc_Ctl Register
GD32L23x User Manual It is forbidden to increase the AHB clock frequency before configure the WSCNT. 2. If want to decrease the AHB clock frequency. First, decrease the AHB clock frequency to target frequency. Then refer to the correspondence table between WSCNT bit and AHB clock frequency, configure the WSCNT bits according the target AHB clock frequency.
Page 47: Page Erase
GD32L23x User Manual 2.3.4. Page erase The FMC provides a page erase function which is used to initialize the contents of a main flash memory page to a high state. Each page can be erased independently without affecting the contents of other pages. The following steps show the access sequence of the registers for a page erase operation.
Page 48: Mass Erase
GD32L23x User Manual Figure 2-1. Process of page erase operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish 2.3.5.
Page 49: Main Flash Programming
GD32L23x User Manual and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. Since all flash data will be modified to a value of 0xFFFF_FFFF, the mass erase operation can be implemented using a program that runs in SRAM or using the debugging tool that accesses the FMC registers directly.
Page 50 GD32L23x User Manual  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in the FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
Page 51: Main Flash Fast Programming
GD32L23x User Manual Figure 2-3. Process of word program operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0 Finish Note: Reading the flash should be avoided when a program/erase operation is ongoing in the same bank.
Page 52: Figure 2-4. Process Of Fast Program Operation
GD32L23x User Manual FMC_STAT register.  Read and verify the Flash memory if required using a BUS access. When the operation is executed successfully, the END in FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. Note that there are some program error need caution: The program operation will be ignored on erase/program protected pages and WPERR bit in FMC_STATx is set.
Page 53: Otp Programming
GD32L23x User Manual 2. If try to read the flash memory(use BUS from eflash macro(not CBUF/PBUF/cache)) while fast programming mode is ongoing, the fast programming will be aborted and the END bit in FMC_STAT register will be set. 3. When the flash interface has received the first word, programming starts automatically. When the high voltage is applied for the first word, the BUSY bit is set, and when the last word has been programmed, the BUSY bit is cleared.
Page 54: Option Bytes Modify
GD32L23x User Manual  Read and verify the flash memory using a DBUS access if required. When the operation is executed successful, the ENDF bit in the FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. 2.3.10.
Page 55: Page Erase / Program Protection
GD32L23x User Manual Address Name Description 0x1fff f801 SPC_N SPC complement value [7:5]: BOR_TH (Brown out reset threshold) 000/101/110/111: BOR Level 0, brownout threshold level 0 (1.6V) 001: BOR Level 1, brownout threshold level 1 (2.0V) 010: BOR Level 2, brownout threshold level 2 (2.2V) 011: BOR Level 3, brownout threshold level 3 (2.5V) 100: BOR Level 4, brownout threshold level 4 (2.8V) [4:3]: reserved...
Page 56: Security Protection
GD32L23x User Manual page, the WPERR bit in the FMC_STAT register will be set by the FMC. If the WPERR bit is set and the ERRIE bit is also set to 1 to enable the corresponding interrupt, then the flash operation error interrupt will be triggered by the FMC to draw the attention of the CPU.
Page 57: Register Definition
GD32L23x User Manual 2.4. Register definition FMC base address: 0x4002 2000 2.4.1. Wait state register (FMC_WS) Address offset: 0x00 Reset value: 0x0000 0630 This register has to be accessed by word (32-bit). Reserved SLEEP_S Reserved RUN_SLP Reserved Reserved PFEN Reserved WSCNT[2:0] Bits Fields...
Page 58: Unlock Key Register (Fmc_Key)
GD32L23x User Manual Reserved Must be kept at reset value. WSCNT[2:0] Wait state counter register These bits is set and reset by software. 000: 0 wait state added 001: 1 wait state added 010: 2 wait state added 011: 3 wait state added 010 ~111: reserved 2.4.2.
Page 59: Status Register (Fmc_Stat)
GD32L23x User Manual Write OBKEY[31:0] with keys to unlock option bytes command in the FMC_CTL register. 2.4.4. Status register (FMC_STAT) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FSTAT Reserved ENDF WPERR PGAERR PGERR Reserved...
Page 60: Control Register (Fmc_Ctl)
GD32L23x User Manual 2.4.5. Control register (FMC_CTL) Address offset: 0x10 Reset value: 0x0000 0080 This register has to be accessed by word (32-bit). Reserved Reserved ENDIE Reserved ERRIE OBWEN FSTPG START OBER OBPG Reserved Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. ENDIE End of operation interrupt enable bit This bit is set or cleared by software...
Page 61: Address Register (Fmc_Addr)
GD32L23x User Manual 1: option byte erase command OBPG Option bytes program command bit This bit is set or clear by software 0: no effect 1: option bytes program command Reserved Must be kept at reset value. Main flash mass erase command bit This bit is set or cleared by software 0: no effect 1: main flash mass erase command...
Page 62: Erase/Program Protection Register (Fmc_Wp)
GD32L23x User Manual Reset value: 0x0XXX XXXX. This register has to be accessed by word(32-bit). Reserved DATA[15:6] DATA[5:0] USER[7:0] OBERR Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:10 DATA[15:0] Store DATA[15:0] of option bytes block after system reset. USER[7:0] Store USER of option bytes block after system reset.
Page 63: Product Id Register (Fmc_Pid)
GD32L23x User Manual This register has to be accessed by word (32-bit). SLPKEY[31:16] SLPKEY[15:0] Bits Fields Descriptions 31:0 SLPKEY[31:0] RUN_SLP unlock register These bits are only be written by software. Write SLPKEY[31:0] with keys to unlock RUN_SLP bit in FMC_WS register. SLPKEY1: 0x04152637 SLPKEY2: 0xBCAD9E8F 2.4.10.
Page 64: Power Management Unit (Pmu)
GD32L23x User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32L23x series. According to the Power management unit (PMU), provides ten types of power saving modes, including Run, Run1, Run2, Sleep, Sleep1, Sleep2, Deep-sleep, Deep- sleep 1, Deep-sleep 2 and Standby mode.
Page 65: Function Overview
GD32L23x User Manual 3.3. Function overview Figure 3-1. Power supply overview provides details on the internal configuration of the PMU and the relevant power domains. Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR PC13 WKUPx WKUPR BKP PAD WKUPN NRST...
Page 66 GD32L23x User Manual RC oscillator (IRC32K) or the Low Speed Crystal oscillator (LXTAL), or HXTAL clock divided by 32. When V is shut down, only LXTAL is valid for RTC. Before entering the power saving ® mode by executing the WFI/WFE instruction, the Cortex -M23 can setup the RTC register with an expected alarm time and enable the alarm function and according EXTI lines to achieve the RTC alarm event.
Page 67: Figure 3-2. Waveform Of The Por/Pdr
GD32L23x User Manual which resets the whole chip except the Backup domain when the supply voltage is lower than the specified threshold. Figure 3-2. Waveform of the POR/PDR shows the relationship between the supply voltage and the power reset signal. V , which typical value is 1.60V, indicates the threshold of power on reset, while V , which typical value is 1.56V, means the...
Page 68 GD32L23x User Manual Figure 3-3. Waveform of the BOR 100mV hyst BOR Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in PMU_CS, indicates if V higher or lower than the LVD threshold.
Page 69: Power Domain
GD32L23x User Manual Figure 3-4. Waveform of the LVD threshold threshold 100mV hyst LVD output Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply V is implemented to achieve better performance of analog circuits.
Page 70: Power Saving Modes
GD32L23x User Manual default. The COREOFF1 domain needs to be powered on when using modules in the COREOFF1 domain. The COREOFF1 domain can be powered off in order to reduce the power consumption in Run/Run1/Run2 mode. To further reduce power consumption in low- power mode (Sleep/Sleep1/Sleep2/Deep-sleep/Deep-sleep1/Deep-sleep2), the COREOFF1 domain can be powered off before entering the low-power mode.
Page 71 GD32L23x User Manual Sleep mode ® The Sleep mode is corresponding to the SLEEPING mode of the Cortex -M23. In Sleep mode, ® only clock of Cortex -M23 is off. To enter the Sleep mode, it is only necessary to clear the ®...
Page 72 GD32L23x User Manual Note: In order to enter Deep-sleep mode smoothly, all EXTI line pending status (in the EXTI_PD register) and RTC Alarm/timestamp/tamper/auto wakeup flag must be reset. If not, the program will skip the entry process of Deep-sleep mode to continue to execute the following procedure.
Page 73: Table 3-1. Power Saving Mode Summary
GD32L23x User Manual IRC16M, IRC48M, HXTAL and PLLs are disabled. Before entering the Standby mode, it is ® necessary to set the SLEEPDEEP bit in the Cortex -M23 System Control Register, and set the LPMOD bits to “11” in the PMU_CTL0 register, and clear WUF bit in the PMU_CS register. Then, the device enters the Standby mode after a WFI or WFE instruction is executed, and the STBF status flag in the PMU_CS register indicates that the MCU has been in Standby mode.
Page 74 GD32L23x User Manual Wakeup Wakeup Mode Description Entry Wakeup status Latency sleep 1 domain are off LPLDO on 1, LPMOD = 01, lines for WFI wakeup time, 2. Disable IRC16M, WFI or WFE Any event(or interrupt + NPLDO IRC48M, HXTAL and when SEVONPEND is wakeup PLLs...
Page 75: Register Definition
GD32L23x User Manual 3.4. Register definition PMU base address: 0x4000 7000 3.4.1. Control register 0 (PMU_CTL0) Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode). This register can be accessed by half-word(16-bit) or word(32-bit). Reserved LDNPDS LDOVS[1:0] VCRSEL VCEN...
Page 76: Control And Status Register (Pmu_Cs)
GD32L23x User Manual BKPWEN Backup Domain Write Enable 0: Disable write access to the registers in Backup domain. 1: Enable write access to the registers in Backup domain. After reset, any write access to the registers in Backup domain is ignored. This bit has to be set to enable write access to these registers.
Page 77 GD32L23x User Manual LDOVSR Reserved Reserved WUPEN4 WUPEN3 WUPEN2 WUPEN1 WUPEN0 Reserved LVDF STBF Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. LPRDY LPLDO ready flag 0: LPLDO is not ready. 1: LPLDO is ready. NPRDY NPLDO ready flag 0: NPLDO is not ready.
Page 78: Control Register 1 (Pmu_Ctl1)
GD32L23x User Manual WUPEN1 WKUP Pin1(PC13) enable 0: Disable WKUP pin1 function. 1: Enable WKUP pin1 function. If WUPEN1 is set before entering the power saving mode, a rising edge on the WKUP pin1 wakes up the system from the power saving mode. As the WKUP pin1 is active high, the WKUP pin1 is internally configured to input pull down mode.
Page 79: Status Register (Pmu_Stat)
GD32L23x User Manual SRAM1P Reserved NRRD2 CORE1W CORE1S SRAM1P SRAM1P Reserved Reserved LEEP WAKE SLEEP Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. SRAM1PD2 Power state of SRAM1 when enters Deep-sleep2 mode 0: SRAM1 power-off. 1: SRAM1 power same as Run/Run1/Run2 mode. Note: When wakeup from the Deep-sleep2 mode, the power state of SRAM1 is the same as the power state before entering the Deep-sleep2 mode.
Page 80: Parameter Register (Pmu_Par)
GD32L23x User Manual Reserved CORE1P SRAM1P CORE1P SRAM1P Reserved S_ACTIV S_ACTIV DPF2 Reserved S_SLEEP S_SLEEP rc_w0 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. CORE1PS_ACTIVE COREOFF1 domain is in active state. CORE1PS_SLEEP COREOFF1 domain is in sleep state. SRAM1PS_ACTIVE SRAM1 is in active state.
Page 81 GD32L23x User Manual TWKCORE1EN Use software value when wake up COREOFF1 or not 0: use hardware ack signal when wake up COREOFF1. 1: use software value when wake up COREOFF1, the value is set by TWK_CORE1[7:0]. 28:21 TWK_CORE1[7:0] Wakeup time of power switch of COREOFF1 domain. 4 clock step and the max value is 64us.
Page 82: Reset And Clock Unit (Rcu)
GD32L23x User Manual Reset and clock unit (RCU) 4.1. Reset control unit (RCTL) 4.1.1. Overview GD32L23x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power on reset, known as a cold reset, resets the full system except the backup domain during a power up.
Page 83: Clock Control Unit (Cctl)
GD32L23x User Manual Figure 4-1. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us pulse System Reset FWDGT_RSTn generator SW_RSTn OB_STDBY_RSTn OB_DPSLP_RSTn Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V power on).
Page 84: Figure 4-2. Clock Tree
GD32L23x User Manual Figure 4-2. Clock tree CK_I2S (to I2S) IRC16M CK_IRC1 divide 6MDIV CK_FMC ÷ 1,2,4,8,16 FMC enable SCS[1:0] (to FMC) (by hardware) HCLK CK_IRC16M AHB enable (to AHB bus,Cortex-M23,SRAM,DMA) 16 MHz CK_CST X4,5， CK_PLL CK_SYS CK_AHB IRC16M ÷ 1,2. ÷...
Page 85: Characteristics
GD32L23x User Manual The FWDGT is clocked by IRC32K clock, which is forced on when FWDGT started. The LPTIMER is clocked by IRC16MDIV clock or LXTAL clock or system clock or APB2 clock, which selected by LPTIMERSEL bits in configuration register 2 (RCU_CFG2). If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1.
Page 86 GD32L23x User Manual Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the control register 0, RCU_CTL0. The CK_HXTAL is equal to the external clock which drives the OSCIN pin. Internal 16 MHz RC Oscillator (IRC16M) The Internal 16 MHz RC oscillator, IRC16M, has a fixed frequency of 16 MHz and is the default clock source selection for the CPU when the device is powered up.
Page 87 GD32L23x User Manual RCU_CTL0. The PLLSTB flag in the Control register 0, RCU_CTL0 will indicate if the PLL clock is stable. An interrupt can be generated if the related interrupt enable bit, PLLSTBIE, in the Interrupt register, RCU_INT, is set as the PLL becomes stable. Low Speed Crystal Oscillator (LXTAL) The low speed crystal or ceramic resonator oscillator, which has a frequency of 32,768 Hz, produces a low power but highly accurate clock source for the Real Time Clock circuit.
Page 88: Table 4-1. Clock Source Select
GD32L23x User Manual source to IRC16M and the PLL will be disabled automatically LXTAL Clock Monitor (LCKM) A clock monitor on LXTAL can be activated by software writing the LXTALCKMEN bit in the control register (RCU_CTL). LXTALCKMEN can not be enabled before LXTAL and IRC32K are enabled and ready.
Page 89 GD32L23x User Manual LPUART/USART0/USART1 can’t close the LXTAL), which used to the LPUART to wake up the deep-sleep 1/2 mode. If the I2C0 / I2C1 / I2C2 clock is selected IRC16M_DIV clock in deep-sleep 1/2 mode, they have capable of open IRC16M clock or close IRC16M clock, which used to the I2C0 / I2C1 / I2C2 to wake up the deep-sleep 1/2 mode.
Page 90: Register Definition
GD32L23x User Manual 4.3. Register definition RCU base address: 0x4002 1000 4.3.1. Control register (RCU_CTL) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) LXTALCK LXTALCK IRC48MS IRC48ME HXTALB HXTALST HXTALE...
Page 91 GD32L23x User Manual enabled) and ready (LXTALSTB flag set by hardware). IRC48MSTB IRC48M oscillator stabilization flag Set by hardware to indicate if the IRC48M oscillator is stable and ready for use. 0: IRC48M oscillator is not stable 1: IRC48M oscillator is stable IRC48MEN Internal high speed oscillator enable Set and reset by software.
Page 92: Configuration Register 0 (Rcu_Cfg0)
GD32L23x User Manual MHz ± 1%. Reserved Must be kept at reset value. IRC16MSTB IRC16M high speed internal oscillator stabilization flag Set by hardware to indicate if the IRC16M oscillator is stable and ready for use. 0: IRC16M oscillator is not stable 1: IRC16M oscillator is stable IRC16MEN Internal high speed oscillator enable...
Page 93 GD32L23x User Manual see bits 23:18 of RCU_CFG0 26:24 CKOUTSEL[2:0] CK_OUT clock source selection Set and reset by software. 000: No clock selected 001: Internal 48MHz RC oscillator clock selected 010: Internal 32K RC oscillator clock selected 011: External low speed oscillator clock selected 100: System clock selected 101: Internal 16MHz RC oscillator clock selected 110: External high speed oscillator clock selected...
Page 94 GD32L23x User Manual 1111: (CK_AHB / 17) selected 13:11 APB2PSC[2:0] APB2 prescaler selection Set and reset by software to control the APB2 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected 10:8 APB1PSC[2:0]...
Page 95: Interrupt Register (Rcu_Int)
GD32L23x User Manual 11: select CK_IRC48M as the CK_SYS source 4.3.3. Interrupt register (RCU_INT) Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) LXTALCK IRC48M HXTAL IRC16M LXTAL IRC32K Reserved CKMIC STBIC STBIC STBIC STBIC...
Page 96 GD32L23x User Manual Write 1 by software to reset the IRC16MSTBIF flag. 0: Not reset IRC16MSTBIF flag 1: Reset IRC16MSTBIF flag LXTALSTBIC LXTAL stabilization interrupt clear Write 1 by software to reset the LXTALSTBIF flag. 0: Not reset LXTALSTBIF flag 1: Reset LXTALSTBIF flag IRC32KSTBIC IRC32K stabilization interrupt clear...
Page 97 GD32L23x User Manual 1: Enable the IRC32K stabilization interrupt CKMIF HXTAL clock stuck interrupt flag Set by hardware when the HXTAL clock is stuck. Reset by software when setting the CKMIC bit. 0: Clock operating normally 1: HXTAL clock stuck LXTALCKMIF LXTAL clock stuck interrupt flag Set by hardware when the LXTAL clock is stuck.
Page 98: Apb2 Reset Register (Rcu_Apb2Rst)
GD32L23x User Manual Set by hardware when the internal 32kHz RC oscillator clock is stable and the IRC32KSTBIE bit is set. Reset by software when setting the IRC32KSTBIC bit. 0: No IRC32K stabilization clock ready interrupt generated 1: IRC32K stabilization interrupt generated 4.3.4.
Page 99: Apb1 Reset Register (Rcu_Apb1Rst)
GD32L23x User Manual Reserved Must be kept at reset value CMPRST Comparator reset This bit is set and reset by software. 0: No reset 1: Reset comparator SYSCFGRST System configuration reset This bit is set and reset by software. 0: No reset 1: Reset system configuration 4.3.5.
Page 100 GD32L23x User Manual I2C2RST I2C2 reset This bit is set and reset by software. 0: No reset 1: Reset I2C2 USBDRST USBD reset This bit is set and reset by software. 0: No reset 1: Reset USBD I2C1RST I2C1 reset This bit is set and reset by software.
Page 101: Ahb Enable Register (Rcu_Ahben)
GD32L23x User Manual This bit is set and reset by software. 0: No reset 1: Reset window watchdog timer SLCDRST SLCD reset This bit is set and reset by software. 0: No reset 1: Reset SLCD LPTIMERRST LPTIMER timer reset This bit is set and reset by software.
Page 102 GD32L23x User Manual Reserved PFEN Reserved PDEN PCEN PBEN PAEN Reserved SRAM1SP FMCSPE SRAM0S Reserved CRCEN Reserved Reserved Reserved DMAEN Bits Fields Descriptions 31:23 Reserved Must be kept at reset value PFEN GPIO port F clock enable This bit is set and reset by software. 0: Disabled GPIO port F clock 1: Enabled GPIO port F clock Reserved...
Page 103: Apb2 Enable Register (Rcu_Apb2En)
GD32L23x User Manual 0: Disabled CRC clock 1: Enabled CRC clock Reserved Must be kept at reset value FMCSPEN FMC clock enable This bit is set and reset by software to enable/disable FMC clock during Sleep mode. 0: Disabled FMC clock during Sleep mode 1: Enabled FMC clock during Sleep mode Reserved Must be kept at reset value...
Page 104: Apb1 Enable Register (Rcu_Apb1En)
GD32L23x User Manual 1: Enabled DBGMCU clock 21:15 Reserved Must be kept at reset value USART0EN USART0 clock enable This bit is set and reset by software. 0: Disabled USART0 clock 1: Enabled USART0 clock Reserved Must be kept at reset value SPI0EN SPI0 clock enable This bit is set and reset by software.
Page 105 GD32L23x User Manual WWDGT LPTIMER TIMER11 TIMER6E TIMER5E TIMER2E TIMER1E Reserved SPI1EN Reserved SLCDEN Reserved Reserved Bits Fields Descriptions BKPEN BKP (RTC) clock enable This bit is set and reset by software. 0: Disabled BKP(RTC) clock 1: Enabled BKP (RTC) clock CTCEN CTC clock enable This bit is set and reset by software.
Page 106 GD32L23x User Manual 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software. 0: Disabled UART3 clock 1: Enabled UART3 clock LPUARTEN LPUART clock enable...
Page 107: Backup Domain Control Register (Rcu_Bdctl)
GD32L23x User Manual Reserved Must be kept at reset value TIMER6EN TIMER6 timer clock enable This bit is set and reset by software. 0: Disabled TIMER6 timer clock 1: Enabled TIMER6 timer clock TIMER5EN TIMER5 timer clock enable This bit is set and reset by software. 0: Disabled TIMER5 timer clock 1: Enabled TIMER5 timer clock Reserved...
Page 108: Reset Source /Clock Register (Rcu_Rstsck)
GD32L23x User Manual 1: Resets Backup domain RTCEN RTC clock enable This bit is set and reset by software. 0: Disabled RTC clock 1: Enabled RTC clock 14:10 Reserved Must be kept at reset value RTCSRC[1:0] RTC clock entry selection Set and reset by software to control the RTC clock source.
Page 109 GD32L23x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDGT FWDGTR PORRST LPRSTF SWRSTF EPRSTF Reserved RSTFC V12RSTF Reserved RSTF IRC32K IRC32K Reserved Bits Fields Descriptions LPRSTF Low-power reset flag Set by hardware when Deep-sleep /standby reset generated. Reset by writing 1 to the RSTFC bit.
Page 110: Ahb Reset Register (Rcu_Ahbrst)
GD32L23x User Manual 1: External PIN reset generated Reserved Must be kept at reset value RSTFC Reset flag clear This bit is set by software to clear all reset flags. 0: Not clear reset flags 1: Clear reset flags V12RSTF 1.2V domain Power reset flag Set by hardware when a 1.2V domain Power reset generated.
Page 111: Configuration Register 1 (Rcu_Cfg1)
GD32L23x User Manual Reserved Must be kept at reset value PDRST GPIO port D reset This bit is set and reset by software. 0: No reset GPIO port D 1: Reset GPIO port D PCRST GPIO port C reset This bit is set and reset by software. 0: No reset GPIO port C 1: Reset GPIO port C PBRST...
Page 112: Configuration Register 2 (Rcu_Cfg2)
GD32L23x User Manual The source clock is divided by (PREDV + 1). 0000: input to PLL not divided 0001: input to PLL divided by 2 0010: input to PLL divided by 3 0011: input to PLL divided by 4 0100: input to PLL divided by 5 0101: input to PLL divided by 6 0110: input to PLL divided by 7 0111: input to PLL divided by 8...
Page 113 GD32L23x User Manual 17:16 USART1SEL[1:0] CK_USART1 clock source selection This bit is set and reset by software. 00: CK_USART1 select CK_APB1 01: CK_USART1 select CK_SYS 10: CK_USART1 select CK_LXTAL 11: CK_USART1 select CK_IRC16MDIV 15:14 Reserved Must be kept at reset value USBDSEL CK_USBD clock source selection This bit is set and reset by software.
Page 114: Ahb2 Enable Register (Rcu_Ahb2En)
GD32L23x User Manual 10/11: CK_I2C0 select CK_IRC16MDIV USART0SEL[1:0] CK_USART0 clock source selection This bit is set and reset by software. 00: CK_USART0 select CK_APB2 01: CK_USART0 select CK_SYS 10: CK_USART0 select CK_LXTAL 11: CK_USART0 select CK_IRC16MDIV 4.3.14. AHB2 enable register (RCU_AHB2EN) Address offset: 0x34 Reset value: 0x0000 0000.
Page 115: Voltage Key Register (Rcu_Vkey)
GD32L23x User Manual Reserved TRNGRST Reserved CAURST Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value TRNGST TRNG reset This bit is set and reset by software. 0: No reset TRNG module 1: Reset TRNG module Reserved Must be kept at reset value CAURST CAU reset...
Page 116: Low Power Bandgap Mode Register (Rcu_Lpb)
GD32L23x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved LPLDOVD Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value LPLDOVOS Deep-sleep 1 mode and Deep-sleep 2 mode voltage select These bits is set and reset by software 1: LP_LDO output voltage 0.8V 0: LP_LDO output voltage 0.9V 4.3.18.
Page 117: Clock Trim Controller (Ctc)
GD32L23x User Manual Clock trim controller (CTC) 5.1. Overview The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. If using IRC48M clock to USBD, the IRC48M must be 48 MHz with 500ppm. The internal oscillator without such a high degree of accuracy needs to be trimmed.
Page 118: Ref Sync Pulse Generator
GD32L23x User Manual Figure 5-1. CTC overview PCLK1 APB1 BUS Register REFSEL REFPSC SWREFPUL USBD_SOF Prescale CTC_SYNC (/1,/2,/4, ,/128 LXTAL 1'b0 REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM 5.3.1. REF sync pulse generator Firstly, the reference signal source can select GPIO, LXTAL clock output, or USBSOF by setting REFSEL bits in CTC_CTL1 register.
Page 119: Frequency Evaluation And Automatically Trim Process
GD32L23x User Manual and then up- counting to 128 x CKLIM (defined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 120: Software Program Guide
GD32L23x User Manual If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 121 GD32L23x User Manual The typical step size is 0.12%. Where the �� is the frequency of correct clock (IRC48M), �� the �� is the frequency of reference sync pulse. ��...
Page 122: Register Definition
GD32L23x User Manual 5.4. Register definition CTC base address: 0x4000 C800 5.4.1. Control register 0 (CTC_CTL0) Address offset: 0x00 Reset value: 0x0000 4000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[6:0] CNTEN Reserved EREFIE ERRIE CKOKIE TRIM...
Page 123: Control Register 1 (Ctc_Ctl1)
GD32L23x User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable CKWARNIE Clock trim warning (CKWARNIF) interrupt enable...
Page 124: Status Register (Ctc_Stat)
GD32L23x User Manual 01: LXTAL clock selected 10: USBD_SOF 11: Reserved, equals 0 selected. Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8...
Page 125 GD32L23x User Manual REFDIR CTC trim counter direction when reference sync pulse When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value. TRIMERR Trim value error bit This bit is set by hardware when the TRIMVALUE in CTC_CTL0 register overflow...
Page 126: Interrupt Clear Register (Ctc_Intc)
GD32L23x User Manual 0 : No Error occur 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 127 GD32L23x User Manual REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register. Write 0 is no effect. CKOKIC CKOKIF interrupt clear bit This bit is written by software and read as 0.
Page 128: Interrupt/Event Controller (Exti)
GD32L23x User Manual Interrupt/event controller (EXTI) 6.1. Overview ® Cortex -M23 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. You can read the ®...
Page 129: Table 6-2. Interrupt Vector Table
GD32L23x User Manual 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt HardFault 0x0000_000C All class of fault 0x0000_0010 - 4-10 Reserved 0x0000_002B System service call via SWI SVCall Programmable 0x0000_002C instruction 0x0000_0030 – 12-13 Reserved 0x0000_0034 Pendable request for system PendSV Programmable 0x0000_0038...
Page 130 GD32L23x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 23 TIMER8 global interrupt 0x0000_009C IRQ 24 TIMER11 global interrupt 0x0000_00A0 IRQ 25 TIMER5 global interrupt 0x0000_00A4 IRQ 26 TIMER6 global interrupt 0x0000_00A8 IRQ 27 USART0 global interrupt 0x0000_00AC IRQ 28 USART1 global interrupt...
Page 131: External Interrupt And Event (Exti) Block Diagram
GD32L23x User Manual 6.4. External interrupt and event (EXTI) block diagram Figure 6-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~29 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 6.5. External interrupt and Event function overview The EXTI contains up to 30 independent edge detectors and generates interrupts request or event to the processer.
Page 132: Table 6-3. Exti Source
GD32L23x User Manual Table 6-3. EXTI source EXTI Line Source Number PA0 / PB0 / PC0 / PD0 / PF0 PA1 / PB1 / PC1 / PD1 / PF1 PA2 / PB2 / PC2 / PD2 PA3 / PB3 / PC3 / PD3 PA4 / PB4 / PC4 / PD4 PA5 / PB5 / PC5 / PD5 PA6 / PB6 / PC6 / PD6...
Page 133: Register Definition
GD32L23x User Manual 6.6. Register definition EXTI base address: 0x4001 0400 6.6.1. Interrupt enable register (EXTI_INTEN) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved INTEN29 INTEN28 INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8...
Page 134: Rising Edge Trigger Enable Register (Exti_Rten)
GD32L23x User Manual 1: Event from Linex is enabled 6.6.3. Rising edge trigger enable register (EXTI_RTEN) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved RTEN29 RTEN28 RTEN27 RTEN26 RTEN25 RTEN24 RTEN23 RTEN22 RTEN21 RTEN20...
Page 135: Software Interrupt Event Register (Exti_Swiev)
GD32L23x User Manual 6.6.5. Software interrupt event register (EXTI_SWIEV) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved SWIEV29 SWIEV28 SWIEV27 SWIEV26 SWIEV25 SWIEV24 SWIEV23 SWIEV22 SWIEV21 SWIEV21 SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7...
Page 136: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32L23x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 7.1. Overview There are up to 59 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0~PD6，PD8~PD9，PF0~ PF1 for the device to implement logic input/output functions.
Page 137: Figure 7-1. Basic Structure Of A Standard I/O Port Bit
GD32L23x User Manual as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up/pull-down registers (GPIOx_PUD). Table 7-1. GPIO configuration table PAD TYPE CTLy PUDy Floating GPIO pull-up INPUT pull-down Floating push-pull pull-up GPIO pull-down OUTPUT Floating open-drain pull-up pull-down Floating...
Page 138: Gpio Pin Configuration
GD32L23x User Manual Figure 7-1. Basic structure of a standard I/O port bit Write Bit Operate Registers Output Output driver Control Read/Write Register Output Control Alternate Function Output protection Analog ( Input / Output ) I/O pin Alternate Function Input Input Read Status...
Page 139: Alternate Functions (Af)
GD32L23x User Manual 7.3.3. Alternate functions (AF) When the port is configured as AFIO (set CTLy bits to “0b10”, which is in GPIOx_CTL registers), the port is used as peripheral alternate functions. Each port has sixteen alternate functions can be configured by GPIO alternate functions selected registers (GPIOx_AFSELy (y = 0,1)).
Page 140: Analog Configuration
GD32L23x User Manual  Open Drain Mode: The pad output low level when a “0” in the output control register; while the pad leaves Hi-Z when a “1” in the output control register. Push-Pull Mode: The pad output low level when a “0” in the output control register; while ...
Page 141: Alternate Function (Af) Configuration
GD32L23x User Manual 7.3.8. Alternate function (AF) configuration To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software. When be configured as alternate function:  The output buffer is enabled in open-drain or push-pull configuration. ...
Page 142: Gpio Single Cycle Toggle Function
GD32L23x User Manual 7.3.10. GPIO single cycle toggle function GPIO could toggle the I/O output level in single AHB cycle by writing 1 to the corresponding bit of GPIOx_TG register. The output signal frequency could up to the half of the AHB clock.
Page 143: Register Definition
GD32L23x User Manual 7.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOD base address: 0x4800 0C00 GPIOF base address: 0x4800 1400 7.4.1. Port control register (GPIOx_CTL, x=A..D,F) Address offset: 0x00 Reset value: 0x2800 0000 for port A;...
Page 144: Port Output Mode Register (Gpiox_Omode, X=A
GD32L23x User Manual These bits are set and cleared by software. Refer to CTL0[1:0] description 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 17:16 CTL8[1:0] Pin 8 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 15:14 CTL7[1:0]...
Page 145 GD32L23x User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value OM15 Pin 15 output mode bit These bits are set and cleared by software.
Page 146: Port Output Speed Register (Gpiox_Ospd, X=A
GD32L23x User Manual Refer to OM0 description Pin 6 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 4 output mode bit These bits are set and cleared by software.
Page 147 GD32L23x User Manual Refer to OSPD0[1:0] description 29:28 OSPD14[1:0] Pin 14 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 25:24 OSPD12[1:0]...
Page 148: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32L23x User Manual OSPD2[1:0] Pin 2 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD0[1:0] Pin 0 output max speed bits These bits are set and cleared by software.
Page 149 GD32L23x User Manual Refer to PUD0[1:0] description 21:20 PUD10[1:0] Pin 10 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 19:18 PUD9[1:0] Pin 9 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 17:16 PUD8[1:0]...
Page 150: Port Input Status Register (Gpiox_Istat, X=A
GD32L23x User Manual 7.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) Address offset: 0x10 Reset value: 0x0000 XXXX This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT9 ISTAT8 ISTAT7 ISTAT6 ISTAT5 ISTAT4 ISTAT3 ISTAT2 ISTAT1...
Page 151: Port Bit Operate Register (Gpiox_Bop, X=A
GD32L23x User Manual 7.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F) Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6...
Page 152: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
GD32L23x User Manual LOCK key writing sequence: Write 1→Write 0→Write 1→ Read 0→ Read 1 Note: The value of LKy(y=0..15) must be held during the LOCK Key writing sequence. 15:0 Port lock bit y(y=0..15) These bits are set and cleared by software. 0: Port configuration not locked 1: Port configuration locked 7.4.9.
Page 153: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
GD32L23x User Manual Refer to SEL0[3:0] description SEL1[3:0] Pin 1 alternate function selected These bits are set and cleared by software. Refer to SEL0[3:0] description SEL0[3:0] Pin 0 alternate function selected These bits are set and cleared by software. 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected 0011: AF3 selected...
Page 154: Bit Clear Register (Gpiox_Bc, X=A
GD32L23x User Manual Refer to SEL8[3:0] description 19:16 SEL12[3:0] Pin 12 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description 15:12 SEL11[3:0] Pin 1 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description 11:8 SEL10[3:0]...
Page 155: Port Bit Toggle Register (Gpiox_Tg, X=A
GD32L23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 Port clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit 7.4.12.
Page 156: Crc Calculation Unit (Crc)
GD32L23x User Manual CRC calculation unit (CRC) 8.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial 8.2.
Page 157: Function Overview
GD32L23x User Manual 8.3. Function overview  CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 158: Register Definition
GD32L23x User Manual 8.4. Register definition CRC base address: 0x4002 3000 8.4.1. Data register (CRC_DATA) Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 159: Control Register (Crc_Ctl)
GD32L23x User Manual by any other peripheral. The CRC_CTL register will generate no effect to the byte. 8.4.3. Control register (CRC_CTL) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O REV_I[1:0] PS[1:0] Reserved...
Page 160: Polynomial Register (Crc_Poly)
GD32L23x User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value. 8.4.5. Polynomial register (CRC_POLY) Address offset: 0x14 Reset value: 0x04C1 1DB7 This register has to be accessed by word (32-bit).
Page 161: True Random Number Generator (Trng)
GD32L23x User Manual True random number generator (TRNG) 9.1. Overview The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. 9.2. Characteristics  About 40 periods of TRNG_CLK are needed between two consecutive random numbers. ...
Page 162: Operation Flow
GD32L23x User Manual generated random number depends on TRNG_CLK exclusively, no matter what HCLK frequency was set or not. The 32-bit value of LFSR will transfer into TRNG_DATA register after a sufficient number of seeds have been sent to the LFSR. At the same time, the analog seed and TRNG_CLK clock are monitored.
Page 163: Register Definition
GD32L23x User Manual 9.4. Register definition TRNG base address: 0x5006 0800 9.4.1. Control register (TRNG_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TRNGEN Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value.
Page 164: Data Register (Trng_Data)
GD32L23x User Manual 31:7 Reserved Must be kept at reset value. SEIF Seed error interrupt flag This bit will be set if more than 64 consecutive same bit or more than 32 consecutive 01(or 10) changing are detected. 0: No fault detected 1: Seed error has been detected.
Page 165 GD32L23x User Manual Bits Fields Descriptions 31:0 TRNDATA[31:0] 32-bit random data...
Page 166: Direct Memory Access Controller (Dma)
GD32L23x User Manual Direct memory access controller (DMA) 10.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 167: Block Diagram
GD32L23x User Manual 10.3. Block diagram Figure 10-1. Block diagram of DMA AHB slave interface Configuration … dma_req Channel 6 dma_ack master interface Channel 2 dma_req Master dma_ack Port Channel 1 dma_req dma_ack Channel 0 dma_req dma_ack Memory control state & counter management Peripheral control Arbiter...
Page 168: Table 10-1. Dma Transfer Operation
GD32L23x User Manual Table 10-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 169: Peripheral Handshake
GD32L23x User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 170: Address Generation
GD32L23x User Manual  For channels with equal software priority level, priority is given to the channel with lower channel number. 10.4.4. Address generation Two kinds of address generation algorithm are implemented independently for memory and peripheral, including the fixed mode and the increased mode. The PNAGA and MNAGA bit in the DMA_CHxCTL register are used to configure the next address generation algorithm of peripheral and memory.
Page 171: Interrupt
GD32L23x User Manual 6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register. 7. Configure the DMA_CHxPADDR register for setting the peripheral base address. 8. Configure the DMA_CHxMADDR register for setting the memory base address. 9.
Page 172: Register Definition
GD32L23x User Manual 10.5. Register definition DMA base address: 0x4002 0000 10.5.1. Interrupt flag register (DMA_INTF) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ERRIF6 HTFIF6 FTFIF6 GIF6 ERRIF5 HTFIF5 FTFIF5 GIF5 ERRIF4 HTFIF4...
Page 173: Channel X Control Register (Dma_Chxctl)
GD32L23x User Manual Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0 Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 27/23/19/15 ERRIFCx Clear bit for error flag of channel x (x=0…6)
Page 174 GD32L23x User Manual 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’. 11:10 MWIDTH[1:0] Transfer data size of memory...
Page 175: Channel X Counter Register (Dma_Chxcnt)
GD32L23x User Manual 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt Software set and cleared 0: Disable the channel error interrupt 1: Enable the channel error interrupt HTFIE...
Page 176: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32L23x User Manual transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode. 10.5.5. Channel x peripheral base address register (DMA_CHxPADDR) x = 0...6, where x is a channel number Address offset: 0x10 + 0x14 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 177 GD32L23x User Manual When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these bits are ignored. Access is automatically aligned to a word address.
Page 178: Dma Request Multiplexer (Dmamux)
GD32L23x User Manual DMA request multiplexer (DMAMUX) 11.1. Overview DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer is used for routing a DMA request line between the peripherals / generated DMA request (from the DMAMUX request generator) and the DMA controller. Each DMAMUX request multiplexer channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.
Page 179: Block Diagram
GD32L23x User Manual 11.3. Block diagram Figure 11-1. Block diagram of DMAMUX Request multiplexer Slave Port Channel 6 Channel 2 … … Channel 1 Peri_reqx To DMA controller: … Channel 0 Reqx_out … … Sync Counter underrun: Reqx_in … Evtx_out Configuration Register Input selector...
Page 180: Function Overview
GD32L23x User Manual 11.5. Function overview As shown in Figure 11-1. Block diagram of DMAMUX, DMAMUX includes two sub-blocks:  DMAMUX request multiplexer. DMAMUX request multiplexer inputs (Reqx_in) source from: – Peripherals (Peri_reqx). – DMAMUX request generator outputs (Gen_reqx). DMAMUX request multiplexer outputs (Reqx_out) is connected to channels of DMA controller.
Page 181: Figure 11-2. Synchronization Mode
GD32L23x User Manual Note: The NBR[4:0] bits value shall only be written by software when both synchronization enable bit SYNCEN and event generation enable EVGEN bit of the corresponding request multiplexer channel x are disabled. When synchronization mode is enabled A channel x in synchronization mode, when a rising/falling edge on the selected synchronization input is detected, the pending selected input DMA request line is routed to the multiplexer channel x output.
Page 182: Figure 11-3. Event Generation
GD32L23x User Manual be routed to the DMAMUX multiplexer channel output until a synchronization input event occurs again. Channel event generation Each DMA request line multiplexer channel has an event output called Evtx_out, which is the DMA request multiplexer counter underrun event. Signals Evt0_out ~ Evt3_out can be used for DMA request chaining.
Page 183: Dmamux Request Generator
GD32L23x User Manual 11.5.2. DMAMUX request generator The DMAMUX request generator produces DMA requests upon trigger input event. Its component unit is the request generator channels. DMA request trigger inputs are connected in parallel to all request generator channels. And there is a built-in DMAMUX request generator counter for each request generator channel.
Page 184: Interrupt
GD32L23x User Manual Set and configure the DMA channel x completely, except enabling the channel x. Set and configure the related DMAMUX channel y completely. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the DMA channel 11.5.4.
Page 185: Table 11-2. Request Multiplexer Input Mapping
GD32L23x User Manual Table 11-2. Request multiplexer input mapping Request multiplexer channel input identification Source MUXID[5:0] Gen_req0 Gen_req1 Gen_req2 Gen_req3 Reserved Reserved Reserved I2C0_RX I2C0_TX I2C1_RX I2C1_TX I2C2_RX I2C2_TX SPI0_RX SPI0_TX SPI1_RX SPI1_TX Reserved Reserved Reserved Reserved Reserved TIMER1_CH0 TIMER1_CH1 TIMER1_CH2 TIMER1_CH3 Reserved...
Page 186: Table 11-3. Trigger Input Mapping
GD32L23x User Manual Request multiplexer channel input identification Source MUXID[5:0] Reserved Reserved Reserved TIMER5_UP TIMER6_UP CAU_IN CAU_OUT Reserved Reserved Reserved Reserved USART0_RX USART0_TX USART1_RX USART1_TX UART3_RX UART3_TX UART4_RX UART4_TX LPUART_RX LPUART_TX Reserved Reserved Reserved Reserved Trigger input mapping The DMA request trigger input for the DMAMUX request generator channel x is selected through the TID[4:0] bits in DMAMUX_RG_CHxCFG register, the sources can refer to Table 11-3.
Page 187: Table 11-4. Synchronization Input Mapping
GD32L23x User Manual Trigger input identification Source TID[4:0] EXTI_5 EXTI_6 EXTI_7 EXTI_8 EXTI_9 EXTI_10 EXTI_11 EXTI_12 EXTI_13 EXTI_14 EXTI_15 Evt0_out Evt1_out Evt2_out Evt3_out Reserved Reserved TIMER11_CH0_O Reserved Synchronization input mapping The synchronization input is selected by SYNCID[4:0] bits in the DMAMUX_RM_CHxCFG register, the sources can refer to Table 11-4.
Page 188 GD32L23x User Manual Synchronization input Source identification SYNCID[4:0] EXTI_13 EXTI_14 EXTI_15 Evt0_out Evt1_out Evt2_out Evt3_out Reserved Reserved TIMER11_CH0_O Reserved...
Page 189: Register Definition
GD32L23x User Manual 11.6. Register definition DMAMUX base address: 0x4002 0800 11.6.1. Request multiplexer channel configuration register (DMAMUX_RM_CHxCFG) x = 0...6, where x is a channel number Address offset: 0x00 + 0x04 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SYNCID[4:0] NBR[4:0]...
Page 190: Request Multiplexer Channel Interrupt Flag Register (Dmamux_Rm_Intf)
GD32L23x User Manual 1: Enable event generation SOIE Synchronization overrun interrupt enable 0: Disable interrupt 1: Enable interrupt Reserved Must be kept at reset value. MUXID[5:0] Multiplexer input identification Selects the input DMA request in multiplexer input sources. 11.6.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) Address offset: 0x80 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 191: Request Multiplexer Channel Interrupt Flag Clear Register (Dmamux_Rm_Intc)
GD32L23x User Manual It is cleared by writing 1 to the corresponding SOIFC0 bit in DMAMUX_RM_INTC register. 11.6.3. Request multiplexer channel interrupt flag clear register (DMAMUX_RM_INTC) Address offset: 0x084 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved SOIFC6...
Page 192: Request Generator Channel Interrupt Flag Register (Dmamux_Rg_Intf)
GD32L23x User Manual Address offset: 0x100 + 0x04 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved NBRG[4:0] RGTP[1:0] RGEN Reserved TOIE Reserved TID[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:19 NBRG[4:0] Number of DMA requests to be generated...
Page 193: Rquest Generator Channel Interrupt Flag Clear Register (Dmamux_Rg_Intc)
GD32L23x User Manual Reserved TOIF3 TOIF2 TOIF1 TOIF0 Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. TOIF3 Trigger overrun event flag of request generator channel 3 Refers to TOIF0 descriptions. TOIF2 Trigger overrun event flag of request generator channel 2 Refers to TOIF0 descriptions.
Page 194 GD32L23x User Manual TOIFC1 Clear bit for trigger overrun event flag of request generator channel 1 Refers to TOIFC0 descriptions. TOIFC0 Clear bit for trigger overrun event flag of request generator channel 0 Writing 1 clears the corresponding trigger overrun flag TOIF0 in the DMAMUX_RG_INTF register.
Page 195: Debug (Dbg)
GD32L23x User Manual Debug (DBG) 12.1. Overview The GD32L23x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM Cortex-M23.
Page 196: Jtag Daisy Chained Structure
GD32L23x User Manual The pin assignment are: Table 12-1. Pin assignment Debug interface PA15 JTDI PA14 JTCK/SWCLK PA13 JTMS/SWDIO NJTRST JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions. (NJTRST tied to 1 by hardware).
Page 197: Debug Hold Function Overview
GD32L23x User Manual 12.3. Debug hold function overview 12.3.1. Debug support for power saving mode When the STB_HOLD bit in DBG control register 0 (DBG_CTL0) is set, and entering the standby mode, the clock of AHB bus and system clock are provided by CK_IRC16M, and the debugger can debug in standby mode.
Page 198: Register Definition
GD32L23x User Manual 12.4. Register definition DBG base address: 0x4001 5800 12.4.1. ID code register (DBG_ID) Address offset: 0x00 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits can only be read by software.
Page 199 GD32L23x User Manual This bit is set and reset by software. 0: no effect 1: hold the TIMER 8 counter for debugging when the core is halted. Reserved Must be kept at reset value. TIMER6_HOLD TIMER 6 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER 6 counter for debugging when the core is halted.
Page 200: Control Register 1 (Dbg_Ctl1)
GD32L23x User Manual This bit is set and reset by software. 0: no effect 1: hold the FWDGT counter clock for debugging when the core is halted. Reserved Must be kept at reset value. STB_HOLD Standby mode hold bit This bit is set and reset by software. 0: no effect 1: In the standby mode, the clock of AHB bus and system clock are provided by CK_IRC16M, a system reset generated when exiting standby mode.
Page 201 GD32L23x User Manual 0: no effect 1: hold the LPTIMER counter for debugging when the core is halted. 15:11 Reserved Must be kept at reset value. RTC_HOLD RTC hold bit This bit is set and reset by software. 0: no effect 1: hold the RTC counter for debugging when the core is halted.
Page 202: Analog To Digital Converter (Adc)
GD32L23x User Manual Analog to digital converter (ADC) 13.1. Overview The 12-bit ADC is an analog-to-digital converter using the successive approximation method. The ADC includes 16 external channels and 4 internal channels that can convert analog signals. The analog watchdog allows the application to detect whether the input voltage exceeds the user-defined threshold.
Page 203: Pins And Internal Signals
GD32L23x User Manual 16-bit data register Oversampling ratio adjustable from 2x to 256x Programmable data shift up to 8-bits ≤ V ≤ V  ADC input range: V 13.3. Pins and internal signals Figure 13-1. ADC module block diagram shows the ADC block diagram. Table 13-1.
Page 204: Function Overview
GD32L23x User Manual 13.4. Function overview Figure 13-1. ADC module block diagram Trig select Trig select DMA request Regular Inserted channels channels Interrupt EOIC Interrupt Channel Mangement generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Inserted data registers （16 bits x 4） ADC_IN15 Over SAR ADC...
Page 205: Dual Clock Domain Architecture
GD32L23x User Manual Set CLB=1; Wait for CLB =0. 13.4.2. Dual clock domain architecture The ADC sub-module, with exception of the APB interface block, is feed by an ADC clock, which can be asynchronous and independent from the APB clock. Application can reduce PLCK frequency for low power operation while still keeping optimum ADC performance.
Page 206: Figure 13-2. Single Conversion Mode
GD32L23x User Manual Figure 13-2. Single conversion mode Sample Regular trigger Convert After the conversion of a single regular channel, the conversion data will be stored in the ADC_RDATA register, the EOC will be set. An interrupt will be generated if the EOCIE bit is set.
Page 207: Figure 13-3. Continuous Conversion Mode
GD32L23x User Manual Figure 13-3. Continuous conversion mode Sample Regular trigger Convert Software procedure for continuous conversion on a regular channel: Set the CTN bit in the ADC_CTL1 register; Configure the RSQ0 with the analog channel number; Configure the ADC_SAMPTx register; Configure the ETERC and ETSRC bits in the ADC_CTL1 register if it is needed;...
Page 208: Figure 13-4. Scan Conversion Mode, Continuous Disable
GD32L23x User Manual Figure 13-4. Scan conversion mode, continuous disable · · · CH11 CH16 CH12 CH17 Regular trigger One circle of regular group, RL=8 · · · CH10 CH10 Sample Inserted trigger Convert EOIC One circle of inserted group, IL=4 Software procedure for scan conversion on a regular channel group: Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register;...
Page 209: Figure 13-6. Discontinuous Conversion Mode
GD32L23x User Manual ADC_RSQ0~ADC_RSQ2 registers. The value of n is defined by the DISNUM[2:0] bits in the ADC_CTL0 register. When the corresponding software trigger or external trigger is active, the ADC samples and converts the next n channels selected in the ADC_RSQ0~ADC_RSQ2 registers until all the channels in the regular sequence are done.
Page 210: Inserted Channel Management
GD32L23x User Manual Set the SWICST bit, or generate an external trigger for the inserted group; Repeat step4 if in need; Wait the EOC/EOIC flags to be set; Read the converted result in the ADC_IDATAx register; Clear the EOC/EOIC flag by writing 0 to them. 13.4.6.
Page 211: Analog Watchdog
GD32L23x User Manual 13.4.7. Analog watchdog The analog watchdog is enabled when the RWDEN and IWDEN bits in the ADC_CTL0 register are set for regular and inserted channel groups respectively. When the analog voltage converted by the ADC is below the low threshold or above the high threshold, the WDE bit in ADC_STAT register will be set.
Page 212: Programmable Sampling Time
GD32L23x User Manual Figure 13-10. Data alignment of 10-bit resolution Regular group data Inserted group data Sign Sign Sign Sign Sign Sign DAL=0 Regular group data Inserted group data Sign DAL=1 Figure 13-11. Data alignment of 8-bit resolution Figure 13-12. Data alignment of 6-bit resolution Regular group data Inserted group data Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign...
Page 213: External Trigger
GD32L23x User Manual the SPTn [2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers. Different sampling time can be specified for each channel. For 12-bit resolution, the total conversion time is “sampling time + 12.5” ADCCLK cycles. Example: ADCCLK = 16MHz and sampling time is 2.5 cycles, the total conversion time is “2.5+12.5” ADCCLK cycles, that means 0.9375us.
Page 214: Temperature Sensor And Internal Reference Voltage
GD32L23x User Manual request at the end of conversion of a regular channel. When this request is received, the DMA will transfer the converted data from the ADC_RDATA register to the destination which is specified by the user. 13.4.12. Temperature sensor and internal reference voltage V REFINT When the TSVEN bit in ADC_CTL1 register is set, the temperature sensor channel (ADC_IN16) is enabled.
Page 215: Battery Voltage Monitoring
GD32L23x User Manual 13.4.13. Battery voltage monitoring The V channel can be used to measure the backup battery voltage on the V pin. When the VBATEN bit in ADC_CTL1 register is set, V channel (ADC_IN18) is enabled and abridge divider by 3 integrated on the V pin is also enabled automatically with it.
Page 216: On-Chip Hardware Oversampling
GD32L23x User Manual 13.4.17. On-chip hardware oversampling The on-chip hardware oversampling circuit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted, and D (n) is the n-th output digital signal of the ADC: n=N−1...
Page 217: Table 13-6. Maximum Output Results For N And M Combimations (Grayed Values Indicates Truncation)
GD32L23x User Manual Figure 13-14. A numerical example with 5-bit shifting and rounding Raw 20-bit data Final result after 5-bit shift and rounding to nearest Table 13-6. Maximum output results for N and M combimations (grayed values indicates truncation) below gives the data format for the various N and M combinations, and the raw conversion data equals 0xFFF.
Page 218 GD32L23x User Manual  Analog watchdog The oversampling configuration can only be changed when ADCON is reset. Make sure configuring the oversampling before setting ADCON to 1.
Page 219: Register Definition
GD32L23x User Manual 13.5. Register definition ADC base address: 0x4001 2400 13.5.1. Status register (ADC_STAT) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved STRC STIC EOIC rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields...
Page 220: Control Register 0 (Adc_Ctl0)
GD32L23x User Manual 1: Analog watchdog event Set by hardware when the converted voltage crosses the values programmed in the ADC_WDLT and ADC_WDHT registers. Cleared by software writing 0 to it. 13.5.2. Control register 0 (ADC_CTL0) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 221: Control Register 1 (Adc_Ctl1)
GD32L23x User Manual Inserted channel group convert automatically 0: Inserted channel group convert automatically disable 1: Inserted channel group convert automatically enable WDSC When in scan mode, analog watchdog is effective on a single channel 0: Analog watchdog is effective on all channels 1: Analog watchdog is effective on a single channel Scan mode 0: Scan mode disable...
Page 222 GD32L23x User Manual Reserved VSLCDEN VBATEN INREFEN TSVEN SWRCST SWICST ETERC ETSRC [2:0] Reserved ETEIC ETSIC [2:0] Reserved Reserved RSTCLB ADCON Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. VSLCDEN Channel 19 (1/3 voltage of ) enable of ADC. SLCD channel disabled SLCD...
Page 223 GD32L23x User Manual ETEIC External trigger enable for inserted channel 0: External trigger for inserted channel disable 1: External trigger for inserted channel enable 14:12 ETSIC[2:0] External trigger select for inserted channel 000: reserved 001: reserved 010: TIMER1 TRGO 011: TIMER1 CH0 100: TIMER2 CH3 101: reserved 110: EXTI line15...
Page 224: Sample Time Register 0 (Adc_Sampt0)
GD32L23x User Manual 13.5.4. Sample time register 0 (ADC_SAMPT0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved SPT19[2:0] SPT18[2:0] SPT17[2:0] SPT16[2:0] SPT15[2:0] SPT15[0] SPT14[2:0] SPT13[2:0] SPT12[2:0] SPT11[2:0] SPT10[2:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value.
Page 225: Inserted Channel Data Offset Register X (Adc_Ioffx) (X=0
GD32L23x User Manual Reserved SPT9[2:0] SPT8[2:0] SPT7[2:0] SPT6[2:0] SPT5[2:1] SPT5[0] SPT4[2:0] SPT3[2:0] SPT2[2:0] SPT1[2:0] SPT0[2:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:27 SPT9[2:0] Refer to SPT0[2:0] description 26:24 SPT8[2:0] Refer to SPT0[2:0] description 23:21 SPT7[2:0] Refer to SPT0[2:0] description 20:18 SPT6[2:0]...
Page 226: Watchdog High Threshold Register (Adc_Wdht)
GD32L23x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 IOFF[11:0] Data offset for inserted channel x These bits will be subtracted from the raw converted data when converting inserted channels. The conversion result can be read from the ADC_IDATAx registers. 13.5.7.
Page 227: Regular Sequence Register 0 (Adc_Rsq0)
GD32L23x User Manual These bits define the low threshold for the analog watchdog. 13.5.9. Regular sequence register 0 (ADC_RSQ0) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RL [3:0] RSQ15[4:1] RSQ15[0] RSQ14[4:0] RSQ13[4:0] RSQ12[4:0]...
Page 228: Regular Sequence Register 2 (Adc_Rsq2)
GD32L23x User Manual 24:20 RSQ10[4:0] Refer to RSQ0[4:0] description 19:15 RSQ9[4:0] Refer to RSQ0[4:0] description 14:10 RSQ8[4:0] Refer to RSQ0[4:0] description RSQ7[4:0] Refer to RSQ0[4:0] description RSQ6[4:0] Refer to RSQ0[4:0] description 13.5.11. Regular sequence register 2 (ADC_RSQ2) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 229: Inserted Data Register X (Adc_Idatax) (X= 0
GD32L23x User Manual ISQ3[0] ISQ2[4:0] ISQ1[4:0] ISQ0[4:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:20 IL[1:0] Inserted channel group length. The total number of conversion in inserted group equals IL[1:0] + 1. 19:15 ISQ3[4:0] Refer to ISQ0[4:0] description. 14:10 ISQ2[4:0] Refer to ISQ0[4:0] description.
Page 230: Oversampling Control Register (Adc_Ovsampctl)
GD32L23x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RDATA [15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RDATA[15:0] Regular channel data These bits contain the conversion result from regular channel, which is read only. 13.5.15.
Page 231: Charge Control Register (Adc_Cctl)
GD32L23x User Manual 0100: Shift 4 bits 0101: Shift 5 bits 0110: Shift 6 bits 0111: Shift 7 bits 1000: Shift 8 bits Other: reserved Note: Software is allowed to write this bit only when ADCON =0 (which ensures that no conversion is ongoing).
Page 232 GD32L23x User Manual 31:17 Reserved Must be kept at reset value. CHARGE ADC charge status 0: not charging 1: charging Set and reset by hardware. 15:12 Reserved Must be kept at reset value. 11:0 CCNT [11:0] ADC charge pulse width counter This bit-field controls the value of the ADC charge pulse width.
Page 233: Digital-To-Analog Converter (Dac)
GD32L23x User Manual Digital-to-analog converter (DAC) 14.1. Introduction The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 234: Function Description
GD32L23x User Manual Figure 14-1. DAC block diagram DAC control register DTSEL[2:0] DBOFF TIMER1_TRGO TIMER2_TRGO TIMER6_TRGO TIMER5_TRG O EXTI9 SWTRIG Buff Control DAC_OUT logic OUT_DO OUT_DH 12-bit 12-bit Table 14-1. DAC pins Name Description Signal type Analog power supply Input, analog supply Ground for analog power supply Input, analog supply ground Positive reference voltage for the DAC,...
Page 235: Dac Data Configuration
GD32L23x User Manual The output buffer, which is turned on by default, can be turned off by setting the DBOFF bits in the DAC_CTL0 register. 14.3.3. DAC data configuration The 12-bit DAC holding data (OUT_DH) can be configured by writing any one of the OUT_R12DH, OUT_L12DH and OUT_R8DH registers.
Page 236: Dac Output Voltage
GD32L23x User Manual bit width (DWBW) bits in the DAC_CTL0 register. LFSR noise wave mode: there is a Linear Feedback Shift Register (LFSR) in the DAC control logic, it controls the LFSR noise signal which is added to the OUT_DH value, and then the result is stored into the OUT_DO register When the configured DAC noise wave bit width is less than 12, the noise signal equals to the LSB DWBW bits of the LFSR register, while the MSB bits are masked.
Page 237: Dma Request
GD32L23x User Manual The digital input is linearly converted to an analog output voltage, its range is 0 to V REF+ 14.3.8. DMA request When the external trigger is enabled, the DMA request is enabled by setting the DDMAEN bits of the DAC_CTL0 register. A DAC DMA request will be generated when an external hardware trigger (not a software trigger) occurs.
Page 238: Dac Registers
GD32L23x User Manual 14.4. DAC registers DAC base address: 0x4000 7400 14.4.1. Control register 0 (DAC_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DDUDR DDMA Reserved DDISC DWBW[3:0] DWM[1:0] DTSEL[2:0] DTEN DBOFF Bits...
Page 239: Software Trigger Register (Dac_Swt)
GD32L23x User Manual 0111: The bit width of the wave signal is 8 1000: The bit width of the wave signal is 9 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM[1:0] DAC_OUT noise wave mode...
Page 240: Dac_Out 12-Bit Right-Aligned Data Holding Register (Out_R12Dh)
GD32L23x User Manual Reserved SWTR Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. SWTR DAC_OUT software trigger, cleared by hardware. 0: Software trigger disabled 1: Software trigger enabled 14.4.3. DAC_OUT 12-bit right-aligned data holding register (OUT_R12DH) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 241: Dac_Out 8-Bit Right-Aligned Data Holding Register (Out_R8Dh)
GD32L23x User Manual 31:16 Reserved Must be kept at reset value. 15:4 OUT_DH[11:0] DAC_OUT 12-bit left-aligned data. These bits specify the data that is to be converted by DAC_OUT. Reserved Must be kept at reset value. 14.4.5. DAC_OUT 8-bit right-aligned data holding register (OUT_R8DH) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 242: Dac Status Register 0 (Dac_Stat0)
GD32L23x User Manual 14.4.7. DAC Status register 0 (DAC_STAT0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved DDUDR Reserved rc_w1 Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. DDUDR DAC_OUT DMA underrun flag, set by hardware, cleared by software write 1.
Page 243: Watchdog Timer (Wdgt)
GD32L23x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 244: Figure 15-1. Free Watchdog Block Diagram
GD32L23x User Manual Figure 15-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then counter starts counting down. When the counter reaches the value (0x000), there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at any time.
Page 245: Table 15-1. Min/Max Fwdgt Timeout Period At 32Khz (Irc32K)
GD32L23x User Manual Table 15-1. Min/max FWDGT timeout period at 32KHz (IRC32K) Min timeout (ms) RL[11:0]= Max timeout (ms) RL[11:0]= Prescaler divider PSC[2:0] bits 0x000 0xFFF 0.03125 511.90625 0.03125 1023.78125 1/16 0.03125 2047.53125 1/32 0.03125 4095.03125 1/64 0.03125 8190.03125 1/128 0.03125 16380.03125 1/256...
Page 246: Register Definition
GD32L23x User Manual 15.1.4. Register definition FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMD[15:0] Write only.
Page 247 GD32L23x User Manual before writing these bits. During a write operation to this register, the PUD bit in the FWDGT_STAT register is set and the value read from this register is invalid. 000: 1/4 001: 1/8 010: 1/16 011: 1/32 100: 1/64 101: 1/128 110: 1/256...
Page 248 GD32L23x User Manual Status register (FWDGT_STAT) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value Watchdog counter window value update When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 249 GD32L23x User Manual operation is performed while the counter is greater than the value stored in this register. The WUD bit in the FWDGT_STAT register must be reset in order to be able to change the reload value. These bits are write protected. Write 0x5555 in the FWDGT_CTL register before writing these bits.
Page 250: Window Watchdog Timer (Wwdgt)
GD32L23x User Manual 15.2. Window watchdog timer (WWDGT) 15.2.1. Overview The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 251: Figure 15-2. Window Watchdog Timer Block Diagram
GD32L23x User Manual Figure 15-2. Window watchdog timer block diagram The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F(it implies that the CNT[6] bit should be set).
Page 252: Figure 15-3. Window Watchdog Timing Diagram
GD32L23x User Manual Figure 15-3. Window watchdog timing diagram CNT[6:0] Start Start 0x7F Write CNT 0x3F CNT[6]=0 cause a reset Write WWDG_CTL when CNT>WIN cause a reset Calculate the WWDGT timeout by using the formula below. ×4096 ×2 × ( CNT [ 5:0 ] +1 ) (ms) (15-1) WWDGT PCLK1...
Page 253 GD32L23x User Manual If the WWDGT_HOLD bit in DBG module is cleared, the WWDGT continues to work even the ® Cortex -M23 core halted (Debug mode). While the WWDGT_HOLD bit is set, the WWDGT stops in Debug mode.
Page 254: Register Definition
GD32L23x User Manual 15.2.4. Register definition WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. WDGTEN Start the Window watchdog timer.
Page 255 GD32L23x User Manual counter. 0000: (PCLK1 / 4096) / 1 0001: (PCLK1 / 4096) / 2 0010: (PCLK1 / 4096) / 4 0011: (PCLK1 / 4096) / 8 0100: (PCLK1 / 4096) / 16 0101: (PCLK1 / 4096) / 32 0110: (PCLK1 / 4096) / 64 0111: (PCLK1 / 4096) / 128 1000: (PCLK1 / 4096) / 256...
Page 256 GD32L23x User Manual EWIF Early wakeup interrupt flag. When the counter reaches 0x40 or refreshes before it reaches the window value, this bit is set by hardware even the interrupt is not enabled (EWIE in WWDGT_CFG is cleared). This bit is cleared by writing 0. There is no effect when writing 1.
Page 257: Real Time Clock (Rtc)
GD32L23x User Manual Real time clock (RTC) 16.1. Overview The RTC provides a time which includes hour/minute/second/sub-second and a calendar includes year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time. Working in power saving mode and smart wakeup is software configurable.
Page 258: Function Overview
GD32L23x User Manual 16.3. Function overview 16.3.1. Block diagram Figure 16-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre (Default 1 Hz) IRC32K 7-bit...
Page 259: Clock Source And Prescalers
GD32L23x User Manual reference clock input: RTC_REFIN(PB15) 16.3.2. Clock source and prescalers RTC unit has three independent clock sources: LXTAL, IRC32K and HXTAL with divided by 32(configured in RCU_CFG register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions.
Page 260: Configurable Periodic Auto-Wakeup Counter
GD32L23x User Manual If a field is masked, the field is considered as matched in logic. If all the fields have been masked, the Alarm Flag will assert 3 RTC clock later after ALRMxEN(x=0,1) is set. 16.3.5. Configurable periodic auto-wakeup counter In the RTC block, there is a 16-bit down counter designed to generate periodic wakeup flag.
Page 261: Calendar Reading
GD32L23x User Manual RTC_ALRM1TD, RTC_SHIFTCTL, RTC_HRFC, RTC_ALRM0SS, RTC_ALRM1SS Calendar initialization and configuration The prescaler and calendar value can be programmed by the following steps: Enter initialization mode (by setting INITM=1) and polling INITF bit until INITF=1. Program both the asynchronous and synchronous prescaler factors in RTC_PSC register. Write the initial calendar values into the shadow calendar registers (RTC_TIME and RTC_DATE), and use the CS bit in the RTC_CTL register to configure the time format (12 or 24 hours).
Page 262 GD32L23x User Manual frequency, the calendar reading flow should be obeyed: reading calendar time register and date register twice if the two values are equal, the value can be seen as the correct value if the two values are not equal, a third reading should performed the third value can be seen as the correct value RSYNF is asserted once every 2 RTC clock and at this time point, the shadow registers will be updated to current time and date.
Page 263: Resetting The Rtc
GD32L23x User Manual the same, the data is coherent and correct. 16.3.8. Resetting the RTC There are two reset sources used in RTC unit: system reset and backup domain reset. System reset will affect calendar shadow registers and some bits of the RTC_STAT. When system reset is valid, the bits or registers mentioned before are reset to the default value.
Page 264: Rtc Reference Clock Detection
GD32L23x User Manual 16.3.10. RTC reference clock detection RTC reference clock detection is another way to increase the precision of RTC second. To enable this function, you should have an external clock source (50Hz or 60 Hz) which is more precise than LXTAL clock source.
Page 265 GD32L23x User Manual So using CMSK can mask clock cycles from 0 to 511 and thus the RTC frequency can be reduced by up to 487.1PPM. To increase the RTC frequency the FREQI bit can be set. If FREQI bit is set, there will be 512 additional cycles to be added during period time which means every 211/210/29(32/16/8 seconds) RTC clock insert one cycle.
Page 266: Time-Stamp Function
GD32L23x User Manual the measure is within 0.477PPM (0.5 RTCCLK cycles over 32s)  When the calibration period is 16 seconds(by setting CWND16 bit) In this configuration, CMSK[0] is fixed to 0 by hardware. Using exactly 16s period to measure the accuracy of the calibration 1Hz output can guarantee the measure is within 0.954PPM (0.5 RTCCLK cycles over 16s) ...
Page 267 GD32L23x User Manual mode or level detection mode with configurable filtering setting. The purposes of the tamper detect configuration are the following: 1. The default configuration will erase the RTC backup registers 2. It can wakeup from DeepSleep and Standby modes, and generate an interrupt 3.
Page 268 GD32L23x User Manual Trigger output generation on tamper event The tamper event detection can be used as trigger input for the low-power timers To allow a new tamper detection on the same pin, the TPxF flag must be cleared by software When TPxMASK bit is cleared.
Page 269: Calibration Clock Output
GD32L23x User Manual 16.3.14. Calibration clock output Calibration clock can be output on the RTC_OUT if COEN bit is set to 1. When the COS bit is set to 0(this is default) and asynchronous prescaler is set to 0x7F(FACTOR_A), the frequency of RTC_CALIB is f /64.When the RTCCLK is 32.768KHz, rtcclk RTC_CALIB output is corresponding to 512Hz.It’s recommend to using rising edge of...
Page 270: Rtc Power Saving Mode Management
GD32L23x User Manual function OS[1:0] COEN TP0EN TSEN ALARMOUTTYP configuration (output (calibration (tamper (time E(RTC_ALARM and pin function selection output enabled) stamp output type enabled) Don’t care TIMESTAMP input floating Don’t care Standard GPIO It is possible to output RTC_OUT on PB2 pin thanks to OUT2EN bit in RTC_CTL[31]. This output is not available in VBAT only mode.
Page 271: Rtc Interrupts
GD32L23x User Manual 16.3.18. RTC interrupts All RTC interrupts are connected to the EXTI controller. Below steps should be followed if you want to use the RTC alarm/tamper/timestamp/auto wakeup interrupt: Configure enable corresponding interrupt line alarm/tamper/timestamp/auto wakeup event of EXTI and set the rising edge for triggering Configure and enable the RTC alarm/tamper/timestamp/auto wakeup interrupt Configure and enable the RTC alarm/tamper/timestamp/auto wakeup function Table 16-4 RTC interrupts control...
Page 272: Register Definition
GD32L23x User Manual 16.4. Register definition RTC base address: 0x4000 2800 16.4.1. Time register (RTC_TIME) Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state This register has to be accessed by word (32-bit) Reserved HRT[1:0]...
Page 273: Control Register (Rtc_Ctl)
GD32L23x User Manual This register has to be accessed by word (32-bit) Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0]...
Page 274 GD32L23x User Manual 1: RTC_OUT is output on PB2 30:25 Reserved Must be kept at reset value. ITSEN Internal timestamp event enable 0: Disable Internal timestamp event 1: Enable Internal timestamp event COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0]...
Page 275 GD32L23x User Manual 1: Enable auto-wakeup timer interrupt ALRM1IE RTC alarm-1 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt ALRM0IE RTC alarm-0 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt TSEN Time-stamp function enable 0: Disable time-stamp function 1: Enable time-stamp function WTEN Auto-wakeup timer function enable...
Page 276: Status Register (Rtc_Stat)
GD32L23x User Manual 0x1:RTC Clock divided by 8 0x2:RTC Clock divided by 4 0x3:RTC Clock divided by 2 0x4:0x5: ck_spre (default 1Hz) clock 0x6:0x7: ck_spre (default 1Hz) clock and 2 is added to wake-up counter. 16.4.4. Status register (RTC_STAT) Address offset: 0x0C System reset: Only INITM, INITF and RSYNF bits are set to 0.
Page 277 GD32L23x User Manual before. Cleared by software writing 0. Time-stamp flag Set by hardware when time-stamp event is detected. Cleared by software writing 0. Wakeup timer flag Set by hardware when wakeup timer decreased to 0. Cleared by software writing 0. This flag must be cleared at least 1.5 RTC Clock periods before WTF is set to 1 again.
Page 278: Prescaler Register (Rtc_Psc)
GD32L23x User Manual 0: No shift operation is pending 1: Shift function operation is pending WTWF Wakeup timer write enable flag 0: Wakeup timer update is not allowed 1: Wakeup timer update is allowed ALRM1WF Alarm 1 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM1EN bit has reset.
Page 279: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32L23x User Manual Backup domain reset value: 0x0000 FFFF This register is writing protected. This register has to be accessed by word (32-bit) Reserved WTRV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 WTRV[15:0] Auto-wakeup timer reloads value. Every (WTRV[15:0]+1) ck_wut period the WTF bit is set after WTEN=1.The ck_wut is selected by WTCS[2:0] bits.
Page 280: Alarm 1 Time And Date Register (Rtc_Alrm1Td)
GD32L23x User Manual MSKH Alarm hour mask bit 0: Not mask hour field 1: Mask hour field AM/PM flag 0: AM or 24-hour format 1: PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit 0: Not mask minutes field...
Page 281: Write Protection Key Register (Rtc_Wpk)
GD32L23x User Manual 1: DAYU[3:0] indicates the week day and DAYT[3:0] has no means. 29:28 DAYT[1:0] Day tens in BCD code 27:24 DAYU[3:0] Day units or week day in BCD code MSKH Alarm hour mask bit 0: Not mask hour field 1: Mask hour field AM/PM flag 0: AM or 24-hour format...
Page 282: Sub Second Register (Rtc_Ss)
GD32L23x User Manual 16.4.10. Sub second register (RTC_SS) Address offset: 0x28 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register has to be accessed by word (32-bit) Reserved SSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 283: Time Of Time Stamp Register (Rtc_Tts)
GD32L23x User Manual When only using SFS, the clock will delay because the synchronous prescaler is a down counter: Delay (seconds) = SFS / ( FACTOR_S + 1 ) When jointly using A1S and SFS, the clock will advance: Advance (seconds) = ( 1 - ( SFS / ( FACTOR_S + 1 ) ) ) Note: Writing to this register will cause RSYNF bit to be cleared.
Page 284: Date Of Time Stamp Register (Rtc_Dts)
GD32L23x User Manual 16.4.13. Date of time stamp register (RTC_DTS) Address offset: 0x34 Backup domain reset value: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1. Reset TSF bit will also clear this register. This register has to be accessed by word (32-bit) Reserved DOW[2:0]...
Page 285: High Resolution Frequency Compensation Register (Rtc_Hrfc)
GD32L23x User Manual 31:16 Reserved Must be kept at reset value. 15:0 SSC[15:0] Sub second value This value is the counter value of synchronous prescaler when TSF is set to 1. 16.4.15. High resolution frequency compensation register (RTC_HRFC) Address offset: 0x3C Backup domain reset: 0x0000 0000 System Reset: no effect This register is write protected.
Page 286: Tamper Register (Rtc_Tamp)
GD32L23x User Manual 16.4.16. Tamper register (RTC_TAMP) Address offset: 0x40 Backup domain reset: 0x0000 0000 System reset: no effect This register has to be accessed by word (32-bit) TP2NOER TP1NOER TP0NOER ALRMOU Reserved TP2IE TP1IE TP0IE Reserved TP2MASK TP1MASK TP0MASK Reserved Reserved TTYPE DISPU...
Page 287 GD32L23x User Manual Note: The Tamper 0 interrupt must not be enabled when TP0MASK is set. Reserved Must be kept at reset value. TP2NOERASE Tamper 2 no erase: 0:Tamper 2 event erases the backup registers 1:Tamper 2 event does not erase the backup registers TP1NOERASE Tamper 1 no erase: 0:Tamper 1 event erases the backup registers...
Page 288 GD32L23x User Manual 0x3: Sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) 0x4: Sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) 0x5: Sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) 0x6: Sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) 0x7: Sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) TPTS Make tamper function used for timestamp function 0:No effect...
Page 289: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32L23x User Manual 1:Enable tamper 0 detection function Note: It’s strongly recommended that reset the TPxEN before change the tamper configuration. 16.4.17. Alarm 0 sub second register (RTC_ALRM0SS) Address offset: 0x44 Backup domain reset: 0x0000 0000 System reset: no effect This register is write protected and can only be wrote when ALRM0EN=0 or INITM=1 This register has to be accessed by word (32-bit) Reserved...
Page 290: Alarm 1 Sub Second Register (Rtc_Alrm1Ss)
GD32L23x User Manual synchronous prescaler counter SSC. Bit number is controlled by MSKSSC bits. 16.4.18. Alarm 1 sub second register (RTC_ALRM1SS) Address offset: 0x48 Backup domain reset: 0x0000 0000 System reset: no effect This register is write protected and can only be wrote when ALRM1EN=0 or INITM=1 This register has to be accessed by word (32-bit) Reserved MSKSSC[3:0]...
Page 291: Backup Registers (Rtc_Bkpx) (X=0
GD32L23x User Manual 16.4.19. Backup registers (RTC_BKPx) (x=0..4) Address offset: 0x50~0x64 Backup domain reset: 0x0000 0000 System reset: no effect This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be wrote or read by software. The content remains valid even in power saving mode because they can powered-on by VBAT.
Page 292: Timer (Timerx)
GD32L23x User Manual Timer (TIMERx) Table 17-1. Timers (TIMERx) are devided into six sorts TIMER TIMER1/2 TIMER8/11 TIMER5/6 TYPE General-L0 General-L1 Basic Prescaler 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit UP,DOWN, Count mode UP ONLY UP ONLY Center-aligned × × ×...
Page 293: General Level0 Timer (Timerx, X=1, 2)
GD32L23x User Manual 17.1. General level0 timer (TIMERx, x=1, 2) 17.1.1. Overview The general level0 timer module (TIMER1, 2) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 294: Function Overview
GD32L23x User Manual Figure 17-1. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 TIMERx_CHxCV CK_TIMER Counter External Trigger Trigger processor Input logic PSC_CLK Trigger Selector&Counter Polarity selection TIMER_CK Quadrate Decoder DMA REQ/ACK...
Page 295: Figure 17-2. Normal Mode, Internal Clock Divided By 1
GD32L23x User Manual Figure 17-2. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC[2:0] = 3’b111 (external clock mode 0). External input pin is selected as timer clock source.
Page 296: Figure 17-3. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32L23x User Manual Figure 17-3. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB FC Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 297 GD32L23x User Manual Figure 17-4. Timing chart of up counting mode, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 298: Figure 17-5. Timing Chart Of Up Counting, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 17-5. Timing chart of up counting, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear...
Page 299 GD32L23x User Manual Figure 17-6. Timing chart of down counting mode, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG 5C 5B Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 300: Figure 17-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 17-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 301: Figure 17-8. Timing Chart Of Center-Aligned Counting Mode
GD32L23x User Manual When an update event occurs, all the registers (auto-reload register, prescaler register) are updated. Figure 17-8. Timing chart of center-aligned counting mode shows the example of the counter behavior when TIMERx_CAR=0x63, TIMERx_PSC=0x0 Figure 17-8. Timing chart of center-aligned counting mode TIMER_CK CNT_CLK (PSC_CLK)
Page 302: Figure 17-9. Input Capture Logic
GD32L23x User Manual register, at the same time the CHxIF bit is set and the channel interrupt is generated if it is enabled when CHxIE=1. Figure 17-9. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK CI0FE0 Rising/Falling...
Page 303: Figure 17-10. Output Compare Logic (X=0,1,2,3)
GD32L23x User Manual Enable the related interrupt to get the interrupt and DMA request. Step5: Capture enable (CHxEN in TIMERx_CHCTL2) Result: When the wanted input signal is captured, TIMERx_CHxCV will be set by counter’s value and CHxIF is asserted. If the CHxIF is 1, the CHxOF will also be asserted. The interrupt and DMA request will be asserted or not based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN.
Page 304: Figure 17-11. Output-Compare Under Three Modes
GD32L23x User Manual request will be asserted, if CxCDE=1. So, the process can be divided into several steps as below: Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration.  Set the shadow enable mode by CHxCOMSEN. ...
Page 305: Figure 17-12. Timing Chart Of Eapwm
GD32L23x User Manual Based on the counter mode, PWM can also be divided into EAPWM (Edge-aligned PWM) and CAPWM (Center-aligned PWM). The EAPWM’s period is determined by TIMERx_CAR and the duty cycle is determined by TIMERx_CHxCV.Figure 17-12. Timing chart of EAPWM shows the EAPWM output and interrupts waveform.
Page 306 GD32L23x User Manual Figure 17-13. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal As is shown in Figure 17-10.
Page 307: Table 17-2. Counting Direction Versus Encoder Signals
GD32L23x User Manual can be forced to 0 when the ETIFP signal derived from the external ETI pin is set to a high level. The OxCPRE signal will not return to its active level until the next update event occurs. Quadrature decoder The quadrature decoder function uses two quadrature inputs CI0 and CI1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact with each other to generate the...
Page 308: Figure 17-14. Example Of Counter Operation In Encoder Interface Mode
GD32L23x User Manual Figure 17-14. Example of counter operation in encoder interface mode Counter down Figure 17-15. Example of encoder interface mode with CI0FE0 polarity inverted Counter down Hall sensor function Hall sensor is generally used to control BLDC Motor; the general level0 timer can support this function.
Page 309: Figure 17-16. Restart Mode
GD32L23x User Manual Slave controller The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode which is selected by the SMC[2:0] bits in the TIMERx_SMCFG register. The input trigger of these modes can be selected by the TRGS[2:0] bits in the TIMERx_SMCFG register.
Page 310: Figure 17-17. Pause Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler the trigger input is rising edge only. high. Figure 17-17. Pause mode Exam3 Event mode TRGS[2:0] = ETP = 0, the polarity ETPSC = 1, ETI is 3’b111 The counter will start of ETI does not divided by 2.
Page 311: Figure 17-19. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X60
GD32L23x User Manual automatically cleared to 0 by a hardware update event, the counter will be reinitialized. In the single pulse mode, the active edge of trigger which sets the CEN bit to 1 will enable the counter. However, there exists several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value.
Page 312 GD32L23x User Manual Figure 17-20. TIMER1 Master/Slave mode timer example TIMER1 TRGS TIMER 2 ITI0 Master TRG O mode Pre scaler Counter control CI0F_ED Trigger Slave mode Pre scaler Counter selection control CI0FE0 CI1FE1 ETIFP Other interconnection examples:  TIMER2 as prescaler for TIMER1 We configure TIMER2 as a prescaler for TIMER1.
Page 313: Figure 17-21. Triggering Timer1 With Enable Of Timer2
GD32L23x User Manual prescaler compared to TIMER_CK (f /3). Do as follow: CNT_CLK TIMER_CK 1. Configure TIMER2 master mode to send its enable signal as trigger output(MMC=001 in the TIMER2_CTL1 register) 2. Configure TIMER1 to select the input trigger from TIMER2 (TRGS=000 in the TIMER1_SMCFG register).
Page 314: Figure 17-23. Pause Timer1 With Enable Of Timer2
GD32L23x User Manual  Enable TIMER1 count with TIMER2’s enable/O0CPRE signal In this example, we control the enable of TIMER1 with the enable output of TIMER2 .Refer to Figure 17-23. Pause TIMER1 with enable of TIMER2 TIMER1 counts on the divided internal clock only when TIMER2 is enable.
Page 315: Figure 17-24. Pause Timer1 With O0Cpreof Timer2
GD32L23x User Manual Figure 17-24. Pause TIMER1 with O0CPREof TIMER2 TIMER2 TIMER_CK CNT_REG O0CPRE TIMER1 TRGIF CNT_REG  Using an external trigger to start 2 timers synchronously We configure the start of TIMER1 is triggered by the enable of TIMER2, and TIMER2 is triggered by its CI0 input rises edge.
Page 316: Figure 17-25. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32L23x User Manual Figure 17-25. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input TIMER2 TIMER_CK TRGIF CNT_REG TIMER1 TRGIF CNT_CK CNT_REG Timer DMA mode DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event.
Page 317: Timerx Registers(X=1, 2)
GD32L23x User Manual 17.1.5. TIMERx registers(x=1, 2) TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits...
Page 318 GD32L23x User Manual can be set. 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when the counter is counting up and counting down, compare interrupt flag of channels can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00.
Page 319 GD32L23x User Manual Control register 1 (TIMERx_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input.
Page 320 GD32L23x User Manual is used as TRGO DMAS DMA request source selection 0: DMA request of channel x is sent when channel x capture/compare event occurs. 1: DMA request of channel x is sent when update event occurs. Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000...
Page 321 GD32L23x User Manual 10: ETI frequency will be divided by 4 11: ETI frequency will be divided by 8 11:8 ETFC[3:0] External trigger filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events.
Page 322 GD32L23x User Manual SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 323 GD32L23x User Manual 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: disabled...
Page 324 GD32L23x User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 325 GD32L23x User Manual mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs. 0: No Channel 1 interrupt occurred 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software.
Page 326 GD32L23x User Manual This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 327 GD32L23x User Manual Refer to CH0COMSEN description CH1MS[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is configured as output 01: Channel 1 is configured as input, IS1 is connected to CI1FE1 10: Channel 1 is configured as input, IS1 is connected to CI0FE1...
Page 328 GD32L23x User Manual When this bit is set, the shadow register of TIMERx_CH0CV register, which updates at each update event, will be enabled. 0: Channel 0 output compare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used without validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set).
Page 329 GD32L23x User Manual occurs after N input events. This bit-field specifies the frequency used to sample CI0 input signal and the length of the digital filter applied to CI0. 0000: Filter disabled, f , N=1 SAMP 0001: f , N=2 SAMP TIMER_CK 0010: f...
Page 330 GD32L23x User Manual Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN...
Page 331 GD32L23x User Manual 101: Force high. O2CPRE is forced high level. 110: PWM mode0. When counting up, O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV else inactive. When counting down, O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV else active. 111: PWM mode1.
Page 332 GD32L23x User Manual Input capture mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 CH3CAPFLT[3:0] Channel 3 input capture filter control Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode...
Page 333 GD32L23x User Manual Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH3NP Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved CH0P CH0EN Bits Fields Descriptions...
Page 334 GD32L23x User Manual When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, In conjunction with CH0P, this bit is used to define the polarity of CI0. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
Page 335 GD32L23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved...
Page 336 GD32L23x User Manual 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH0VAL[15:0]...
Page 337 GD32L23x User Manual 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 338 GD32L23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 339 GD32L23x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed.
Page 340: General Level1 Timer (Timerx, X=8, 11)
GD32L23x User Manual 17.2. General level1 timer (TIMERx, x=8, 11) 17.2.1. Overview The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 341: Block Diagram
GD32L23x User Manual 17.2.3. Block diagram Figure 18-50. General level1 timer block diagram provides details on the internal configuration of the general level1 timer. Figure 17-26. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1 ITI2...
Page 342: Figure 17-27. Normal Mode, Internal Clock Divided By 1
GD32L23x User Manual Figure 17-27. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 ( ). External input pin source external clock mode 0 The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 343: Figure 17-28. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32L23x User Manual Figure 17-28. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK FA FB FC CNT_REG Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 344: Figure 17-30. Up-Counter Timechart, Change Timerx_Car On The Go
GD32L23x User Manual Figure 17-29. Up-counter timechart, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 17-30.
Page 345: Figure 17-31. Input Capture Logic
GD32L23x User Manual Capture/compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ...
Page 346 GD32L23x User Manual CHxCAPFLT. Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 347: Figure 17-32. Output-Compare Under Three Modes
GD32L23x User Manual About the CHxVAL, you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN. Figure 17-32. Output-compare under three modes below show the three compare modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 17-32.
Page 348: Figure 17-33. Eapwm Timechart
GD32L23x User Manual If TIMERx_CHxCV is greater than TIMERx_CAR, the output will be always active under PWM mode0 (CHxCOMCTL==3’b110). And if TIMERx_CHxCV is equal to zero, the output will be always inactive under PWM mode0 (CHxCOMCTL==3’b110). Figure 17-33. EAPWM timechart CHxVAL PWM MODE0 Cx OUT...
Page 349: Table 17-4．Slave Controller Examples
GD32L23x User Manual Channel output reference signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function. These include, keeping the original level by setting the CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register.
Page 350: Figure 17-35. Restart Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler TRGS[2:0]=3’b000 Exam1 Restart mode For ITI0, no polarity selector ITI0 is the For the ITI0, no filter and The counter can be can be used. selection. prescaler can be used. clear and restart when a rising trigger input.
Page 351: Figure 17-37. Event Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 17-37. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event automatically.
Page 352: Figure 17-38. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32L23x User Manual Figure 17-38. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG …. O2CPRE Timers interconnection Refer to Timers interconnection Timer debug mode ® When the Cortex -M23 halted, and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1, the TIMERx counter stops.
Page 353: Timerx Registers(X=8, 11)
GD32L23x User Manual 17.2.5. TIMERx registers(x=8, 11) TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits...
Page 354 GD32L23x User Manual 1: When enabled, only counter overflow/underflow generates an update interrupt or DMA request. UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: update event enable. The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs: The UPG bit is set The counter generates an overflow or underflow event...
Page 355 GD32L23x User Manual to synchronize the counter. 000: Internal trigger input 0 (ITI0), only for TIMER8 001: Internal trigger input 1 (ITI1) 010: Internal trigger input 2 (ITI2), only for TIMER11 011: Reserved 100: CI0 edge flag (CI0F_ED) 101: channel 0 input Filtered output (CI0FE0) 110: channel 1 input Filtered output (CI1FE1) 111: External trigger input filter output(ETIFP) These bits must not be changed when slave mode is enabled.
Page 356 GD32L23x User Manual 1: enabled Reserved Must be kept at reset value. CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000...
Page 357 GD32L23x User Manual in pause mode both edges on trigger input generates a trigger event. 0: No trigger event occurred. 1: Trigger interrupt occurred. Reserved Must be kept at reset value. Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software.
Page 358 GD32L23x User Manual Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 359 GD32L23x User Manual TIMERx_CHCTL2 register is reset). 00: Channel 1 is configured as output 01: Channel 1 is configured as input, IS1 is connected to CI1FE1 10: Channel 1 is configured as input, IS1 is connected to CI0FE1 11: Channel 1 is configured as input, IS1 is connected to ITS. This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register.
Page 360 GD32L23x User Manual CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison.
Page 361 GD32L23x User Manual 0111: f /4, N=8 SAMP 1000: f /8, N=6 SAMP 1001: f /8, N=8 SAMP 1010: f /16, N=5 SAMP 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f...
Page 362 GD32L23x User Manual CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, In conjunction with CH0P, this bit is used to define the polarity of CI0. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
Page 363 GD32L23x User Manual CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 364 GD32L23x User Manual This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 365 GD32L23x User Manual the shadow register updates every update event. Channel input remap register(TIMERx_IRMP, x=8) Address offset: 0x50 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CI0_RMP[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CI0_RMP[1:0] Channel 0 input remap 00: Channel 0 input is connected to GPIO(TIMER8_CH0)
Page 366 GD32L23x User Manual Configuration register (TIMERx_CFG ) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software.
Page 367: Basic Timer (Timerx, X=5, 6)
GD32L23x User Manual 17.3. Basic timer (TIMERx, x=5, 6) 17.3.1. Overview The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 368: Figure 17-40. Normal Mode, Internal Clock Divided By 1
GD32L23x User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Figure 17-40. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse...
Page 369: Figure 17-41. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32L23x User Manual Figure 17-41. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK FA FB FC CNT_REG Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 370 GD32L23x User Manual Figure 17-42. Timing chart of up counting mode, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 371: Figure 17-43. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 17-43. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear...
Page 372: Timerx Registers(X=5,6)
GD32L23x User Manual 17.3.5. TIMERx registers(x=5,6) TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions 31:8...
Page 373 GD32L23x User Manual loaded with their preloaded values when one of the following events occurs: The UPG bit is set The counter generates an overflow or underflow event The slave mode controller generates an update event. 1: update event disable. The buffered registers keep their value, while the counter and the prescaler are reinitialized if the UG bit is set or if the slave mode controller generates a hardware reset event.
Page 374 GD32L23x User Manual TRGO. 011~111: Reserved. Reserved Must be kept at reset value. Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value.
Page 375 GD32L23x User Manual 31:1 Reserved Must be kept at reset value. UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 This register has to be accessed by word(32-bit).
Page 376 GD32L23x User Manual 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 This register has to be accessed by word(32-bit).
Page 377: Low Power Timer (Lptimer)
GD32L23x User Manual Low power timer (LPTIMER) 18.1. Overview The LPTIMER is a 32-bit timer and it is able to keep running in all power modes except for Standby mode with its diversity of clock sources. The LPTIMER provides a flexible mechanism of the clock, which reduces the power consumption to a minimum while also achieving the required functions and performance.
Page 378: Block Diagram
GD32L23x User Manual 18.3. Block diagram Figure 18-1. LPTIMER block diagram provides details of the internal configuration of the low power timer. Figure 18-1. LPTIMER block diagram High level counter IN1FP IN1F LPTIMER_IN1 Polarity Filter DECODER selection IN0FP Counter IN0F PCLK2 LPTIMER_IN0 LPTIMER_CK...
Page 379: Figure 18-2. Lptimer Clock Source Selection
GD32L23x User Manual Figure 18-2. LPTIMER clock source selection Polarity selection Polarity Filter selection LPTIMER has the capability of being clocked by either the internal clock signal or external clock signal controlled by bits CNTMEN and CKSSEL in LPTIMER_CTL0 register. The CKSSEL bit is used to select which clock drivies the counter prescaler and the default clock source is the PCLK2.
Page 380: Figure 18-3. Internal Clock Mode1 (Ckssel = 0 And Cntmen = 1 And Psc[2:0] = 000)
GD32L23x User Manual the external input clock signal, but not on both edges. Since the external signal added to the LPTIMER external input 0 (LPTIMER_IN0) is also used to clock the LPTIMER core logic, there is some initial latency (after the LPTIMER is enabled) before the counter is counting.
Page 381: Figure 18-4. Input Filter Timing Diagram (Eckflt=2'B01)
GD32L23x User Manual 18.4.4. Input filter The external (mapped to GPIOs) or internal (mapped on-chip peripherals, such as comparators) signal on the LPTIMER_INx needs to be filtered by a digital filter to prevent the glitches and noise interference from spreading in LPTIMER. This can be used to prevent false counts and triggers.
Page 382: Figure 18-5. External Inputs High Level Counter
GD32L23x User Manual LPTIMER_INx high level counter equal to the value of INHLCMVAL bits (in LPTIMER_INHLCMV register). An interrupr will generated if the INHLCOIE bit is enabled (in LPTIMER_INTEN register). The INHLCOIF flag can be cleared by writing 1 to the INHLCOIC bit in the INTC register.
Page 383: Table 18-2. External Trigger Mapping
GD32L23x User Manual 18.4.7. External trigger mapping The LPTIMER external trigger connections are detailed hereafter: Table 18-2. External trigger mapping ETSEL[2:0] External trigger ETI0 GPIO ETI1 RTC alarm 0 ETI2 RTC alarm 1 ETI3 RTC_TAMP0 input detection ETI4 RTC_TAMP1 input detection ETI5 RTC_TAMP2 input detection ETI6...
Page 384: Figure 18-6. Lptimer Output With Smst = 1
GD32L23x User Manual Figure 18-6. LPTIMER output with SMST = 1 External Trigger CARL[31:0] CMPVAL[31:0] COUNT LPTIMER_O When the OMSEL bit in the LPTIMER_CTL0 register is set, the Set mode is enable. In this case, the counter is only started once after the first trigger, and all subsequent trigger events is ignored, as shown in Figure 18-7.
Page 385: Figure 18-8. Lptimer Output With Ctnmst = 1
GD32L23x User Manual Figure 18-8. LPTIMER output with CTNMST = 1 ignored ignored External Trigger CARL[31:0] CMPVAL[31:0] COUNT LPTIMER_O The SMST and CTNMST bits can be only when the timer is enabled (The LPTEN bit modified is set to 1). And the single counting mode and continuous counting mode can be modified on the fly.
Page 386: Figure 18-9. Lptimer_O Output Mode With Opsel Bit
GD32L23x User Manual mode waveform (depending on the CTNMST bit or SMST bit is set).  OMSEL = 1: the LPTIMER to generate a Set mode waveform. The OPSEL bit controls the LPTIMER output polarity, the modification of this bit will take effect immediately.
Page 387: Figure 18-10. Lptimer Timeout Mode
GD32L23x User Manual Figure 18-10. LPTIMER timeout mode External Trigger TIMEOUT = 0 ignored CARL[31:0] CMPVAL[31:0] COUNT TIMEOUT = 1 CARL[31:0] CMPVAL[31:0] Counter CMPVMIE = 1 CMPVMIF Clear flag LPTIMER_ WAKEUP 18.4.11. Decoder mode The LPTIMER has two decoder modes: ...
Page 388: Figure 18-11. Counter Operation In Decoder Mode 0 With Rising-Edge-Mode
GD32L23x User Manual Therefore, users must configure the TIMERx_CAR register before the counter starts to count. When the counter direction changes, the corresponding flag is set. When the counter direction moves from up to down, the DOWNIF bit is set. When the counter direction moves from down to up, the UPIF bit is set.
Page 389: Figure 18-12. Counter Operation In Decoder Mode 0 With Falling-Edge-Mode
GD32L23x User Manual Figure 18-12. Counter operation in decoder mode 0 with falling-edge-mode IN0F IN1F CARL Counter Down Down UPIF DOWNIF Decoder mode 1 The decoder mode 1 function uses two non-quadrature inputs derived from the LPTIMER_IN0 and LPTIMER_IN1 pins respectively to generate the counter value. At first, the CTNMST bit is set to 1 to enable the the continuous counting mode and the DECMEN bit is set to 1 to enable the decoder mode.
Page 390: Figure 18-14. Counter Operation In Decoder Mode 1 With Non-Inverted(In1Eif)
GD32L23x User Manual Figure 18-13. Counter operation in decoder mode 1 with non-inverted IN1FP IN0FP CARL Counter IN1FP IN0FP CARL Counter When the inputs of LPTIMER_IN0 and LPTIMER_IN1 do not meet the timing relationship in Figure 18-13. Counter operation in decoder mode 1 with non-inverted, the counter cannot count.
Page 391: Figure 18-15. Counter Operation In Decoder Mode 1 With Non-Inverted(In0Eif)
GD32L23x User Manual Figure 18-15. Counter operation in decoder mode 1 with non-inverted(IN0EIF) IN1FP IN0FP CARL Counter IN0EIF Figure 18-16. Counter operation in decoder mode 1 with non-inverted(INRFOEIF) IN1FP IN1FP IN0FP IN0FP CARL CARL Counter Counter INRFOEIF INRFOEIF Figure 18-17. Counter operation in decoder mode 1 with non-inverted(INHLOEIF) IN1FP IN1FP IN0FP...
Page 392: Table 18-4. Lptimer Works In Low-Power Modes
GD32L23x User Manual 000). In this case, the internal clock signal frequency should be at least four times the frequency of the external clock signal. 18.4.12. Register update The LPTIMER_CAR register and LPTIMER_CMPV register are updated immediately after the APB bus write operation, or updated at the end of the current period, when the LPTIMER has already started.
Page 393: Table 18-5. Lptimer Interrupt Events
GD32L23x User Manual Mode Description LPTIMER interrupts cause the device to exit the Deep-sleep 2 Deep-sleep2 mode mode. 18.4.14. Interrupts The following events can generate an interrupt/wake-up event, if they are enabled through the LPTIMER_INTEN register:  LPTIMER_IN1 error  LPTIMER_IN0 error ...
Page 394 GD32L23x User Manual Interrupt event Description register update LPTIMER_INHLCMV register has been successfully completed. LPTIMER counter direction Interrupt flag is set when the counter direction moves from up to change up to down down. LPTIMER counter direction Interrupt flag is set when the counter direction moves from down change down to up to up.
Page 395 GD32L23x User Manual 18.5. LPTIMER registers LPTIMER base address: 0x4000 9400 18.5.1. Interrupt flag register (LPTIMER_INTF) Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word (32-bit). HLCMV IN1EIF IN0EIF INRFOEIF INHLOEIF INHLCOIF Reserved UPIF CMPV ETED CMPV Reserved...
Page 396 GD32L23x User Manual Note: This flag just used in decoder mode 1. INHLCOIF LPTIMER_INx(x=0,1) high level counter overflow interrupt flag This flag is set by hardware when LPTIMER_INx high level counter equal to external input high level counter max value register (LPTIMER_INHLCMV). INHLCOIF flag can be cleared by writing 1 to the INHLCOIC bit in the INTC register.
Page 397 GD32L23x User Manual CMPVMIC bit in the INTC register. 18.5.2. Interrupt flag clear register (LPTIMER_INTC) Address offset: 0x04 Reset value: 0x0000 This register has to be accessed by word (32-bit). HLCMV IN1EIC IN0EIC INRFOEIC INHLOEIC INHLCOIC Reserved UPIC CMPV ETED CMPV Reserved DOWNIC...
Page 398 GD32L23x User Manual CMPVUPIC Compare value register update interrupt flag clear bit. Write 1 to this bit to clear the CMPVUPIF flag, and write 0 has no effect. ETEDEVIC External trigger edge event interrupt flag clear bit. Write 1 to this bit to clear the ETEDEVIF flag, and write 0 has no effect. CARMIC Counter auto reload register match interrupt flag clear bit.
Page 399 GD32L23x User Manual INHLOEIE The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt enable bit. 0: disabled 1: enabled This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). INHLCOIE LPTIMER_INx(x=0,1) high level counter overflow interrupt enable bit 0: disabled 1: enabled...
Page 400 GD32L23x User Manual This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). CARMIE Counter auto reload register match interrupt enable bit 0: disabled 1: enabled This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0).
Page 401 GD32L23x User Manual 1: The counter is count with each active clock pulse on the LPTIMER_IN0. This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). SHWEN LPTIMER_CAR and LPTIMER_CMPV shadow registers enable 0: The shadow registers are disable.
Page 402 GD32L23x User Manual Reserved Must be kept at reset value. 15:13 ETSEL[2:0] External trigger select The ETSEL bits are used to select the external trigger source for LPTIMER. 000: ETI0 (GPIO) 001: ETI1 (RTC Alarm 0) 010: ETI2 (RTC Alarm 1) 011: ETI3 (RTC_TAMP0 input detection) 100: ETI4 (RTC_TAMP1 input detection) 101: ETI5 (RTC_TAMP2 input detection)
Page 403 GD32L23x User Manual Reserved Must be kept at reset value. ECKFLT[1:0] External clock filter The ECKFLT bits are used to configure the digital filter for external clock. An internal clock source must be used in this function. 00: Filter disabled, any active level change of external clock is valid. 01: The active level change of the external clock need to be maintained at least 2 clock periods.
Page 404 GD32L23x User Manual LPTIMER_CTL1 register is 0). CKSSEL Clock source select This bit is used to select the clock source for LPTIMER. 0: LPTIMER is clocked by internal clock source. 1: LPTIMER is clocked by external clock source on the LPTIMER_IN0. This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0).
Page 405 GD32L23x User Manual This bit is set and reset by software. 0: LPTIMER is disabled 1: LPTIMER is enabled 18.5.6. Compare value register (LPTIMER_CMPV) Address offset: 0x14 Reset value: 0x0000 This register has to be accessed by word (32-bit). CMPVAL[31:16] CMPVAL[15:0] Bits Fields...
Page 406 GD32L23x User Manual 18.5.8. Counter register (LPTIMER_CNT) Address offset: 0x1C Reset value: 0x0000 This register has to be accessed by word (32-bit). CNT[31:16] CNT[15:0] Bits Fields Descriptions 31:0 CNT[31:0] Counter value Note: When the LPTIMER is running with an asynchronous clock, reading the LPTIMER_CNT register may return unreliable values.
Page 407 GD32L23x User Manual 18.5.10. Input high level counter max value register (LPTIMER_INHLCMV) Address offset: 0X24 Reset value: 0x0000 This register has to be accessed by word (32-bit). Reserved INHLCMVAL [25:16] INHLCMVAL [15:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:0 INHLCMVAL Input high level counter max value...
Page 408 GD32L23x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 19.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK, CK_SYS, LXTAL or IRC16M) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 409 GD32L23x User Manual  Parity control – Transmits parity bit – Checks parity of received data byte  LIN Break generation and detection  IrDA Support  Synchronous mode and transmitter clock output for synchronous transmission  ISO 7816-3 compliant smartcard interface –...
Page 410: Figure 19-1. Usart Module Block Diagram
GD32L23x User Manual 19.3. Function overview The interface is externally connected to another device by the main pins listed in Table 19-1. Description of USART important pins. Table 19-1. Description of USART important pins Type Description Input Receive Data Output I/O (single- Transmit Data.
Page 411: Figure 19-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32L23x User Manual Figure 19-2. USART character frame (8 bits data and 1 stop bit) CLOCK Data frame or parity bit Start bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 Start Stop Idle frame Start Start Stop Break frame In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register.
Page 412 GD32L23x User Manual Get the value of USART_BAUD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). 16*0.37=5.92, the nearest integer is 6, so FRADIV=6 (0x6). USART_BAUD=0x1E6. Note: If the roundness FRADIV is 16 (overflow), the carry must be added to the integer part.
Page 413: Figure 19-3. Usart Transmit Procedure
GD32L23x User Manual Figure 19-3. USART transmit procedure It is necessary to wait for the TC bit to be asserted before disabling the USART or entering the power saving mode. This bit can be cleared by set the TCC bit in USART_INTC register. The break frame is sent when the SBKCMD bit is set, and SBKCMD bit is reset after the transmission.
Page 414: Figure 19-4. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32L23x User Manual frame bit is 0, the frame bit is confirmed as a 0, else 1. If the value of the three samples of any bit are not the same, whatever it is a start bit, data bit, parity bit or stop bit, a noisy error (NERR) status will be generated for the frame.
Page 415: Figure 19-5. Configuration Step When Using Dma For Usart Transmission
GD32L23x User Manual 19.3.5. Use DMA for data buffer access To reduce the burden of the processor, DMA can be used to access the transmitting and receiving data buffer. The DENT bit in USART_CTL2 is used to enable the DMA transmission, and the DENR bit in USART_CTL2 is used to enable the DMA reception.
Page 416: Figure 19-6. Configuration Step When Using Dma For Usart Reception
GD32L23x User Manual Figure 19-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 417: Figure 19-8. Hardware Flow Control
GD32L23x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 418 GD32L23x User Manual The idle frame wake up method is selected by default. If the RWU bit is reset, an idle frame is detected on the RX pin, the IDLEF bit in USART_STAT will be set. If the RWU bit is set, an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode.
Page 419: Figure 19-9. Break Frame Occurs During Idle State
GD32L23x User Manual Figure 19-9. Break frame occurs during idle state frame0 frame1 frame2 RX pin 1 frame time FERR data0 data1 00000000 data2 USART_RDATA LBDF As shown in Figure 19-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame.
Page 420: Figure 19-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32L23x User Manual Figure 19-12. 8-bit format USART synchronous waveform (CLEN=1) 19.3.10. IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode.
Page 421: Figure 19-14. Irda Data Modulation
GD32L23x User Manual pulse width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times of PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block.
Page 422: Figure 19-15. Iso7816-3 Frame Format
GD32L23x User Manual smartcard, the TX pin must be configured as open drain mode, and drives a bidirectional line that is also driven by the smartcard. Figure 19-15. ISO7816-3 frame format ISO 7816-3 frame without parity error 0.5 bit 1 bit ISO 7816-3 frame with parity error Character (T=0) mode Compared to the timing in normal operation, the transmission time from transmit shift register...
Page 423 GD32L23x User Manual When requesting a read from the smartcard, the RT[23:0] bits in USART_RT register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. A timeout interrupt will be generated, if no answer is received from the card before the expiration of this period.
Page 424: Figure 19-16. Usart Receive Fifo Structure
GD32L23x User Manual ABDM bits in the USART_CTL1 register. These methods are: The USART will measure the duration of the start bit (falling edge to rising edge). In this case the receiving pattern should be any character starting with a bit at 1. The USART will measure the duration of the start and of the 1st data bit.
Page 425: Table 19-3. Usart Interrupt Requests
GD32L23x User Manual If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out. The PERR/NERR/FERR/EBF/ABDE/ABDF flags should be cleared before reading a receive data out.
Page 426: Figure 19-17. Usart Interrupt Mapping Diagram
GD32L23x User Manual Interrupt event Event flag Enable Control bit overrun error, framing error) Character match AMIE Receiver timeout error RTIE End of Block EBIE Wakeup from Deep-sleep WUIE mode All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time.
Page 427 GD32L23x User Manual 19.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 19.4.1. Control register 0 (USART_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved EBIE RTIE...
Page 428 GD32L23x User Manual This bit field cannot be written when the USART is enabled (UEN=1). OVSMOD Oversample mode 0: Oversampling by 16 1: Oversampling by 8 This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be written when the USART is enabled (UEN=1). AMIE ADDR match interrupt enable 0: ADDR match interrupt is disabled...
Page 429 GD32L23x User Manual RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 0: Read data register not empty interrupt and overrun error interrupt disabled 1: An interrupt will occur whenever the ORERR bit is set or the RBNE bit is set in USART_STAT.
Page 430 GD32L23x User Manual only the ADDR[3:0] bits are used to compare. In normal reception, these bits are also used for character detection. The whole received character (8-bit) is compared to the ADDR[7:0] value and AMF flag is set on matching. This bit field cannot be written when both reception (REN=1) and USART (UEN=1) are enabled.
Page 431 GD32L23x User Manual 1: The TX and RX pins functions are swapped This bit field cannot be written when the USART is enabled (UEN=1). LMEN LIN mode enable 0: LIN mode disabled 1: LIN mode enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in UART3 and UART4.
Page 432 GD32L23x User Manual 0: 10 bit break detection 1: 11 bit break detection This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in UART3 and UART4. ADDM Address detection mode This bit is used to select between 4-bit address detection and full-bit address detection.
Page 433 GD32L23x User Manual This bit is reserved in UART3 and UART4. 19:17 SCRTNUM[2:0] Smartcard auto-retry number In smartcard mode, these bits specify the number of retries in transmission and reception. In transmission mode, a transmission error (FERR bit set) will occur after this number of automatic retransmission retries.
Page 434 GD32L23x User Manual This bit field cannot be written when the USART is enabled (UEN=1). One sample bit method 0: Three sample bit method 1: One sample bit method This bit field cannot be written when the USART is enabled (UEN=1). CTSIE CTS interrupt enable 0: CTS interrupt is disabled...
Page 435 GD32L23x User Manual 1: Low-power mode This bit field cannot be written when the USART is enabled (UEN=1). IREN IrDA mode enable 0: IrDA disabled 1: IrDA enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in UART3 and UART4.
Page 436 GD32L23x User Manual Reserved GUAT[7:0] PSC[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:8 GUAT[7:0] Guard time value in smartcard mode This bit field cannot be written when the USART is enabled (UEN=1). PSC[7:0] Prescaler value for dividing the system clock In IrDA Low-power mode, the division factor is the prescaler value.
Page 437 GD32L23x User Manual Bits Fields Descriptions 31:24 BL[7:0] Block Length These bits specify the block length in smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2- CRC) - 1. This value, which must be programmed only once per received block, can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field).
Page 438 GD32L23x User Manual RXFCMD Receive data flush command Writing 1 to this bit clears the RBNE flag to discard the received data without reading it. MMCMD Mute mode command Writing 1 to this bit makes the USART into mute mode and sets the RWU flag. SBKCMD Send break command Writing 1 to this bit sets the SBKF flag and makes the USART send a BREAK...
Page 439 GD32L23x User Manual 1: Wakeup from Deep-sleep mode. An interrupt is generated if WUFIE=1 in the USART_CTL2 register and the MCU is in Deep-sleep mode. This bit is set by hardware when a wakeup event, which is defined by the WUM bit field, is detected.
Page 440 GD32L23x User Manual Cleared by software, by writing 1 to the ABDCMD bit in the USART_CMD register. This bit is reserved in UART3 and UART4. Reserved Must be kept at reset value End of block flag 0: End of Block not reached 1: End of Block (number of characters) reached.
Page 441 GD32L23x User Manual set in USART_CTL0 Set by hardware when the content of the USART_TDATA register has been transferred into the transmit shift register or writing 1 to TXFCMD bit of the USART_CMD register. Cleared by a write to the USART_TDATA. Transmission completed 0: Transmission is not completed 1: Transmission is complete.
Page 442 GD32L23x User Manual FERR Frame error flag 0: No framing error is detected 1: Frame error flag or break character is detected. In multibuffer communication, an interrupt will occur if the ERRIE bit is set in USART_CTL2. Set by hardware when a de-synchronization, excessive noise or a break character is detected.
Page 443 GD32L23x User Manual This bit is reserved in UART3 and UART4. Receiver timeout clear Writing 1 to this bit clears the RTF flag in the USART_STAT register. This bit is reserved in UART3 and UART4. Reserved Must be kept at reset value CTSC CTS change clear Writing 1 to this bit clears the CTSF bit in the USART_STAT register.
Page 444 GD32L23x User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value RDATA[8:0] Receive Data value The received data character is contained in these bits. The value read in the MSB (bit 7 or bit 8 depending on the data length) will be the received parity bit, if receiving with the parity is enabled (PCEN bit set to 1 in the USART_CTL0 register).
Page 445 GD32L23x User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value EPERR Early parity error flag. This flag will be set as soon as the parity bit has been detected, which is before RBNE flag. This flag is cleared by writing 0. 0: No parity error is detected 1: Parity error is detected.
Page 446 GD32L23x User Manual RFEN Receive FIFO enable This bit can be set when UESM = 1. 0: Receive FIFO disable 1: Receive FIFO enable Reserved Must be kept at reset value ELNACK Early NACK when smartcard mode is selected. The NACK pulse occurs 1/16 bit time earlier when the parity error is detected. 0:Early NACKdisable when smartcard mode is selected 1:Early NACKenable when smartcard mode is selected This bit is reserved in UART3 and UART4.
Page 447 GD32L23x User Manual Low-power universal asynchronous receiver /transmitter (LPUART) 20.1. Overview The Low-power universal Asynchronous Receiver/Transmitter (LPUART) provides a flexible serial data exchange interface with a limited power consumption. LPUART can perform asynchronous serial communication even with low power consumption. Data frames can be transferred in full duplex or half duplex mode, asynchronously through this interface.
Page 448: Table 20-1. Description Of Lpuart Important Pins
GD32L23x User Manual – Transmits parity bit – Checks parity of received data byte  Multiprocessor communication – Enter into mute mode if address match does not occur – Wake up from mute mode by idle line or address mark detection ...
Page 449: Figure 20-1. Lpuart Module Block Diagram
GD32L23x User Manual Figure 20-1. LPUART module block diagram CPU/DMA Transmit Shift Register LPUART Data Register Receive Shift Register nRTS Hardware Flow nCTS Controler LPUART Control Registers LPUART Address Transmitter Transimit clock Controler Receiver Receiver Wakeup Unit Controler clock LPUCLK /LPUARTDIV (PCLK or CK_SYS or IRC16M or LXTAL)
Page 450: Figure 20-2. Lpuart Character Frame
GD32L23x User Manual Figure 20-2. LPUART character frame 8 bit word length (WL = 00), 1 stop bit CLOCK Data frame or parity bit Start bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 Start Stop Idle frame Start Start Stop Stop Break frame 9 bit word length (WL = 01), 1 stop bit...
Page 451 GD32L23x User Manual (3 x baudrate) ≤ LPUCLK ≤ (4096 x baudrate). The value of the LPUART_BAUD register should not be changed during communication. 20.3.3. LPUART transmitter If the transmit enable bit (TEN) in LPUART_CTL0 register is set, when the transmit data buffer is not empty, the transmitter shifts out the transmit data frame through the TX pin.
Page 452: Figure 20-3. Lpuart Transmit Procedure
GD32L23x User Manual Figure 20-3. LPUART transmit procedure It is necessary to wait for the TC bit to be asserted before disabling the LPUART or entering the power saving mode. This bit can be cleared by set TCC bit in LPUART_INTC register. The break frame is sent when the SBKCMD bit is set, and SBKCMD bit is reset after the transmission.
Page 453 GD32L23x User Manual If the parity check function is enabled by setting the PCEN bit in the LPUART_CTL0 register, the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value. If they are not the same, the parity error (PERR) bit in LPUART_STAT register will be set.
Page 454: Figure 20-4. Configuration Step When Using Dma For Lpuart Transmission
GD32L23x User Manual Figure 20-4. Configuration step when using DMA for LPUART transmission Clear the TC bit in LPUART_STAT Set the address of LPUART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 455: Figure 20-5. Configuration Step When Using Dma For Lpuart Reception
GD32L23x User Manual Figure 20-5. Configuration step when using DMA for LPUART reception Set the address of LPUART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 456: Figure 20-7. Hardware Flow Control
GD32L23x User Manual RTS flow control The LPUART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The LPUART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 457 GD32L23x User Manual 20.3.7. Multi-processor communication In multiprocessor communication, several LPUARTs are connected as a network. It will be a big burden for a device to monitor all of the messages on the RX pin. To reduce the burden of a device, the MEN bit in LPUART_CTL0 register is used to enable the mute mode function, software can put an LPUART module into a mute mode by writing 1 to the MMCMD bit in LPUART_CMD register.
Page 458: Table 20-3. Lpuart Interrupt Requests
GD32L23x User Manual The UESM bit must be set and the LPUART clock must be set to IRC16M or LXTAL (refer to the reset and clock unit RCU section). When the LPUART clock source is configured to be IRC16M or LXTAL, it is possible to keep enabled this clock during Deep-sleep mode by setting the UCESM bit in LPUART_CTL2 register.
Page 459: Figure 20-8. Lpuart Interrupt Mapping Diagram
GD32L23x User Manual Figure 20-8. LPUART interrupt mapping diagram IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ORERR ERRIE LPUART_INT AMIE WUIE TCIE TBEIE CTSF CTSIE...
Page 460 GD32L23x User Manual 20.4. Register definition LPUART base address: 0x4000 8000 20.4.1. Control register 0 (LPUART_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved DEA[4:0] DED[4:0] Reserved AMIE PCEN PERRIE TBEIE TCIE RBNEIE...
Page 461 GD32L23x User Manual 1: ADDR match interrupt is enabled Mute mode enable 0: Mute mode disabled 1: Mute mode enabled Word length This bit, with WL1 bit determines the word length WL[1:0] = 00, 8 data bits WL[1:0] = 01, 9 data bits WL[1:0] = 10, 7 data bits WL[1:0] = 11, 7 data bits This bit field cannot be written when the LPUART is enabled (UEN=1).
Page 462 GD32L23x User Manual 1: An interrupt will occur whenever the IDLEF bit is set in LPUART_STAT. Transmitter enable 0: Transmitter is disabled 1: Transmitter is enabled Receiver enable 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit UESM LPUART enable in Deep-sleep mode 0: LPUART not able to wake up the MCU from Deep-sleep mode.
Page 463 GD32L23x User Manual 23:20 Reserved Must be kept at reset value. MSBF Most significant bit first 0: Data is transmitted/received with the LSB first 1: Data is transmitted/received with the MSB first This bit field cannot be written when the LPUART is enabled (UEN=1). DINV Data bit level inversion 0: Data bit signal values are not inverted...
Page 464 GD32L23x User Manual 20.4.3. Control register 2 (LPUART_CTL2) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved UCESM WUIE WUM[1:0] Reserved DDRE OVRD Reserved CTSIE CTSEN RTSEN DENT DENR Reserved HDEN Reserved ERRIE Bits Fields...
Page 465 GD32L23x User Manual DDRE Disable DMA on reception error 0: DMA is not disabled in case of reception error. The DMA request is not asserted to make sure the erroneous data is not transferred, but the next correct received data will be transferred. The RBNE is kept 0 to prevent overrun, but the corresponding error flag is set.
Page 466 GD32L23x User Manual 1: Half duplex mode is enabled This bit field cannot be written when the LPUART is enabled (UEN=1). Reserved Must be kept at reset value ERRIE Error interrupt enable 0: Error interrupt disabled 1: An interrupt will occur whenever the FERR bit or the ORERR bit or the NERR bit is set in LPUART_STAT in multibuffer communication 20.4.4.
Page 467 GD32L23x User Manual RXFCMD Receive data flush command Writing 1 to this bit clears the RBNE flag to discard the received data without reading it. MMCMD Mute mode command Writing 1 to this bit makes the LPUART into mute mode and sets the RWU flag. Reserved Must be kept at reset value.
Page 468 GD32L23x User Manual This bit can also be cleared when UESM is cleared. Receiver wakeup from mute mode This bit is used to indicate if the LPUART is in mute mode. 0: Receiver in active mode 1: Receiver in mute mode It is cleared/set by hardware when a wakeup/mute sequence (address or IDLEIE) is recognized, which is selected by the WM bit in the LPUART_CTL0 register.
Page 469 GD32L23x User Manual 0: Transmission is not completed 1: Transmission is complete. An interrupt will occur if the TCIE bit is set in LPUART_CTL0. Set by hardware if the transmission of a frame containing data is completed and if the TBE bit is set. Cleared by writing 1 to TCC bit in LPUART_INTC register.
Page 470 GD32L23x User Manual Cleared by writing 1 to FEC bit in LPUART_INTC register. PERR Parity error flag 0: No parity error is detected 1: Parity error flag is detected. An interrupt will occur if the PERRIE bit is set in LPUART_CTL0.
Page 471 GD32L23x User Manual Writing 1 to this bit clears the ORERR bit in the LPUART_STAT register. Noise detected clear Writing 1 to this bit clears the NERR bit in the LPUART_STAT register. Frame error flag clear Writing 1 to this bit clears the FERR bit in the LPUART_STAT register Parity error clear Writing 1 to this bit clears the PERR bit in the LPUART_STAT register.
Page 472 GD32L23x User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value TDATA[8:0] Transmit Data value The transmit data character is contained in these bits. The value written in the MSB (bit 7 or bit 8 depending on the data length) will be replaced by the parity, when transmitting with the parity is enabled (PCEN bit set to 1 in the LPUART_CTL0 register).
Page 473: Figure 21-1. I2C Module Block Diagram
GD32L23x User Manual Inter-integrated circuit interface (I2C) 21.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 474: Table 21-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32L23x User Manual Figure 21-1. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Register Digital Noise Noise filter filter...
Page 475: Figure 21-2. Data Validation
GD32L23x User Manual  < t I2CCLK HIGH with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters Analog filter delay is maximum 260ns. Digital filter delay is DNF[3:0] x tI2CCLK The period of PCLK clock tPCLK match the conditions as follows: ...
Page 476: Figure 21-3. Start And Stop Condition
GD32L23x User Manual Figure 21-3. START and STOP condition START STOP Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device.
Page 477: Figure 21-5. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32L23x User Manual Figure 21-5. I2C communication flow with 7-bit address (Master Transmit) Figure 21-6. I2C communication flow with 7-bit address (Master Receive) Start Slave address …… DATAN R(1) DATA0 NACK Stop data transfer (N+1 bytes) From master to slave From slave to master In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent.
Page 478: Figure 21-9. Data Hold Time
GD32L23x User Manual 21.3.3. Noise filter The noise filters must be configured before setting the I2CEN bit in I2C_CTL0 register if it is necessary. The analog noise filter is present on the SDA and SCL inputs by default. The analog filter requires the suppression of spikes with a pulse width up to 50ns in fast mode and fast mode plus.
Page 479: Figure 21-10. Data Setup Time
GD32L23x User Manual Figure 21-10. Data setup time SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t = SDADELY * t where t = (PSC+1) * t SDADELY I2CCLK I2CCLK SDADELY...
Page 480: Table 21-2. Data Setup Time And Data Hold Time
GD32L23x User Manual Table 21-2. Data setup time and data hold time Standard Fast mode Fast mode SMBus Symbol Parameter mode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of 1000 1000 SCL and SDA...
Page 481: Figure 21-11. Data Transmission
GD32L23x User Manual Figure 21-11. Data transmission SCL Stretch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA Data Reception When receiving data, the SDA input fills the shift register. After the 8th SCL pulse, the complete data byte is received. If RBNE=0 (I2C_RDATA register is empty), the data in the shift register is moved into I2C_RDATA register.
Page 482: Table 21-3. Communication Modes To Be Shut Down
GD32L23x User Manual Table 21-3. Communication modes to be shut down Working mode Action Master mode NACK, STOP and RESTART generation Slave receiver mode ACK control SMBus mode PEC generation/checking The byte counter is always used in master mode. It is disabled in slave mode by default, but it can be enabled by software by setting the SBCTL (slave byte control) bit in the I2C_CTL0 register.
Page 483 GD32L23x User Manual 21.3.7. I2C slave mode Initialization When works in slave mode, at least one slave address should be enabled. Slave address 1 can be programmed in I2C_SADDR0 register and slave address 2 can be programmed in I2C_SADDR1 register. ADDRESSEN in I2C_SADDR0 register and ADDRESS2EN in I2C_SADDR1 register should be set when the corresponding address is used.
Page 484 GD32L23x User Manual the first SCL pulse corresponding to its transfer occurs. Or else the OUERR bit in the I2C_STAT register will be set, if the ERRIE bit is set, an interrupt will be generated. When the STPDET bit is set and the first data transmission starts, OUERR bit in the I2C_STAT register will also be set.
Page 485: Figure 21-13. I2C Initialization In Slave Mode
GD32L23x User Manual Figure 21-13. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0 Clear ADDRESS2EN in I2C_SADDR1 Configure ADDRESS[9:0], ADDFORMAT and ADDRESSEN in I2C_SADDR0, ADDRESS2[7:1], ADDMSK2[2:0] and ADDRESS2EN in I2C_SADDR1, ADDM[6:0] in I2C_CTL2...
Page 486: Figure 21-14. Programming Model For Slave Transmitting When Ss=0
GD32L23x User Manual When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set. In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine. So the first data byte to be sent must be programmed in the I2C_TDATA register previously.
Page 487: Figure 21-15. Programming Model For Slave Transmitting When Ss=1
GD32L23x User Manual Figure 21-15. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND...
Page 488: Figure 21-16. Programming Model For Slave Receiving
GD32L23x User Manual Figure 21-16. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1)
Page 489: Figure 21-17. I2C Initialization In Master Mode
GD32L23x User Manual SCL synchronization with I2CCLK clock, which generally 2 to 3 I2CCLK periods. The t SYNC2 depends on the SCL rising slope, delay by input analog and digital noise filter and SCL synchronization with I2CCLK clock, which generally 2 to 3 I2CCLK periods. The delay by digital noise filter is DNF[3:0] x t I2CCLK When works in master mode, the ADD10EN bit, SADDRESS[9:0] bits, TRDIR bit should be...
Page 490: Figure 21-18. Programming Model For Master Transmitting (N<=255)
GD32L23x User Manual be transferred is greater than 255, RELOAD bit in I2C_CTL0 register must be set to enable the reload mode. In reload mode, when data of BYTENUM[7:0] bytes have been transferred, the TCR bit in I2C_STAT register will be set and the SCL stretches unitil BYTENUM[7:0] is modified with a non-zero value.
Page 491: Figure 21-19. Programming Model For Master Transmitting (N>255)
GD32L23x User Manual Figure 21-19. Programming model for master transmitting (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave...
Page 492: Figure 21-20. Programming Model For Master Receiving (N<=255)
GD32L23x User Manual Figure 21-20. Programming model for master receiving (N<=255) I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) ……（Data transmission）...
Page 493: Figure 21-21. Programming Model For Master Receiving (N>255)
GD32L23x User Manual Figure 21-21. Programming model for master receiving (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) ……（Data transmission）...
Page 494 GD32L23x User Manual specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications. I2C devices that do not adhere to these protocols cannot be accessed by standard methods as defined in the SMBus and Advanced Configuration and Power Management Interface (abbreviated to ACPI) specifications.
Page 495: Table 21-5. Smbus With Pec Configuration
GD32L23x User Manual In order to enable the t , the BUSTOA[11:0] must be programmed with the timer to check TIMEOUT the t parameter. To detect SCL low level timeout, the TOIDLE bit must be configured to TIMEOUT "0". Then set TOEN in the I2C_TIMEOUT register to enable the timer. If the low level time of SCL is greater than (BUSTOA + 1) x 2048 x t , the TIMEOUT flag is set in the I2C_STAT I2CCLK...
Page 496 GD32L23x User Manual the same time. Only the device(s) which pulled SMBALERT# low will acknowledge the Alert Response Address. When SMBHAEN is 0, it is configured as a slave device, the SMBA pin is pulled low by setting the SMBALTEN bit in the I2C_CTL0 register. Meanwhile the Alert Response Address is enabled.
Page 497: Figure 21-22. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32L23x User Manual BYTENUM=0x1 and PECTRANS bit is set at the same time, the contents of the I2C_PEC register are automatically transferred. If the automatic end mode is selected (AUTOEND=1), the SMBus master automatically sends the STOP condition after the PEC byte. If the automatic end mode is not selected (AUTOEND=0), the SMBus master can send a RESTART condition after the PEC.
Page 498: Figure 21-23. Smbus Master Receiver And Slave Transmitter Communication Flow
GD32L23x User Manual master is greater than BYTENUM-1, the total number of TI interrupts will be BYTENUM-1, and the contents of the I2C_PEC register will be transmitted automatically. Note: After the RELOAD bit is set, the PECTRANS cannot be changed. Figure 21-23.
Page 499: Table 21-6. I2C Error Flags
GD32L23x User Manual 21.3.13. I2C error and interrupts The I2C error flags are listed in Table 21-6. I2C error flags. Table 21-6. I2C error flags I2C Error Name Description BERR Bus error LOSTARB Arbitration lost OUERR Overrun/Underrun flag CRC value doesn’t match PECERR TIMEOUT Bus timeout in SMBus mode...
Page 500 GD32L23x User Manual 21.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 I2C2 base address: 0x4000 C000 21.4.1. Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). SMBALT SMBDAE SMBHAE...
Page 501 GD32L23x User Manual 0: Slave won’t response to a General Call 1: Slave will response to a General Call WUEN Wakeup from Deep-sleep mode enable This bit is cleared when mcu wakeup from Deep-sleep mode. 0: Wakeup from Deep-sleep mode disable. 1: Wakeup from Deep-sleep mode enable.
Page 502 GD32L23x User Manual 0: Error interrupt disabled 1: Error interrupt enabled. When BERR, LOSTARB, OUERR, PECERR, TIMEOUT or SMBALT bit is set, an interrupt will be generated. TCIE Transfer complete interrupt enable 0: Transfer complete interrupt is disabled 1: Transfer complete interrupt is enabled STPDETIE Stop detection interrupt enable 0: Stop detection (STPDET) interrupt is disabled...
Page 503 GD32L23x User Manual Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. PECTRANS PEC Transfer Set by software. Cleared by hardware in the following cases: When PEC byte is transferred or ADDSEND bit is set or STOP condition is detected or I2CEN=0.
Page 504 GD32L23x User Manual the arbitration is lost, or a timeout error occurred, or I2CEN=0, this bit can also be cleared by hardware. It can be cleared by software by setting the ADDSENDC bit in I2C_STATC register. 0: START will not be sent 1: START will be sent HEAD10R 10-bit address header executes read direction only in master receive mode...
Page 505 GD32L23x User Manual ADDRES ADDFOR ADDRES Reserved ADDRESS[9:8] ADDRESS[7:1] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ADDRESSEN I2C address enable 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address...
Page 506 GD32L23x User Manual 1: Second I2C address enable. 14:11 Reserved Must be kept at reset value. 10:8 ADDMSK2[2:0] ADDRESS2[7:1] mask Defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don’t care). 000: No mask, all the bits must be compared. n(001~110): ADDRESS2[n:0] is masked.
Page 507 GD32L23x User Manual = (SCLDELY +1) x t SCLDELY 19:16 SDADELY[3:0] Data hold time A delay t between SCL falling edge and SDA edge can be generated by SDADELY configuring these bits. And during t , the SCL line is stretched low in master SDADELY mode and in slave mode when SS = 0.
Page 508 GD32L23x User Manual TOEN Clock timeout detection enable If the SCL stretch time greater than t when TOIDLE =0 or high for more than TIMEOUT when TOIDLE =1, a timeout error is detected. IDLE 0: SCL timeout detection is disabled 1: SCL timeout detection is enabled 14:13 Reserved...
Page 509 GD32L23x User Manual hardware after a STOP condition. When I2CEN=0, this bit is also cleared by hardware. 0: No I2C communication. 1: I2C communication active. Reserved Must be kept at reset value. SMBALT SMBus Alert When SMBHAEN=1, SMBALTEN=1, and a SMBALERT event (falling edge) is detected on SMBA pin, this bit will be set by hardware.
Page 510 GD32L23x User Manual Transfer complete reload This bit is set by hardware when RELOAD=1 and data of BYTENUM[7:0] bytes have been transferred. It is cleared by software when BYTENUM[7:0] is written to a non- zero value. 0: When RELOAD=1, transfer of BYTENUM[7:0] bytes is not completed 1: When RELOAD=1, transfer of BYTENUM[7:0] bytes is completed Transfer complete in master mode This bit is set by hardware when RELOAD=0, AUTOEND=0 and data of...
Page 511 GD32L23x User Manual 1: I2C_TDATA is empty and the I2C is ready to transmit data I2C_TDATA is empty during transmitting This bit is set by hardware when the I2C_TDATA register is empty. It is cleared when the next data to be sent is written in the I2C_TDATA register. This bit can be set by software in order to empty the I2C_TDATA register.
Page 512 GD32L23x User Manual NACKC Not Acknowledge flag clear Software can clear the NACK bit of I2C_STAT by write 1 to this bit ADDSENDC ADDSEND flag clear Software can clear the ADDSEND bit of I2C_STAT by write 1 to this bit Reserved Must be kept at reset value.
Page 513 GD32L23x User Manual 21.4.11. Transmit data register (I2C_TDATA) Address offset: 0x28 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). Reserved Reserved TDATA [7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value 21.4.12.
Page 514 GD32L23x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 22.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 515: Figure 22-1. Block Diagram Of Spi
GD32L23x User Manual  Transmission and reception using DMA. 22.3. SPI block diagram Figure 22-1. Block diagram of SPI SYSCLK MOSI TXBuffer/ TXFIFO MISO RX Buffer/ RXFIFO 22.4. SPI signal description 22.4.1. Normal configuration (Not Quad-SPI Mode) Table 22-1. SPI signal description Pin name Direction Description...
Page 516: Table 22-2. Quad-Spi Signal Description
GD32L23x User Manual Pin name Direction Description Slave in hardware NSS mode: NSS input, as a chip select signal for slave. 22.4.2. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0).
Page 517: Figure 22-2. Spi0 Timing Diagram In Normal Mode
GD32L23x User Manual Figure 22-2. SPI0 timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI LF=1 DZ=0 MISO In SPI1 normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. Data length is 16 bits if FF16=1, otherwise is 8 bits.
Page 518: Figure 22-4. Spi0 Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32L23x User Manual Figure 22-4. SPI0 timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample D[4] D[0] D[4] D[0] MOSI D[5] D[1] D[5] D[1] MISO D[6] D[2] D[6] D[2] D[7] D[3] D[7] D[3] In SPI0 normal mode, the length of data is configured by the DZ bits in the SPI_CTL1 register. It can be set from 4-bit up to 16-bit length and the setting applies for both transmission and reception, and the read access to the FIFO must be aligned with the BYTEN bit setting in the SPI_CTL1 register.
Page 519 GD32L23x User Manual A write access to the SPI_DATA register stores the written data in the end of TXFIFO, while a read access to the SPI_DATA returns the oldest value in RXFIFO which has not been read. Write access of a data frame to be transmitted is managed by the TBE event. This event is triggered when the TXFIFO level is less than or equal to half of its capacity, and at the time the TXFIFO is considered as empty .
Page 520: Table 22-3. Spi Operation Modes
GD32L23x User Manual Master mode In master mode (MSTMOD=1) if the application uses multi-master connection, NSS can be configured to hardware input mode (SWNSSEN=0, NSSDRV=0) or software mode (SWNSSEN=1). Then, once the NSS pin (in hardware NSS mode) or the SWNSS bit (in software NSS mode) goes low, the SPI automatically enters slave mode and triggers a master fault flag CONFERR.
Page 521: Figure 22-6. A Typical Full-Duplex Connection
GD32L23x User Manual Mode Description Register configuration Data pin usage unidirectional connection RO = 0 MISO: Transmission BDEN = 0 BDOEN: Don’t care MSTMOD = 0 Slave reception with RO = 1 MOSI: Reception unidirectional connection BDEN = 0 MISO: Not used BDOEN: Don’t care MSTMOD = 0 Slave transmission with...
Page 522: Figure 22-8. A Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
GD32L23x User Manual Figure 22-8. A typical simplex connection (Master: Transmit only, Slave: Receive) Master MTU Slave SRU MISO MISO MOSI MOSI Figure 22-9. A typical bidirectional connection Initialization sequence SPI0: Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise,...
Page 523 GD32L23x User Manual 11. Enable the SPI (set the SPIEN bit). SPI1: Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 524: Figure 22-10. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32L23x User Manual SPI operation sequence in different modes (Not Quad-SPI, TI mode or NSSP mode) In full-duplex mode, either MFD or SFD, the RBNE and TBE flags should be monitored and then follow the sequences described above. The transmission mode (MTU, MTB, STU or STB) is similar to the transmission sequence of full-duplex mode regardless of the RBNE and OVRE bits.
Page 525: Figure 22-12. Timing Diagram Of Ti Slave Mode
GD32L23x User Manual In master TI mode, SPI can perform continuous or non-continuous transfer. If the master writes SPI_DATA register fast enough, the transfer is continuous, otherwise non-continuous. In non-continuous transfer there is an extra header clock cycle before each byte. While in continuous transfer, the extra header clock cycle only exists before the first byte and the following bytes’...
Page 526: Figure 22-13. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32L23x User Manual Figure 22-13. Timing diagram of NSS pulse with continuous transmit MOSI MISO Don t Care Don t Care Don t Care 1 SCK Quad-SPI mode operation sequence The Quad-SPI mode is designed to control Quad-SPI flash. In order to enter Quad-SPI mode, the software should first verify that the TBE bit is set and TRANS bit is cleared, then set QMOD bit in SPI_QCTL register.
Page 527: Figure 22-14. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32L23x User Manual Figure 22-14. Timing diagram of quad write operation in Quad-SPI mode Software Write Hadware Sets TBE again SPI_DATA MOSI D1[4] D1[0] D2[4] D2[0] MISO D1[5] D1[1] D2[5] D2[1] D1[6] D1[2] D2[6] D2[2] D1[7] D1[3] D2[7] D2[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 528: Figure 22-15. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32L23x User Manual Figure 22-15. Timing diagram of quad read operation in Quad-SPI mode Software Writes Hadware Sets TBE SPI_DATA Software Writes SPI_DATA Software Reads SPI_DATA RBNE MOSI D1[4] D1[0] D2[4] D2[0] MISO D1[5] D1[1] D2[5] D2[1] D1[6] D1[2] D2[6] D2[2] D1[7] D1[3]...
Page 529 GD32L23x User Manual confirm the TRANS=0 and read data until RXLVL[1:0]=00. For SPI1, after getting the second last RBNE flag, read out this data and delay for a SCK clock time and then, disable the SPI by clearing SPIEN bit. Wait until the last RBNE flag is set and read out the last data.
Page 530 GD32L23x User Manual If data packing mode is used and the number of data to transfer is not a multiple of 2, the TXDMA_ODD/RXDMA_ODD bits must be set. Then SPI will consider only one data for the transmission or reception to serve the last DMA transfer. 22.5.6.
Page 531 GD32L23x User Manual the SPI_DATA register.  Receive buffer/RXFIFO not empty flag (RBNE) For SPI0, this bit is set depending on the BYTEN bit in the SPI_CTL1: If BYTEN = 0, the RBNE is set when the RXFIFO level is greater or equal to 1/2(16-bit). If BYTEN = 1, the RBNE is set when the RXFIFO level is greater or equal to 1/4(8-bit).
Page 532: Figure 22-16. Block Diagram Of I2S
GD32L23x User Manual Table 22-4. SPI interrupt requests Interrupt Flag Description Clear method enable bit Transmit buffer/TXFIFO Write SPI_DATA register. TBEIE empty Receive buffer/RXFIFO not RBNE Read SPI_DATA register. RBNEIE empty Read or write SPI_STAT register, CONFERR Configuration fault error then write SPI_CTL0 register.
Page 533 GD32L23x User Manual 22.8. I2S signal description There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
Page 534: Figure 22-17. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32L23x User Manual Figure 22-17. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD Figure 22-18. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 535: Figure 22-22. I2S Phillips Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32L23x User Manual Figure 22-22. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 8-bit 0 24-bit data I2S_SD When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 536: Figure 22-26. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32L23x User Manual Figure 22-26. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD Figure 22-27. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 537: Figure 22-32. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32L23x User Manual Figure 22-32. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit 0 16-bit data I2S_SD LSB justified standard For LSB justified standard, I2S_WS and I2S_SD are updated on the falling edge of I2S_CK. In the case that the channel length is equal to the data length, LSB justified standard and MSB justified standard are exactly the same.
Page 538: Figure 22-36. Lsb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32L23x User Manual Figure 22-36. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame.
Page 539: Figure 22-38. Pcm Standard Short Frame Synchronization Mode Timing Diagram
GD32L23x User Manual (DTLEN=10, CHLEN=1, CKPL=1) Figure 22-41. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 22-42. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2 24-bit data 8-bit 0 Figure 22-43.
Page 540: Figure 22-46. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32L23x User Manual (DTLEN=00, CHLEN=0, CKPL=0) Figure 22-46. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 22-47. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 frame 2 13 bits 32 bits Figure 22-48.
Page 541: Figure 22-51. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32L23x User Manual Figure 22-51. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16-bit data 16-bit 0 I2S_SD Figure 22-52. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK...
Page 542: Table 22-6. Audio Sampling Frequency Calculation Formulas
GD32L23x User Manual So, in order to get the desired audio sampling frequency, the clock generator needs to be configured according to the formulas listed in Table 22-6. Audio sampling frequency calculation formulas. Table 22-6. Audio sampling frequency calculation formulas MCKOEN CHLEN Formula...
Page 543 GD32L23x User Manual  Step 3: Configure the I2SSEL bit, the I2SSTD [1:0] bits, the PCMSMOD bit, the I2SOPMOD [1:0] bits, the DTLEN [1:0] bits, and the CHLEN bit in the SPI_I2SCTL register to define the I2S feature.  Step 4: Configure the TBEIE bit, the RBNEIE bit, the ERRIE bit, the DMATEN bit, and the DMAREN bit in the SPI_CTL1 register, in order to select the potential interrupt sources and the DMA capabilities.
Page 544 GD32L23x User Manual necessary to disable and then enable I2S before resuming the communication. For all standards except PCM, the I2SCH flag is used to distinguish the channel side which the received data belongs to. The I2SCH flag is refreshed at the moment when the RBNE flag goes high.
Page 545 GD32L23x User Manual between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication. The reception sequence begins when the external master sends the clock and when the I2S_WS signal indicates a start of the data transfer. In slave mode, I2SCH is sensitive to the I2S_WS signal coming from the external master.
Page 546: Table 22-8. I2S Interrupt
GD32L23x User Manual This situation occurs when the transmit buffer is empty when the valid SCK signal starts in slave transmission mode.  Reception overrun error flag (RXORERR) This situation occurs when the receive buffer is full and a newly incoming data has been completely received.
Page 547 GD32L23x User Manual 22.11. Register definition SPI0 base address: 0x4001 3000 SPI1/ I2S1 base address: 0x4000 3800 22.11.1. Control register 0 (SPI_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode.
Page 548 GD32L23x User Manual received. FF16 Data frame format (for SPI1) 0: 8-bit data frame format 1: 16-bit data frame format CRCL CRC length (only for SPI0) 0: 8-bit crc length. 1: 16-bit crc length. Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN...
Page 549 GD32L23x User Manual MSTMOD Master mode enable 0: Slave mode 1: Master mode CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle. 1: CLK pin is pulled high when SPI is idle. CKPH Clock phase selection 0: Capture the first data at the first clock transition.
Page 550 GD32L23x User Manual This bit is used to indicate the access size to FIFO, and set the threshold of the RXFIFO that generate RBNE. 0: Half-word access, and RBNE is generated when RXLVL >= 2. 1: Byte access, and RBNE is generated when RXLVL >= 1. 11:8 DZ[3:0] Date size (only for SPI0)
Page 551 GD32L23x User Manual DMAREN Receive buffer / RXFIFO DMA enable 0: Receive buffer / RXFIFO DMA is disabled. 1: Receive buffer / RXFIFO DMA is enabled, when the RBNE bit in SPI_STAT is set, it will be a DMA request on corresponding DMA channel. 22.11.3.
Page 552 GD32L23x User Manual TRANS Transmitting ongoing bit 0: SPI is idle. 1: SPI is currently transmitting and/or receiving a frame. This bit is set and cleared by hardware. RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register.
Page 553 GD32L23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register. For SPI0, the hardware has two FIFOs, including TXFIFO and RXFIFO. The SPI_DATA register serves as an interface between the Rx and Tx FIFOs. Write data to SPI_DATA will save the data to TXFIFO and read data from SPI_DATA will get the data from RXFIFO.
Page 554 GD32L23x User Manual Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the received bytes and saves them in RCRC register. For SPI1, if the data frame format is set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the value in RCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in RCRC[15:0].
Page 555 GD32L23x User Manual saves the value in TCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC[15:0]. For SPI0, CRC function is valid only when the data length is 8 bits or 16 bits. And if the CRC length is set to 8-bit and the data size is equal to 8-bit, the CRC calculation is based on CRC8 standard, and saves the value in TCRC[7:0].
Page 556 GD32L23x User Manual This bit is not used in SPI mode. PCMSMOD PCM frame synchronization mode 0: Short frame synchronization 1: long frame synchronization This bit has a meaning only when PCM standard is used. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode.
Page 557 GD32L23x User Manual Reserved Reserved MCKOEN DIV[7:0] Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: I2S_MCK output is disabled. 1: I2S_MCK output is enabled. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode.
Page 558 GD32L23x User Manual 1: IO2 and IO3 are driven to high in single wire mode. This bit is only available in SPI0. Quad-SPI mode read select. 0: SPI is in quad wire write mode. 1: SPI is in quad wire read mode. This bit should be only be configured when SPI is not busy (TRANS bit cleared) This bit is only available in SPI0.
Page 559 GD32L23x User Manual Cryptographic Acceleration Unit (CAU) 23.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ...
Page 560: Figure 23-1. Datam No Swapping And Half-Word Swapping
GD32L23x User Manual and OFB modes  8*32-bit input and output FIFO  Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping  Data can be transferred by DMA, CPU during interrupts, or without both of them 23.3.
Page 561: Figure 23-2. Datam Byte Swapping And Bit Swapping
GD32L23x User Manual Figure 23-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping 23.3.2. Initialization vectors The initialization vectors are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes to XOR with data blocks.
Page 562 GD32L23x User Manual Figure 23-3. CAU diagram CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_CTL CAU_STAT0 DMAEN INTEN INTF STAT1 KEY0..3 IV0..1 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Config 8*32 8*32 Data swapping Data swapping Cryptographic acceleration core (DES/TDES/AES) 23.4.1.
Page 563: Figure 23-4. Des/Tdes Ecb Encryption
GD32L23x User Manual DES/TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1. The output is fed back directly to next DEA and then decrypted using KEY2. After that, the output is fed back directly to the last DEA and encrypted with KEY3.
Page 564: Figure 23-5. Des/Tdes Ecb Decryption
GD32L23x User Manual Figure 23-5. DES/TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES/TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors.
Page 565: Figure 23-6. Des/Tdes Cbc Encryption
GD32L23x User Manual Figure 23-6. DES/TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES/TDES CBC decryption In DES/TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3.
Page 566: Figure 23-7. Des/Tdes Cbc Decryption
GD32L23x User Manual Figure 23-7. DES/TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext 23.4.2. AES cryptographic acceleration processor The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce.
Page 567: Figure 23-8. Aes Ecb Encryption
GD32L23x User Manual Figure 23-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption.
Page 568: Figure 23-9. Aes Ecb Decryption
GD32L23x User Manual Figure 23-9. AES ECB decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt SWAP CAU_DO Plaintext AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the AEA and encrypted using the 128-, 192-, 256-bit key.
Page 569: Figure 23-10. Aes Cbc Encryption
GD32L23x User Manual Figure 23-10. AES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0..1(H/L) CAU_KEY0..3 AEA, encrypt SWAP CAU_DO Ciphertext AES-CBC mode decryption Similar to that in AES-ECB mode decryption, the key derivation also must be completed first to prepare the decryption keys, the input of the key schedule should be the same to that used in encryption.
Page 570: Figure 23-11. Aes Cbc Decryption
GD32L23x User Manual Figure 23-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) SWAP CAU_DO Plaintext AES-CTR mode In counter mode, a counter is used in addition with a nonce value to be encrypted and decrypted in AEA, and the result will be used for the XOR operation with the plaintext or the ciphertext.
Page 571 GD32L23x User Manual Figure 23-13. AES CTR encryption/decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext CAU_DO Plaintext AES-GCM mode The AES Galois/counter mode (GCM) can be used to encrypt or authenticate message, and then ciphertext and tag can be obtained. This algorithm is based on AES CTR mode to ensure confidentiality.
Page 572 GD32L23x User Manual Repeat (h) until all AAD data are supplied, wait until BUSY bit is cleared. 3. GCM encryption/decryption phase This phase must be performed after GCM AAD phase. In this phase, the message is authenticated and encrypted/decrypted. Configure GCM_CCMPH[1:0] bits to ‘10’. (k) Configure the computation direction in CAUDIR.
Page 573 GD32L23x User Manual 1. CCM prepare phase In this phase, B0 packet (the first packet) is programmed into the CAU_DI register. CAU_DO never contain data in this phase. (a) Clear the CAUEN bit to make sure CAU is disabled. (b) Configure the ALGM[3:0] bits to ‘1001’. (c) Configure GCM_CCMPH[1:0] bits to ‘00’.
Page 574 GD32L23x User Manual (q) Wait until the ONE flag is set to 1, and then read CAU_DO 4 times. The output corresponds to the authentication tag. (r) Disable the CAU AES-CFB mode The Cipher Feedback (CFB) mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and vice versa.
Page 575 GD32L23x User Manual Decryption 1. Disable the CAU by resetting the CAUEN bit in the CAU_CTL register. 2. Enable CAU power domain by setting the CORE1WAKE bit in the PMU_CTL1 register, and then enable CAU clock. 3. Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen.
Page 576 GD32L23x User Manual word is read from the CAU. DMA channel for output data has a higher priority than that channel for input data so that the output FIFO can be empty earlier than that the input FIFO is full. 23.7.
Page 577 GD32L23x User Manual chaining mode, the initialization vectors should also be stored. When it is GCM, GMAC or CCM mode, the context switch CAU_GCMCCMCTXSx (x=0..7) and CAU_GCMCTXSx (x=0..7) registers should also be stored. 5. Configure and process the new data block. 6.
Page 578 GD32L23x User Manual 23.9. Register definition CAU base address: 0x5006 0000 23.9.1. Control register (CAU_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved NBPILB[3:0] ALGM[3] Reserved GCM_CCMPH[1:0] CAUEN FFLUSH Reserved KEYM[1:0] DATAM[1:0] ALGM[2:0] CAUDIR...
Page 579 GD32L23x User Manual Reading this bit always returns 0 13:10 Reserved Must be kept at reset value. KEYM[1:0] AES key size mode configuration, must be configured when BUSY=0 00: 128-bit key length 01: 192-bit key length 10: 256-bit key length 11: never use DATAM[1:0] Data swapping type mode configuration, must be configured when BUSY=0...
Page 580 GD32L23x User Manual Reserved Must be kept at reset value. 23.9.2. Status register 0 (CAU_STAT0) Address offset: 0x04 Reset value: 0x0000 0003 This register has to be accessed by word (32-bit) Reserved Reserved BUSY Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing.
Page 581 GD32L23x User Manual The data input register is used to transfer plaintext or ciphertext blocks into the input FIFO for processing. The MSB is firstly written into the FIFO and the LSB is the last one. If the CAUEN is 0 and the input FIFO is not empty, when it is read, then the first data in the FIFO is popped out and returned.
Page 582 GD32L23x User Manual 23.9.5. DMA enable register (CAU_DMAEN) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved DMAOEN DMAIEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DMAOEN DMA output enable 0: DMA for OUT FIFO data is disabled 1: DMA for OUT FIFO data is enabled...
Page 583 GD32L23x User Manual IINTEN IN FIFO interrupt enable 0: IN FIFO interrupt is disable 1: IN FIFO interrupt is enable 23.9.7. Status register 1 (CAU_STAT1) Address offset: 0x18 Reset value: 0x0000 0001 This register has to be accessed by word (32-bit) Reserved Reserved OSTA...
Page 584 GD32L23x User Manual 31:2 Reserved Must be kept at reset value. OINTF OUT FIFO enabled interrupt flag 0: OUT FIFO Interrupt not pending 1: OUT FIFO Interrupt pending IINTF IN FIFO enabled interrupt flag 0: IN FIFO Interrupt not pending 1: IN FIFO Interrupt pending when CAUEN is 1 23.9.9.
Page 585 GD32L23x User Manual CAU_KEY0L Address offset: 0x24 Reset value: 0x0000 0000 KEY0L[31:16] KEY0L[15:0] CAU_KEY1H Address offset: 0x28 Reset value: 0x0000 0000 KEY1H[31:16] KEY1H[15:0] CAU_KEY1L Address offset: 0x2C Reset value: 0x0000 0000 KEY1L[31:16] KEY1L[15:0] CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0]...
Page 586 GD32L23x User Manual CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 KEY2L[31:16] KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 KEY3H[31:16] KEY3H[15:0] CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000 KEY3L[31:16] KEY3L[15:0] Bits Fields Descriptions 31:0 KEY0...3(H/L) The key for DES, TDES, AES 23.9.10.
Page 587 GD32L23x User Manual In DES/TDES mode, IV0H is the leftmost bits, and IV0L is the rightmost bits of the initialization vectors. In AES mode, IV0H is the leftmost bits, and IV1L is the rightmost bits of the initialization vectors. CAU_IV0H Address offset: 0x40 Reset value: 0x0000 0000 IV0H[31:16]...
Page 588 GD32L23x User Manual IV1L[15:0] Bits Fields Descriptions 31:0 IV0...1(H/L) The initialization vector for DES, TDES, AES 23.9.11. GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x=0..7) Address offset: 0x50 to 0x6C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) CTXx[31:16] CTXx[15:0] Bits...
Page 589 GD32L23x User Manual 31:0 CTXx[31:0] The internal status of the CAU core. Read and save the register data when a high- priority task is coming to be processed, and restore the saved data back to the registers to resume the suspended processing. Note: These registers are used only when GCM or GMAC mode is selected.
Page 590: Figure 24-1. Precision Reference Connection
GD32L23x User Manual VREF 24.1. Overview A precision internal reference circuit is inside. The precision internal reference is used to provide reference voltage for ADC/DAC, or used by off-chip circuit connecting to V pin. 24.2. Characteristics The precision internal reference features are described as follows: ...
Page 591: Table 24-1 Vref Modes
GD32L23x User Manual Table 24-1 VREF MODES VREFEN HIPM Mode VREF disabled – pin pulled-down to V External voltage reference mode: – VREF disabled – pin floating Internal voltage reference mode: – VREF enabled – pin connected to VREF output Hold mode: –...
Page 592 GD32L23x User Manual Reserved Must be kept at reset value. HIPM High impedance mode 0: V is internally connected to the VREF output REF+ 1: V pin is high impedance REF+ VREFEN VREF enable 0: VREF is disabled 1: VREF is enabled 24.4.2.
Page 593 GD32L23x User Manual Segment LCD controller (SLCD) 25.1. Overview The SLCD controller directly drives LCD displays by creating the AC segment and common voltage signals automatically. It can drive the monochrome passive liquid crystal display (LCD) which composed of a plurality of segments (pixels or complete symbols) that can be converted to visible or invisible.
Page 594: Figure 25-1. Slcd Block Diagram
GD32L23x User Manual Figure 25-1. SLCD Block Diagram COM0...7 control signal ANALOG matrix SEG0...31 The SLCD REG is the register of SLCD controller, which configured by APB bus, and generate interrupt to CPU. It includes SLCD_CTL, SLCD_CFG, SLCD_STAT, SLCD_STATC, SLCD_DATAx registers. The Clock generator generates SLCD clock from input clock.
Page 595: Figure 25-2. 1/3 Bias, 1/4 Duty
GD32L23x User Manual Note: The DUTY is the number defined as 1/ (the number of common terminals on a given SLCD display). The SOF bit in SLCD_STAT register is set by the hardware at the start of the frame, and the SLCD interrupt is executed if the SOFIE bit in SLCD_CFG is set.
Page 596: Table 25-1. The Odd Frame Voltage
GD32L23x User Manual Table 25-1. The odd frame voltage BIAS Static 1/2 bias 1/3 bias 1/4 bias VSLCD VSLCD VSLCD VSLCD COM active COM inactive 1/2 VSLCD 1/3 VSLCD 1/4 VSLCD SEG active SEG inactive VSLCD VSLCD 2/3 VSLCD 1/2 VSLCD Table 25-2.
Page 597: Figure 25-3. 1/4 Bias, 1/6 Duty
GD32L23x User Manual Figure 25-3. 1/4 Bias, 1/6 Duty VSLCD 3/4VSLCD COM0 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM2 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM3 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM5 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD SEG2 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD SEG4 1/2VSLCD 1/4VSLCD DEAD time: The dead time is using DTD bits in SLCD_CFG register.
Page 598 GD32L23x User Manual 25.3.5. Double buffer memory The double buffer memory is used to ensure the coherency of the displayed information. The application access the first buffer according to modify the SLCD_DATAx registers. After writing the displayed information into the SLCD_DATAx registers, the application need to set the UPRF bit in SLCD_STAT register, then the hardware will transfer the data from the first buffer to the seconed buffer, during this time, the UPRF keeps set and the SLCD_DATAx registers are write protected.
Page 599 GD32L23x User Manual switched on depend on the PULSE[2:0] bits in the SLCD_CFG register. The R can be always switched on according to setting the HDEN bit in the SLCD_CFG register. Enhance mode: The SLCD module integrates an optional voltage output driver, which can enter the enhanced mode by enabling the VODEN bit of the SLCD_CTL register.
Page 600 GD32L23x User Manual 25.4. Register definition SLCD base address: 0x4000 2400 25.4.1. Control register (SLCD_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved VODEN COMS BIAS[1:0] DUTY[2:0] VSRC SLCDON Bits Fields Descriptions 31:9 Reserved...
Page 601 GD32L23x User Manual 010: 1/3 duty 011: 1/4 duty 100: 1/8 duty 101: 1/6 duty 110: Reserved 111: Reserved VSRC SLCD Voltage source Set this bit determines which is the SLCD voltage source. 0: Internal source 1: External source (VSLCD pin) SLCDON SLCD controller start Set this bit by software to start SLCD controller.
Page 602 GD32L23x User Manual 0001: f SLCD 0010: f SLCD 1111: f SLCD 17:16 BLKMOD[1:0] Blink mode 00: No Blink 01: Blink on SEG[0], COM[0] (1 pixel) 10: Blink on SEG[0], all COMs (up to 8 pixels depending on the programmed duty) 11: Blink on all SEGs and all COMs (all pixels) 15:13 BLKDIV[2:0]...
Page 603 GD32L23x User Manual 001: 1/f 010: 2/f 011: 3/f 100: 4/f 101: 5/f 110: 6/f 111: 7/f UPDIE SLCD update done interrupt enable This bit is set and cleared by software. 0: SLCD Update Done interrupt disabled 1: SLCD Update Done interrupt enabled Reserved Must be kept at reset value.
Page 604 GD32L23x User Manual cleared by hardware when writing to the SLCD_CFG register. 0: SLCD_CFG Register not yet synchronized 1: SLCD_CFG Register synchronized to SLCD clock domain VRDYF SLCD voltage ready flag This bit is set and cleared by the hardware according to the SLCD voltage. 0: SLCD voltage Is not ready 1: Step-up converter is enabled and ready to provide the correct voltage UPDF...
Page 605 GD32L23x User Manual Reserved UPDC Reserved SOFC Reserved rc_w1 rc_w1 Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. UPDC SLCD data update done clear bit Set this bit to clear the UPDF flag in SLCD_STAT register. 0: No effect 1: Clear UPDF flag Reserved Must be kept at reset value.
Page 606 GD32L23x User Manual Comparator (CMP) 26.1. Overview The general purpose comparators, CMP0 and CMP1, can work either standalone or together with the timers. It could be used to wake up the MCU from low-power mode by an analog signal, provide a trigger source when an analog signal is in a certain condition, achieves some current control by working together with a PWM output of a timer and the DAC.
Page 607: Figure 26-1. Cmp Block Diagram Of Gd32L23X Series
GD32L23x User Manual Figure 26-1. CMP block diagram of GD32L23x series CMP0_IP:PA1 CMP0_IP CMP0_OUT GPIO CMP0 CMP0_IM4:PA0 to EXTI DAC_OUT CMP0_IM to TIMER& REFINT *3/4 LPTIMER REFINT REFINT REFINT MSEL PSEL WINDOW_MODE CMP1_IP0:PA3 CMP1_IP1:PB4 CMP1_IP2:PB5 CMP1_IP CMP1_IP3:PB6 CMP1_OUT CMP1_IP4:PB7 GPIO CMP1 to EXTI CMP1_IM...
Page 608: Table 26-1 Cmp Inputs And Outputs Summary
GD32L23x User Manual mechanism is used to exit from power saving modes. Table 26-1 CMP inputs and outputs summary CMP0 CMP1 CMP non inverting PA3 / PB4 / PB5 inputs connected / PB6 / PB7 to I/Os CMP inverting PA2 / PB3 inputs connected to I/Os REFINT...
Page 609: Figure 26-2. Cmp Hysteresis
GD32L23x User Manual Figure 26-2. CMP hysteresis CMP_IP CMP_IM+V hyst CMP_IM CMP_IM-V hyst CMP_OUT 26.3.6. CMP output blanking To avoid the short current spikes on the start moment of PWM period, a timer output compare signal is selected as blanking source by software. The complementary of the blanking signal is ANDed with the comparator output, so as to output the comparator expected result.
Page 610 GD32L23x User Manual 26.3.7. CMP register write protection The CMP control and status register (CMPx_CS) can be protected from writing by setting LK bit to 1. The CMPx_CS register, including the LK bit will be read-only, and can only be reset by the MCU reset.
Page 611 GD32L23x User Manual 26.4. CMP registers CMP base address: 0x4001 7C00 26.4.1. Comparator 0 Control / Status register (CMP0_CS) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved BLK[2:0] HST1:0] OSEL[1:0] Reserved MSEL[2:0] PM[1:0]...
Page 612 GD32L23x User Manual 000: No blanking 001: TIMER1 OC1 selected as blanking source 010: TIMER2 OC1 selected as blanking source 100: TIMER8 OC1 selected as blanking source 101: TIMER11 OC1 selected as blanking source All other values: reserved 17:16 HST[1:0] CMP0 hysteresis These bits are used to control the hysteresis level.
Page 613 GD32L23x User Manual 26.4.2. Comparator 1 Control / Status register (CMP1_CS) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved BLK[2:0] HST1:0] OSEL[1:0] Reserved PSEL[2:0] Reserved MSEL[2:0] PM[1:0] Bits Fields Descriptions CMP1 lock bit This bit could set all control bits of CMP1 as read-only.
Page 614 GD32L23x User Manual 101: TIMER11 OC1 selected as blanking source All other values: reserved 17:16 HST[1:0] CMP1 hysteresis These bits are used to control the hysteresis level. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Polarity of CMP1 output This bit is used to select the CMP1 output.
Page 615 GD32L23x User Manual 11: low speed / low power Windows mode enable bit 0: Input plus of Comparator 1 is not connected to Comparator 0 1: Input plus of Comparator 1 is connected with input plus of Comparator 0 CMP1 enable. 0: disable CMP1 1: enable CMP1...
Page 616: Figure 27-1. Usbd Block Diagram
GD32L23x User Manual Universal Serial Bus full-speed device interface (USBD) 27.1. Overview The Universal Serial Bus full-speed device interface (USBD) module provides a device solution for implementing a USB 2.0 full-speed compliant peripheral. It contains a full-speed internal USB PHY and no more external PHY chip is needed. USBD supports all the four types of transfer (control, bulk, interrupt and isochronous) defined in USB 2.0 protocol.
Page 617: Table 27-1. Usbd Signal Description
GD32L23x User Manual 27.4. Signal description Table 27-1. USBD signal description I/O port Type Description VBUS Input Bus power port Input/Output Differential data line - port Input/Output Differential data line + port Note: As soon as the USBD is enabled, these pins are connected to the USBD internal transceiver automatically.
Page 618 GD32L23x User Manual Endpoint buffer The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. To efficiently manage USB endpoint communications, USBD implements a dedicated data packet buffer of 512-bytes SRAM memory accessed directly by the USB peripheral.
Page 619: Figure 27-2. An Example With Buffer Descriptor Table Usage (Usbd_Baddr = 0)
GD32L23x User Manual Figure 27-2. An example with buffer descriptor table usage (USBD_BADDR = 0) offset 0x1FF IN endpoint 1 double buffer 0 IN endpoint 1 double buffer 1 Endpoint 0 reception buffer Endpoint 0 transmission buffer COUNT1_TX1 ADDR1_TX1 COUNT1_TX0 Endpoint 1 buffer descriptor (double buffer) ADDR1_TX0 COUNT0_RX...
Page 620: Table 27-2. Double-Buffering Buffer Flag Definition
GD32L23x User Manual Table 27-2. Double-buffering buffer flag definition Buffer flag Tx endpoint Rx endpoint TX_DTG (USBD_EPxCS bit 6) RX_DTG (USBD_EPxCS bit 14) SW_BUF USBD_EPxCS bit 14 USBD_EPxCS bit 6 The DTG bit and the SW_BUF bit are responsible for the flow control. When a transfer completes, the USB peripheral toggle the DTG bit;...
Page 621 GD32L23x User Manual After the transaction process is completed, an endpoint-specific interrupt is generated. In the interrupt routine, the application can process it accordingly. Transaction formatting is performed by the hardware, including CRC generation and checking. Once the endpoint is enabled, endpoint control and status register, buffer address and COUNT filed should not be modified by the application software.
Page 622 GD32L23x User Manual length of data is greater than actually allocated length, the excess data are not copied. This is a buffer overrun situation. A STALL handshake is sent, and this transaction fails. If an addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the ACK, according to the endpoint status and no data is written to the endpoint data buffers.
Page 623 GD32L23x User Manual Isochronous transfers Isochronous transfers can guarantee constant data rate and bounded latency, but do not support data retransmission in response to errors on the bus. A receiver can determine that a transmission error occurred. The low-level USB protocol does not allow handshakes to be returned to the transmitter of an isochronous pipe.
Page 624 GD32L23x User Manual When this event occurs, the USB peripheral status is the same as the moment system reset. The USB firmware should do as follows:  Set USBEN bit in AR register to enable USB module in 10ms.  Initialize the USBD_EP0CS register and its related packet buffers.
Page 625 GD32L23x User Manual NVIC table. An interrupt will be generated when both the interrupt status bit and the corresponding interrupt enable bit are set. The interrupt status bit is set by hardware if the interrupt condition occurs (irrespective of the interrupt enable bit). ...
Page 626 GD32L23x User Manual is a Tx endpoint, clear the TX_DTG and RX_DTG bit in USBD_EPxCS register, or if endpoint is a Rx endpoint, it needs to toggle TX_DTG bit. 2) Program USBD_EPxTBCNT and USBD_EPxRBCNT register to set transfer data bit count.
Page 627 GD32L23x User Manual 27.7. Registers definition USBD base address: 0x4000 5C00 27.7.1. USBD control register (USBD_CTL) Address offset: 0x40 Reset value: 0x0003 This register can be accessed by half-word (16-bit) or word (32-bit) L1RSRE STIE PMOUIE ERRIE WKUPIE SPSIE RSTIE SOFIE ESOFIE L1REQIE Reserved...
Page 628 GD32L23x User Manual 1: Interrupt generated when ESOFIF bit in USBD_INTF register is set. L1REQIE LPM L1 state request interrupt enable 0: LPM L1 state request interrupt disabled 1: Interrupt generated when L1REQ bit in USBD_INTF register is set. Reserved Must be kept at reset value.
Page 629 GD32L23x User Manual STIF PMOUIF ERRIF WKUPIF SPSIF RSTIF SOFIF ESOFIF L1REQ Reserved EPNUM[3:0] rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions STIF Successful transfer interrupt flag This bit set by hardware when a successful transaction completes PMOUIF Packet memory overrun/underrun interrupt flag This bit set by hardware to indicate that the packet memory is inadequate to hold...
Page 630 GD32L23x User Manual 27.7.3. USBD status register (USBD_STAT) Address offset: 0x48 Reset value: 0x0XXX where X is undefined This register can be accessed by half-word (16-bit) or word (32-bit) RX_DP RX_DM LOCK SOFLN[1:0] FCNT[10:0] Bits Fields Descriptions RX_DP Receive data + line status Represent the status on the DP line RX_DM Receive data - line status...
Page 631 GD32L23x User Manual USBDAR[6:0] USBD device address After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR 27.7.5. USBD buffer address register (USBD_BADDR) Address offset: 0x50 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) BAR[12:0]...
Page 632: Table 27-4. Reception Status Encoding
GD32L23x User Manual Toggle by writing 1 by software Remain unchanged by writing 0 Refer to the table below SETUP Setup transaction completed Set by hardware when a SETUP transaction completed. 10:9 EP_CTL[1:0] Endpoint type control Refer to the table below EP_KCTL Endpoint kind control The exact meaning depends on the endpoint type...
Page 633: Table 27-7. Transmission Status Encoding
GD32L23x User Manual Table 27-7. Transmission status encoding TX_STA[1:0] Meaning DISABLED: ignore all transmission requests of this endpoint STALL: STALL handshake status NAK: NAK handshake status VALID: enable endpoint for transmission 27.7.7. USBD endpoint transmission buffer address register (USBD_EPxTBADDR), x can be in [0..7] Address offset: [USBD_BADDR] + x * 16 USB local address: [USBD_BADDR] + x * 8 This register can be accessed by half-word (16-bit) or word (32-bit)
Page 634 GD32L23x User Manual 27.7.9. USBD endpoint reception buffer address register (USBD_EPxRBADDR), x can be in [0..7] Address offset: [USBD_BADDR] + x * 16 + 8 USB local Address: [USB_BADDR] + x * 8 + 4 This register can be accessed by half-word (16-bit) or word (32-bit) EPRBAR[ EPRBAR[15:1] Bits...
Page 635 GD32L23x User Manual 27.7.11. USBD LPM control and status register (USBD_LPMCS) Address offset: 0x54 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CHIRD Reserved RHIRD BLSTAT[3:0] REMWK Reserved LPMACK LPMEN Bits Fields Descriptions 31:20 Reserved Must be kept at reset value.
Page 636 GD32L23x User Manual Reserved DPUEN Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. DPUEN DP pull-up control. 0:Disable the embedded pull-up on the DP line, disconnect to host. 1:Enable the embedded pull-up on the DP line, connect to host. 14:0 Reserved Must be kept at reset value...
Page 637: Table 28-1. List Of Abbreviations Used In Register
GD32L23x User Manual Document appendix 28.1. List of abbreviations used in registers Table 28-1. List of abbreviations used in register abbreviations for Descriptions registers read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit.
Page 638: Table 29-1. Revision History
GD32L23x User Manual Revision history Table 29-1. Revision history Revision No. Description Date Initial Release Oct. 21, 2021...
Page 639 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.