GigaDevice Semiconductor GD32H75E User Manual

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GigaDevice Semiconductor Inc.

GD32H75E

Arm

Cortex

-M7 32-bit MCU

User Manual

Revision 1.0

(Nov. 2024)

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Summary of Contents for GigaDevice Semiconductor GD32H75E

Page 1 GigaDevice Semiconductor Inc. GD32H75E ® Cortex -M7 32-bit MCU ® User Manual Revision 1.0 (Nov. 2024)
Page 2: Table Of Contents
GD32H75E User Manual Table of Contents Table of Contents ......................2 List of Figures ......................29 List of Tables ........................ 41 1. System and memory architecture ................ 46 1.1. ® Cortex ® -M7 processor ..................46 1.2. System architecture ....................47 1.2.1.
Page 3 GD32H75E User Manual 1.8.18. SRAM configuration register 0 (SYSCFG_SRAMCFG0) ............. 86 1.8.19. SRAM configuration register 1 (SYSCFG_SRAMCFG1) ............. 86 1.8.20. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=0, 7) ........87 1.8.21. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=0, 7) ........89 1.8.22.
Page 4 GD32H75E User Manual 2.3.3. RAMECCMU monitor x status register (RAMECCMU_MxSTAT) ........117 2.3.4. RAMECCMU monitor x failing address register (RAMECCMU_MxFADDR) ...... 118 2.3.5. RAMECCMU monitor x failing data low register (RAMECCMU_MxFDL) ......119 2.3.6. RAMECCMU monitor x failing data high register (RAMECCMU_MxFDH) ......119 2.3.7.
Page 5 GD32H75E User Manual 3.4.18. Option byte status register 1 (FMC_OBSTAT1_MDF) ............160 3.4.19. NO-RTDEC area register (FMC_NODEC) ................. 161 3.4.20. AES IV register (FMC_AESIVx_EFT) (x = 0…2) ..............161 3.4.21. AES IV register (FMC_AESIVx_MDF) (x = 0…2) ............... 162 3.4.22.
Page 6 GD32H75E User Manual 6. Reset and clock unit (RCU) ................. 206 6.1. Reset control unit (RCTL) ..................206 6.1.1. Overview ..........................206 6.1.2. Function overview ....................... 206 6.2. Clock control unit (CCTL) ..................207 6.2.1. Overview ..........................207 6.2.2. Characteristics ........................210 6.2.3.
Page 7 GD32H75E User Manual 6.3.35. Clock configuration register 2 (RCU_CFG2) ..............274 6.3.36. Clock configuration register 3 (RCU_CFG3) ..............276 6.3.37. PLL all configuration register (RCU_PLLALL) ..............277 6.3.38. PLL0 fraction configuration register (RCU_PLL0FRA) ............279 6.3.39. PLL1 fraction configuration register (RCU_PLL1FRA) ............279 6.3.40.
Page 8 GD32H75E User Manual 8.6.4. Falling edge trigger enable register 0 (EXTI_FTEN0) ............315 8.6.5. Software interrupt event register 0 (EXTI_SWIEV0) ............315 8.6.6. Pending register 0 (EXTI_PD0) ..................316 8.6.7. Interrupt enable register 1 (EXTI_INTEN1) ................ 316 8.6.8. Event enable register 1 (EXTI_EVEN1) ................317 8.6.9.
Page 9 GD32H75E User Manual 9.5.27. Trigger selection for TIMER3_ETI register (TRIGSEL_TIMER3ETI) ......... 348 9.5.28. Trigger selection for TIMER4_ETI register (TRIGSEL_TIMER4ETI) ......... 349 9.5.29. Trigger selection for TIMER7_ETI register (TRIGSEL_TIMER7ETI) ......... 349 9.5.30. Trigger selection for TIMER22_ETI register (TRIGSEL_TIMER22ETI) ......350 9.5.31.
Page 10 GD32H75E User Manual 10.4.4. Port pull-up/down register (GPIOx_PUD, x=A…H) ............377 10.4.5. Port input status register (GPIOx_ISTAT, x=A…H) ............. 379 10.4.6. Port output control register (GPIOx_OCTL, x=A…H) ............379 10.4.7. Port bit operate register (GPIOx_BOP, x=A...H) ..............380 10.4.8. Port configuration lock register (GPIOx_LOCK, x=A...H) ........... 380 10.4.9.
Page 11 GD32H75E User Manual Trigonometric Math Unit (TMU) ............... 405 Overview ....................... 405 13.1. Characteristics ..................... 405 13.2. 13.3. Block diagram ...................... 405 13.4. Function overview ....................406 13.4.1. Data format and configuration .................... 406 13.4.2. Mode configuration ......................407 13.4.3.
Page 12 GD32H75E User Manual 14.5.7. Channel x peripheral base address register (DMA_CHxPADDR) ........448 14.5.8. Channel x memory 0 base address register (DMA_CHxM0ADDR) ........449 14.5.9. Channel x memory 1 base address register (DMA_CHxM1ADDR) ........449 14.5.10. Channel x FIFO control register (DMA_CHxFCTL) ............450 Master direct memory access controller (MDMA) ..........
Page 13 GD32H75E User Manual 16.6. Register definition ....................494 16.6.1. Request multiplexer channel x configuration register (DMAMUX_RM_CHxCFG) ..... 494 16.6.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) ....... 495 16.6.3. Request multiplexer channel interrupt flag clear register (DMAMUX_RM_INTC) ....495 16.6.4.
Page 14 GD32H75E User Manual 18.4.11. DMA request ........................521 18.4.12. Overflow detection ......................521 18.4.13. ADC internal channels ......................522 18.4.14. Battery voltage monitoring ....................523 18.4.15. Using HPDF to managing the conversion results ............... 523 18.4.16. Programmable resolution (DRES) ..................524 18.4.17.
Page 15 GD32H75E User Manual 19.1. Overview ....................... 556 19.2. Characteristics ..................... 556 19.3. Function description .................... 558 19.3.1. DAC enable ......................... 558 19.3.2. DAC output buffer ....................... 558 19.3.3. DAC data configuration ....................... 558 19.3.4. DAC trigger ......................... 558 19.3.5. DAC conversion ........................558 19.3.6.
Page 16 GD32H75E User Manual 20.2. Window watchdog timer (WWDGT) ..............586 20.2.1. Overview ..........................586 20.2.2. Characteristics ........................586 20.2.3. Function overview ....................... 586 20.2.4. Register definition ....................... 589 Real time clock (RTC) ..................591 21.1. Overview ....................... 591 21.2. Characteristics ..................... 591 21.3.
Page 17 GD32H75E User Manual 21.4.15. High resolution frequency compensation register (RTC_HRFC) ........617 21.4.16. Tamper register (RTC_TAMP) .................... 618 21.4.17. Alarm 0 sub second register (RTC_ALRM0SS) ..............620 21.4.18. Alarm 1 sub second register (RTC_ALRM1SS) ..............621 21.4.19. Configuration register (RTC_CFG) ..................622 21.4.20.
Page 18 GD32H75E User Manual 23.3. Function overview ....................917 23.3.1. USART frame format ......................917 23.3.2. Baud rate generation ......................918 23.3.3. USART transmitter ......................919 23.3.4. USART receiver ........................920 23.3.5. Use DMA for data buffer access ..................921 23.3.6.
Page 19 GD32H75E User Manual 24.3.8. I2C master mode ........................ 973 24.3.9. SMBus support ........................978 24.3.10. SMBus mode ........................981 24.3.11. Wakeup from power saving mode ..................982 24.3.12. Use DMA for data transfer ....................983 24.3.13. I2C error and interrupts ....................... 983 24.3.14.
Page 20 GD32H75E User Manual 25.4.5. RxFIFO and TxFIFO ......................1032 25.4.6. Operation .......................... 1033 25.4.7. DMA function........................1035 25.4.8. I2S interrupts........................1035 25.5. Register definition ....................1038 25.5.1. Control register 0 (SPI_CTL0) ..................1038 25.5.2. Control register 1 (SPI_CTL1) ..................1040 25.5.3.
Page 21 GD32H75E User Manual 27.5. OSPI configuration ..................... 1068 27.5.1. OSPI system configuration ....................1068 27.5.2. OSPI device configuration ....................1069 27.5.3. OSPI regular commamd configuration ................1069 27.6. Data sampling shift .................... 1070 27.7. Busy ........................1070 27.8. Error management ..................... 1070 27.9.
Page 22 GD32H75E User Manual 28.3.5. External device address mapping..................1095 28.3.6. NOR/PSRAM controller ....................1099 28.3.7. NAND flash controller ......................1119 28.3.8. SDRAM controller ......................1123 28.4. Register definition ....................1135 28.4.1. NOR/PSRAM controller registers ..................1135 28.4.2. NAND flash controller registers ..................1140 28.4.3.
Page 23 GD32H75E User Manual 31.1. Overview ......................1170 31.2. Characteristics ....................1170 31.3. Function overview ....................1170 31.4. Z-phase output mode ..................1171 31.5. Operation guidance ..................... 1172 31.5.1. EDOUT initialization ......................1172 31.5.2. EDOUT update processing ....................1173 31.5.3. EDOUT working example ....................1173 31.6.
Page 24 GD32H75E User Manual 32.5.9. Control register 2 (CAN_CTL2) ..................1230 32.5.10. CRC for classical frame register (CAN_CRCC) ............... 1232 32.5.11. Receive FIFO public filter register (CAN_RFIFOPUBF) ........... 1233 32.5.12. Receive FIFO identifier filter matching number register (CAN_RFIFOIFMN) ....1234 32.5.13. Bit timing register (CAN_BT) .................... 1234 32.5.14.
Page 25 GD32H75E User Manual 33.3.9. CMP interrupt ........................1253 33.4. Register definition ....................1254 33.4.1. CMP status register (CMP_STAT) ..................1254 33.4.2. CMP interrupt flag clear register (CMP_IFC) ..............1255 33.4.3. CMP alternate select register (CMP_SR) ................. 1255 33.4.4. CMP0 control/status register (CMP0_CS) ................ 1256 33.4.5.
Page 26 GD32H75E User Manual 35.3.9. FIR filters ........................... 1313 35.3.10. IIR filters ..........................1315 35.4. Register definition ....................1317 35.4.1. FAC X0 buffer configure register (FAC_X0BCFG) ............1317 35.4.2. FAC X1 buffer configure register (FAC_X1BCFG) ............1317 35.4.3. FAC Y buffer configure register (FAC_YBCFG) ..............1318 35.4.4.
Page 27 GD32H75E User Manual 37.1.9. ESC core controller register definition ................1427 37.1.10. System configuration controller (ESC_SYSCFG)............. 1434 37.1.11. System configuration register definition ................1434 37.2. Power management unit (PMU) ................. 1437 37.2.1. Overview ........................... 1437 37.2.2. Characteristics ........................1437 37.2.3.
Page 28 GD32H75E User Manual 38.2. List of terms......................1629 38.3. Available peripherals ..................1630 Revision history ....................1631...
Page 29: List Of Figures
-M7 processor ............47 ® Figure 1-1. The structure of the Cortex Figure 1-2. The system architecture of GD32H75E devices ........... 49 Figure 1-3. Bus matrix Region 0 ....................50 Figure 1-4. Bus matrix Region 1 ....................51 Figure 1-5. Bus matrix Region 2 ....................51 Figure 1-6.
Page 30 GD32H75E User Manual Figure 10-1. Basic structure of a standard I/O port bit ............364 Figure 10-2. Input configuration ....................365 Figure 10-3. Output configuration ................... 366 Figure 10-4. Analog configuration ..................366 Figure 10-5. Alternate function configuration ................ 367 Figure 10-6.
Page 31 GD32H75E User Manual Figure 18-15. ADC sync block diagram .................. 528 Figure 18-16. Routine parallel mode on 16 channels ............528 Figure 18-17. Routine follow-up mode on 1 channel in continuous operation mode ..529 Figure 19-1. DAC block diagram ..................... 557 Figure 19-2.
Page 32 GD32H75E User Manual Figure 22-32. BRKINx (x=0...2) pins logic with BREAK0 function ........655 Figure 22-33. Example of counter operation in decoder interface mode ......656 Figure 22-34. Example of decoder interface mode with CI0FE0 polarity inverted .... 656 Figure 22-35. Quadrature decoder signal disconnection detection block diagram ..657 Figure 22-36.
Page 33 GD32H75E User Manual Figure 22-72. Example of decoder interface mode with CI0FE0 polarity inverted .... 757 Figure 22-73. Quadrature decoder signal disconnection detection block diagram ..758 Figure 22-74. Example of counter operation in non-quadrature decoder mode 0 with CH1P=0 ..........................758 Figure 22-75.
Page 34 GD32H75E User Manual Figure 22-112. Timing diagram of up counting mode, PSC=0/2 .......... 862 Figure 22-113. Timing diagram of up counting mode, change TIMERx_CAR on the go .. 863 Figure 22-114. Repetition timechart for up-counter .............. 864 Figure 22-115. Input capture logic for channel 0 ..............865 Figure 22-116.
Page 35 GD32H75E User Manual Figure 24-6. I2C communication flow with 7-bit address (Master Receive) ....... 963 Figure 24-7. I2C communication flow with 10-bit address (Master Receive when HEAD10R=0) ............................. 963 Figure 24-8. I2C communication flow with 10-bit address (Master Receive when HEAD10R=1) ........................
Page 36 GD32H75E User Manual ............................1025 Figure 25-22. I2S Philips standard timing diagram (DTLEN = 10, CHLEN = 1, CKPL = 0) ............................1025 Figure 25-23. I2S Philips standard timing diagram (DTLEN = 10, CHLEN = 1, CKPL = 1) ............................1025 Figure 25-24.
Page 37 GD32H75E User Manual 10, CHLEN = 1, CKPL = 1) ....................1029 Figure 25-44. PCM standard short frame synchronization mode timing diagram (DTLEN = 01, CHLEN = 1, CKPL = 0) ....................1029 Figure 25-45. PCM standard short frame synchronization mode timing diagram (DTLEN = 01, CHLEN = 1, CKPL = 1) ....................
Page 38 GD32H75E User Manual Figure 28-14. Mode C read access ..................1109 Figure 28-15. Mode C write access ..................1109 Figure 28-16. Mode D read access ..................1111 Figure 28-17. Mode D write access ..................1111 Figure 28-18. Multiplex mode read access ................1112 Figure 28-19.
Page 39 GD32H75E User Manual Figure 35-2 Input buffer area ....................1306 Figure 35-3 Circular input buffer area ................... 1307 Figure 35-4 Circular input buffer operation ................. 1308 Figure 35-5 Circular output buffer ..................1308 Figure 35-6 Circular output buffer area ................1309 Figure 35-7 The structure of FIR filter function ..............
Page 40 GD32H75E User Manual Figure 37-29. OSPI WRITE ...................... 1497 Figure 37-30. SPI DUAL DATA WRITE ................... 1498 Figure 37-31. SPI QUAD DATA WRITE .................. 1500 Figure 37-32. SPI DUAL ADDRESS / DATA WRITE .............. 1501 Figure 37-33. SPI QUAD ADDRESS / DATA WRITE.............. 1502 Figure 37-34.PHY functional block diagram ................
Page 41: List Of Tables
Table 2-1. RAMECC monitor x unit for Region 0 (x=0..4) ............115 Table 2-2. RAMECC monitor x unit for Region 1 (x=0..2) ............115 Table 3-1. GD32H75E base address and size for flash memory .......... 122 Table 3-2. Option byte ....................... 131 Table 3-3.
Page 42 GD32H75E User Manual Table 13-10. Mode 6 description ....................413 Table 13-11. Mode 7 description ....................414 Table 13-12. Mode 8 description ....................415 Table 13-13. Recommended scaling factors in mode 8 ............415 Table 13-14. Mode 9 description ....................415 Table 13-15.
Page 43 GD32H75E User Manual Table 22-4. Complementary outputs controlled by parameters (MCHxMSEL =2’b11) ..649 Table 22-5. Output behavior of the channel in response to a BREAK0 and BREAK1 (the break input is high active) ....................653 Table 22-6. Break function input pins locked/ released conditions ........654 Table 22-7.
Page 44 GD32H75E User Manual Table 28-3. NOR flash interface signals description ............1099 Table 28-4. PSRAM non-muxed signal description .............. 1100 Table 28-5. EXMC bank 0 supports all transactions ............1100 Table 28-6. NOR / PSRAM controller timing parameters ............. 1102 Table 28-7.
Page 45 GD32H75E User Manual Table 34-7. Relationship between the maximum output resolution and IOR, SFOR, SFO of the integrator ........................1278 Table 34-8. Features of threshold monitor working mode ..........1278 Table 34-9. Maximum output rate ..................1282 Table 34-10. HPDF interrupt event ..................1283 Table 35-1 IEEE 32-Bit Single Precision Floating-Point Format ........
Page 46: System And Memory Architecture
GD32H75E User Manual System and memory architecture The devices of GD32H75E series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M7 processor. The Arm Cortex -M7 processor includes 64-bit AMBA4 AXI, 32-bit AHB peripheral (AHBP) port, 32-bit AHB slave port for external master to access memories and APB interface for CoreSight debug components.
Page 47: System Architecture
GD32H75E User Manual  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrumentation Trace Macrocell (ITM)  Embedded Trace Macrocell (ETM)  JTAG or SWD Debug Port  Trace Port Interface Unit (TPIU) ...
Page 48: Table 1-1. The Interconnection Relationship Of The Interconnect Matrix
APB1 APB2 APB3 APB4 EXMC OSPI The system architecture of GD32H75E devices is shown in Figure 1-2. The system architecture of GD32H75E devices, and the work frequency is related to the voltage of power supply, please refer to the datasheet.
Page 49: Figure 1-2. The System Architecture Of Gd32H75E Devices
GD32H75E User Manual Figure 1-2. The system architecture of GD32H75E devices Powered By LDO (0.9V) TPIU SW/JTA G I-Cache AHBP 32KB D-Cache DTCM 32KB ITCM ARM Cortex-M7 RAM share d Processor AXI SRAM Fmax: 600MHz AXIM Flash Memory Powered By V...
Page 50: Bus Matrix Region 0
GD32H75E User Manual Bus matrix Region 0 1.2.1. The 64-bit AXI bus matrix Region 0 is shown in Figure 1-3. Bus matrix Region Figure 1-3. Bus matrix Region 0 64-bit AXI bus matrix Region 0 Cortex-M7 AHBP to Region 1...
Page 51: Bus Matrix Region 2
GD32H75E User Manual Figure 1-4. Bus matrix Region 1 32-bit AHB bus matrix DMA0 DMA1 USBHS0 USBHS1 Region 1 AHBP to Region 1 AHB Master interface APB Master interface Region 0 to Region 1 Slave interface SRAM0 32-bit 16KB SRAM1...
Page 52: Memory Map
Table 1-2. Memory map of GD32H75E devices shows the memory map of the GD32H75E series devices, including Code, SRAM, peripheral, and other pre-defined regions. Almost each peripheral is allocated 1KB of space. This allows simplifying the address decoding for each peripheral.
Page 53 GD32H75E User Manual Pre-defined Address Peripherals Regions Reserved 0x5800 6C00 - 0x5800 6FFF LPDTS 0x5800 6800 - 0x5800 6BFF 0x5800 5800 - 0x5800 67FF Reserved 0x5800 5400 - 0x5800 57FF Reserved 0x5800 4C00 - 0x5800 53FF FWDGT 0x5800 4800 - 0x5800 4BFF...
Page 54 GD32H75E User Manual Pre-defined Address Peripherals Regions 0x5006 1000 - 0x50FF FFFF Reserved 0x5006 0C00 - 0x5006 0FFF Reserved 0x5006 0800 - 0x5006 0BFF Reserved 0x5006 0400 - 0x5006 07FF Reserved 0x5006 0000 - 0x5006 03FF Reserved 0x5005 0400 - 0x5005 FFFF...
Page 55 GD32H75E User Manual Pre-defined Address Peripherals Regions 0x4003 3000 - 0x4003 7FFF Reserved 0x4003 0000 - 0x4003 2FFF Reserved 0x4002 C000 - 0x4002 FFFF Reserved 0x4002 BC00 - 0x4002 BFFF 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF...
Page 56 GD32H75E User Manual Pre-defined Address Peripherals Regions 0x4001 8000 - 0x4001 83FF Reserved(APB2) 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF HPDF 0x4001 6C00 - 0x4001 6FFF...
Page 57 GD32H75E User Manual Pre-defined Address Peripherals Regions 0x4000 DC00 - 0x4000 DFFF Reserved 0x4000 D800 - 0x4000 DBFF Reserved 0x4000 D400 - 0x4000 D7FF Reserved 0x4000 D000 - 0x4000 D3FF Reserved 0x4000 CC00 - 0x4000 CFFF Reserved 0x4000 C800 - 0x4000 CBFF...
Page 58 GD32H75E User Manual Pre-defined Address Peripherals Regions 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x3880 1000 - 0x3FFF FFFF...
Page 59 GD32H75E User Manual Pre-defined Address Peripherals Regions 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 7400 - 0x1FFF 77FF Reserved 0x1FFF 7000 - 0x1FFF 73FF Reserved 0x1FFF 0000 - 0x1FFF 6FFF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F...
Page 60: On-Chip Sram Memory
On-chip SRAM memory 1.3.1. The devices of GD32H75E series contain up to 512KB of on-chip SRAM (AXI SRAM), 4KB of backup SRAM and up to 512KB RAM shared by ITCM/DTCM/AXI SRAM. All of AHB SRAM support byte, half-word (16 bits), and word (32 bits) accesses. The on-chip SRAM (AXI SRAM) support byte, half-word (16 bits), word (32 bits) and double words (64 bits) accesses.
Page 61: Figure 1-7. Block Digram Of Ram Shared By Itcm/Dtcm/Axi Sram
GD32H75E User Manual 512KB of RAM can be used by ITCM or DTCM or AXI SRAM, which can be configured through ITCM_SZ_SHRRAM and DTCM_SZ_SHRRAM bits in option byte status register 1 register, as described in Table 1-3. Configuration of ITCM/DTCM/AXI SRAM.
Page 62: On-Chip Flash Memory Overview
Refer to Flash Memory Controller (FMC) Chapter for more details. Boot configuration 1.4. The GD32H75E devices provide different boot sources which can be selected by the BOOT ® ® pin and BOOT_ADDR0/1[15:0] in Boot address for Arm Cortex -M7 core register (FMC_BTADDR_MDF).
Page 63: System Configuration Controller (Syscfg)
BootLoader(BOOT Pin = SYSTEM BOOT The embedded bootloader supports multi interfaces to update the Flash memory. There will be USART ports, USBHS ports can be used on GD32H75E line products. The details are shown in the datasheet. System configuration controller (SYSCFG) 1.5.
Page 64: Timer Break Input Lock
GD32H75E User Manual Timer break input lock 1.6. When internal SRAM/FMC ECC error, LVD or CPU core lockup occurs, this function allows to disable TIMER output. Refer to Lockup control register (SYSCFG_LKCTL) for details. AXI interconnect matrix (AXIIM) 1.7. ®...
Page 65: Table 1-6. Configuration Of Asibs
GD32H75E User Manual The configurations of ASIB and AMIB are shown in Table 1-6. Configuration of ASIBs Table 1-7. Configuration of AMIBs. Table 1-6. Configuration of ASIBs ASIB Protocol Bus width Read issuing Write issuing Master interface INI 0 AHB-lite...
Page 66: System Configuration Registers
GD32H75E User Manual System configuration registers 1.8. SYSCFG base address: 0x5800 0400 Peripheral mode configuration register (SYSCFG_PMCFG) 1.8.1. Address offset: 0x004 Reset value: 0x0F00 0000 This register has to be accessed by word (32-bit). PC3SWO PC2SWO PA1SWO PA0SWO Reserved Reserved...
Page 67: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32H75E User Manual 23:8 Reserved Must be kept at reset value. PB9FMPEN I2C Fm+ mode on PB9 pin enable This bit controls I2C Fm+ mode, the speed control of the pin is bypassed. 0: Disable Fm+ mode 1: Enable Fm+ mode...
Page 68 GD32H75E User Manual Reserved EXTI3_SS[3:0] EXTI2_SS[3:0] EXTI1_SS[3:0] EXTI0_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS[3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin 0010: PC3 pin 0011: PD3 pin 0100: PE3 pin...
Page 69: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32H75E User Manual 0100: PE0 pin 0101: PF0 pin 0110: PG0 pin 0111: PH0 pin EXTI sources selection register 1 (SYSCFG_EXTISS1) 1.8.3. Ad Address offset: 0x00C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved...
Page 70: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32H75E User Manual 0011: PD5 pin 0100: PE5 pin 0101: PF5 pin 0110: PG5 pin 0111: PH5 pin EXTI4_SS[3:0] EXTI 4 sources selection 0000: PA4 pin 0001: PB4 pin 0010: PC4 pin 0011: PD4 pin 0100: PE4 pin 0101: PF4 pin...
Page 71: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32H75E User Manual 0010: PC10 pin 0011: PD10 pin 0100: PE10 pin 0101: PF10 pin 0110: PG10 pin 0111: PH10 pin EXTI9_SS[3:0] EXTI 9 sources selection 0000: PA9 pin 0001: PB9 pin 0010: PC9 pin 0011: PD9 pin 0100: PE9 pin...
Page 72: Lockup Control Register (Syscfg_Lkctl)
GD32H75E User Manual 0001: PB15 pin 0010: PC15 pin 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: PG15 pin 0111: PH15 pin 11:8 EXTI14_SS[3:0] EXTI 14 sources selection 0000: PA14 pin 0001: PB14 pin 0010: PC14 pin 0011: PD14 pin...
Page 73 GD32H75E User Manual Reserved AXIRAM_ ITCM_LO DTCM_LO SRAM0_L SRAM1_L BKPRAM_ CPU_LOC LVD_LOC Reserved Reserved Reserved LOCK LOCK Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. AXIRAM_LOCK Region 0 AXI-SRAM ECC double error lock bit This bit is set by software and cleared by a system reset.
Page 74: I/O Compensation Control Register (Syscfg_Cpsctl)
GD32H75E User Manual BKPRAM_LOCK Region 2 backup SRAM ECC double error lockup bit This bit is set by software and cleared by a system reset. 0: Region 2 backup SRAM ECC double error signal is disconnected from the break input of TIMER0/7/14/15/16...
Page 75: I/O Compensation Cell Code Configuration Register (Syscfg_Cpscccfg)
GD32H75E User Manual Setting this bit when V is higher than 2.5V might be destructive. 0: No I/O speed optimization 1: I/O speed optimization 15:9 Reserved Must be kept at reset value. CPS_RDY Compensation cell ready flag This bit provides the status of the compensation cell.
Page 76 GD32H75E User Manual TIMER0_CI3_SEL[3:0] TIMER0_CI2_SEL[3:0] TIMER0_CI1_SEL[3:0] TIMER0_CI0_SEL[3:0] TIMER7_CI3_SEL[3:0] TIMER7_CI2_SEL[3:0] TIMER7_CI1_SEL[3:0] TIMER7_CI0_SEL[3:0] Bits Fields Descriptions 31:28 TIMER0_CI3_SEL[3: Selects TIMER0_CI3 input selection These bits select the TIMER input source. 0000: TIMER0_CH3 input Others: Reserved 27:24 TIMER0_CI2_SEL[3: Selects TIMER0_CI2 input selection These bits select the TIMER input source.
Page 77: Timer Input Selection Register 1 (Syscfg_Timercisel1)
GD32H75E User Manual 0001: CMP1 output Others: Reserved Timer input selection register 1 (SYSCFG_TIMERCISEL1) 1.8.10. Address offset: 0x038 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). TIMER1_CI3_SEL[3:0] TIMER1_CI2_SEL[3:0] TIMER1_CI1_SEL[3:0] TIMER1_CI0_SEL[3:0] TIMER2_CI3_SEL[3:0] TIMER2_CI2_SEL[3:0] TIMER2_CI1_SEL[3:0] TIMER2_CI0_SEL[3:0] Bits...
Page 78: Timer Input Selection Register 2 (Syscfg_Timercisel2)
GD32H75E User Manual These bits select the TIMER input source. 0000: TIMER2_CH2 input Others: Reserved TIMER2_CI1_SEL[3: TIMER2_CI1 input selection These bits select the TIMER input source. 0000: TIMER2_CH1 input Others: Reserved TIMER2_CI0_SEL[3: TIMER2_CI0 input selection These bits select the TIMER input source.
Page 79: Timer Input Selection Register 3 (Syscfg_Timercisel3)
GD32H75E User Manual 19:16 TIMER3_CI0_SEL[3: TIMER3_CI0 input selection These bits select the TIMER input source. 0000: TIMER3_CH0 input Others: Reserved 15:12 TIMER4_CI3_SEL[3: TIMER4_CI3 input selection These bits select the TIMER input source. 0000: TIMER4_CH3 input Others: Reserved 11:8 TIMER4_CI2_SEL[3: TIMER4_CI2 input selection These bits select the TIMER input source.
Page 80: Timer Input Selection Register 5 (Syscfg_Timercisel5)
GD32H75E User Manual Others: Reserved 27:24 TIMER22_CI2_SEL[3 TIMER22_CI2 input selection These bits select the TIMER input source. 0000: TIMER22_CH2 input Others: Reserved 23:20 TIMER22_CI1_SEL[3 TIMER22_CI1 input selection These bits select the TIMER input source. 0000: TIMER22_CH1 input Others: Reserved 19:16...
Page 81 GD32H75E User Manual Bits Fields Descriptions 31:28 TIMER42_CI1_SEL[3 Selects TIMER42_CI1 input These bits select the TIMER input source. 0000: TIMER42_CH1 input 0001: TIMER4_CH1 input 0010: TIMER22_CH1 input 0011: TIMER23_CH1 input Others: Reserved 27:24 TIMER42_CI0_SEL[3 Selects TIMER42_CI0 input These bits select the TIMER input source.
Page 82: Timer Input Selection Register 6 (Syscfg_Timercisel6)
GD32H75E User Manual 0011: TIMER4_CH1 input Others: Reserved 11:8 TIMER40_CI0_SEL[3 Selects TIMER40_CI0 input These bits select the TIMER input source. 0000: TIMER40_CH0 input 0001: TIMER2_CH0 input 0010: TIMER3_CH0 input 0011: TIMER4_CH0 input 0100: LXTAL 0101: LPIRC4M 0110: CKOUT1 Others: Reserved...
Page 83 GD32H75E User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 TIMER44_CI1_SEL[3 Selects TIMER44_CI1 input These bits select the TIMER input source. 0000: TIMER44_CH1 input 0001: TIMER23_CH1 input 0010: Reserved 0011: Reserved Others: Reserved 19:16 TIMER44_CI0_SEL[3 Selects TIMER44_CI0 input These bits select the TIMER input source.
Page 84: Cpu Icache Error Status Register(Syscfg_Cpuicac)
GD32H75E User Manual 0011: CKOUT0 Others: Reserved TIMER15_CI0_SEL[3 Selects TIMER15_CI0 input These bits select the TIMER input source. 0000: TIMER15_CH0 input 0001: IRC32K 0010: LXTAL 0011: WKUP_IT Others: Reserved CPU ICACHE error status register(SYSCFG_CPUICAC) 1.8.15. Address offset: 0x054 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 85: Fpu Interrupt Enable Register (Syscfg_Fpuinten)
GD32H75E User Manual Bits Fields Descriptions 31:28 CPU_DCDET[3:0] The DCACHE error detection information These bits are provided by the CPU to indicate the DCACHE error detection information. 27:6 CPU_DCERR[21:0] The DCACHE error bank information These bits are provided by the CPU to indicate the DCACHE error bank information.
Page 86: Sram Configuration Register 0 (Syscfg_Sramcfg0)
GD32H75E User Manual 0: Invalid operation interrupt disable 1: Invalid operation interrupt enable SRAM configuration register 0 (SYSCFG_SRAMCFG0) 1.8.18. Address offset: 0x64 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SECURE_SRAM_SIZ Reserved E[1:0] Bits...
Page 87: Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=0, 7)
GD32H75E User Manual This bit is used to insert wait-state in ITCM / D0TCM / D1TCM. Note: When the system clock frequency is higher than f , this bit must be set. 0: No wait-state 1: Insert wait-state TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=0, 7) 1.8.20.
Page 88 GD32H75E User Manual 10001: Internal trigger input 12 (ITI12) 10010: Internal trigger input 13 (ITI13) 10011: Internal trigger input 14 (ITI14) Others: Reserved 25:21 TSCFG4[4:0] Pause mode configuration The trigger input enables the counter clock when it is high and disables the counter when it is low when these bits are not 0.
Page 89: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=0, 7)
GD32H75E User Manual 01100: The filtered output of multi mode channel 1 input (MCI1FEM1) 01101: The filtered output of multi mode channel 2 input (MCI2FEM2) 01110: The filtered output of multi mode channel 3 input (MCI3FEM3) 01111: Reserved 10000: Reserved...
Page 90 GD32H75E User Manual 31:21 Reserved Must be kept at reset value. 20:16 TSCFG9[4:0] Non-quadrature decoder mode 1 configuration 00000: Non-quadrature decoder mode 1 disable Others: The CI0 signal is used as the count pulse( with the CH0P is used to select the counter edge) and the CI1 signal is used as the count direction selection.
Page 91: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=0, 7)
GD32H75E User Manual 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2) 00100: Internal trigger input 3 (ITI3) 00101: CI0 edge flag (CI0F_ED) 00110: The filtered output of channel 0 input (CI0FE0)
Page 92: Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=1, 2, 3, 4, 22, 23)
GD32H75E User Manual 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2) 00100: Internal trigger input 3 (ITI3) 00101: CI0 edge flag (CI0F_ED) 00110: Reserved 00111: Reserved 01000: Reserved 01001: Reserved 01010: Reserved 01011: Reserved 01100: Reserved...
Page 93 GD32H75E User Manual Reserved TSCFG2[4:0] TSCFG1[4:0] TSCFG0[4:0] Bits Fields Descriptions Reserved Must be kept at reset value. 30:26 TSCFG5[4:0] Event mode configuration A rising edge of the trigger input enables the counter. 00000: Event mode disable 00001: Internal trigger input 0 (ITI0)
Page 94 GD32H75E User Manual 01011: Reserved 01100: Internal trigger input 7 (ITI7) 01101: Reserved 01110: Internal trigger input 9 (ITI9) 01111: Internal trigger input 10 (ITI10) 10000: Internal trigger input 11 (ITI11) 10001: Internal trigger input 12 (ITI12) 10010: Internal trigger input 13 (ITI13)
Page 95: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=1, 2, 3, 4, 22, 23)
GD32H75E User Manual CI0FE0 level TSCFG0[4:0] Quadrature decoder mode 0 configuration 00000: Quadrature decoder mode 0 disable Others: The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=1, 2, 3, 4, 22, 1.8.24.
Page 96 GD32H75E User Manual that the CI1 signal is low. TSCFG7[4:0] Restart + event mode configuration The counter is reinitialized and started, the shadow registers are updated on the rising edge of the selected trigger input when these bits are not 0.
Page 97: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=1, 2, 3, 4, 22, 23)
GD32H75E User Manual 01111: Internal trigger input 10 (ITI10) 10000: Internal trigger input 11 (ITI11) 10001: Internal trigger input 12 (ITI12) 10010: Internal trigger input 13 (ITI13) 10011: Internal trigger input 14 (ITI14) Others: Reserved TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=1, 2, 3, 4, 22, 1.8.25.
Page 98: Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=14, 40, 41, 42, 43, 44)
GD32H75E User Manual 01010: Internal trigger input 5 (ITI5) 01011: Reserved 01100: Internal trigger input 7 (ITI7) 01101: Reserved 01110: Internal trigger input 9 (ITI9) 01111: Internal trigger input 10 (ITI10) 10000: Internal trigger input 11 (ITI11) 10001: Internal trigger input 12 (ITI12)
Page 99 GD32H75E User Manual 00000: Event mode disable 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2) 00100: Internal trigger input 3 (ITI3) 00101: Reserved 00110: The filtered output of channel 0 input (CI0FE0)
Page 100: Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=14, 40, 41, 42, 43, 44)
GD32H75E User Manual 01001: Reserved 01010: Reserved 01011: The filtered output of multi mode channel 0 input (MCI0FEM0) 10011: Internal trigger input 14 (ITI14) Others: Reserved 15:0 Reserved Must be kept at reset value. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=14, 40, 41, 1.8.27.
Page 101: Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=14, 40, 41, 42, 43, 44)
GD32H75E User Manual 01000: Reserved 01001: Reserved 01010: Reserved 01011: The filtered output of multi mode channel 0 input (MCI0FEM0) 10011: Internal trigger input 14 (ITI14) Others: Reserved TSCFG6[4:0] External clock mode 0 configuration The counter counts on the rising edges of the selected trigger when these bits are not 0.
Page 102: User Configuration Register (Syscfg_Usercfg)
GD32H75E User Manual Reserved Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:16 TSCFG15[4:0] Internal trigger input source configuration 00000: Reserved 00001: Internal trigger input 0 (ITI0) 00010: Internal trigger input 1 (ITI1) 00011: Internal trigger input 2 (ITI2)
Page 103: Axi Interconnect Registers
GD32H75E User Manual These bits indicate the mode of BOOT. 000: BOOT from SRAM (ITCM/DTCM/RAM shared/AXI SRAM) 001: BOOT from Security 010: BOOT_SYS (BootLoader) 011: BOOT_USER (User flash OSPI0/1) Others: Reserved Reserved Must be kept at reset value. BOR_TH[1:0] BOR threshold status bits...
Page 104: Axi Peripheral Id1 Register (Axi_Periph_Id1)
GD32H75E User Manual Reserved Reserved PARTNUM[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PARTNUM[7:0] Part number[7:0] AXI peripheral ID1 register (AXI_PERIPH_ID1) 1.9.3. Address offset: 0x1FE4 Reset value: 0x0000 00B4 This register has to be accessed by word (32-bit).
Page 105: Axi Peripheral Id3 Register (Axi_Periph_Id3)
GD32H75E User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PARTREV[3:0] Part revision JEP106CF JEP106 code flag JEP106ID[6:4] Part number[6:4] AXI peripheral ID3 register (AXI_PERIPH_ID3) 1.9.5. Address offset: 0x1FEC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 106: Axi Componet Id1 Register (Axi_Comp_Id1)
GD32H75E User Manual PREAMB[7:0] Preamble bits AXI componet ID1 register (AXI_COMP_ID1) 1.9.7. Address offset: 0x1FF4 Reset value: 0x0000 00F0 This register has to be accessed by word (32-bit). Reserved Reserved CLASS[3:0] PREAMB[11:8] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 107: Axi Master Port X Bus Matrix Issuing Functionality Control Register (Axi_Mpxbm_Iss_Ctl)
GD32H75E User Manual Reserved Reserved PREAMB[27:20] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PREAMB[27:20] Preamble bits AXI Master Port x bus matrix issuing functionality control register 1.9.10. (AXI_MPxBM_ISS_CTL) Address offset: 0x2008 + 0x1000 * x, where x = 0 to 7 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 108: Axi Master Port X Long Burst Functionality Control Register (Axi_Mpx_Lb_Ctl)
GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved BPDIS Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. BPDIS Beats packing function disable configure 0: Normal operation 1: Disable beats packing function...
Page 109: Axi Slave Port X Functionality Control Register (Axi_Spx_Ctl)
GD32H75E User Manual Reserved WR_ISSO RD_ISSO Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. WR_ISSOV Override AMIB write issuing function 0: Normal issuing function 1: The AMIB write issuing capability is forced set to 1 RD_ISSOV...
Page 110: Axi Slave Port X Read Qos Control Register (Axi_Spx_Rdqos_Ctl)
GD32H75E User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RD_AHB_I WR_AHB_ Reserved SSOV ISSOV Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. RD_AHB_ISSOV Converts AHB-Lite read transaction to single beat AXI transaction function...
Page 111: Axi Slave Port X Write Qos Control Register (Axi_Spx_Wrqos_Ctl)
GD32H75E User Manual AXI Slave Port x write QOS control register (AXI_SPx_WRQOS_CTL) 1.9.17. Address offset: 0x42104 + 0x1000 * x, where x = 0 to 5 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved...
Page 112: Device Electronic Signature
GD32H75E User Manual 1: The ASIB read issuing capability is forced set to 1 Device electronic signature 1.10. The device electronic signature contains memory density information and the 96-bit unique device ID. The 96-bit unique device ID is unique for each device. It can be used as serial numbers, or part of security keys, etc.
Page 113 GD32H75E User Manual 31:0 UNIQUE_ID[31:0] Unique device ID Base address: 0x1FF0 F7EC The value is factory programmed and can never be altered by user. UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FF0 F7F0 The value is factory programmed and can never be altered by user.
Page 114: Ram Ecc Monitor Unit (Rameccmu)
 Identification for RAM failing address/data Function overview 2.2. GD32H75E features two RAMECC monitor units mounted on AHB3 in Region 0 and AHB2 in Region 1 separately. The block architechture of RAMECCMU is shown as Figure 2-1. Block architecture of RAMECCMU.
Page 115: Table 2-1. Ramecc Monitor X Unit For Region 0 (X=0
GD32H75E User Manual Table 2-1. RAMECC monitor x unit for Region 0 (x=0..4) RAMECC monitor RAMECC monitor status number AXI SRAM ECC ITCM-RAM ECC DTCM-RAM ECC(D0TCM) DTCM-RAM ECC(D1TCM) RAM shared(ITCM/DTCM/AXI SRAM) ECC Table 2-2. RAMECC monitor x unit for Region 1 (x=0..2)
Page 116: Register Definition
GD32H75E User Manual Register definition 2.3. RAMECCMU Region 0 base address: 0x5200 9000 RAMECCMU Region 1 base address: 0x4802 3000 RAMECCMU global interruput register (RAMECCMU_INT) 2.3.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 117 GD32H75E User Manual for Region 1) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ECCERRL ECCDER ECCDER ECCSERR Reserved Reserved ATEN RBWIE Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. ECCERRLATEN...
Page 118 GD32H75E User Manual rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. ECCDERRBWDF ECC double error on byte write detected flag This bit is set by hardware and cleared by writing 0. 0: Double error is detected during read when ECCDERRDF is set...
Page 119 GD32H75E User Manual RAMECCMU monitor x failing data low register (RAMECCMU_MxFDL) 2.3.5. Address offset: 0x2C + 0x20 * x, (x= ECC monitoring number, x=0..4 for Region 0, while x=0..2 for Region 1) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 120 GD32H75E User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). ECCFECODE[31:16] ECCFECODE[15:0] Bits Fields Descriptions 31:0 ECCFECODE[31:0] ECC failing error code This register contains the index where the bit error occurs and the ECC code.
Page 121: Flash Memory Controller (Fmc)
GD32H75E User Manual Flash memory controller (FMC) Overview 3.1. The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. It also provides sector erase, mass erase, program operations for flash memory. Characteristics 3.2.  Up to 3840KB of on-chip flash memory for instruction and data.
Page 122: Table 3-1. Gd32H75E Base Address And Size For Flash Memory
The flash memory consists of 3840KB main flash organized into 960 sectors with 4KB and 64KB information block. Each sector can be erased individually. Table 3-1. GD32H75E base address and size for flash memory shows the details of flash organization Table 3-1.
Page 123 GD32H75E User Manual initialization vector AES_IV[127:0] = AESIV[95:0] || 12'b0 || ReadAddress[23:4]. User can modify the high 96 bits of the initial vector (AESIV[95:0]) by modifying the FMC_AESIVx_MDF register. The AESIV[95:0] is formed with [AESIV2, AESIV1,AESIV0]. When the initial vector needs to be modified, user must write the FMC_ASIV0_MDF, FMC_ASIV1_MDF, and FMC_ASIV2_MDF registers in sequence.
Page 124: Sector Erase
GD32H75E User Manual Sector erase 3.3.4. The FMC provides a sector erase function which is used to initialize the contents of a main flash block sector to a high state. Each sector can be erased independently without affecting the contents of other sectors. The following steps show the access sequence of the registers for a sector erase operation.
Page 125: Mass Erase
GD32H75E User Manual Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the SER bit, Write ADDR bits Send the command to FMC by set START bit Is the BUSY bit is 0...
Page 126: Figure 3-3. Process Of Typical Mass Erase Operation
GD32H75E User Manual Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT register. Read and verify the flash memory if required. If mass erase and sector erase is request at the same time, the mass erase operation will replace the sector erase operation.
Page 127: Figure 3-4. Process Of Protection-Removed Mass Erase Operation
GD32H75E User Manual Protection-removed mass erase The FMC provides a protection-removed mass erase function which is used to erase all sectors include sectors contain secure user or protected data. This erase can affect by setting the MER bit to 1 in the FMC_CTL register. The following steps show the protection-removed mass erase register access sequence.
Page 128 GD32H75E User Manual Start Unlock the Is the OBLK bit is 0 FMC_OBCTL Set DCRP_EREN bit, and modify DCRP area start/end address to make Is DCRP area exist DCRP_AREA_END < DCRP_AREA_START Set SCR_EREN bit, and modify secure user Is secure user...
Page 129: Figure 3-5. Proccess Of Program Operation
GD32H75E User Manual Main flash Programming 3.3.6. The FMC provides a 64-bit/32-bit programming function by AXI interface which is used to modify the main flash block contents. The following steps show the register access sequence of the word programming operation.
Page 130: Option Bytes Description
GD32H75E User Manual Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform write Is the BUSY bit is 0 Finish Note: When programming, erasing, especially the mass erasing, abnormal power off or reset should be avoided as far as possible, otherwise unpredictable consequences may occur.
Page 131: Table 3-2. Option Byte
GD32H75E User Manual The option bytes block is reloaded to "_EFT" registers after each system reset, and the option Table 3-2. Option byte.The bytes take effect. The option bytes description is shown in the option bytes are configured according to the requirements of the application.
Page 132 GD32H75E User Manual Launch a system reset to start option bytes loading. Read from FMC_XXX_EFT register and verify the option bytes if required. Note: “XXX” includes OBSTAT0, DCRPADDR, SCRADDR, WP, BTADDR or OBSTAT1. When the operation is executed successfully, the ENDF in FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set.
Page 133 GD32H75E User Manual level low to no protection demotion or a protection-removed mass erase. Otherwise will be preserved. The DCRP_EREN bit can be set without any restriction. The DCRP_EREN bit can be reset only when the SPC level low to no protection demotion or a protection-removed mass erase is requested simultaneously.
Page 134: Table 3-3. Wp Bit For Sectors Protected
GD32H75E User Manual FMC on protected sectors. If the sector erase or program command is sent to the FMC on a protected sector, the WPERR bit in the FMC_STAT register will then be set by the FMC. Note that the WPERR also set when sector erase while MER set or sector address not valid. The sector protection function can be individually enabled by configuring the WP[21:0] bit field to 0 in the option bytes.
Page 135 GD32H75E User Manual No protection When setting SPC[7:0] bits in FMC_OBSTAT0_EFT to 0xAA, no protection performed. The main flash and option bytes block are accessible by all operations. And access to other secured regions is also allowed. Protection level low When SPC_H in EFUSE is 0, as long as setting SPC_L to 1 or SPC[7:0] option bits to any value except 0xAA or 0xCC, protection level low performed.
Page 136: Table 3-4. Spc Protection Level Configuration
GD32H75E User Manual The debug port is always disabled when level high is active. Therefore, it is impossible to debug and analyze the defective parts with level high security protection. If security protection level high is set while the debugger is still connected, apply a power on reset.
Page 137: Table 3-5. Dcrp Area Configuration
GD32H75E User Manual configured by setting the same value to the start and end addresses of the DCRP area. When executing code in this area, the debug events will be ignored. Only CPU can access DCRP area, using only instruction fetch transactions. In all other cases, access to the DCRP area is illegal.
Page 138 GD32H75E User Manual in the product, if configure DCRP area by the option byte, the start and end address of the DCRP area in EFUSE should be both set to 0, and the DCRPLK bit in EFUSE should be set to 1, otherwise there may be vulnerability in the DCRP area.
Page 139: Table 3-6. Secure User Area Configuration
GD32H75E User Manual performed unless erase is performed during the SPC level low to no protection demotion or protection-removed mass erase. Only CPU can modify the secure user area definition bits and SCR_EREN bit. If secure user area is valid ( not empty ), during the SPC level low to no protection demotion, if the...
Page 140: Figure 3-6. Memory Architecture In Standard Mode And Secure Mode
GD32H75E User Manual Secure mode 3.3.12. Security should be performed for some sensitive programs to avoid potentially malware attacks. For example, licensed firmware update software requires highly protection because it processes confidential data ( such as encryption keys ) that cannot get by other processes.
Page 141: Table 3-7. Function Resetandinitializesecureareas
GD32H75E User Manual Standard mode can be returned when the SCR bit in option byte is 1 and the SCR bit in EFUSE is 0. To return to standard mode, the secure area and DCRP area need to be removed before or at the same time as the SCR option bit is cleared.
Page 142: Error Description
GD32H75E User Manual Function name exitSecureArea void exitSecureArea(unsigned int vectors, unsigned int jtagState); Function prototype Function descriptions exit from the secure user area and jump to the user application. Precondition The called functions Input parameter{in} vectors address of application vector to jump after exit secure user area.
Page 143 GD32H75E User Manual is set. The software can clear it by writing 1. Program sequence error (PGSERR) The following operation will set the PGSERR in the FMC_STAT register, and the current program operation is aborted:  When a program operation is requested but the program enable bit (PG) has not been set in FMC_CTL register ...
Page 144: Table 3-9 Fmc Interrupt Requests
GD32H75E User Manual loader mode, access main flash block.  Access secure user area without correct access rights. Access address out of range.  Any wrong sequence to unlock the FMC_CTL or FMC_OBCTL register.  FMC interrupts 3.3.15. The FMC interrupt events and flags are listed in Table 3-9 FMC interrupt requests.
Page 145: Register Definition
GD32H75E User Manual Register definition 3.4. FMC base address: 0x5200 2000 Unlock key register (FMC_KEY) 3.4.1. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL unlock register These bits are only be written by software.
Page 146 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved RSERRIE RPERRIE Reserved PGSERRIE WPERRIE ENDIE Reserved START Reserved PGCHEN Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. RSERRIE Read secure error interrupt enable.
Page 147 GD32H75E User Manual 0: Disable check whether the programming area is all 0xFF before programming. 1: Enable check whether the programming area is all 0xFF before programming. If this bit is set, and the programming area is not all 0xFF, PGSERR flag is set. And the program operation is invalid.
Page 148 GD32H75E User Manual This bit is set by hardware. The software can clear it by writing 1. 0: Disable option byte modify error 1: Enable option byte modify error 29:25 Reserved Must be kept at reset value. RSERR Read secure error flag bit.
Page 149 GD32H75E User Manual ADDR[31:16] ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Flash erase command address bits These bits are configured by software. ADDR bits are the address of flash to be erased. Option byte control register (FMC_OBCTL) 3.4.6. Address offset: 0x18 Reset value: 0x0000 0001 This register has to be accessed by word (32-bit).
Page 150 GD32H75E User Manual Option byte status register 0 (FMC_OBSTAT0_EFT) 3.4.7. Address offset: 0x1C Reset value: 0xXXXX XXXX. Factory value is 0x01C6 AAD0 This register is the effective values of corresponding option bits. Load flash values after reset. This register has to be accessed by word (32-bit).
Page 151 GD32H75E User Manual 0: FWDGT is suspend in system deepsleep mode 1: FWDGT is running in system deepsleep mode. Reserved Must be kept at reset value. 15:8 SPC[7:0] Security protection level option byte status bits 0xAA: No protection 0xCC: Protection level high Any value except 0xAA or 0xCC: Protection level low.
Page 152 GD32H75E User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. IOSPDOPEN Allowed enable configuration bit for I/O speed optimization at low-voltage. 0: Chip operating voltage greater than 2.5V, so I/O speed optimization is not allowed 1: Chip operating voltage is less than 2.5V, so I/O speed optimization is allowed...
Page 153 GD32H75E User Manual 1: No reset when entering deep-sleep mode Reserved Must be kept at reset value. nWDG_HW Watchdog configuration bit 0: Hardware free watchdog 1: Software free watchdog BOR_TH[1:0] BOR threshold configuration bits 00: No BOR function 01: BOR threshold value 1...
Page 154 GD32H75E User Manual 15:11 Reserved Must be kept at reset value. 10:0 DCRP_AREA_STAR DCRP area start address status bits T[10:0] These bits contain the first 4K-byte block of the DCRP area. Start absolute address = DCRP_AREA_START[10:0] * 4096 + 0x0800_0000.
Page 155 GD32H75E User Manual whole main flash block. If DCRP_AREA_END[10:0] < DCRP_AREA_START[10:0], protection is invalid. Secure address register (FMC_SCRADDR_EFT) 3.4.11. Address offset: 0x30 Reset value: 0xXXXX 0XXX. Factory value is 0x0000 00FF This register is the effective values of corresponding option bits. Load flash values after reset This register has to be accessed by word (32-bit).
Page 156 GD32H75E User Manual Reset value: 0xXXXX 0XXX This register is used for modifying values to corresponding option bits. Values after reset is the effective values of the corresponding option bits. This register has to be accessed by word (32-bit). SCR_ER...
Page 157 GD32H75E User Manual Reserved WP[21:16] WP[15:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:0 WP[21:0] Sector erase/program protection option status bit In WP[21], each bit reflects the corresponding 64 sectors to erase/program protection status. 0: Corresponding 64 sectors are erase/program protected.
Page 158 GD32H75E User Manual 0: Set corresponding 64 sectors to erase/program protected. 1: Set corresponding 64 sectors to not erase/program protected. In WP[20:16], each bit can set the corresponding 128 sectors to erase/program protection status. 0: Set corresponding 128 sectors to erase/program protected.
Page 159 GD32H75E User Manual BOOT_ADDR0[15:0] Bits Fields Descriptions 31:16 BOOT_ADDR1[15:0] Boot address 1 configuration bits. Configure the MSB of boot address if the BOOT pin is high. 15:0 BOOT_ADDR0[15:0] Boot address 0 configuration bits. Configure the MSB of the boot address if the BOOT pin is low.
Page 160 GD32H75E User Manual 1000: 128-Kbyte ITCM 1001: 256-Kbyte ITCM 1010: 512-Kbyte ITCM 1011~1111: Reserved Option byte status register 1 (FMC_OBSTAT1_MDF) 3.4.18. Address offset: 0x54 Reset value: 0xXXXX 0XXX. This register is used for modifying values to corresponding option bits. Values after reset is the effective values of the corresponding option bits.
Page 161 GD32H75E User Manual NO-RTDEC area register (FMC_NODEC) 3.4.19. Address offset: 0x60 Reset value: 0x0000 00FF This register has to be accessed by word (32-bit) only when LK is set to 0. Reserved NODEC_AREA_END[10:0] Reserved NODEC_AREA_START[10:0] Bits Fields Descriptions 31:27 Reserved Must be kept at reset value.
Page 162 GD32H75E User Manual AESIV[31:16] AESIV[15:0] Bits Fields Descriptions 31:0 AESIV[31:0] AES initialization vector status value The initialization vector AES_IV[127:0] = AESIV[95:0] || 12'b0 || ReadAddress[23:4]. The 96 bits AESIV[95:0] is formed with [AESIV2, AESIV1, AESIV0]. AES IV register (FMC_AESIVx_MDF) (x = 0…2) 3.4.21.
Page 163 GD32H75E User Manual This register has to be accessed by word (32-bit). PID[31:16] PID[15:0] Bits Fields Descriptions 31:0 PID[31:0] Product reserved ID code register x These bits are read only by software. These bits are unchanged constant after power on. These bits are one time program...
Page 164: Function Overview
GD32H75E User Manual Electronic fuse (EFUSE) Overview 4.1. The EFUSE controller has EFUSE macro that store system parameters. As a non-volatile unit of storage, the bit of EFUSE macro cannot be restored to 0 once it is programmed to 1.
Page 165 GD32H75E User Manual EFUSE adopts the double-bit redundant backup mechanism. The first 512 bits data and the last 512 bits data are backed up with each other to effectively ensure the correctness of the data.When programming the Nth bit of the EFUSE, the EFUSE controller will program both the Nth and (N+512)th bit.
Page 166 GD32H75E User Manual Read operation need a system reset or a EFUSE to load the parameter from EFUSE macro into the register and this newly modified Debug password parameter takes effect only after the system is reset.  AES key parameter:...
Page 167: Table 4-1. System Parameters
GD32H75E User Manual Note: User must continuously write the complete 16 bytes AES key into the EFUSE_AES_KEYx register to ensure that the CRC function can check the contents of all AES key.  User data parameter The register can be read without restriction. After system reset, the register will be restored to the value of parameter which is read out from EFUSE.
Page 168: Read Operation
GD32H75E User Manual Param Width/ Start Program- Read-protected Description eter bytes address protected user verify the For more details, refer to correctness of the written Firmware AES key regi AES key by AES key CRC ster x (EFUSE_AES_KE 0…3) function.
Page 169: Program Operation
GD32H75E User Manual When the read operation is executed successfully, the RDIF in EFUSE_STAT register is set, and an interrupt will be triggered if the RDIE bit in the EFUSE_CTL register is set. Note: EFUSE is very sensitive to current surges which will affect the result of read operation.
Page 170: Table 4-2. Efuse Interrupt Requests
GD32H75E User Manual 16 bytes AES key written to the EFUSE_AES_KEYx register is correct, otherwise the AES key written to the register is wrong. When the AES key stored in EFUSE macro is read out after system reset, the hardware CRC...
Page 171: Figure 4-2 Efuse Interrupt Mapping Diagram
GD32H75E User Manual Figure 4-2 EFUSE interrupt mapping diagram...
Page 172: Register Definition
GD32H75E User Manual Register definition 4.4. EFUSE base address: 0x4002 2800 Control register (EFUSE_CTL) 4.4.1. Address offset: 0x00 Reset value: 0x7E00 0000 This register has to be accessed by word (32-bit). AES_KEY_CRC Reserved PVIE RDIE PGIE IAERRIE MPVEN Reserved EFRW...
Page 173 GD32H75E User Manual 0: Disable the illegal access error interrupt 1: Enable the illegal access error interrupt This bit cannot be modified when the EFSTR bit in EFUSE_CTL register is 1 MPVEN Monitor program voltage function enable 0: Disable monitor program voltage function 1: Enable monitor program voltage function These bits cannot be modified when the EFSTR bit in EFUSE_CTL register is 1.
Page 174 GD32H75E User Manual Status register (EFUSE_STAT) 4.4.3. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved LDO_RDY PVIF RDIF PGIF IAERRIF Bits Fields Descriptions 31:5 Reserved Must be kept at reset value.
Page 175 GD32H75E User Manual Reserved Reserved PVIC RDIC PGIC IAERRIC rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. PVIC Clear bit for program voltage setting error interrupt flag 0: No effect 1: Clear error flag...
Page 176 GD32H75E User Manual 31:24 SCR_AREA_END[7: Secure user area end address bits The factory value of these bits are 0. These bits contain the last 32K-byte block of the secure user area. The secure user area can be defined by EFUSE with a granularity of 32 Kbytes.
Page 177 GD32H75E User Manual 1: JTAG Note: When NDBG[1:0] is selected as no debug function, JTAGNSW bit is invalid and debug function is closed. NDBG[1:0] Debugging permission setting The factory value of these bits are 0. 00: Normal JTAG ( only valid when JTAGNSW bit is 1, otherwise SW debugger is...
Page 178 GD32H75E User Manual 1: Lock EFUSE_DPx register, the register can not be written. When this bit is 1, the JTAGNSW bit is 1, and the NDBG[1:0] bits are 2b'01 or 2b'11, the register can not be read. Otherwise this register can be read.
Page 179 GD32H75E User Manual Refer to Table 3-5. DCRP area configuration for more details. 15:10 MCU_RSV[5:0] MCU reserved data DCRPLK DCRP area address lock bit The factory value of this bit is 0. 0: Unlock the high 16 bits in EFUSE_MCU_RSV register, the bits can be modified.
Page 180 GD32H75E User Manual Used as user data: the register can be read regardless of DPLK bit value. The register can be written only when DPLK bit is 0. But the modified value of register will not be stored in EFUSE macro, unless a EFUSE program operation are executed successfully.
Page 181 GD32H75E User Manual CRC calculation result is generated after writing the EFUSE_AES_KEY3 register (offset address 0x30). User data register x (EFUSE_USER_DATAx) (x = 0…3) 4.4.9. Address offset: 0x34 + 0x4 * x Reset value: 0xXXXX XXXX. Load EFUSE macro values after reset.
Page 182 The power consumption is regarded as one of the most important issues for the devices of GD32H75E series. The Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 183: Figure 5-1. Power Supply Overview
GD32H75E User Manual Function overview 5.3. provides details on the internal configuration of the PMU Figure 5-1. Power supply overview and the relevant power domains. Figure 5-1. Power supply overview VDDSMPS VLXSMPS SMPS VFBSMPS VSSSMPS VBAT Backup Domain VBAK Power Switch 3.3V...
Page 184: Backup Domain
GD32H75E User Manual Backup domain 5.3.1. The Backup domain is powered by the VDD or the battery power source (VBAT) selected by the internal power switch, and the VBAK pin which drives Backup domain, supplies power for RTC unit, LXTAL oscillator, BPOR and BREG, and three BKP PADs, including PC13 to PC15.
Page 185: Figure 5-2. Waveform Of The Backup Domain Voltage Thresholds
GD32H75E User Manual Note: In BKP only mode, V is power-off, and the backup domain is power by VBAT pin. Backup domain voltage thresholds There is an internal power switch, which can select the voltage source of Backup domain V or V .
Page 186: Figure 5-3. Waveform Of The Por / Pdr
GD32H75E User Manual (power off). The POR / PDR circuit is implemented to detect V and generate the power reset signal which resets the whole chip except the Backup domain when the supply voltage is lower than the specified threshold.
Page 187: Figure 5-5. Waveform Of The Lvd Threshold
GD32H75E User Manual Figure 5-4. Waveform of the BOR hyst BOR Reset (Active Low) VDDA domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in PMU_CS, indicates if V is higher or lower than the LVD threshold.
Page 188: Figure 5-6. Waveform Of The Vavd Threshold
GD32H75E User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply VDDA is implemented to achieve better performance of analog circuits. VDDA can be externally connected to VDD through the external filtering circuit that avoids noise on VDDA, and VSSA should be connected to VSS through the specific circuit independently.
Page 189: Figure 5-7. Temperature Thresholds
GD32H75E User Manual Temperature voltage thresholds As will as Backup domain voltage thresholds, The junction temperature can be monitored by comparing it with two threshold levels, TEMP high and TEMP low. TEMPH and TEMPL flags, in the PMU_CTL1, indicate whether the device temperature is higher or lower than the threshold.
Page 190: Figure 5-8. Ldo Supplies For 0.9V Power Domain
GD32H75E User Manual  No configuration power supplies mode After reset, the DVSEN bit is 0b1, the DVSCFG bit is 0b0, and the DVSVC[1:0] bits field is 0b00. At this time, the SMPS step-down stabilizer is on, working in normal mode, working voltage is 1.0V, and SMPS step-down stabilizer can power supplies for LDO;...
Page 191: Figure 5-10. Smps Supplies For Ldo, Ldo Supplies For 0.9V Power Domain
GD32H75E User Manual Figure 5-9. SMPS supplies for 0.9V power domain 0.9V  SMPS power supplies LDO, LDO power supplies V mode: 0.9V The configuration method to enter this mode is that the DVSEN bit is 0b1, DVSCFG bit is 0b0, and the values of DVSVC[1:0] bits are 0b01 / 0b10 / 0b11.
Page 192: Figure 5-11. Smps Supplies For Ldo And External, Ldo Supplies For 0.9V Power Domain
GD32H75E User Manual consumption mode of the system; the BYPASS bit is 0b0, and the 0.9V power domain is not powered through VCORE (external direct power supplies). Figure 5-11. SMPS supplies for shows this power supplies mode. LDO and external, LDO supplies for 0.9V power domain Figure 5-11.
Page 193: Figure 5-13. Bypass
GD32H75E User Manual Figure 5-13. Bypass VDDLDO VDDSMPS SMPS VLXSMPS (off) VSSLDO VFBSMPS (off) VSSSMPS VCORE 0.9V DVSEN LDOEN BYPASS Bypass Table 5-1. supply mode Supply Mode DVSEN DVSCFG LDOEN DVSVC LDOVS BYPASS configuration No configuration power supplies 0b010 mode...
Page 194: Figure 5-14. Waveform Of The Vovd
Power saving modes 5.3.4. After a system reset or a power reset, the GD32H75E MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS[2:0] bits in PMU_CTL3 register.
Page 195: Deep Sleep Mode
GD32H75E User Manual wake up the system. If it is entered by executing a WFE instruction, any wakeup event can wake up the system (If SEVONPEND is 1, any interrupt can wake up the system, refer to Cortex-M7 Technical Reference Manual). The mode offers the lowest wakeup time as no time is wasted in interrupt entry or exit.
Page 196: Table 5-2. Power Saving Mode Summary
GD32H75E User Manual Table 5-2. Power saving mode summary Wakeup Wakeup Mode Description Entry Wakeup status Latency Any interrupt for WFI SLEEPDEEP = Any event (or interrupt normal run Sleep Only CPU clock is off LDO on 0, WFI or WFE...
Page 197: Register Definition
GD32H75E User Manual Register definition 5.4. PMU base address: 0x5800 5800 Control register 0 (PMU_CTL0) 5.4.1. Address offset: 0x00 Reset value: 0x0000 8000 (reset by wakeup from Standby mode) This register can be accessed by word (32-bit). VOVDEN Reserved VAVDVC[1:0]...
Page 198 GD32H75E User Manual 13:9 Reserved Must be kept at reset value. BKPWEN Backup domain write enable bit This bit is set and cleared by software. 0: Disable write access to the registers in backup domain 1: Enable write access to the registers in backup domain After reset, any write access to the registers in Backup domain is ignored.
Page 199 GD32H75E User Manual Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) This register can be accessed by word (32-bit). Reserved VOVDF Reserved VAVDF Reserved WUPEN5 Reserved WUPEN3 Reserved WUPEN1 WUPEN0 Reserved LVDF STBF Bits Fields Descriptions 31:21 Reserved Must be kept at reset value.
Page 200 GD32H75E User Manual 0: Disable WKUP pin1 function 1: Enable WKUP pin1 function If WUPEN1 is set before entering the power saving mode, a rising edge on the WKUP pin1 wakes up the system from the power saving mode. As the WKUP pin1 is active high, the WKUP pin1 is internally configured to input pull down mode.
Page 201 GD32H75E User Manual BKPVS Reserved VBTMEN Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TEMPHF Temperature level monitoring versus high threshold 0: Temperature below high threshold level. 1: Temperature equal or above high threshold level. TEMPLF Temperature level monitoring versus low threshold 0: Temperature above low threshold level.
Page 202 GD32H75E User Manual modes. If BKPVSEN is set, the application must wait till the backup voltage stabilizer ready flag (BKPVSRF) is set. Which indicate that the data written into the SRAM will be maintained in Standby and V modes. 0: Backup voltage stabilizer disabled.
Page 203 GD32H75E User Manual 15:10 Reserved Must be kept at reset value. VCEN VBAT battery charging enable 0: Disable V battery charging 1: Enable V battery charging VCRSEL VBAT battery charging resistor selection 0: 5kOhms resistor is selected for charing V battery.
Page 204 GD32H75E User Manual Reserved LDOVS[2:0] Reserved Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. VOVRF voltage ready bit 0.9V This bit is set by hardware to indicate that the V supply is ready. 0.9V 0: V supply not ready 0.9V...
Page 205 GD32H75E User Manual 31:21 Reserved Must be kept at reset value. When enter Deep-sleep, switch to LPIRC4M / IRC64M (confirmed by 20:16 TSW_IRCCNT[4:0] DSPWUSSEL) clock. Wait the LPIRC4M / IRC64M (confirmed by DSPWUSSEL) counter and then set Deep-sleep mode. The default is 10 clocks.
Page 206: Reset And Clock Unit (Rcu)
Overview 6.1.1. GD32H75E reset control unit includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain. The system reset resets the processor core and peripheral IP components except for the SW-DP controller and the backup domain.
Page 207: Figure 6-1. The System Reset Circuit
GD32H75E User Manual DP controller and the backup domain. A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset). Figure 6-1. The system reset circuit NRST Filter POWER_RSTn min 20 us...
Page 208: Figure 6-2. Clock Tree
GD32H75E User Manual Figure 6-2. Clock tree RTCDIV[5:0] FCLK CK_HXTAL /2 to /63 (free running clock) CK_CST CK_RTC ÷ 8 32.768 KHz (to Cortex-M7 SysTick) LXTAL OSC (to RTC) RTCSRC[1:0] CK_FWDGT CK_DAC 32 KHz 300 MHz max IRC32K ACLK (to FWDGT)
Page 209 GD32H75E User Manual CK_LPIRC4M or CK_PLL0R. (4). The ADCSCK is ADC synchronization clock seclection bits, refer to Sync control register (ADC_SYNCCTL). (5). USBHSx 60M is USBHSx internal PHY 60M input source clock, refer to Internal embedded PHY. (6). TIMER clock frequency, refer to the TIMERSEL bit in the RCU_CFG1 register.
Page 210: Characteristics
GD32H75E User Manual RCU_CFG5 register. The SPI5 / I2S5 supports clock switch dynamically. The OSPI is clocked by the clock of CK_AHB. The LPDTS is clocked by the clock of CK_APB4 or CK_LXTAL. The CAN is clocked by the clock of CK_HXTAL, CK_APB2, CK_APB2 / 2 or CK_IRC64MDIV which defined by CANxSEL bits in RCU_CFG1 register.
Page 211: Function Overview
GD32H75E User Manual Function overview 6.2.3. High speed crystal oscillator (HXTAL) The high speed external crystal oscillator (HXTAL), which has a frequency from 4 to 50 MHz, produces a highly accurate clock source for use as the system clock. A crystal with a specific frequency must be connected and located close to the two HXTAL pins.
Page 212 GD32H75E User Manual clock source selection for the CPU when the device is powered up. If the IRC64MDIV[1:0] bits in RCU_ADDCTL1 register is configured, the CK_IRC64MDIV can output 8, 16, 32, 64MHz clock. The IRC64M oscillator provides a lower cost type clock source as no external components are required.
Page 213: Phase Locked Loop (Pll)
GD32H75E User Manual drives the OSC32IN pin. Internal 32K RC oscillator (IRC32K) The internal RC oscillator has a frequency of about 32 kHz and is a low power clock source for the real time clock circuit or the rree watchdog timer. The IRC32K offers a low cost clock source as no external components are required.
Page 214: System Clock (Ck_Sys) Selection
GD32H75E User Manual The PLL0 can be switched on or off by using the PLL0EN bit in the RCU_CTL Register. The PLL0STB flag in the RCU_CTL register will indicate if the PLL0 clock is stable. An interrupt can be generated if the related interrupt enable bit, PLL0STBIE, in the RCU_INT register, is set as the PLL0 becomes stable.
Page 215: Clock Output Capability
GD32H75E User Manual HXTAL clock monitor (CKM) The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit, CKMEN, in the control register (RCU_CTL). This function should be enabled after the HXTAL start-up delay and disabled when the HXTAL is stopped. Once the HXTAL failure is detected, the HXTAL will be automatically disabled.
Page 216: Table 6-2. Clock Output 1 Source Select
GD32H75E User Manual Clock Source 0 Selection bits Clock Source CK_PER USBHS0 60M USBHS1 60M Table 6-2. Clock output 1 source select Clock Source 1 Selection bits Clock Source CK_SYS CK_PLL1R CK_HXTAL CK_PLL0P CK_LPIRC4M CK_IRC32K CK_PLL2R The CK_OUT0 frequency can be reduced by a configurable binary divider, controlled by the CKOUT0DIV bits, in the clock cnfiguration register (RCU_CFG2).
Page 217: Register Definition
GD32H75E User Manual Register definition 6.3. RCU base address: 0x5802 4400 Control register (RCU_CTL) 6.3.1. Address offset: 0x00 Reset value: 0xC000 8040 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). IRC64MS IRC64ME HXTALB HXTALST HXTALE...
Page 218 GD32H75E User Manual 1: PLL1 is stable PLL1EN PLL1 enable Set and reset by software. Reset by hardware when entering Deep-sleep or Standby mode. 0: PLL1 is switched off 1: PLL1 is switched on PLL0STB PLL0 clock stabilization flag Set by hardware to indicate if the PLL0 output clock is stable and ready for use.
Page 219: Pll0 Register (Rcu_Pll0)
GD32H75E User Manual 1: High speed 4 ~ 50 MHz crystal oscillator enabled 15:7 IRC64MCALIB[8:0] Internal 64MHz RC Oscillator calibration value These bits are load automatically at power on. IRC64MADJ[6:0] Internal 64MHz RC Oscillator clock trim adjust value These bits are set by software. The trimming value is these bits IRC64MADJ[6:0] added to the IRC64MCALIB[8:0] bits.
Page 220 GD32H75E User Manual Reserved Must be kept at reset value. 22:16 PLL0P[6:0] The PLL0P output frequency division factor from PLL0 VCO clock Set and reset by software when the PLL0 is disable. These bits used to generator PLL0P output clock (CK_PLL0P) from PLL0 VCO clock (CK_PLL0VCO). The CK_PLL0P is used to system clock (no more than 600MHz).
Page 221: Clock Configuration Register 0 (Rcu_Cfg0)
GD32H75E User Manual 111111: CK_PLL0SRC / 63 Clock configuration register 0 (RCU_CFG0) 6.3.3. Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). I2C0SEL[1:0] APB3PSC[2:0] APB4PSC[2:0] Reserved RTCDIV[5:0] APB2PSC[2:0] APB1PSC[2:0]...
Page 222 GD32H75E User Manual 000010: CK_HXTAL / 2 000011: CK_HXTAL / 3 … 111111: CK_HXTAL / 63 15:13 APB2PSC[2:0] APB2 prescaler selection Set and reset by software to control the APB2 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected...
Page 223: Clock Interrupt Register (Rcu_Int)
GD32H75E User Manual HXTAL is selected directly or indirectly as the clock source of CK_SYS. 00: Select CK_IRC64MDIV as the CK_SYS source 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_LPIRC4M as the CK_SYS source 11: Select CK_PLL0P as the CK_SYS source Clock interrupt register (RCU_INT) 6.3.4.
Page 224 GD32H75E User Manual Set by hardware when the LPIRC4M clock is stuck. Reset when setting the LPIRC4MSTBIC bit by software. 0: Clock operating normally 1: LPIRC4M clock stuck CKMIC HXTAL clock stuck interrupt clear Write 1 by software to reset the CKMIF flag.
Page 225 GD32H75E User Manual 0: Disable the PLL2 stabilization interrupt 1: Enable the PLL2 stabilization interrupt PLL1STBIE PLL1 stabilization interrupt enable Set and reset by software to enable/disable the PLL1 stabilization interrupt. 0: Disable the PLL1 stabilization interrupt 1: Enable the PLL1 stabilization interrupt...
Page 226: Ahb1 Reset Register (Rcu_Ahb1Rst)
GD32H75E User Manual 0: No PLL1 stabilization interrupt generated 1: PLL1 stabilization interrupt generated PLL0STBIF PLL0 stabilization interrupt flag Set by hardware when the PLL0 is stable and the PLL0STBIE bit is set. Reset when setting the PLL0STBIC bit by software.
Page 227: Ahb2 Reset Register (Rcu_Ahb2Rst)
GD32H75E User Manual USBHS0R Reserved Reserved Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. USBHS1RST USBHS1 reset This bit is set and reset by software. 0: No reset 1: Reset the USBHS1 28:25 Reserved Must be kept at reset value.
Page 228: Ahb3 Reset Register (Rcu_Ahb3Rst)
GD32H75E User Manual Reserved TRNGRS Reserved TMURST Reserved FACRST Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TMURST TMU reset This bit is set and reset by software. 0: No reset 1: Reset the TMU TRNGRST TRNG reset This bit is set and reset by software.
Page 229: Ahb4 Reset Register (Rcu_Ahb4Rst)
GD32H75E User Manual OSPI1RST OSPI1 reset This bit is set and reset by software. 0: No reset 1: Reset the OSPI1 OSPI0RST OSPI0 reset This bit is set and reset by software. 0: No reset 1: Reset the OSPI0 OSPIMRST OSPIM reset This bit is set and reset by software.
Page 230: Apb1 Reset Register (Rcu_Apb1Rst)
GD32H75E User Manual 1: Reset the CRC 13:8 Reserved Must be kept at reset value. PHRST GPIO port H reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port H PGRST GPIO port G reset This bit is set and reset by software.
Page 231 GD32H75E User Manual This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). UART7R UART6R DACHOL UART4R UART3R USART2 USART1 DACRST Reserved I2C3RST I2C2RST I2C1RST I2C0RST Reserved DRST TIMER51 TIMER50 TIMER23 TIMER22 TIMER6R TIMER5R TIMER4R TIMER3R TIMER2R...
Page 232 GD32H75E User Manual 1: Reset the I2C2 I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C1 I2C0RST I2C0 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C0...
Page 233 GD32H75E User Manual 1: Reset the TIMER51 TIMER50RST TIMER50 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER50 Reserved Must be kept at reset value. TIMER23RST TIMER23 reset This bit is set and reset by software.
Page 234: Apb2 Reset Register (Rcu_Apb2Rst)
GD32H75E User Manual APB2 reset register (RCU_APB2RST) 6.3.10. Address offset: 0x24 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). TRIGSEL EDOUTR TIMER44 TIMER43 TIMER42 TIMER41 TIMER40 HPDFRS TIMER16 TIMER15 TIMER14 Reserved...
Page 235 GD32H75E User Manual 1: Reset the TIMER40 24:22 Reserved Must be kept at reset value. SPI5RST SPI5 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI5 SPI4RST SPI4 reset This bit is set and reset by software.
Page 236: Apb3 Reset Register (Rcu_Apb3Rst)
GD32H75E User Manual 0: No reset 1: Reset the all ADC2 ADC1RST ADC1 reset This bit is set and reset by software. 0: No reset 1: Reset the all ADC1 ADC0RST ADC0 reset This bit is set and reset by software.
Page 237: Apb4 Reset Register (Rcu_Apb4Rst)
GD32H75E User Manual WWDGT Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. WWDGTRST WWDGT reset This bit is set and reset by software. 0: No reset 1: Reset the WWDGT Reserved Must be kept at reset value.
Page 238: Ahb1 Enable Register (Rcu_Ahb1En)
GD32H75E User Manual 0: No reset 1: Reset the CMP SYSCFGRST SYSCFG reset This bit is set and reset by software. 0: No reset 1: Reset the SYSCFG AHB1 enable register (RCU_AHB1EN) 6.3.13. Address offset: 0x30 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 239: Ahb2 Enable Register (Rcu_Ahb2En)
GD32H75E User Manual DMA0EN DMA0 clock enable This bit is set and reset by software. 0: Disabled DMA0 clock 1: Enabled DMA0 clock 20:16 Reserved Must be kept at reset value. USBHS0ULPIEN USBHS0 ULPI clock enable This bit is set and reset by software.
Page 240: Ahb3 Enable Register (Rcu_Ahb3En)
GD32H75E User Manual This bit is set and reset by software. 0: Disabled TRNG clock 1: Enabled TRNG clock Reserved Must be kept at reset value. FACEN FAC clock enable This bit is set and reset by software. 0: Disabled FAC clock...
Page 241: Ahb4 Enable Register (Rcu_Ahb4En)
GD32H75E User Manual 1: Enabled OSPI1 clock OSPI0EN OSPI0 clock enable This bit is set and reset by software. 0: Disabled OSPI0 clock 1: Enabled OSPI0 clock OSPIMEN OSPIM clock enable This bit is set and reset by software. 0: Disabled OSPIM clock...
Page 242 GD32H75E User Manual This bit is set and reset by software. 0: Disabled Backup SRAM clock 1: Enabled Backup SRAM clock 12:8 Reserved Must be kept at reset value. PHEN GPIO port H clock enable This bit is set and reset by software.
Page 243: Apb1 Enable Register (Rcu_Apb1En)
GD32H75E User Manual APB1 enable register (RCU_APB1EN) 6.3.17. Address offset: 0x40 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). UART7E UART6E DACHOL UART4E UART3E USART2 USART1 DACEN CTCEN Reserved I2C3EN I2C2EN...
Page 244 GD32H75E User Manual 1: Enabled I2C3 clock I2C2EN I2C2 clock enable This bit is set and reset by software. 0: Disabled I2C2 clock 1: Enabled I2C2 clock I2C1EN I2C1 clock enable This bit is set and reset by software. 0: Disabled I2C1 clock...
Page 245 GD32H75E User Manual 13:12 Reserved Must be kept at reset value. TIMER51EN TIMER51 clock enable This bit is set and reset by software. 0: Disabled TIMER51 clock 1: Enabled TIMER51 clock TIMER50EN TIMER50 clock enable This bit is set and reset by software.
Page 246: Apb2 Enable Register (Rcu_Apb2En)
GD32H75E User Manual TIMER1EN TIMER1 clock enable This bit is set and reset by software. 0: Disabled TIMER1 clock 1: Enabled TIMER1 clock APB2 enable register (RCU_APB2EN) 6.3.18. Address offset: 0x44 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 247 GD32H75E User Manual TIMER41EN TIMER41 clock enable This bit is set and reset by software. 0: Disabled TIMER41 clock 1: Enabled TIMER41 clock TIMER40EN TIMER40 clock enable This bit is set and reset by software. 0: Disabled TIMER40 clock 1: Enabled TIMER40 clock...
Page 248: Apb3 Enable Register (Rcu_Apb3En)
GD32H75E User Manual SPI0EN SPI0 clock enable This bit is set and reset by software. 0: Disabled SPI0 clock 1: Enabled SPI0 clock Reserved Must be kept at reset value. ADC2EN ADC2 clock enable This bit is set and reset by software.
Page 249: Apb4 Enable Register (Rcu_Apb4En)
GD32H75E User Manual Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved WWDGT Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. WWDGTEN WWDGT clock enable This bit is set and reset by software.
Page 250: Ahb1 Sleep Mode Enable Register (Rcu_Ahb1Spen)
GD32H75E User Manual 1: Enabled LPDTS clock VREFEN VREF clock enable This bit is set and reset by software. 0: Disabled VREF clock 1: Enabled VREF clock CMPEN CMP clock enable This bit is set and reset by software. 0: Disabled CMP clock...
Page 251: Ahb2 Sleep Mode Enable Register (Rcu_Ahb2Spen)
GD32H75E User Manual DMAMUXSPEN DMAMUX clock enable when sleep mode This bit is set and reset by software. 0: Disabled DMAMUX clock when sleep mode 1: Enabled DMAMUX clock when sleep mode DMA1SPEN DMA1 clock enable when sleep mode This bit is set and reset by software.
Page 252: Ahb3 Sleep Mode Enable Register (Rcu_Ahb3Spen)
GD32H75E User Manual RAMECC TMUSPE TRNGSP Reserved Reserved FACSPEN Reserved MU1SPEN Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. RAMECCMU1SPEN RAMECCMU1 clock enable when sleep mode This bit is set and reset by software. 0: Disabled RAMECCMU1 clock when sleep mode...
Page 253 GD32H75E User Manual 31:16 Reserved Must be kept at reset value. FMCSPEN FMC clock enable when sleep mode This bit is set and reset by software. 0: Disabled FMC clock when sleep mode 1: Enabled FMC clock when sleep mode...
Page 254: Ahb4 Sleep Mode Enable Register (Rcu_Ahb4Spen)
GD32H75E User Manual AHB4 sleep mode enable register (RCU_AHB4SPEN) 6.3.24. Address offset: 0x5C Reset value: 0x0000 63FF This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved BKPSRAM Reserved CRCSPEN Reserved PHSPEN PGSPEN PFSPEN PESPEN PDSPEN PCSPEN PBSPEN PASPEN...
Page 255: Apb1 Sleep Mode Enable Register (Rcu_Apb1Spen)
GD32H75E User Manual 1: Enabled GPIO port E clock when sleep mode PDSPEN GPIO port D clock enable when sleep mode This bit is set and reset by software. 0: Disabled GPIO port D clock when sleep mode 1: Enabled GPIO port D clock when sleep mode...
Page 256 GD32H75E User Manual 1: Enabled UART6 clock when sleep mode DACSPEN DAC clock enable when sleep mode This bit is set and reset by software. 0: Disabled DAC clock when sleep mode 1: Enabled DAC clock when sleep mode DACHOLDSPEN DAC hold clock enable when sleep mode This bit is set and reset by software.
Page 257 GD32H75E User Manual USART2SPEN USART2 clock enable when sleep mode This bit is set and reset by software. 0: Disabled USART2 clock when sleep mode 1: Enabled USART2 clock when sleep mode USART1SPEN USART1 clock enable when sleep mode This bit is set and reset by software.
Page 258: Apb2 Sleep Mode Enable Register (Rcu_Apb2Spen)
GD32H75E User Manual 1: Enabled TIMER6 clock when sleep mode TIMER5SPEN TIMER5 clock enable when sleep mode This bit is set and reset by software. 0: Disabled TIMER5 clock when sleep mode 1: Enabled TIMER5 clock when sleep mode TIMER4SPEN TIMER4 clock enable when sleep mode This bit is set and reset by software.
Page 259 GD32H75E User Manual 1: Enabled TRIGSEL clock when sleep mode EDOUTSPEN EDOUT clock enable when sleep mode This bit is set and reset by software. 0: Disabled EDOUT clock when sleep mode 1: Enabled EDOUT clock when sleep mode TIMER44SPEN TIMER44 clock enable when sleep mode This bit is set and reset by software.
Page 260 GD32H75E User Manual TIMER16SPEN TIMER16 clock enable when sleep mode This bit is set and reset by software. 0: Disabled TIMER16 clock when sleep mode 1: Enabled TIMER16 clock when sleep mode TIMER15SPEN TIMER15 clock enable when sleep mode This bit is set and reset by software.
Page 261: Apb3 Sleep Mode Enable Register (Rcu_Apb3Spen)
GD32H75E User Manual 1: Enabled USART5 clock when sleep mode USART0SPEN USART0 clock enable when sleep mode This bit is set and reset by software. 0: Disabled USART0 clock when sleep mode 1: Enabled USART0 clock when sleep mode Reserved Must be kept at reset value.
Page 262: Backup Domain Control Register (Rcu_Bdctl)
GD32H75E User Manual This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved PMUSPE LPDTSS VREFSPE CMPSPE SYSCFG Reserved SPEN Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. PMUSPEN PMU clock enable when sleep mode This bit is set and reset by software.
Page 263 GD32H75E User Manual Reserved BKPRST LXTALBP LXTALST RTCEN Reserved RTCSRC[1:0] Reserved LCKMD LCKMEN LXTALDRI[1:0] LXTALEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. BKPRST Backup domain reset This bit is set and reset by software. 0: No reset...
Page 264: Reset Source/Clock Register (Rcu_Rstsck)
GD32H75E User Manual and ready (LXTALSTB flag set by hardware). Note: Once LCKMEN bit is set, this bit can be reset by backup domain reset or reseting this bit after detecting LXTAL clock failure (LCKMD = 1). LXTALDRI[1:0] LXTAL drive capability Set and reset by software.
Page 265 GD32H75E User Manual Reset by writing 1 to the RSTFC bit. 0: No Low-power management reset generated 1: Low-power management reset generated WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated. Reset by writing 1 to the RSTFC bit.
Page 266: Pll Clock Additional Control Register (Rcu_Plladdctl)
GD32H75E User Manual Set by hardware to indicate if the IRC32K output clock is stable and ready for use. 0: IRC32K is not stable 1: IRC32K is stable IRC32KEN IRC32K enable Set and reset by software. 0: Disable IRC32K 1: Enable IRC32K PLL clock additional control register (RCU_PLLADDCTL) 6.3.31.
Page 267 GD32H75E User Manual 1: Enable the CK_PLL1P output PLL1REN PLL1R divider output enable This bit is set and reset by software. The PLL1REN bit can be written only if the PLL1EN is 0. 0: Disable the CK_PLL1R output 1: Enable the CK_PLL1R output...
Page 268: Pll1 Register (Rcu_Pll1)
GD32H75E User Manual PLL1Q output clock (CK_PLL1Q) from PLL1 VCO clock (CK_PLL1VCO). The CK_PLL1VCO is described in PLL1N bits in RCU_PLL1 register. 0000000: CK_PLL1Q = CK_PLL1VCO 0000001: CK_ PLL1Q = CK_PLL1VCO / 2 0000010: CK_PLL1Q = CK_PLL1VCO / 3. 0000011: CK_PLL1Q = CK_PLL1VCO / 4 0000100: CK_PLL1Q = CK_PLL1VCO / 5 …...
Page 269 GD32H75E User Manual Reserved Must be kept at reset value. 30:24 PLL1R[6:0] The PLL1R output frequency division factor from PLL1 VCO clock Set and reset by software when the PLL1 is disable. These bits used to generate PLL1R output clock (CK_PLL1R) from PLL1 VCO clock (CK_PLL1VCO). The CK_PLL1VCO is described in PLL1N bits in RCU_PLL1 register.
Page 270: Pll2 Register (Rcu_Pll2)
GD32H75E User Manual PLL1PSC[5:0] The PLL1 VCO source clock prescaler Set and reset by software when the PLL1 is disable. These bits used to generate the clock of PLL1 VCO source clock (CK_PLL1VCOSRC) from PLL1 source clock (CK_PLL1SRC) which is described in PLLSEL in RCU_PLLALL register.
Page 271 GD32H75E User Manual Reserved Must be kept at reset value. 22:16 PLL2P[6:0] The PLL2 P output frequency division factor from PLL2 VCO clock Set and reset by software when the PLL2 is disable. These bits used to generator PLL2 P output clock (CK_PLL2P) from PLL2 VCO clock (CK_PLL2VCO). The CK_PLL2P is used to USBHS (48MHz), TRNG (48MHz).
Page 272: Clock Configuration Register 1 (Rcu_Cfg1)
GD32H75E User Manual Clock configuration register 1 (RCU_CFG1) 6.3.34. Address offset: 0x8C Reset value: 0x0000 3F00 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). HPDFSE TIMERSE Reserved USART5SEL[1:0] USART2SEL[1:0] USART1SEL[1:0] PLL2RDIV[1:0] PERSEL[1:0] CAN2SEL[1:0] CAN1SEL[1:0] CAN0SEL[1:0]...
Page 273 GD32H75E User Manual 10: CK_LXTAL selected as USART2 source clock 11: CK_IRC64MDIV selected as USART2 source clock 19:18 USART1SEL[1:0] USART1 clock source selection Set and reset by software to control the USART1 clock source 00: CK_APB1 selected as USART1 source clock...
Page 274: Clock Configuration Register 2 (Rcu_Cfg2)
GD32H75E User Manual Set and reset by software to control the USART0 clock source 00: CK_APB2 selected as USART0 source clock 01: CK_AHB selected as USART0 source clock 10: CK_LXTAL selected as USART0 source clock 11: CK_IRC64MDIV selected as USART0 source clock Clock configuration register 2 (RCU_CFG2) 6.3.35.
Page 275 GD32H75E User Manual after resetting but before enabling HXTAL and PLLs. 11:8 CKOUT1DIV[3:0] The CK_OUT1 divider which the CK_OUT1 frequency can be reduced see bits14:12 of RCU_CFG2 for CK_OUT1 0000: inhibit predividers 0001: CK_OUT1 is divided by 1 0010: CK_OUT1 is divided by 2...
Page 276: Clock Configuration Register 3 (Rcu_Cfg3)
GD32H75E User Manual Clock configuration register 3 (RCU_CFG3) 6.3.36. Address offset: 0x94 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). DSPWUS Reserved ADC2SEL[1:0] ADC01SEL[1:0] Reserved Reserved Reserved I2C3SEL[1:0] I2C2SEL[1:0] I2C1SEL[1:0] Bits...
Page 277: Pll All Configuration Register (Rcu_Pllall)
GD32H75E User Manual needs to set IRC64MEN in RCU_CTL register to turn on IRC64M clock again. When the CKMEN bit is set and the system clock is CK_HXTAL or switched to HXTAL, this bit cannot be changed. 23:6 Reserved Must be kept at reset value.
Page 278 GD32H75E User Manual 00: CK_IRC64MDIV selected as source clock of PLL0, PLL1, PLL2 01: CK_LPIRC4M selected as source clock of PLL0, PLL1, PLL2 10: CK_HXTAL slected as source clock of PLL0, PLL1, PLL2 11: No clock selected as source clock of PLL0, PLL1, PLL2...
Page 279: Pll0 Fraction Configuration Register (Rcu_Pll0Fra)
GD32H75E User Manual PLL0 fraction configuration register (RCU_PLL0FRA) 6.3.38. Address offset: 0x9C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved PLL0FRA Reserved PLL0FRAN[12:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 280: Pll2 Fraction Configuration Register (Rcu_Pll2Fra)
GD32H75E User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. PLL1FRAEN PLL1 fractional latch enable. These bits are set and reset by software. These bits can lock the PLL1FRAN value into a Sigma-Delta modulator .When PLL1FRAEN bit switchs from "0" to "1", the PLL1FRAN value will transfer to modulator.
Page 281: Additional Clock Control Register 0 (Rcu_Addctl0)
GD32H75E User Manual When PLL2VCOSEL = 0, the range is 192MHz to 836MHz; When PLL2VCOSEL = 1, the range is 150MHz to 420MHz. Additional clock control register 0 (RCU_ADDCTL0) 6.3.41. Address offset: 0xC0 Reset value: 0x8000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 282: Additional Clock Control Register 1(Rcu_Addctl1)
GD32H75E User Manual 0: Don’t select IRC48M clock (use CK_PLL0Q clock or CK_PLL2P clock select by PLL48MSEL) 1: Select IRC48M clock Additional clock control register 1(RCU_ADDCTL1) 6.3.42. Address offset: 0xC4 Reset value: 0x0000 7080 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 283: Additional Clock Interrupt Register (Rcu_Addint)
GD32H75E User Manual to quickly be used as a kernel clock for some peripherals. This bit has no effect on the value of LPIRC4MEN. 0: Has no impact on LPIRC4M 1: Force LPIRC4M to run even in deepsleep mode 19:18 Reserved Must be kept at reset value.
Page 284 GD32H75E User Manual PLLUSB IRC48MS PLLUSBH PLLUSBH IRC48MS PLLUSBH Reserved Reserved HS1STBI Reserved TBIE S1STBIE S0STBIE TBIF S0STBIF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization interrupt clear Write 1 by software to reset the IRC48MSTBIF flag.
Page 285: Clock Configuration Register 4 (Rcu_Cfg4)
GD32H75E User Manual 1: IRC48M stabilization interrupt generated PLLUSBHS1STBIF Internal PLL of USBHS1 stabilization interrupt flag Set by hardware when the USBHS1 PLL clock is stable and the PLLUSBHS1STBIE bit is set. Reset by software when setting the PLLUSBHS1STBIC bit.
Page 286: Table 19-2
GD32H75E User Manual Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved USBHS1PSC[2:0] USBHS0PSC[2:0] PLLUSBH PLLUSBH USBHS1S USBHS1S USBHS0S USBHS0S Reserved USBHS148MSEL[1:0] S1PRESE Reserved Reserved USBHS048MSEL[1:0] S0PRESE Reserved Reserved Bits Fields...
Page 287 GD32H75E User Manual 01: CK_PLLUSBHS1/USBHS1DV output clock selected as USBHS1 48M source clock 10: CK_PLL1Q/USBHS1PSC output selected as USBHS1 48M source clock 11: CK_IRC48M selected as USBHS1 48M source clock USBHS1SWEN USBHS1 clock source selection enable 0: Hardware switch USBHS1 clock by USBHS1 module...
Page 288: Pllusb Configuration Register (Rcu_Pllusbcfg)
GD32H75E User Manual PLLUSB configuration register (RCU_PLLUSBCFG) 6.3.46. Address offset: 0xD8 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved PLLUSBHS1MF[6:0] Reserved USBHS1DV[2:0] PLLUSBHS1PREDV[3:0] Reserved PLLUSBHS0MF[6:0] Reserved USBHS0DV[2:0] PLLUSBHS0PREDV[3:0] Bits Fields...
Page 289: Apb2 Additional Reset Register (Rcu_Addapb2Rst)
GD32H75E User Manual 1111: PLLUSBHS1PREDV input source clock divided by / 15 Reserved Must be kept at reset value. 14:8 PLLUSBHS0MF[6:0] The PLLUSBHS0 clock multiplication factor 0000000: Reserved 0000001: Reserved … 0001111: Reserved 0010000: PLLUSBHS0MF input source clock multiplied by 16...
Page 290: Apb2 Additional Enable Register (Rcu_Addapb2En)
GD32H75E User Manual CAN2RS CAN1RS CAN0RS Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. CAN2RST CAN2 reset This bit is set and reset by software. 0: No reset 1: Reset CAN2 unit CAN1RST CAN1 reset This bit is set and reset by software.
Page 291: Apb2 Additional Sleep Enable Register (Rcu_Addapb2Spen)
GD32H75E User Manual 1: Enable CAN1 clock CAN0EN CAN0 clock enable This bit is set and reset by software. 0: Disable CAN0 clock 1: Enable CAN0 clock APB2 additional sleep enable register (RCU_ADDAPB2SPEN) 6.3.49. Address offset: 0xE8 Reset value: 0x0000 0007 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit).
Page 292 GD32H75E User Manual Reserved SPI5SEL[2:0] Reserved SPI4SEL[2:0] Reserved SPI3SEL[2:0] Reserved SPI2SEL[2:0] Reserved SPI1SEL[2:0] Reserved SPI0SEL[2:0] Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. 22:20 SPI5SEL[2:0] SPI5 / I2S5 clock source selection Set and reset by software to control the SPI5 / I2S5 clock source...
Page 293 GD32H75E User Manual Set and reset by software to control the SPI2 / I2S2 clock source 000: CK_PLL0Q selected as SPI2 / I2S2 source clock 001: CK_PLL1P selected as SPI2 / I2S2 source clock 010: CK_PLL2P selected as SPI2 / I2S2 source clock...
Page 294: Clock Trim Controller (Ctc)
GD32H75E User Manual Clock trim controller (CTC) Overview 7.1. The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trim the frequency of the IRC48M based on an external accurate reference signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 295: Ref Sync Pulse Generator
GD32H75E User Manual Figure 7-1. CTC overview PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 7.3.1.
Page 296: Frequency Evaluation And Automatically Trim Process
GD32H75E User Manual and then up- counting to 128 x CKLIM (defined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 297: Software Program Guide
GD32H75E User Manual CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 298 GD32H75E User Manual RLVALUE = ( F ÷ F ) - 1 (7-2) clock The typical step size is 0.12%. Where the F is the frequency of correct clock (IRC48M), clock the F is the frequency of reference sync pulse.
Page 299: Register Definition
GD32H75E User Manual Register definition 7.4. CTC base address: 0x4000 8400 Control register 0 (CTC_CTL0) 7.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE...
Page 300: Control Register 1 (Ctc_Ctl1)
GD32H75E User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable...
Page 301: Status Register (Ctc_Stat)
GD32H75E User Manual 01: LXTAL clock selected Other values are reserved. Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2...
Page 302 GD32H75E User Manual When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value. TRIMERR Trim value error bit This bit is set by hardware when the TRIMVALUE in CTC_CTL0 register overflow or underflow.
Page 303: Interrupt Clear Register (Ctc_Intc)
GD32H75E User Manual 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 304 GD32H75E User Manual REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register. Write 0 is no effect.
Page 305: Interrupt / Event Controller (Exti)
GD32H75E User Manual Interrupt / event controller (EXTI) Overview 8.1. ® Cortex -M7 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processer core. More details about ®...
Page 306: Table 8-1. Nvic Exception Types In Cortex ® -M7
GD32H75E User Manual ® Table 8-1. NVIC exception types in Cortex Vector Exception type Priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management...
Page 307 GD32H75E User Manual Interrupt Vector Peripheral interrupt description Vector address number number DMA0 channel0 global interrupt 0x0000_006C IRQ 11 IRQ 12 DMA0 channel1 global interrupt 0x0000_0070 IRQ 13 DMA0 channel2 global interrupt 0x0000_0074 IRQ 14 DMA0 channel3 global interrupt 0x0000_0078...
Page 308 GD32H75E User Manual Interrupt Vector Peripheral interrupt description Vector address number number UART4 global interrupt 0x0000_0114 IRQ 53 TIMER5 global interrupt and DAC underrun error IRQ 54 0x0000_0118 interrupt IRQ 55 TIMER6 global interrupt 0x0000_011C IRQ 56 DMA1 channel 0 global interrupt...
Page 309 GD32H75E User Manual Interrupt Vector Peripheral interrupt description Vector address number number 0x0000_01DC- IRQ 103-109 119-125 Reserved 0x0000_01F4 HPDF global interrupt 0 IRQ 110 0x0000_01F8 HPDF global interrupt 1 IRQ 111 0x0000_01FC HPDF global interrupt 2 IRQ 112 0x0000_0200 HPDF global interrupt 3...
Page 310 GD32H75E User Manual Interrupt Vector Peripheral interrupt description Vector address number number TIMER43 global interrupt 0x0000_02E0 IRQ 168 IRQ 169 TIMER44 global interrupt 0x0000_02E4 IRQ 170 TIMER50 global interrupt 0x0000_02E8 IRQ 171 TIMER51 global interrupt 0x0000_02EC IRQ 172 USBHS1 endpoint 1 out interrupt...
Page 311: External Interrupt And Event (Exti) Block Diagram
GD32H75E User Manual Interrupt Vector Peripheral interrupt description Vector address number number I2C2 wakeup through EXTI line detection IRQ 203 0x0000_036C interrupt I2C3 wakeup through EXTI line detection IRQ 204 0x0000_0370 interrupt LPDTS interrupt IRQ 205 0x0000_0374 LPDTS wakeup through EXTI line detection...
Page 312: External Interrupt And Event Function Overview
GD32H75E User Manual External interrupt and event function overview 8.5. The EXTI contains up to 38 independent edge detectors and generates interrupts request or event to the processer. The EXTI has three trigger types: rising edge, falling edge and both edges.
Page 313: Table 8-3. Exti Source
GD32H75E User Manual Table 8-3. EXTI source EXTI line Source number PA0 / PB0 / PC0 / PD0 / PE0 / PH0 PA1 / PB1 / PC1 / PD1 / PE1 / PH1 PA2 / PB2 / PC2 / PD2 / PE2 / PH2...
Page 314: Register Definition
GD32H75E User Manual Register definition 8.6. EXTI base address: 0x5800 0000 Interrupt enable register 0 (EXTI_INTEN0) 8.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). INTEN31 INTEN30 INTEN29 INTEN28 INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16...
Page 315 GD32H75E User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). RTEN31 RTEN30 RTEN29 RTEN28 RTEN27 RTEN26 RTEN25 RTEN24 RTEN23 RTEN22 RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8...
Page 316 GD32H75E User Manual Bits Fields Descriptions Interrupt / event software trigger bit x (x = 0…31) 31:0 SWIEVx 0: Deactivate the EXTIx software interrupt / event request 1: Activate the EXTIx software interrupt / event request Pending register 0 (EXTI_PD0) 8.6.6.
Page 317 GD32H75E User Manual Event enable register 1 (EXTI_EVEN1) 8.6.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved EVEN37 EVEN36 EVEN35 EVEN34 EVEN33 EVEN32 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
Page 318 GD32H75E User Manual Reserved Reserved FTEN37 FTEN36 FTEN35 FTEN34 FTEN33 FTEN32 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. Falling edge trigger enable bit x (x = 32…37) FTENx 0: Falling edge of linex is invalid 1: Falling edge of linex is valid as an interrupt / event request Software interrupt event register 1 (EXTI_SWIEV1) 8.6.11.
Page 319 GD32H75E User Manual rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. Interrupt pending status bit x (x = 32…37) 0: EXTI linex is not triggered 1: EXTI linex is triggered. This bit is cleared to 0 by writing 1 to it.
Page 320: Function Overview
GD32H75E User Manual Trigger selection controller (TRIGSEL) Overview 9.1. The trigger selection controller (TRIGSEL) allows software to select the trigger input signal for various peripherals. TRIGSEL provides a flexible mechanism for a peripheral to select different trigger inputs. With TRIGSEL, there are up to 150 trigger input signals could be selected. Configure the corresponding register to select the different trigger signal for the specified trigger input of each peripheral.
Page 321: Figure 9-1. Trigsel Main Composition Example
GD32H75E User Manual Figure 9-1. TRIGSEL main composition example Trigger Select Trigger input 0 Trigger input 1 Trigger output 2 Peripherals Trigger output 1 Trigger output 0 Trigger input n INSELx[7:0] Trigger selection for xxx Register Internal connect 9.4. The TRIGSEL allows software to select the trigger input for peripherals. The Table 9-1.
Page 322 GD32H75E User Manual fields bits value trigger input selection 0x10 LXTAL_TRG 0x11 TIMER0_TRGO0 0x12 TIMER0_TRGO1 0x13 TIMER0_CH0 0x14 TIMER0_CH1 0x15 TIMER0_CH2 0x16 TIMER0_CH3 0x17 TIMER0_MCH0 0x18 TIMER0_MCH1 0x19 TIMER0_MCH2 0x1a TIMER0_MCH3 0x1b~0x20 Reserved 0x21 TIMER0_BRKIN0 0x22 TIMER0_BRKIN1 0x23 TIMER0_BRKIN2 0x24...
Page 323 GD32H75E User Manual fields bits value trigger input selection 0x3e TIMER6_TRGO0 0x3f TIMER7_TRGO0 0x40 TIMER7_TRGO1 0x41 TIMER7_CH0 0x42 TIMER7_CH1 0x43 TIMER7_CH2 0x44 TIMER7_CH3 0x45 TIMER7_MCH0 0x46 TIMER7_MCH1 0x47 TIMER7_MCH2 0x48 TIMER7_MCH3 0x49~0x4e Reserved 0x4f TIMER7_BRKIN0 0x50 TIMER7_BRKIN1 0x51 TIMER7_BRKIN2 0x52...
Page 324 GD32H75E User Manual fields bits value trigger input selection 0x6f TIMER23_ETI 0x70 Reserved 0x71 Reserved 0x72 Reserved 0x73 Reserved 0x74 Reserved 0x75 Reserved 0x76 Reserved 0x77 Reserved 0x78 Reserved 0x79 Reserved 0x7a Reserved 0x7b Reserved 0x7c TIMER40_TRGO0 0x7d TIMER40_CH0 0x7e...
Page 325: Table 9-2. Trigsel Input And Output Mapping
GD32H75E User Manual fields bits value trigger input selection 0x9c~0x9d Reserved 0x9e TIMER44_BRKIN0 0x9f TIMER50_TRGO0 0xa0 TIMER51_TRGO0 0xa1 RTC_Alarm 0xa2 RTC_TPTS 0xa3 ADC0_WD0_OUT 0xa4 ADC0_WD1_OUT 0xa5 ADC0_WD2_OUT 0xa6 ADC1_WD0_OUT 0xa7 ADC1_WD1_OUT 0xa8 ADC1_WD2_OUT 0xa9 ADC2_WD0_OUT 0xaa ADC2_WD1_OUT 0xab ADC2_WD2_OUT 0xac...
Page 326 GD32H75E User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TRIGSEL_IN10 TRIGSEL_IN11 TRIGSEL_EXTOUT_ Output0 TRIGSEL_OUT6 TRIGSEL_IN12 Output1 TRIGSEL_OUT7 TRIGSEL_IN13 LXTAL_TRG TIMER0_TRGO0 Output0 ADC0_ROUTRG TRIGSEL_ADC0 TIMER0_TRGO1 Output1 ADC0_INSTRG TIMER0_CH0 TIMER0_CH1 TIMER0_CH2 Output0 ADC1_ROUTRG TRIGSEL_ADC1 TIMER0_CH3 Output1 ADC1_INSTRG TIMER0_MCH0 TIMER0_MCH1...
Page 327 GD32H75E User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TIMER4_CH2 TIMER4_CH3 TRIGSEL_TIMER16B Output0 TIMER16_BRKIN0 TIMER4_ETI RKIN TIMER5_TRGO0 TIMER6_TRGO0 TIMER7_TRGO0 TRIGSEL_TIMER40B Output0 TIMER40_BRKIN0 TIMER7_TRGO1 RKIN TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 TRIGSEL_TIMER41B Output0 TIMER41_BRKIN0 TIMER7_CH3 RKIN TIMER7_MCH0 TIMER7_MCH1 TIMER7_MCH2 TRIGSEL_TIMER42B Output0...
Page 328 GD32H75E User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TIMER23_CH3 TIMER23_ETI TRIGSEL_EDOUT Output0 EDOUT_TRG TIMER40_TRGO0 TIMER40_CH0 TIMER40_CH1 TIMER40_MCH0 TRIGSEL_HPDF Output0 HPDF_ITRG TIMER40_BRKIN0 TIMER41_TRGO0 TIMER41_CH0 TIMER41_CH1 TRIGSEL_TIMER0ET Output0 TIMER0_ETI TIMER41_MCH0 TIMER41_BRKIN0 TIMER42_TRGO0 TIMER42_CH0 TRIGSEL_TIMER1ET Output0 TIMER1_ETI TIMER42_CH1 TIMER42_MCH0...
Page 329 GD32H75E User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output CMP0_OUT CMP1_OUT TRIGSEL_TIMER0ITI Output0 TIMER0_ITI14 TRIGSEL_TIMER1ITI Output0 TIMER1_ITI14 TRIGSEL_TIMER2ITI Output0 TIMER2_ITI14 TRIGSEL_TIMER3ITI Output0 TIMER3_ITI14 TRIGSEL_TIMER4ITI Output0 TIMER4_ITI14 TRIGSEL_TIMER7ITI Output0 TIMER7_ITI14 TRIGSEL_TIMER14I Output0 TIMER14_ITI14 TI14 TRIGSEL_TIMER22I Output0 TIMER22_ITI14 TI14...
Page 330 GD32H75E User Manual Trigger TRIGSEL Trigger Source TRIGSEL Register Peripherals select output TRIGSEL_TIMER41I Output0 TIMER41_ITI14 TI14 TRIGSEL_TIMER42I Output0 TIMER42_ITI14 TI14 TRIGSEL_TIMER43I Output0 TIMER43_ITI14 TI14 TRIGSEL_TIMER44I Output0 TIMER44_ITI14 TI14 Note: TIMERx_BRKINx can only select TIMERx_BRKINx as trigger. TIMERx_ITI14 cannot select CMPx_OUT ,LXTAL_TRG, TIMERx_BRKINx and their own signals as trigger input.
Page 331: Register Definition
GD32H75E User Manual Register definition 9.5. TRIGSEL base address: 0x4001 8400 Trigger selection for EXTOUT register 0 (TRIGSEL_EXTOUT_0) 9.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock.
Page 332 GD32H75E User Manual INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_EXTOUT_1 register. 0: TRIGSEL_EXTOUT_1 register write is enabled.
Page 333 GD32H75E User Manual These bits are used to select trigger input signal connected to output1. The output can be as the source of TRIGSEL_OUT5 (external output5 signal). For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 334 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved INSEL1[7:0] INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_ADC0 register.
Page 335 GD32H75E User Manual disables write access to TRIGSEL_ADC1 register. 0: TRIGSEL_ADC1 register write is enabled. 1: TRIGSEL_ADC1 register write is disabled. 30:16 Reserved Must be kept at reset value. 15:8 INSEL1[7:0] Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1. The output is used as the source of ADC1_INSTRG(ADC1 inserted sequence) trigger input.
Page 336 GD32H75E User Manual INSEL0[7:0] Trigger input source selection for output0 These bits are used to select trigger input signal connected to output0. The output is used as the source of ADC2_ROUTRG(ADC2 routine sequence) trigger input. For the detailed configuration, please refer to Table 9-1.
Page 337 GD32H75E User Manual Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_DAC0OUT1 register. 0: TRIGSEL_DAC0OUT1 register write is enabled.
Page 338 GD32H75E User Manual These bits are used to select trigger input signal connected to output1. The output is used as the source of TIMER0_BRKIN1 trigger input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 339 GD32H75E User Manual Trigger selection TIMER14_BRKIN register 9.5.12. (TRIGSEL_TIMER14BRKIN) Address offset: 0x2C Reset value: 0x0000 0059 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER14BRKIN register.
Page 340 GD32H75E User Manual TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER15BRKIN register. 0: TRIGSEL_TIMER15BRKIN register write is enabled. 1: TRIGSEL_TIMER15BRKIN register write is disabled.
Page 341 GD32H75E User Manual Trigger selection TIMER40_BRKIN register 9.5.15. (TRIGSEL_TIMER40BRKIN) Address offset: 0x38 Reset value: 0x0000 0082 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER40BRKIN register.
Page 342 GD32H75E User Manual TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER41BRKIN register. 0: TRIGSEL_TIMER41BRKIN register write is enabled. 1: TRIGSEL_TIMER41BRKIN register write is disabled.
Page 343 GD32H75E User Manual Trigger selection TIMER43_BRKIN register 9.5.18. (TRIGSEL_TIMER43BRKIN) Address offset: 0x44 Reset value: 0x0000 0097 This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER43BRKIN register.
Page 344 GD32H75E User Manual TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER44BRKIN register. 0: TRIGSEL_TIMER44BRKIN register write is enabled. 1: TRIGSEL_TIMER44BRKIN register write is disabled.
Page 345 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_CAN1 register.
Page 346 GD32H75E User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of CAN2_EX_TIME_TICK trigger input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 347 GD32H75E User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER0ETI register. 0: TRIGSEL_TIMER0ETI register write is enabled. 1: TRIGSEL_TIMER0ETI register write is disabled.
Page 348 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER2ETI register.
Page 349 GD32H75E User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER3_ETI trigger input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 350 GD32H75E User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER7ETI register. 0: TRIGSEL_TIMER7ETI register write is enabled. 1: TRIGSEL_TIMER7ETI register write is disabled.
Page 351 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER23ETI register.
Page 352 GD32H75E User Manual These bits are used to select trigger input signal connected to output0. The output is used as the souce of EDOUT_TRG trigger input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection Trigger selection for HPDF register (TRIGSEL_HPDF) 9.5.33.
Page 353 GD32H75E User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER0ITI14 register. 0: TRIGSEL_TIMER0ITI14 register write is enabled. 1: TRIGSEL_TIMER0ITI14 register write is disabled.
Page 354 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER2ITI14 register.
Page 355 GD32H75E User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER3_ITI14 trigger input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 356 GD32H75E User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER7ITI14 register. 0: TRIGSEL_TIMER7ITI14 register write is enabled. 1: TRIGSEL_TIMER7ITI14 register write is disabled.
Page 357 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER22ITI14 register.
Page 358 GD32H75E User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER23_ITI14 trigger input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 359 GD32H75E User Manual Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER41ITI14 register. 0: TRIGSEL_TIMER41ITI14 register write is enabled. 1: TRIGSEL_TIMER41ITI14 register write is disabled.
Page 360 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved INSEL0[7:0] Bits Fields Descriptions TRIGSEL register lock. This bit is set by software and cleared only by a system reset. When it is set, it disables write access to TRIGSEL_TIMER43ITI14 register.
Page 361 GD32H75E User Manual These bits are used to select trigger input signal connected to output0. The output is used as the source of TIMER44_ITI14 trigger input. For the detailed configuration, please refer to Table 9-1. Trigger input bit fields selection.
Page 362: Function Overview
GD32H75E User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 10.1. There are up to 116 general purpose I/O pins (GPIO), named PA0~PA15, PB0~PB15, PC0~PC15, PD0~PD15, PE0~PE15, PF5~PF15, PG6~PG9, PG13~PG15, PH0~PH13, PA0_C, PA1_C, PC2_C, PC3_C for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications.
Page 363: Figure 10-1. Basic Structure Of A Standard I/O Port Bit
GD32H75E User Manual be configured by GPIO output speed registers (GPIOx_OSPD). Each port can be configured as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up/pull-down registers (GPIOx_PUD). Table 10-1. GPIO configuration table PAD TYPE CTLy PUDy...
Page 364: Gpio Pin Configuration
GD32H75E User Manual Figure 10-1. Basic structure of a standard I/O port bit Write Bit Operate Registers Output Output driver Control Read/Write Register Output Control Alternate Function Output protection Analog ( Input / Output ) I/O pin Alternate Function Input...
Page 365: Alternate Functions (Af)
GD32H75E User Manual External interrupt/event lines 10.3.2. All ports have external interrupt capability. To use external interrupt lines, the port must be configured as input mode. Alternate functions (AF) 10.3.3. When the port is configured as AFIO (set CTLy bits to “0b10”, which is in GPIOx_CTL registers), the port is used as peripheral alternate functions.
Page 366: Figure 10-3. Output Configuration
GD32H75E User Manual  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors could be chosen.  The output buffer is enabled. Open Drain Mode: The pad output low level when a “0” in the output control register;...
Page 367: Figure 10-5. Alternate Function Configuration
GD32H75E User Manual Alternate function (AF) configuration 10.3.8. To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software. When be configured as alternate function:  The output buffer is enabled in open-drain or push-pull configuration.
Page 368: Figure 10-6. Analog Configuration For Adc
GD32H75E User Manual bit of GPIOx_TG register. The output signal frequency could up to the half of the AHB clock. I/O compensation unit 10.3.11. The compensation unit is used to control the commutation slew rate (tfall/trise) to reduce I/O noise on the power supply.
Page 369: Figure 10-7. Filtering Using The Sampling Window
GD32H75E User Manual In the case of GPIO, filtering can be specified to synchronize only to CK_AHB or through the sampling window. For pins configured as peripheral input, in addition to synchronization to CK_AHB or through the sampling window, the input can also be asynchronous.
Page 370 GD32H75E User Manual If FLPRD0 in register GPIOx_IFL is 0, the sampling frequency is f . For example, if CK_AHB =100MHz, the signal will be sampled at 100 MHz or every 10ns. CK_AHB FLPRD0 register GPIOx_IFL 0xFF(255), sampling frequency ×1÷ ( 2×FLPRDx ) . For example, if f...
Page 371: Figure 10-8. Input Filtering Clock Cycle
GD32H75E User Manual =120+10=130ns CK_AHB  Figure 10-8. Input filtering clock cycle, the interference (A) is shorter than the total sampling window, so it will be filtered. Figure 10-8. Input filtering clock cycle GPIO Signal Sampling Period determined by FLPRDx...
Page 372: Register Definition
GD32H75E User Manual Register definition 10.4. GPIOA base address: 0x5802 0000 GPIOB base address: 0x5802 0400 GPIOC base address: 0x5802 0800 GPIOD base address: 0x5802 0C00 GPIOE base address: 0x5802 1000 GPIOF base address: 0x5802 1400 GPIOG base address: 0x5802 1800 GPIOH base address: 0x5802 1C00 Port control register (GPIOx_CTL, x=A...H)
Page 373 GD32H75E User Manual 23:22 CTL11[1:0] Pin 11 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 21:20 CTL10[1:0] Pin 10 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 19:18...
Page 374 GD32H75E User Manual 11: Analog mode(reset value) Port output mode register (GPIOx_OMODE, x=A…H) 10.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be write by byte (8-bit), half-word (16-bit) and word (32-bit) and be read by word (32-bit).
Page 375 GD32H75E User Manual These bits are set and cleared by software. Refer to OM0 description Pin 7 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 6 output mode bit These bits are set and cleared by software.
Page 376 GD32H75E User Manual Bits Fields Descriptions 31:30 OSPD15[1:0] Pin 15 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 29:28 OSPD14[1:0] Pin 14 output max speed bits These bits are set and cleared by software.
Page 377 GD32H75E User Manual Refer to OSPD0[1:0] description OSPD3[1:0] Pin 3 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD2[1:0] Pin 2 output max speed bits These bits are set and cleared by software.
Page 378 GD32H75E User Manual Refer to PUD0[1:0] description 25:24 PUD12[1:0] Pin 12 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 23:22 PUD11[1:0] Pin 11 pull-up or pull-down bits These bits are set and cleared by software.
Page 379 GD32H75E User Manual PUD0[1:0] Pin 0 pull-up or pull-down bits These bits are set and cleared by software. 00: Floating mode, no pull-up and pull-down (reset value) 01: With pull-up mode 10: With pull-down mode 11: Reserved Port input status register (GPIOx_ISTAT, x=A…H) 10.4.5.
Page 380 GD32H75E User Manual 31:16 Reserved Must be kept at reset value 15:0 OCTLy Port output control (y=0..15) These bits are set and cleared by software. 0: Pin output low 1: Pin output high Port bit operate register (GPIOx_BOP, x=A...H) 10.4.7.
Page 381 GD32H75E User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value Lock key It can only be set by using the lock key writing sequence. And is always readable. 0: GPIOx_LOCK register and the port configuration are not locked...
Page 382 GD32H75E User Manual Refer to SEL0[3:0] description 15:12 SEL3[3:0] Pin 3 alternate function selected These bits are set and cleared by software. Refer to SEL0[3:0] description 11:8 SEL2[3:0] Pin 2 alternate function selected These bits are set and cleared by software.
Page 383 GD32H75E User Manual Bits Fields Descriptions 31:28 SEL15[3:0] Pin 15 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description 27:24 SEL14[3:0] Pin 14 alternate function selected These bits are set and cleared by software.
Page 384 GD32H75E User Manual 1111: AF15 selected Bit clear register (GPIOx_BC, x=A…H) 10.4.11. Address offset: 0x28 Reset value: 0x0000 0000 This register can be write by byte (8-bit), half-word (16-bit) and word (32-bit) and be read by word (32-bit). Reserved CR15...
Page 385 GD32H75E User Manual 1: Toggle the corresponding OCTLy bit Input filtering register (GPIOx_IFL, x=A...H) 10.4.13. Address offset: 0x30 Reset value: 0x0000 0000 This register can be write by byte (8-bit), half-word (16-bit) and word (32-bit) and be read by word (32-bit).
Page 386 GD32H75E User Manual Bits Fields Descriptions 31:30 IFTP15[1:0] Pin 15 input filtering type bits These bits are set and cleared by software. Refer to IFTP0[1:0] description 29:28 IFTP14[1:0] Pin 14 input filtering type bits These bits are set and cleared by software.
Page 387 GD32H75E User Manual Refer to IFTP0[1:0] description IFTP3[1:0] Pin 3 input filtering type bits These bits are set and cleared by software. Refer to IFTP0[1:0] description IFTP2[1:0] Pin 2 input filtering type bits These bits are set and cleared by software.
Page 388 GD32H75E User Manual Cyclic redundancy checks management unit (CRC) Overview 11.1. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7 / 8 / 16 / 32 bits CRC code within user...
Page 389: Figure 11-1. Block Diagram Of Crc Calculation Unit
GD32H75E User Manual Figure 11-1. Block diagram of CRC calculation unit Data Input Input Data Register (32 bit) CRC Calculation Unit configurable polynomial Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) Function overview 11.3.
Page 390 GD32H75E User Manual 1) byte reverse: 32-bit data is divided into 4 groups and reverse implement in group inside. Reversed data: 0x2C6AB3F7 2) half-word reverse: 32-bit data is divided into 2 groups and reverse implement in group inside. Reversed data: 0x6A2CF7B3 3) word reverse: 32-bit data is divided into 1 group and reverse implement in group inside.
Page 391: Register Definition
GD32H75E User Manual Register definition 11.4. CRC base address: 0x4002 3000 Data register (CRC_DATA) 11.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 392 GD32H75E User Manual by any other peripheral. The CRC_CTL register will generate no effect to the byte. Control register (CRC_CTL) 11.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O...
Page 393 GD32H75E User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value. Polynomial register (CRC_POLY) 11.4.5.
Page 394: Figure 12-1. Trng Block Diagram
GD32H75E User Manual True random number generator (TRNG) Overview 12.1. The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise and it has been pre-certified NIST SP800-90B. Characteristics 12.2.  LFSR (Linear Feedback Shift Register) mode and NIST (National Institute of Standards and Technology) mode to generate random number.
Page 395: Post Processing
GD32H75E User Manual There are two modes in TRNG module, NIST mode and LFSR mode. In the NIST mode, the analog seeds of random number come from 4 noise sources. The noise source signal is first operated by XOR and then digitized to obtain a 1-bit analog seed. This analog seed is then plugged into a conditioning logic (uint) to generate 128-bit or 256-bit data output.
Page 396: Table 12-1. Algo Configurations
GD32H75E User Manual and these data are stored in the output FIFO temporarily. When all words have been read from the output FIFO through the TRNG_DATA register, a new round of conditioning process is automatically started, then another 128-bit or 256-bit conditioning output data is pushed into the output FIFO and waiting for the next reading.
Page 397 GD32H75E User Manual  Adaptive proportion test: refer to the start-up health tests.  Repetition count test: refer to the start-up health tests. GD-Defined continuous health tests: Additional health tests specified by vendor.  Transition count test: if the noise source provided more than 32 consecutive occurrence of two bits patterns(01 or 10), an error will occur and the relevant error flag will be set.
Page 398: Operation Flow
GD32H75E User Manual Operation flow 12.3.7. The following steps are recommended for using TRNG block: Set CONDRST bit in TRNG_CTL register. Write the required configuration in the TRNG_CTL register, such as module power consumption, clock frequency division factor, operating mode, input / output bit-width, algorithm, etc.
Page 399 GD32H75E User Manual through the register TRNG_DATA. If a new random number is required, enable TRNG to activate the random number generation again.
Page 400 GD32H75E User Manual Register definition 12.4. TRNG base address: 0x4802 1800 Control register (TRNG_CTL) 12.4.1. Address offset: 0x00 Reset value: 0x0300 0410 This register has to be accessed by word (32-bit). CONDRS CTL_LK Reserved NR[1:0] Reserved CLKDIV[3:0] INMOD OUTMOD ALGO[1:0]...
Page 401 GD32H75E User Manual 0: 256 bits 1: 440 bits OUTMOD Select random data width output of conditioning module 0: 128-bit 1: 256-bit conditioning module hash algorithm selection 13:12 ALGO[1:0] 00: SHA1 01: MD5 10: SHA224 11: SHA256 Reserved Must be kept at reset value.
Page 402 GD32H75E User Manual Must be kept at reset value. Reserved Status register (TRNG_STAT) 12.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved SEIF CEIF Reserved ERR_STA SECS CECS DRDY rc_w0...
Page 403 GD32H75E User Manual DRDY Random data ready status bit. This bit is cleared by reading the TRNG_DATA register and set when a new random number is generated. 0: The content of TRNG data register is not available. 1: The content of TRNG data register is available.
Page 404 GD32H75E User Manual Must be kept at reset value. 15:7 Reserved RCT_TH[6:0] Repetition count test threshold. Default 40.
Page 405: Figure 13-1. Tmu Block Diagram
GD32H75E User Manual Trigonometric Math Unit (TMU) Overview 13.1. The Trigonometric Math Unit (TMU) is a fully configurable block that execute common trigonometric and arithmetic operations. The TMU can reduce the burden of CPU, and it is usually used in motor control, signal processing and many other applications.
Page 406: Table 13-1. Input Data Configuration
GD32H75E User Manual The Post-process module converts and scales the data (x ) and writes the processed results into TMU_ODATA register. The contents of the TMU_ODATA register are in q1.31 or q1.15 format. Function overview 13.4. Data format and configuration 13.4.1.
Page 407: Table 13-2. Output Data Configuration
GD32H75E User Manual Table 13-2. Output data configuration OWIDTH bit ONUM bit Fixed format read operation to TMU_ODATA q1.31 Only one read operation q1.31 Two successive read operation q1.15 Only one read operation q1.15 Not available Mode configuration 13.4.2. The MODE[3:0] bit-field in TMU_CS register is used to configure the mode of the CORDIC- algorithm core.
Page 408 GD32H75E User Manual Table 13-4. Mode 0 description Parameter Range Description The angle θ in radians range from –π to π. The θ must be divide by π in software to convert it to the θ ∈[-1,1) First input data π...
Page 409: Table 13-5. Mode 1 Description
GD32H75E User Manual Mode 1: m*sin ( θ ) Mode 1 calculates the sine of an angle. This mode take two input datas and generate two ouput datas. Detailed information refer to Table 13-5. Mode 1 description Table 13-5. Mode 1 description...
Page 410: Table 13-6. Mode 2 Description
GD32H75E User Manual The scaling 128 is used for the input and output data in this example. Of course, other scaling, such as 101, can also be used. Mode 2: phase= atan2 (y,x) Mode 2 calculates the atan2(y,x) of a vector (x,y) . This mode take two input datas and generate two ouput datas.
Page 411: Table 13-7. Mode 3 Description
GD32H75E User Manual Mode 3: modulus=√x Mode 3 calculates the modulus √x of a vector (x,y). This mode take two input datas and generate two ouput datas. Detailed information refer to Table 13-7. Mode 3 description Table 13-7. Mode 3 description...
Page 412: Table 13-8. Mode 4 Description
GD32H75E User Manual Mode 4: tan Mode 4 calculates the tan (x). This mode take one input data and generate one ouput data. Detailed information refer to Table 13-8. Mode 4 description Table 13-8. Mode 4 description Parameter Range Description If x∈[-1,1), the software does not need to process it, and the...
Page 413: Table 13-10. Mode 6 Description
GD32H75E User Manual Parameter Range Description The output data is multiplied 2 to get the real Second output sinh (x) ∈ [ -0.683,0.683 ] hyperbolic sine of a hyperbolic angle ��. data The bit-field FACTOR[2:0] is configured as 3’b001 FACTOR[2:0] Note: The scaling factor FACTOR[2:0] must be 1.
Page 414: Table 13-11. Mode 7 Description
GD32H75E User Manual 2. The scaling factor f=3 b001 is written into FACTOR[2:0] bit-field in TMU_CS register. 3. The input data 0x4000 is written into TMU_IDATA. Then the TMU calculation starts. 4. When the ENDF flag is set to 1, reading the TMU_ODATA register can get the first output sinh (1.0)
Page 415: Table 13-12. Mode 8 Description
GD32H75E User Manual 8 description Table 13-12. Mode 8 description Parameter Range Description x∈[0.107,9.35], a scaling factor 2 −�� is applied in ∈[0.0535,0.875] Input data <(1- ). Then write softwate to ensure that to TMU_IDATA in q1.15 or q1.31 format.
Page 416: Table 13-15. Recommended Scaling Factors In Mode 9
GD32H75E User Manual Parameter Range Description <(1- ). Then write softwate to ensure that to TMU_IDATA in q1.15 or q1.31 format. √ x ∈[0.04,1] The output data is multiplied 2 to get the real √ x. Output data f∈ [ 0,2 ]...
Page 417 GD32H75E User Manual Max residual error Mode Number of iterations Number of cycles q1.31 format q1.15 format Mode 1. Max residual error is the maximum error remaining after the given number of iterations, compared to the identical calculation performed in double precision floating point. An...
Page 418 GD32H75E User Manual 1. Configure TMU_CS register as needed. 2. Start the TMU operation by written the input data into TMU_IDATA. 3. Configure the next TMU mode as required and write the input data into TMU_IDATA. 4. Read the result from the TMU_ODATA register. The waiting cycles are automatically inserted into the bus.
Page 419 GD32H75E User Manual Registers definition 13.5. TMU base address: 0x4001 0000 Control and status register (TMU_CS) 13.5.1. Address offset: 0x00 Reset value: 0x0000 0050 This register can be accessed by word(32-bit). ENDF Reserved IWIDTH OWIDTH INUM ONUM WDEN RDEN Reserved...
Page 420 GD32H75E User Manual in q1.31 format. If 16-bit is configured, the TMU_ODATA contains the output data of TMU operation in q1.15 format. The the lower half-word of TMU_IDATA register contains the first output data, and the the upper half-word of TMU_IDATA register contains the second output data.
Page 421 GD32H75E User Manual When the actual input parameter exceeds the specified the input data range [-1,1), FACTOR[2:0] it is need to be divide by 2 and the output data is need to be multiplied by FACTOR[2:0] to get the actual output result, details as follows:...
Page 422 GD32H75E User Manual IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] The input data Table 13-1. Input The input data is written into this register. For details, refer to data configuration Note: 1. When no TMU operation is is ongoing and the required number of arguments has been written, a new operation will be started automatically.
Page 423: Direct Memory Access Controller (Dma)
GD32H75E User Manual Direct memory access controller (DMA) Overview 14.1. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data.
Page 424: Function Overview
GD32H75E User Manual – Multi-data mode: Pack/Unpack data when memory transfer width are different from peripheral transfer width. – Single-data mode: Read data from source when FIFO is empty and wirte data to destination when one data has been pushed into FIFO.
Page 425: Figure 14-2. Data Stream For Three Transfer Modes
GD32H75E User Manual and memory-to-memory, which is determined by the TM bits in the DMA_CHxCTL register, as listed in Table 14-1. Transfer mode. Table 14-1. Transfer mode Transfer mode TM[1:0] Source Destination DMA_CHxM0ADDR/ Peripheral to memory DMA_CHxPADDR DMA_CHxM1ADDR DMA_CHxM0ADDR/ Memory to peripheral...
Page 426: Figure 14-3. Handshake Mechanism
GD32H75E User Manual Peripheral handshake 14.3.2. To ensure a well-organized and efficient data transfer, a handshake mechanism is introduced between the DMA and peripherals, including a request signal and a acknowledge signal:  Request signal asserted by peripheral to DMA controller, indicating that the peripheral is ready to transmit or receive data.
Page 427 GD32H75E User Manual multi-data mode, if PWIDTH is not equal to MWIDTH, the DMA can automatically packs/unpacks data to achieve an integrated and correct data transfer operation. In single- data mode, MWIDTH is automatically locked as PWIDTH by hardware immediately after enable the DMA channel.
Page 428: Table 14-2. Cnt Configuration
GD32H75E User Manual into single transfer automatically. Table 14-2. CNT configuration PWIDTH MWIDTH 8-bit 16-bit Multiple of 2 8-bit 32-bit Multiple of 4 16-bit 32-bit Multiple of 2 Others Any value 1. If the circular mode is enabled by setting the CMEN bit in the DMA_CHxCTL register. The...
Page 429: Table 14-3. Fifo Counter Critical Value Configuration Rules
GD32H75E User Manual configuration, including single-data mode and multi-data mode. When the transfer mode is memory-to-memory, only multi-data mode is supported to implement the DMA data processing. Multi-data mode The multi-data mode is selected by configuring the MDMEN bit in the DMA_CHxFCTL register to ‘1’.
Page 430: Figure 14-4. Data Packing/Unpacking When Pwidth = '00
GD32H75E User Manual entirely fill the FIFO. Then DMA lanches memory burst transfers to pop three words from the FIFO depending on the FIFO counter critical value and a word is still remained in the FIFO. There is no enough space for a peripheral burst transfer and the FIFO counter critical value is not reached, which makes DMA transfer frozen.
Page 431: Figure 14-5. Data Packing/Unpacking When Pwidth = '01
GD32H75E User Manual Suppose the CNT bits are 8, the PWIDTH bits are equal to ‘01’, and both PNAGA and MNAGA are set. The DMA transfer operations for different MWIDTH are shown in the Figure 14-5. Data packing/unpacking when PWIDTH = ‘01’.
Page 432: Circular Mode
GD32H75E User Manual base address registers (DMA_CHxPADDR, DMA_CHxM0ADDR, and DMA_CHxM1ADDR). In the increasing mode, the next address is euqal to the current address plus 1 or 2 or 4, depending on the transfer data width. In Multi-data mode with PBURST in the DMA_CHxCTL register is ‘00’, if PAIF in the DMA_CHxCTL register is enabled, the next peripheral address...
Page 433: Figure 14-7. Dma Operation Of Switch-Buffer Mode
GD32H75E User Manual Figure 14-7. DMA operation of switch-buffer mode MBS = 0 Enable the channel peripheral-to-memory FIFO memory buffer 0 Peripheral push data pop data Memory 0 transfer: transfer finish transfer finish MBS = 0 MBS = 1 FIFO...
Page 434 GD32H75E User Manual Transfer finish 14.3.8. The DMA transfer is finished automatically and the FTFIFx bit in the DMA_INTF0 or DMA_INTF1 register is set when one of the following situations occurs:  Transfer completion.  Software clear.  Error detection.
Page 435: Error Detection
GD32H75E User Manual Error detection Three types error can disable the DMA transfer:  FIFO error: When a wrong FIFO configuration is detected, the DMA channel is disabled immediately without starting any transfers. In this situation, the FTFIFx is not asserted.
Page 436: Table 14-4. Dma Interrupt Events
GD32H75E User Manual Configure the DMA_CHxCNT register to set the total transfer data number. 10. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the channel. When restarting the suspended DMA transfer, it is recommended to respect the following steps: Read the CHEN bit and ensure the DMA suspend operation has been completed.
Page 437 GD32H75E User Manual Flag bit Enable bit Clear bit Interrupt event DMA_INTF0 or DMA_CHxCTL or DMA_INTC0 or DMA_INTF1 DMA_CHxFCTL DMA_INTC1 exception These five events can be divided into three types:  Flag: Full transfer finish flag and half transfer finish flag.
Page 438 GD32H75E User Manual mode is peripheral-to-memory. When a peripheral request is valid and the FIFO is not empty, there are two or more data items stored in the FIFO after responding the peripheral request, which could be a problem for the subsequent processing of the data and the single-data mode exception bit SDEIFx will be set.
Page 439: Bus Error
GD32H75E User Manual Register access error The register access error is detected only when the switch-buffer is enabled. If the software attempts to update a memory address register currently accessed by the DMA controller, a register access error is detected. For example, when the memory 0 buffer is the current source or destination, a write access on the DMA_CHxM0ADDR register could produce a register access error.
Page 440: Figure 14-8. System Connection Of Dma0 And Dma1
GD32H75E User Manual and exception interrupt is set, an interrupt is generated. Figure 14-8. System connection of DMA0 and DMA1 ITCM ITCM DTCM DTCM Bus matrix Bus matrix AXI SRAM AXI SRAM RAM shared RAM shared SRAM0 SRAM0 SRAM1 SRAM1...
Page 441: Register Definition
GD32H75E User Manual Register definition 14.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Interrupt flag register 0 (DMA_INTF0) 14.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIF3...
Page 442 GD32H75E User Manual 23/17/7/1 Reserved Must be kept at reset value. FIFO error and exception of channel x (x=0…3) 22/16/6/0 FEEIFx Hardware set and software cleared by writing 1 to the corresponding bit in DMA_INTC0 register. 0: FIFO error or exception has not occurred on channel x...
Page 443 GD32H75E User Manual 1: Single data mode exception has occurred on channel x 23/17/7/1 Reserved Must be kept at reset value. FIFO error and exception of channel x (x=4…7) 22/16/6/0 FEEIFx Hardware set and software cleared by writing 1 to the corresponding bit in DMA_INTC1 register.
Page 444 GD32H75E User Manual Interrupt flag clear register 1 (DMA_INTC1) 14.5.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIFC7 HTFIFC7 TAEIFC7 SDEIFC7 Reserved FEEIFC7 FTFIFC6 HTFIFC6 TAEIFC6 SDEIFC6 Reserved FEEIFC6 Reserved...
Page 445 GD32H75E User Manual PAIF MWIDTH[1:0] PWIDTH[1:0] MNAGA PNAGA CMEN TM[1:0] Reserved FTFIE HTFIE TAEIE SDEIE CHEN Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. 24:23 MBURST[1:0] Transfer burst type of memory Software set and clear. 00: single burst...
Page 446 GD32H75E User Manual 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’. PAIF Peripheral address increment fixed Software set and clear. 0: The peripheral address increment is determined by PWIDTH 1: The peripheral address increment is fixed to 4 This bit can not be written when CHEN is ‘1’.
Page 447 GD32H75E User Manual Software set and clear. 0: Disable circular mode. 1: Enable circular mode This bit can not be written when CHEN is ‘1’. This bit is automatically locked as ‘1’ by hardware immediately after enable CHEN if SBMEN is configured to ‘1’.
Page 448 GD32H75E User Manual at which point this bit is read as 0. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. Channel x counter register (DMA_CHxCNT) 14.5.6. x = 0...7, where x is a channel number Address offset: 0x14 + 0x18 ×...
Page 449 GD32H75E User Manual These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When PWIDTH is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address. When PWIDTH is 10 (32-bit), the two LSBs of these bits are ignored. Access is automatically aligned to a word address.
Page 450 GD32H75E User Manual M1ADDR[15:0] Bits Fields Descriptions 31:0 M1ADDR[31:0] Memory 1 base address When MBS in the DMA_CHxCTL register is read as to ‘1’, these bits specific the memory base address accessed by DMA during the transmission. These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’ and MBS in the DMA_CHxCTL register is read as ‘1’.
Page 451 GD32H75E User Manual 001: One word 010: Two words 011: Three words 100: Empty 101: Full 110~111: Reserved These bits specific the number of data stored in FIFO during the transmission. When MDMEN is configured to ‘0’, these bits has no meaning.
Page 452 GD32H75E User Manual Master direct memory access controller (MDMA) Overview 15.1. The master direct memory access (MDMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data.
Page 453: Function Overview
GD32H75E User Manual  ® The AHB bus interface is used to access Cortex -M7 TCM memory. And only when the increment and data size are identical and lower than or equal to 32-bit, burst access is allowed. When the increment and data size is larger than 32 bits, burst access is prohibited.
Page 454: Figure 15-2. Connections Of The Four Modes
GD32H75E User Manual Transfer mode TRIGMOD[1:0] Multi-block transfer Link transfer  Buffer transfer can transmit up to 128 bytes at a time.  Block transfer can transmit a maximum of 64KB at a time. The number of bytes to be transferred can be configured by TBNUM[16:0] in the MDMA_CHxBTCFG register.
Page 455 GD32H75E User Manual request sources source TRIGSEL[5:0] DMA1_CH2_TRIG DMA1_CH3_TRIG DMA1_CH4_TRIG DMA1_CH5_TRIG DMA1_CH6_TRIG DMA1_CH7_TRIG Reserved Reserved Reserved Reserved Reserved Reserved OSPI0_FT OSPI0_TC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OSPI1_FT OSPI1_TC Data process 15.3.1. Arbitration MDMA manages requests based on channel request priority through an arbiter. When more...
Page 456: Figure 15-3. Word, Halfword, Byte Order Exchange
GD32H75E User Manual Data type The word, halfword, and byte exchange operations on the target data can be configured by the WES/HWES/BES bits in the MDMA_CHxCTL0 register. The data exchange process is shown in Figure 15-3. Word, halfword, byte order exchange.
Page 457: Figure 15-5. Data Padding And Alignment (Source Less Than Destination)
GD32H75E User Manual Figure 15-4. Data padding and alignment (source greater than destination) PAMOD[1:0] = word 4 write B0[7:0] @0x0 read B3B2B1B0[31:0] @0x0 word 3 write B4[7:0] @0x1 read B7B6B5B4[31:0] @0x4 push data pop data write B8[7:0] @0x2 read B11B10B9B8[31:0] @0x8...
Page 458: Figure 15-6. Data Packing / Unpacking
GD32H75E User Manual SWIDTH[1:0] = 00, DWIDTH[1:0] = 10, the unpacking process is shown in Figure 15-6. Data packing / unpacking. Figure 15-6. Data packing / unpacking read B0[7:0] @0x0 read B8[7:0] @0x8 word 4 read B1[7:0] @0x1 read B9[7:0] @0x9...
Page 459: Table 15-3. Source And Destination Address Generation Configuration
GD32H75E User Manual address generation configuration. Table 15-3. Source and destination address generation configuration SIMOD[1:0] DIMOD[1:0] No increment No increment Increment of the source is Increment of the destination is SIOS DIOS decrement of the source is decrement of the destination is...
Page 460: Block Transfer Mode
GD32H75E User Manual When the buffer transfer is completed, the TCF bit in MDMA_CHxSTAT0 register will be set. The TCF bit can be cleared by writing 1 to the TCFC bit in MDMA_CHxSTATC register If TRIGMOD[1:0] is not 00 and the total number of data to be transferred is greater than 128 bytes, then the arbitrator manages the request event based on the MDMA channel request priority after each buffer transfer.
Page 461: Table 15-4. Update Mode Of Source And Destination Address
GD32H75E User Manual MDMA_CHxBTCFG register. When BRNUM[11:0] is not 0, the multi-block transfer mode is enabled. BRNUM[11:0] can be configured from 0 to 4095. When a block transfer is completed, the BRNUM value is reduced by 1. The source address and the destination address of the...
Page 462: Transfer Status
GD32H75E User Manual If the TRIGSEL[5:0] in the MDMA_CHxCTL1 register changes while loading the channel configuration register, the trigger source will be changed by hardware automatically. Note: In link transfer mode, the SWREQMOD bit and TRIGMOD[1:0] in the MDMA_CHxCFG register cannot be modified.
Page 463: Table 15-7. Mdma Interrupt Events
GD32H75E User Manual Error name Description MDTERR Mask data transmission error flag LDTERR Link data error flag Transmission error flag The transmission error flag (ERR) will be set when the following occurs:  A bus error occurred during MDMA read or write access.
Page 464: Figure 15-7. Mdma Interrupt Logic
GD32H75E User Manual Figure 15-7. MDMA interrupt logic CHTCFx CHTCIEx Interrupt BTCFx events BTCIEx GIFx MBTCFx Global interrupt events MBTCIEx ERRx ERRIEx TCFx TCIEx Note: "x" represents the the number of channels (corresponding to x=0...15).
Page 465: Register Definition
GD32H75E User Manual Register definition 15.4. MDMA base address: 0x52000000 Global interrupt flag register (MDMA_GINTF) 15.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit), word (32-bit). Reserved GIF15 GIF14 GIF13...
Page 466 GD32H75E User Manual REQAF Channel x request active flag If the SWREQ bit in MDMA_CHxCTL0 is set, and CHEN is enabled, this bit will be set. When the request of channel x is completed, this bit is cleared by hardware.
Page 467 GD32H75E User Manual Reserved TCFC BTCFC MBTCFC CHTCFC ERRC Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. TCFC Channel x buffer transfer complete flag clear 0: No effect. 1: Clear the TCF bit in the MDMA_CHxSTAT0 register by writing 1 to this bit.
Page 468 GD32H75E User Manual When the block size is not an integer multiple of the source or destination data size, this bit will be set by hardware. And this bit is cleared by writing 1 to ERRC bit in MDMA_CHxSTATC register.
Page 469 GD32H75E User Manual Reserved HWES Reserved SMODEN PRIO[1:0] TCIE BTCIE MBTCIE CHTCIE ERRIE CHEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. SWREQ Software request When the channel is enabled, request for channel x can be activated by setting this bit.
Page 470 GD32H75E User Manual 01: Medium 10: High 11: Ultra high Note: When the channel is enabled (CHEN=1), these bits cannot be modified. TCIE Buffer transfer complete interrupt enable This bit is set and cleared by software. 0: Buffer transfer complete interrupt disable.
Page 471 GD32H75E User Manual DBURST[ SBURST[2:0] DIOS[1:0] SIOS[1:0] DWIDTH[1:0] SWIDTH[1:0] DIMOD[1:0] SIMOD[1:0] Bits Fields Descriptions BWMOD Bufferable write mode This bit is set and cleared by software. 0: Bufferable write mode disable. 1: Bufferable write mode enable. Note: When the channel is enabled (CHEN=1), this bit cannot be modified.
Page 472 GD32H75E User Manual Reserved Reserved Note: When the packet is enabled (PKEN=1) or the source data size is equal to the destination data size, these bits is invalid. When the channel is enabled (CHEN=1), these bits cannot be modified. PKEN Pack enable This bit is set and cleared by software.
Page 473 GD32H75E User Manual 11: 64-bit Note: When the channel is enabled (CHEN=1), these bits cannot be modified. If DIOS < DWIDTH and DIMOD is not 00, the result will be unpredictable. SIOS[1:0] Offset size of source increment These bits are set and cleared by software.
Page 474 GD32H75E User Manual Channel x block transfer configure register (MDMA_CHxBTCFG) 15.4.7. x = 0...15, where x is a channel number Address offset: 0x54 + 0x40 × x Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit), word (32-bit).
Page 475 GD32H75E User Manual SADDR[31:16] SADDR[15:0] Bits Fields Descriptions 31:0 SADDR[31:0] Source address Channel x destination address register (MDMA_CHxDADDR) 15.4.9. x = 0...15, where x is a channel number Address offset: 0x5C + 0x40 × x Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit), word (32-bit).
Page 476 GD32H75E User Manual value of these bits must be an integer multiple of DWIDTH. When BRNUM=0, these bits are invalid. Note: When the channel is enabled (CHEN=1), these bits cannot be modified. 15:0 SADDRUV[15:0] Source address update value These bits are used to configure the increment or decrement of the source address after the block transfer is completed.
Page 477 GD32H75E User Manual Reserved DBSEL SBSEL Reserved TRIGSEL[5:0] Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. DBSEL Destination bus select This bit is used to configure the destination bus for the selected channel x during write operations.
Page 478 GD32H75E User Manual 31:0 MADDR[31:0] Mask address When the bit field is not 0, the DMA request is acknowledged by writing the MDATA value in the MDMA_CHxMDATA register to the address specified by MADDR. Channel x mask data register (MDMA_CHxMDATA) 15.4.14.
Page 479 GD32H75E User Manual DMA request multiplexer (DMAMUX) Overview 16.1. DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer is used for routing a DMA request line between the peripherals / generated DMA request (from the DMAMUX request generator) and the DMA controller. Each DMAMUX request multiplexer channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.
Page 480: Figure 16-1. Block Diagram Of Dmamux
GD32H75E User Manual Block diagram 16.3. Figure 16-1. Block diagram of DMAMUX Request multiplexer Slave Port Channel 15 Channel 2 Channel 1 Peri_reqx To DMA controller: Channel 0 Reqx_out Sync Counter underrun: Reqx_in Evtx_out Configuration Register Input selector Synchronization inputs:...
Page 481: Function Overview
GD32H75E User Manual Function overview 16.5. As shown in Figure 16-1. Block diagram of DMAMUX, DMAMUX includes two sub-blocks:  DMAMUX request multiplexer. DMAMUX request multiplexer inputs (Reqx_in) source from: – Peripherals (Peri_reqx). – DMAMUX request generator outputs (Gen_reqx). DMAMUX request multiplexer outputs (Reqx_out) is connected to channels of DMA controller.
Page 482: Figure 16-2. Synchronization Mode
GD32H75E User Manual Note: The NBR[4:0] bits value shall only be written by software when both synchronization enable bit SYNCEN and event generation enable EVGEN bit of the corresponding request multiplexer channel x are disabled. When synchronization mode is enabled...
Page 483: Figure 16-3. Event Generation
GD32H75E User Manual be routed to the DMAMUX multiplexer channel output until a synchronization input event occurs again. Channel event generation Each DMA request line multiplexer channel has an event output called Evtx_out, which is the DMA request multiplexer counter underrun event. Signals Evt0_out ~ Evt3_out can be used for DMA request chaining.
Page 484: Trigger Overrun
GD32H75E User Manual DMAMUX request generator 16.5.2. The DMAMUX request generator produces DMA requests upon trigger input event. Its component unit is the request generator channels. DMA request trigger inputs are connected in parallel to all request generator channels. And there is a built-in DMAMUX request generator counter for each request generator channel.
Page 485: Table 16-1. Interrupt Events
GD32H75E User Manual Set and configure the DMA channel x completely, except enabling the channel x. Set and configure the related DMAMUX channel y completely. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the DMA channel Interrupt 16.5.4.
Page 486: Table 16-2. Request Multiplexer Input Mapping
GD32H75E User Manual Request multiplexer input mapping A DMA request is sourced either from the peripherals or from the DMAMUX request generator, the sources can refer to Table 16-2. Request multiplexer input mapping, configured by the MUXID[7:0] bits in the DMAMUX_RM_CHxCFG register for the DMAMUX request multiplexer channel x.
Page 487 GD32H75E User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER2_UP Reserved TIMER2_TRG TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_CH3 Reserved TIMER3_TRG TIMER3_UP I2C0_RX I2C0_TX I2C1_RX I2C1_TX SPI0_RX SPI0_TX SPI1_RX SPI1_TX USART0_RX USART0_TX USART1_RX USART1_TX USART2_RX USART2_TX TIMER7_CH0 TIMER7_CH1 TIMER7_CH2 TIMER7_CH3 TIMER7_MCH0 TIMER7_MCH1...
Page 488 GD32H75E User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER4_UP Reserved TIMER4_TRG SPI2_RX SPI2_TX UART3_RX UART3_TX UART4_RX UART4_TX DAC_CH0 DAC_CH1 TIMER5_UP TIMER6_UP USART5_RX USART5_TX I2C2_RX I2C2_TX Reserved Reserved Reserved Reserved UART6_RX UART6_TX UART7_RX UART7_TX SPI3_RX SPI3_TX SPI4_RX SPI4_TX Reserved...
Page 489 GD32H75E User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER14_MCH0 TIMER14_UP TIMER14_TRG TIMER14_CMT TIMER15_CH0 TIMER15_MCH0 Reserved TIMER15_UP TIMER16_CH0 TIMER16_MCH0 Reserved TIMER16_UP ADC2 FAC_READ FAC_WRITE TMU_READ TMU_WRITE TIMER22_CH0 TIMER22_CH1 TIMER22_CH2 TIMER22_CH3 TIMER22_UP Reserved TIMER22_TRG TIMER23_CH0 TIMER23_CH1 TIMER23_CH2 TIMER23_CH3 TIMER23_UP Reserved...
Page 490 GD32H75E User Manual Request multiplexer channel input identification Source MUXID[7:0] Reserved Reserved Reserved Reserved Reserved Reserved TIMER40_CH0 TIMER40_MCH0 TIMER40_CMT TIMER40_UP TIMER41_CH0 TIMER41_MCH0 TIMER41_CMT TIMER41_UP TIMER42_CH0 TIMER42_MCH0 TIMER42_CMT TIMER42_UP TIMER43_CH0 TIMER43_MCH0 TIMER43_CMT TIMER43_UP TIMER44_CH0 TIMER44_MCH0 TIMER44_CMT TIMER44_UP TIMER50_UP TIMER51_UP Reserved Reserved...
Page 491: Table 16-3. Trigger Input Mapping
GD32H75E User Manual Request multiplexer channel input identification Source MUXID[7:0] TIMER40_CH1 TIMER40_TRG TIMER41_CH1 TIMER41_TRG TIMER42_CH1 TIMER42_TRG TIMER43_CH1 TIMER43_TRG TIMER44_CH1 TIMER44_TRG Trigger input mapping The DMA request trigger input for the DMAMUX request generator channel x is selected through the TID[5:0] bits in DMAMUX_RG_CHxCFG register, the sources can refer to Table 16-3.
Page 492: Table 16-4. Synchronization Input Mapping
GD32H75E User Manual Trigger input identification Source TID[5:0] EXTI_13 EXTI_14 EXTI_15 RTC_WAKEUP CMP0_OUTPUT CMP1_OUTPUT I2C0_WAKEUP I2C1_WAKEUP I2C2_WAKEUP I2C3_WAKEUP I2C0_INT_EVENT I2C1_INT_EVENT I2C2_INT_EVENT I2C3_INT_EVENT ADC2_INT Note: DMA requests are generated only when EXTI interrupt events occur for EXTI x (x=0...15). Synchronization input mapping...
Page 493 GD32H75E User Manual Synchronization input Source identification SYNCID[4:0] EXTI_8 EXTI_9 EXTI_10 EXTI_11 EXTI_12 EXTI_13 EXTI_14 EXTI_15 RTC_WAKEUP CMP0_OUTPUT I2C0_WAKEUP I2C1_WAKEUP I2C2_WAKEUP I2C3_WAKEUP...
Page 494: Register Definition
GD32H75E User Manual Register definition 16.6. DMAMUX base address: 0x4002 0800 Request multiplexer channel configuration register 16.6.1. (DMAMUX_RM_CHxCFG) x = 0...15, where x is a channel number Address offset: 0x00 + 0x04 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 495: Request Multiplexer Channel Interrupt Flag Register (Dmamux_Rm_Intf)
GD32H75E User Manual 1: Enable event generation SOIE Synchronization overrun interrupt enable 0: Disable interrupt 1: Enable interrupt MUXID[7:0] Multiplexer input identification Selects the input DMA request in multiplexer input sources. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) 16.6.2. Address offset: 0x80 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 496: Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
GD32H75E User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SOIFCx Clear bit for synchronization overrun event flag of request multiplexer channel x. Writing 1 clears the corresponding overrun flag SOIFx in the DMAMUX_RM_INTF register.
Page 497: Request Generator Channel Interrupt Flag Register (Dmamux_Rg_Intf)
GD32H75E User Manual Reserved Must be kept at reset value. TID[5:0] Trigger input identification Selects the DMA request trigger input source. Request generator channel interrupt flag register (DMAMUX_RG_INTF) 16.6.5. Address offset: 0x140 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 498 GD32H75E User Manual Writing 1 clears the corresponding trigger overrun flag TOIFx in the DMAMUX_RG_INTF register.
Page 499: Debug (Dbg)
GD32H75E User Manual Debug (DBG) Overview 17.1. The GD32H75E series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSight™ module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the Cortex -M7.
Page 500: Jtag
GD32H75E User Manual Table 17-1. Pin assignment Debug interface PA15 JTDI PA14 JTCK/SWCLK PA13 JTMS/SWDIO NJTRST JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB3 can be used to other GPIO functions (NJTRST tied to 1 by hardware).
Page 501 GD32H75E User Manual 2. EFUSE configuration: EFUSE related bits: JTAGNSW, NDBG[1:0], DPx[31:0](x=0,1) Mode Register configuration NDBG[1:0] = 2b’10 or 2b’11 JTAGNSW: Don’t care No debug DP0[31:0], DP1[31:0]: Don’t care 2b’00 or 2b’01 NDBG[1:0] = 1b’0 JTAGNSW = DP0[31:0], DP1[31:0]: Don’t care NDBG[1:0] = 2b’00...
Page 502: Debug Reset
GD32H75E User Manual Write 5’b11010 to IR, Read value from DR: {30‘b0, wrong_seq, secure_jtag}, Among them, secure_jtag indicates the JTAG status. “1”: The CPU cannot be operated via JTAG “0”: The CPU can be operated via JTAG. wrong_seq indicates the decryption process error flag,“1”: An error occurred in the decryption, “0”: Decryption process without errors.
Page 503 GD32H75E User Manual...
Page 504: Register Definition
GD32H75E User Manual Register definition 17.4. DBG base address: 0xE00E1000 ID code register (DBG_ID) 17.4.1. Address offset: 0x00 Read only This register has to be accessed by word (32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software.
Page 505: Control Register1 (Dbg_Ctl1)
GD32H75E User Manual 00: Trace pin used in asynchronous mode 01: Trace pin used in synchronous mode and the data length is 1 10: Trace pin used in synchronous mode and the data length is 2 11: Trace pin used in synchronous mode and the data length is 4.
Page 506: Control Register2 (Dbg_Ctl2)
GD32H75E User Manual Control register2 (DBG_CTL2) 17.4.4. Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). I2C3_HOL I2C2_HOL I2C1_HOL I2C0_HOL Reserved Reserved TIMER51_ TIMER50_ TIMER23_ TIMER22_ TIMER6_ TIMER5_ TIMER4_ TIMER3_ TIMER2_ TIMER1_ Reserved...
Page 507: Control Register3 (Dbg_Ctl3)
GD32H75E User Manual 1: Hold the TIMER50 counter for debug when core halted. Reserved Must be kept at reset value. TIMER23_HOLD TIMER23 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER23 counter for debug when core halted.
Page 508 GD32H75E User Manual This register has to be accessed by word (32-bit). TIMER44_ TIMER43_ TIMER42_ TIMER41_ TIMER40_ TIMER16_ TIMER15_ TIMER14_ Reserved HOLD HOLD HOLD HOLD HOLD HOLD HOLD HOLD CAN2_HO CAN1_HO CAN0_HO TIMER7_ TIMER0_ Reserved HOLD HOLD Bits Fields Descriptions...
Page 509: Control Register4 (Dbg_Ctl4)
GD32H75E User Manual TIMER14_HOLD TIMER14 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER14 counter for debug when core halted. 15:5 Reserved Must be kept at reset value. CAN2_HOLD CAN2 hold bit This bit is set and reset by software.
Page 510 GD32H75E User Manual 31:19 Reserved Must be kept at reset value. FWDGT_HOLD FWDGT hold bit This bit is set and reset by software. 0: no effect 1: Hold the FWDGT counter clock for debug when core halted. Reserved Must be kept at reset value.
Page 511: Analog-To-Digital Converter (Adc)
GD32H75E User Manual Analog-to-digital converter (ADC) Overview 18.1. A 12 / 14-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip. ADC0 has 20 external channels, 1 internal channel(DAC0_OUT0 channel), ADC1 has 18 external channels, 3 internal channels(the battery voltage, V...
Page 512: Pins And Internal Signals
GD32H75E User Manual By TRIGSEL. –  Operation modes: Converts a single channel or scans a sequence of channels. – Single operation mode converts selected inputs once per trigger. – Continuous operation mode converts selected inputs continuously. – Discontinuous operation mode.
Page 513: Function Overview
GD32H75E User Manual Description Name V ≤V ≤ V (ADC2) REFP The negative reference voltage for the REFN ADC,V REFN ADCx_IN[19:0] Up to 20 external channels Note: V and V have to be connected to V and V , respectively.
Page 514: Dual Clock Domain Architecture
GD32H75E User Manual recommended. When the ADC operating conditions change (such as supply power voltage V , positive reference voltage V , temperature and so on), it is recommended to re-run a calibration REFP cycle. The internal analog calibration can be reset by setting the RSTCLB bit in ADC_CTL1 register.
Page 515: Table 18-3. Adc Differential Channel Pin Matching
GD32H75E User Manual single-ended mode and differential input mode. In single-ended input mode, the negative input is V , in differential input mode, the negative input is V . And therefore, channel m REFN is no longer usable in single-ended mode or in differential mode and must never be configured to be converted.
Page 516: Routine Sequence
GD32H75E User Manual Routine sequence 18.4.5. The channel management circuit can organize the sampling conversion channels into a sequence: routine sequence. The routine sequence supports up to 21 channels, and each channel is called routine channel. The ADC_RSQ0~ADC_RSQ8 registers specify the selected channels of the routine sequence.
Page 517: Figure 18-3. Continuous Operation Mode
GD32H75E User Manual Continuous operation mode The continuous operation mode will be enabled when CTN bit in the ADC_CTL1 register is set. In this mode, the ADC performs conversion on the channel specified in the RSQ0. When the ADCON has been set high, the ADC samples and converts specified channel, once the corresponding software trigger or TRIGSEL trigger is active.
Page 518: Figure 18-4. Scan Operation Mode, Continuous Disable
GD32H75E User Manual After conversion of a routine sequence, the conversion can be restarted automatically if the CTN bit in the ADC_CTL1 register is set. Figure 18-4. Scan operation mode, continuous disable Software procedure for scan operation mode on a routine sequence: Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register Configure ADC_RSQx registers.
Page 519: Figure 18-6. Discontinuous Operation Mode
GD32H75E User Manual Figure 18-6. Discontinuous operation mode · · · CH11 CH16 CH12 CH17 Routine trigger One circle of routine sequence, RL=7, DISNUM=3'b010 Software procedure for discontinuous operation mode on a routine sequence: Set the DISRC bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register.
Page 520: Data Storage Mode
GD32H75E User Manual converted (after oversample) with a low threshold or a high threshold. If OVSEN = 0, analog watchdog 0/1/2 can compare the analog voltage converted (before oversample) with a low threshold or a high threshold. Data storage mode 18.4.8.
Page 521: External Trigger Configuration
GD32H75E User Manual CK_ADC = 40MHz and sample time is 3.5 cycles, the total conversion time is “3.5+12.5” CK_ADC cycles, that means 0.4 us. External trigger configuration 18.4.10. The conversion of routine sequence can be triggered by rising edge of TRIGSEL or software.
Page 522 GD32H75E User Manual ADC internal channels 18.4.13. When the TSVEN1 bit of ADC_CTL1 register is set, the temperature sensor channel (ADC2_CH18) is enabled. When the TSVEN2 bit of ADC_CTL1 register is set, the high- precison temperature sensor channel (ADC2_CH20) is enabled when the INREFEN bit of ADC_CTL1 register is set, the VREFINT channel (ADC1_CH17/ADC2_CH19) is enabled.
Page 523: Battery Voltage Monitoring
GD32H75E User Manual (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the temperature data(V ) in the ADC data register, and get the temperature temperature with the following equation. Temperature (°C) = {(V –...
Page 524: Table 18-5. T Conv Timings Depending On Resolution For Adc0 And Adc1
GD32H75E User Manual Figure 18-10. Schematic diagram of handshake signal between HPDF and ADC module Programmable resolution (DRES) 18.4.16. The resolution can be configured to be either 14, 12, 10, 8, or 6 bits by programming the DRES[1:0] bits in the ADC_CTL0 register. For applications that do not require high data accuracy, lower resolution allows faster conversion time.
Page 525: Figure 18-11. 20-Bit To 16-Bit Result Truncation (For 12Bit Adc)
GD32H75E User Manual digital signal of the ADC: Result= * ∑ (18-2) For 14bit-ADC, the on-chip hardware oversampling circuit performs the following functions: summing and bit right shifting. The oversampling ratio N is defined by the OVSR[9:0] bits in the ADC_OVSAMPCTL register. It can range from 2x to1024x. The division coefficient M means bit right shifting up to 11-bit.
Page 526: Figure 18-12. Numerical Example With 5-Bits Shift And Rounding (For 12Bit Adc)
GD32H75E User Manual Figure 18-12. Numerical example with 5-bits shift and rounding (for 12bit ADC) Figure 18-13. 14bit ADC oversampling with 10bits right shift Raw 24-bit data Shifting(10 bit) Figure 18-14. Numerical example for 14bit ADC oversampling with 10bits right shift...
Page 527: Table 18-8. Adc Sync Mode Table
GD32H75E User Manual 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Oversa shift shift shift shift shift shift shift shift shift mpling OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= ratio data 0000 0001 0010 0011 0100 0101 0110...
Page 528: Figure 18-15. Adc Sync Block Diagram
GD32H75E User Manual The ADC sync scheme is shown in Figure 18-15. ADC sync block diagram Figure 18-15. ADC sync block diagram Routine Routine data registers （32 bits ） channels ADC1 （slave） ADC_IN0 ADC_IN1 GPIO Routine data registers Routine （32 bits ）...
Page 529: Figure 18-17. Routine Follow-Up Mode On 1 Channel In Continuous Operation Mode
GD32H75E User Manual Note: Do not convert the same channel on two ADCs at a given time (no overlapping sampling times for the ADCs when converting the same channel). 2. Make sure to trigger the ADCs when none of them is converting (do not trigger ADC0 when some of the conversions are not finished).
Page 530: Adc Interrupts
GD32H75E User Manual from ADC_SYNCDATA0 or ADC_SYNCDATA1 register. There are two DMA work modes, which can work well with the various ADC sync modes. ADC sync DMA mode 0 In ADC sync DMA mode 0, the bitwidth of DMA transfer is 32. One DMA request transfers one data, which is selected from the routine data of the ADCs in turn.
Page 531: Register Definition
GD32H75E User Manual Register definition 18.7. ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 2C00 Status register (ADC_STAT) 18.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 532 GD32H75E User Manual 0: Conversion is not started 1: Conversion is started Set by hardware when routine sequence conversion starts. Cleared by software writing 0 to it. Reserved Must be kept at reset value. End flag of routine sequence conversion...
Page 533 GD32H75E User Manual 25:24 DRES[1:0] ADC data resolution for ADC0/ADC1 00: 14bit 01: 12bit 10: 10bit 11: 8bit ADC data resolution for ADC2 00: 12bit 01: 10bit 10: 8bit 11: 6bit RWD0EN Routine channel analog watchdog 0 enable 0: Routine channel analog watchdog 0 disable...
Page 534 GD32H75E User Manual 00011: ADC channel 3 00100: ADC channel 4 00101: ADC channel 5 00110: ADC channel 6 00111: ADC channel 7 01000: ADC channel 8 01001: ADC channel 9 01010: ADC channel 10 01011: ADC channel 11 01100: ADC channel 12...
Page 535 GD32H75E User Manual 1: high-precision temperature sensor Channel enable Software start conversion of routine sequence . SWRCST Setting 1 on this bit starts a conversion of a routine sequence channels. It is set by software and cleared by software or by hardware immediately after the conversion starts.
Page 536 GD32H75E User Manual 0: Only at the end of a routine sequence conversions, the EOC bit is set. Overflow detection is disabled unless DMA=1. 1: At the end of each routine sequence conversion, the EOC bit is set. Overflow is...
Page 537 GD32H75E User Manual Watchdog high threshold register0 (ADC_WDHT0) 18.7.4. Address offset: 0x1C Reset value: 0x00FF FFFF This register has to be accessed by word (32-bit). Reserved WDHT0[23:16] WDHT0[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. High threshold for analog watchdog 0, For ADC0/ADC1 are WDHT0[23:0], for...
Page 538 GD32H75E User Manual Reserved RL[3:0] Reserved Reserved RSMP15[9:0] RSQ15[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 RL[3:0] Routine channel length. The total number of conversion in routine sequence equals to RL[3:0]+1. 19:15 Reserved Must be kept at reset value.
Page 539 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 540 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 541 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 542 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 543 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 544 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 545 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 546 GD32H75E User Manual 10’d0: For ADC0/1 is 3.5 cycles, For ADC2 is 2.5 cycles 10’d1: For ADC0/1 is 4.5 cycles, For ADC2 is 3.5 cycles 10’d2: For ADC0/1 is 5.5 cycles, For ADC2 is 4.5 cycles 10’d3: For ADC0/1 is 6.5 cycles, For ADC2 is 5.5 cycles 10’d4: For ADC0/1 is 7.5 cycles, For ADC2 is 6.5 cycles...
Page 547 GD32H75E User Manual Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:16 OVSR[9:0] Oversampling ratio This bit filed defines the number of oversampling ratio. ADC0/1 is 1x~1024x. ADC2 is 1X~256X. 10’d0: 1x(no oversampling) 10’d1: 2x 10’d2: 3x ……...
Page 548 GD32H75E User Manual This bit is set and cleared by software. 0: Oversampler disabled 1: Oversampler enabled Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress). Watchdog 1 Channel Selection Register (ADC_WD1SR) 18.7.17.
Page 549 GD32H75E User Manual AWD2CS[15:0] Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:0 AWD2CS[20:0] Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2.
Page 550 GD32H75E User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WDLT1[23:16] WDLT1[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. Low threshold for analog watchdog 1. For ADC0/1 are WDLT1[23:0], for ADC2 is...
Page 551 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved WDLT2[23:16] WDLT2[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. Low threshold for analog watchdog 2. For ADC0/1 are WDLT2[23:0], for ADC2 is 23:0 WDLT2[23:0] WDLT2[7:0].
Page 552 GD32H75E User Manual Reset value: 0x0000 0000 This register is read only and provides a summary of the three ADCs. This register is not available in ADC1 and ADC2. This register has to be accessed by word (32-bit). ADC2_RO ADC2_ST...
Page 553 GD32H75E User Manual ADC0_WDE2 This bit is the mirror image of the WDE2 bit of ADC0 ADC0_WDE1 This bit is the mirror image of the WDE1 bit of ADC0 ADC0_WDE0 This bit is the mirror image of the WDE0 bit of ADC0 Sync control register (ADC_SYNCCTL) 18.7.25.
Page 554 GD32H75E User Manual 4'b1000:HCLK div2(sync clock mode) 4'b1001:HCLK div4(sync clock mode) 4'b1010:HCLK div6(sync clock mode) 4'b1011:HCLK div8(sync clock mode) 4'b1100:HCLK div10(sync clock mode) 4'b1101:HCLK div12(sync clock mode) 4'b1110:HCLK div14(sync clock mode) 4'b1111:HCLK div16(sync clock mode) All other values are reserved.
Page 555 GD32H75E User Manual SYNCDATA1[15:0] SYNCDATA0[15:0] Bits Fields Descriptions 31:16 SYNCDATA1[15:0] Routine data1(slave adc routine data) in ADC sync mode. SYNCDMA[1:0] must be 2’b10. 15:0 SYNCDATA0[15:0] Routine data0 (master adc routine data) in ADC sync mode. SYNCDMA[1:0] must be 2’b10, Sync routine data register1 (ADC_SYNCDATA1) 18.7.27.
Page 556: Digital-To-Analog Converter (Dac)
GD32H75E User Manual Digital-to-analog converter (DAC) Overview 19.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers.
Page 557: Table 19-1. Dac I/O Description
GD32H75E User Manual Figure 19-1. DAC block diagram DAC control register MODEx TRIGSEL OTVx DAC_CALR SWTRx DAC_ENx Control logic buff Sample and keep Wave OUTx_DH OUTx_DO (optional) 12-bit 12-bit 12-bit 12-bit Table 19-1. DAC I/O description Name Description Signal type...
Page 558: Function Description
GD32H75E User Manual Function description 19.3. DAC enable 19.3.1. The DAC can be turned on by setting the DENx bit in the DAC_CTL0 register. A t time WAKEUP is needed to startup the analog DAC submodule. DAC output buffer 19.3.2.
Page 559: Figure 19-2. Dac Lfsr Algorithm
GD32H75E User Manual automatically. When the DAC holding data (OUTx_DH) is loaded into the OUTx_DO register, after the time which is determined by the analog output load and the power supply voltage, the SETTLING analog output is valid. DAC noise wave 19.3.6.
Page 560: Figure 19-3. Dac Triangle Noise Wave
GD32H75E User Manual Figure 19-3. DAC triangle noise wave DAC output voltage 19.3.7. The following equation determines the analog output voltage on the DAC pin. *OUTx_DO/4096 (19-1) DAC_OUT REFP The digital input is linearly converted to an analog output voltage, its range is 0 to V...
Page 561 GD32H75E User Manual on the application scenario. DAC output buffer calibration 19.3.10. The output voltage may be offset when DAC use buffer, so it is necessary to compensate output voltage. The DAC calibration transfer function is: =(D/2 N−1 )*G*V (19-2)
Page 562: Normal Mode
GD32H75E User Manual DAC modes 19.3.11. DAC can be set to normal mode or sample and keep mode. The DAC out can be connected to external pin or on chip peripherals. Normal mode When the MODEx[2] bit in the DAC_MDCR register is 0, DAC is in normal mode.
Page 563: Figure 19-4. Dac Sample And Keep
GD32H75E User Manual Table 19-4. Formula of sample and refresh time Buffer State sample refresh keep *ln(2 *ln(2*N wakeup wakeup REFP leak *ln(2 *ln(2*N wakeup BOFF wakeup BOFF REFP leak Note: (1) In the above formula, the t is wakeup time from off state to the DAC output reaches wakeup final value, the charge time is calculated with 1/2 LSB error accuracy to desired output voltage.
Page 564: Standby Mode
GD32H75E User Manual Standby mode In Standby mode, DAC stops working. When exting from the standby mode, the DAC need to be reinitialized to work again.
Page 565 GD32H75E User Manual DAC register 19.4. DAC0 base address: 0x4000 7400 DACx control register 0 (DAC_CTL0) 19.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DDUDR DDMA Reserved CALEN1 DWBW1[3:0] DWM1[1:0] Reserved...
Page 566 GD32H75E User Manual 0110: The bit width of the wave signal is 7 0111: The bit width of the wave signal is 8 1000: The bit width of the wave signal is 9 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12...
Page 567 GD32H75E User Manual triangle is ((2<<(n-1))-1) in triangle noise mode, where n is the bit width of wave. 0000: The bit width of the wave signal is 1 0001: The bit width of the wave signal is 2 0010: The bit width of the wave signal is 3...
Page 568 GD32H75E User Manual Reserved SWTR1 SWTR0 Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DACx_OUT1 software trigger, cleared by hardware. 0: Software trigger disabled 1: Software trigger enabled SWTR0 DACx_OUT0 software trigger, cleared by hardware. 0: Software trigger disabled...
Page 569 GD32H75E User Manual Reserved OUT0_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 OUT0_DH[11:0] DACx_OUT0 12-bit left-aligned data. These bits specify the data that is to be converted by DACx_OUT0. Reserved Must be kept at reset value.
Page 570 GD32H75E User Manual Reserved OUT1_DH[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 OUT1_DH[11:0] DACx_OUT1 12-bit right-aligned data. These bits specify the data that is to be converted by DACx_OUT1. DACx_OUT1 12-bit left-aligned data holding register 19.4.7.
Page 571 GD32H75E User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. OUT1_DH[7:0] DACx_OUT1 8-bit right-aligned data These bits specify the MSB 8-bit of the data that is to be converted by DACx_OUT1. DACx concurrent mode 12-bit right-aligned data holding register 19.4.9.
Page 572 GD32H75E User Manual Bits Fields Descriptions 31:20 OUT1_DH[11:0] DACx_OUT1 12-bit left-aligned data These bits specify the data that is to be converted by DACx_OUT1. 19:16 Reserved Must be kept at reset value. 15:4 OUT0_DH[11:0] DACx_OUT0 12-bit left-aligned data These bits specify the data that is to be converted by DACx_OUT0.
Page 573 GD32H75E User Manual Reserved OUT0_DO [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 OUT0_DO [11:0] DACx_OUT0 12-bit output data These bits, which are read only, storage the data that is being converted by DACx_OUT0. DACx_OUT1 data output register (DAC_OUT1_DO) 19.4.13.
Page 574 GD32H75E User Manual BWT1 DACx_OUT1 SKSTR1 writing flag. This bit is set by the system when the sample and keep mode is enabled. When the DACx_SKSTR1 is writing,the bit is set, when the write operation is complete, the bit is cleared by hardware.
Page 575 GD32H75E User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:16 OTV1[4:0] DACx_OUT1 offset calibration value. 15:5 Reserved Must be kept at reset value. OTV0[4:0] DACx_OUT0 offset calibration value. DACx mode control register (DAC_MDCR) 19.4.16. Address offset: 0x3C Reset value: 0x00XX 00XX This register has to be accessed by word(32-bit).
Page 576 GD32H75E User Manual These bits can be written when bit DEN0=0 and bit CALEN0=0 in the DACx_CTL0 register, the write operation is invalid when DEN0=1 or CALEN0=1. DACx_OUT0 in normal mode 000: Buffer is enabled and DACx_OUT0 is connected to external pin 001: Buffer is enabled and DACx_OUT0 is connected to on chip peripherals and to external pin.
Page 577 GD32H75E User Manual Reserved TSAMP1[9:0] rc_w1 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TSAMP1[9:0] DACx_OUT1 sample time. DACx sample and keep keep time register (DAC_SKKTR) 19.4.19. Address offset: 0x48 Reset value: 0x0001 0001 This register has to be accessed by word(32-bit).
Page 578 GD32H75E User Manual 23:16 TREF1[7: 0] DACx_OUT1 refresh time. 15:8 Reserved Must be kept at reset value. TREF0[7: 0] DACx_OUT0 refresh time.
Page 579 GD32H75E User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 580: Figure 20-1. Free Watchdog Block Diagram
GD32H75E User Manual Figure 20-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then counter starts counting down. When the counter reaches the value (0x000), there will be a reset.
Page 581: Table 20-1. Min/Max Fwdgt Timeout Period At 32Khz (Irc32K)
GD32H75E User Manual Table 20-1. Min/max FWDGT timeout period at 32KHz (IRC32K) Min timeout (ms) RLD[11:0]= Max timeout (ms) RLD[11:0]= Prescaler divider PSC[2:0] bits 0x000 0xFFF 0.125 0.25 1024 1/16 2048 1/32 4096 1/64 8192 1/128 16384 1/256 110 or 111 32768 The FWDGT timeout can be more accurately by calibrating the IRC32K.
Page 582 GD32H75E User Manual Register definition 20.1.4. FWDGT base address: 0x5800 4800 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 583 GD32H75E User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1/4 001: 1/8 010: 1/16 011: 1/32 100: 1/64 101: 1/128 110: 1/256 111: 1/256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit has been reset before changing the prescaler value.
Page 584 GD32H75E User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Watchdog counter window value update When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 585 GD32H75E User Manual These bits are write protected. Write 0x5555 in the FWDGT_CTL register before writing these bits. If several window values are used by the application, it is mandatory to wait until WUD bit has been reset before changing the window value. However, after updating...
Page 586: Figure 20-2. Window Watchdog Timer Block Diagram
GD32H75E User Manual Window watchdog timer (WWDGT) 20.2. Overview 20.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 587: Figure 20-3. Window Watchdog Timing Diagram
GD32H75E User Manual The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F(it implies that the CNT[6] bit should be set).
Page 588: Table 20-2. Min-Max Timeout Value At 150 Mhz
GD32H75E User Manual Table 20-2. Min-max timeout value at 150 MHz (f PCLK3 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 27.30 μs 1.75 ms 54.61 μs 3.50 ms 109.22 μs 6.99 ms 218.45 μs 13.98 ms If the WWDGT_HOLD bit in DBG module is cleared, the WWDGT continues to work even the ®...
Page 589 GD32H75E User Manual Register definition 20.2.4. WWDGT base address: 0x5000 3000 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 590 GD32H75E User Manual operation of 0 has no effect. PSC[1:0] Prescaler. The time base of the watchdog counter 00: (PCLK3 / 4096) / 1 01: (PCLK3 / 4096) / 2 10: (PCLK3 / 4096) / 4 11: (PCLK3 / 4096) / 8 WIN[6:0] The Window value.
Page 591: Real Time Clock (Rtc)
GD32H75E User Manual Real time clock (RTC) Overview 21.1. The RTC provides a time which includes hour / minute / second / sub-second and a calendar includes year / month / day / week day. The time and calendar are expressed in BCD code except sub-second.
Page 592: Figure 21-1. Block Diagram Of Rtc
GD32H75E User Manual Function overview 21.3. Block diagram 21.3.1. Figure 21-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre...
Page 593 GD32H75E User Manual RTCDIV[5:0] (configured in RCU_CFG0 register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. Asynchronous prescaler is mainly used for reducing power consumption.
Page 594: Rtc Initialization And Configuration
GD32H75E User Manual Configurable periodic auto-wakeup counter 21.3.5. In the RTC block, there is a 16-bit down counter designed to generate periodic wakeup flag. This function is enabled by set the WTEN to 1 and can be running in power saving mode.
Page 595: Calendar Initialization And Configuration
GD32H75E User Manual Calendar initialization and configuration The prescaler and calendar value can be programmed by the following steps: Enter initialization mode (by setting INITM=1) and polling INITF bit until INITF=1. Program both the asynchronous and synchronous prescaler factors in RTC_PSC register.
Page 596 GD32H75E User Manual reading calendar time register and date register twice if the two values are equal, the value can be seen as the correct value if the two values are not equal, a third reading should performed the third value can be seen as the correct value RSYNF is asserted once every 2 RTC clock and at this time point, the shadow registers will be updated to current time and date.
Page 597: Resetting The Rtc
GD32H75E User Manual Resetting the RTC 21.3.8. There are two reset sources used in RTC unit: system reset and backup domain reset. System reset will affect calendar shadow registers and some bits of the RTC_STAT. When system reset is valid, the bits or registers mentioned before are reset to the default value.
Page 598: Rtc Reference Clock Detection
GD32H75E User Manual RTC reference clock detection 21.3.10. RTC reference clock detection is another way to increase the precision of RTC second. To enable this function, you should have an external clock source (50Hz or 60 Hz) which is more precise than LXTAL clock source.
Page 599: Verifying The Rtc Calibration
GD32H75E User Manual So using CMSK can mask clock cycles from 0 to 511 and thus the RTC frequency can be reduced by up to 487.1PPM. To increase the RTC frequency the FREQI bit can be set. If FREQI bit is set, there will be 512 additional cycles to be added during period time which means every 211/210/29(32/16/8 seconds) RTC clock insert one cycle.
Page 600: Re-Calibration On-The-Fly
GD32H75E User Manual the measure is within 0.477PPM (0.5 RTCCLK cycles over 32s)  When the calibration period is 16 seconds(by setting CWND16 bit) In this configuration, CMSK[0] is fixed to 0 by hardware. Using exactly 16s period to measure the accuracy of the calibration 1Hz output can guarantee the measure is within 0.954PPM...
Page 601: Timestamp On Tamper Event
GD32H75E User Manual mode or level detection mode with configurable filtering setting. The purposes of the tamper detect configuration are the following:  The default configuration will erase the RTC backup registers and BKP sramr  It can wakeup from DeepSleep and Standby modes, and generate an interrupt...
Page 602: Calibration Clock Output
GD32H75E User Manual writing. Tamper detection is still running when V power is switched off if tamper is enabled. Note: Level detection mode with configurable filtering on tamper input detection When FLT bit is not reset to 0x0, the tamper detection is set to level detection mode and FLT bit determines the consecutive number of samples (2, 4 or 8) needed for valid level.
Page 603: Table 21-1 Rtc Pin Configuration And Function
GD32H75E User Manual Table 21-1 RTC pin configuration and function function COEN TP0EN TSEN ALRMOUTTYPE OS[1:0] (output configuration (calibration (tamper (time stamp (RTC_ALARM selection) and pin function output) enabled) enabled) output type Alarm out 01 or 10 or 11 output open drain...
Page 604: Table 21-3 Rtc Interrupts Control
GD32H75E User Manual RTC interrupts 21.3.18. All RTC interrupts are connected to the EXTI controller. Below steps should be followed if you want to use the RTC alarm / tamper / timestamp / auto wakeup interrupt: Configure enable corresponding interrupt...
Page 605: Register Definition
GD32H75E User Manual Register definition 21.4. RTC base address: 0x5800 4000 Time register (RTC_TIME) 21.4.1. Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state...
Page 606 GD32H75E User Manual Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0] Days of the week...
Page 607 GD32H75E User Manual 1: Enable Internal timestamp event COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output...
Page 608 GD32H75E User Manual ALRM0IE RTC alarm-0 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt TSEN Time-stamp function enable 0: Disable time-stamp function 1: Enable time-stamp function WTEN Auto-wakeup timer function enable 0: Disable function 1: Enable function ALRM1EN...
Page 609 GD32H75E User Manual 0x6:0x7: ck_spre (default 1Hz) clock and 2 is added to wake-up counter. Status register (RTC_STAT) 21.4.4. Address offset: 0x0C System reset: Only INITM, INITF and RSYNF bits are set to 0. Others are not affected Backup domain reset value: 0x0000 0007 This register is writing protected except RTC_STAT[13:8].
Page 610 GD32H75E User Manual Wakeup timer flag Set by hardware when wakeup timer decreased to 0. Cleared by software writing 0. This flag must be cleared at least 1.5 RTC Clock periods before WTF is set to 1 again. ALRM1F Alarm-1 occurs flag Set to 1 by hardware when current time/date matches the time/date of alarm 1 setting value.
Page 611 GD32H75E User Manual 1: Wakeup timer update is allowed ALRM1WF Alarm 1 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM1EN bit has reset. 0: Alarm registers programming is not allowed 1: Alarm registers programming is allowed...
Page 612 GD32H75E User Manual WTRV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 WTRV[15:0] Auto-wakeup timer reloads value. Every (WTRV[15:0]+1) ck_wut period the WTF bit is set after WTEN=1.The ck_wut is selected by WTCS[2:0] bits. Note: This configure case is forbidden: WTRV=0x0000 with WTCS[2:0]=0b011.
Page 613 GD32H75E User Manual 1: PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit 0: Not mask minutes field 1: Mask minutes field 14:12 MNT[2:0] Minutes tens in BCD code...
Page 614 GD32H75E User Manual 0: Not mask hour field 1: Mask hour field AM/PM flag 0: AM or 24-hour format 1: PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit...
Page 615 GD32H75E User Manual This register has to be accessed by word (32-bit) Reserved SSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SSC[15:0] Sub second value This value is the counter value of synchronous prescaler. Second fraction value is...
Page 616 GD32H75E User Manual Time of time stamp register (RTC_TTS) 21.4.12. Address offset: 0x30 Backup domain reset value: 0x0000 0000 System reset: no effect This register will record the calendar time when TSF is set to 1. Reset TSF bit will also clear this register.
Page 617 GD32H75E User Manual Reserved DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:13 DOW[2:0] Days of the week MONT Month tens in BCD code 11:8 MONU[3:0] Month units in BCD code Reserved Must be kept at reset value.
Page 618 GD32H75E User Manual This register is write protected. This register has to be accessed by word (32-bit) Reserved FREQI CWND8 CWND16 Reserved CMSK[8:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. FREQI Increase RTC frequency by 488.5PPM...
Page 619 GD32H75E User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. DISPU RTC_TAMPx pull up disable bit 0: Enable inner pull-up before sampling for pre-charge RTC_TAMPx pin 1: Disable pre-charge duration 14:13 PRCH[1:0] Pre-charge duration time of RTC_TAMPx This setting determines the pre-charge time before each sampling.
Page 620 GD32H75E User Manual 0: Low level triggers a tamper detection event 1: High level triggers a tamper detection event TP1EN Tamper 1 detection enable 0:Disable tamper 1 detection function 1:Enable tamper 1 detection function Reserved Must be kept at reset value.
Page 621 GD32H75E User Manual 0x2: SSC[1:0] is to be compared and all others are ignored 0x3: SSC[2:0] is to be compared and all others are ignored 0x4: SSC[3:0] is to be compared and all others are ignored 0x5: SSC[4:0] is to be compared and all others are ignored...
Page 622 GD32H75E User Manual 0x4: SSC[3:0] is to be compared and all others are ignored 0x5: SSC[4:0] is to be compared and all others are ignored 0x6: SSC[5:0] is to be compared and all others are ignored 0x7: SSC[6:0] is to be compared and all others are ignored...
Page 623 GD32H75E User Manual Backup registers (RTC_BKPx) (x=0..31) 21.4.20. Address offset: 0x50~0xCC Backup domain reset: 0x0000 0000 System reset: no effect This register has to be accessed by word (32-bit) DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be wrote or read by software. The content remains valid even in power saving mode because they can powered-on by VBAT.
Page 624: Table 22-1. Timers (Timerx) Are Divided Into Five Sorts
GD32H75E User Manual TIMER (TIMERx) Table 22-1. Timers (TIMERx) are divided into five sorts TIMER14/40 TIMER15/ TIMER TIMER0/7 TIMER1/2/3/4/22/23 TIMER5/6/50/51 /41/42/43/44 General- TYPE Advanced General-L0 General-L3 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit(TIMER2/3/30/31) 32-bit (TIMER5/6) Counter 16-bit 16-bit 16-bit...
Page 625 GD32H75E User Manual TIMER14/40 TIMER15/ TIMER TIMER0/7 TIMER1/2/3/4/22/23 TIMER5/6/50/51 /41/42/43/44 Connection ● ● ● ● ● ● ● ● ● ● Debug Mode TIMERx ITI0 ITI1 ITI2 ITI3 ITI4 ITI5 ITI6 ITI7 ITI8 ITI9 ITI10 ITI11 ITI12 ITI13 ITI14 TIMER14...
Page 626 GD32H75E User Manual Advanced timer (TIMERx, x=0, 7) 22.1. Overview 22.1.1. The advanced timer module (TIMER0/7) is an eight-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 627: Figure 22-1. Advanced Timer Block Diagram
GD32H75E User Manual Block diagram 22.1.3. Figure 22-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer, and Table 22-2. Advanced timer channel description introduces the input and output of the channels. Figure 22-1. Advanced timer block diagram...
Page 628: Figure 22-2. Normal Mode, Internal Clock Divided By 1
GD32H75E User Manual clock CK_TIMER is selected as timer clock source which is from module RCU. The default clock source is the CK_TIMER for driving the counter prescaler when TSCFGy[4:0] (y=0..9,15) = 5’b00000 in SYSCFG_TIMERxCFG(x=0,7) registers. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK.
Page 629: Clock Prescaler
GD32H75E User Manual source is setting the TSCFG6[4:0] to 0x8. Note that the ETI signal is derived from the ETI pin sampled by a digital filter. When the ETI signal is selected as the clock source, the trigger controller including the edge detection circuitry will generate a clock pulse on each ETI signal rising edge to clock the counter prescaler.
Page 630: Figure 22-4. Timing Diagram Of Up Counting Mode, Psc=0/2
GD32H75E User Manual TIMERx_SWEVG register, the counter value will be initialized to 0 and an update event will be generated. If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled. When an update event occurs, all the registers (repetition counter register, auto reload register, prescaler register) are updated.
Page 631: Figure 22-5. Timing Diagram Of Up Counting Mode, Change Timerx_Car Ongoing
GD32H75E User Manual Figure 22-5. Timing diagram of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120...
Page 632: Figure 22-7. Timing Diagram Of Down Counting Mode, Change Timerx_Car Ongoing
GD32H75E User Manual Figure 22-6. Timing diagram of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 22-7.
Page 633: Figure 22-8. Timing Diagram Of Center-Aligned Counting Mode
GD32H75E User Manual Center-aligned counting mode In the center-aligned counting mode, the counter counts up from 0 to the counter reload value and then counts down to 0 alternatively. The timer module generates an overflow event when the counter counts to (TIMERx_CAR-1) in the count-up direction and generates an underflow event when the counter counts to 1 in the count-down direction.
Page 634 GD32H75E User Manual Figure 22-8. Timing diagram of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b01 (downcount only CHxIF Hardware set Software clear...
Page 635: Figure 22-9. Repetition Counter Timing Diagram Of Center-Aligned Counting Mode
GD32H75E User Manual value of CREP0/1 is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP0/1 value takes effect. If an update event is generated by software after writing an odd number to CREP0/1, the update events will be generated on the underflow.
Page 636: Figure 22-11. Repetition Counter Timing Diagram Of Down Counting Mode
GD32H75E User Manual Figure 22-11. Repetition counter timing diagram of down counting mode TIMER_CK CNT_CLK CNT_REG 00 63 00 63 00 63 00 63 00 63 Underflow Overflow TIMERx_CREP0 = 0x0 UPIF TIMERx_CREP0 = 0x1 UPIF TIMERx_CREP0 = 0x2 UPIF...
Page 637: Figure 22-12. Input Capture Logic For Channel 0
GD32H75E User Manual Figure 22-12. Input capture logic for channel 0 Edge Detector Synchronizer Edge selector &inverter Filter Based on CH0P&MCH0P TIMER_CK CI0FE0 Rising/Falling CI0F_ED Capture CI1FE0 Clock Counter Prescaler Register Prescaler MCI0FE0 （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT...
Page 638: Output Compare Mode
GD32H75E User Manual CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits. Step3: Capture source selection (CHxMS bit in TIMERx_CHCTL0 register, MCHxMS bit in TIMERx_MCHCTL0 register).
Page 639: Figure 22-15. Output Compare Logic (When Mchxmsel = 2'11, X=0,1,2,3)
GD32H75E User Manual Figure 22-14. Output compare logic (when MCHxMSEL = 2’00, x=0, 1, 2, 3) OxCPRE/MOxCPRE Capture/ CNT>CHxCV/ Compare register MCHxCV CHxCV/MCHxCV Compare output Output enable and CNT=CHxCV/ CHx_O control polarity selector MCHxCV CHxCOMCTL/ CHxP,CHxEN/ CNT<CHxCV/ MCHx_O MCHxCOMCTL MCHxFP,MCHxEN...
Page 640 GD32H75E User Manual If the output of MOxCPRE is active(high) level, the output of MCHx_O is active(low) level; If the output of MOxCPRE is inactive(low) level, the output of MCHx_O is active(high) level. When MCHxMSEL=2’b11 and CHx_O and MCHx_O are output at the same time, the specific outputs of CHx_O and MCHx_O are related to the relevant bits (ROS, IOS, POE and DTCFG bits) in the TIMERx_CCHP register.
Page 641: Figure 22-16. Output-Compare In Three Modes
GD32H75E User Manual Figure 22-16. Output-compare in three modes CNT_CLK CNT_REG 03 04 03 04 Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL/ MCHxCOMCTL bit to 4’b0110 (PWM mode 0) or to 4’b0111(PWM mode 1)), the channel can generate PWM waveform according...
Page 642 GD32H75E User Manual Figure 22-17. Timing diagram of EAPWM CARL CHxVAL PWM MODE0 OxCPRE PWM MODE1 OxCPRE Interrupt signal CHxIF CHxOF Figure 22-18. Timing diagram of CAPWM CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CAM=2'b01 down only...
Page 643: Table 22-3.The Composite Pwm Pulse Width
GD32H75E User Manual x output is forced high when the counter matches the value of CHxVAL. It is forced low when the counter matches the value of CHxCOMVAL_ADD. The PWM period is determined by (CARL + 0x0001) and the PWM pulse width is determined by the following table.
Page 644: Figure 22-19. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32H75E User Manual Figure 22-19. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF...
Page 645: Figure 22-22. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32H75E User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1...
Page 646: Figure 22-24. Four Channels Outputs In Composite Pwm Mode
GD32H75E User Manual CARL CHxVAL next counter next counter period period PWM MODE 1 OxCPRE PWM MODE 0 OxCPRE Interrupt signal CHxIF CHxCOMADDIF CHxCOMVAL_ADD match If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels.
Page 647: Figure 22-25. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel≠2'B00)
GD32H75E User Manual  CHxOMPSEL = 2’b00, the OxCPRE signal is output normally with the configuration of CHxCOMCTL[3:0] bits; CHxOMPSEL = 2’b01, only the counter is counting up, the OxCPRE signal is output a  pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle.
Page 648 GD32H75E User Manual Channel output prepare signal Figure 22-14. Output compare logic (when MCHxMSEL = 2’00, x=0, 1, 2, As is shown in Figure 22-15. Output compare logic (when MCHxMSEL = 2’11, x=0,1,2,3), when TIMERx is configured in compare match output mode, a middle signal named OxCPRE or MOxCPRE (channel x output or multi mode channel x output prepare signal) will be generated before the channel outputs signal.
Page 649: Table 22-4. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32H75E User Manual When the the outputs of CHx_O and MCHx_O are complementary, there are three situations: output enable、output off-state and output disabled. The details are shown in Table 22-4. =2’b11). Complementary outputs controlled by parameters (MCHxMSEL Table 22-4. Complementary outputs controlled by parameters (MCHxMSEL =2’b11)
Page 650: Figure 22-27. Complementary Output With Dead Time Insertion
GD32H75E User Manual (4) ⊕: Xor calculate. (5) (! OxCPRE)：the complementary output of the OxCPRE signal. Dead time insertion The dead time insertion is enabled when MCHxMSEL=2’b11 and both CHxEN and MCHxEN are configured to 1’b1, it is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for all channels.
Page 651: Figure 22-28. Break0 Function Logic Diagram
GD32H75E User Manual independent control of dead-time insertion function for each pair of channels. When the DTIENCHx (x=0...3) bit is “0”, the corresponding channels CHx_O and CHx_ON will not be inserted into the dead-time. Break function The MCHx_O output is the inverse of the CHx_O output when the MCHxMSEL=2’b11 (and the MCHxOMCTL bits are not used in the generation of the MCHx_O output).
Page 652: Figure 22-29. Break1 Function Logic Diagram
GD32H75E User Manual Figure 22-29. BREAK1 function logic diagram BREAK0 can be used to handle the faults of system sources, on-chip peripheral events and external sources. When a BREAK0 event occurs, the outputs are force at an inactive level, or at a predefined level (either active or inactive) after a deadtime duration. BREAK1 only can be used to handle the faults of on-chip peripheral events and external sources.
Page 653: Figure 22-31. Output Behavior Of The Channel Outputs With The Break0 And Break1
GD32H75E User Manual used when the IOS =1 and ROS =1. Table 22-5. Output behavior of the channel in response to a BREAK0 and BREAK1 (the break input is high active) Output Status BREAK BREAK 0 inputs 1 inputs CHx_O...
Page 654: Table 22-6. Break Function Input Pins Locked/ Released Conditions
GD32H75E User Manual Locked break function The BRKINx(x=0...2) input pins of advanced timer have the locked break function, this function can be enabled by setting the BRK0LK and BRK1LK bits in the TIMERx_CCHP register. When the locked break function is enabled, the BRKINx(x=0...2) pins need to be configured to open-drain output mode with low level active (BRK0P/ BRK1P=0 and BRK0INxP/ BRK1INxP=0).
Page 655: Figure 22-32. Brkinx (X=0
GD32H75E User Manual Figure 22-32. BRKINx (x=0...2) pins logic with BREAK0 function CKM clock monitor LVD lock event LOCKUP_LOCK event SYSBIF BRK0G SRAM parity error event System source Flash ECC error requests BRK0EN HPDF_OUT BRK0HPDFEN Output Logic CMP0_OUT BRK0CMP0EN BRK0CMP0P...
Page 656: Figure 22-33. Example Of Counter Operation In Decoder Interface Mode
GD32H75E User Manual Table 22-7. Counting direction in different quadrature decoder signals CI0FE0 CI1FE1 Counting mode Level Rising Falling Rising Falling CI1FE1=1 Down Quadrature decoder mode 0 TSCFG0[4:0]!= 5’b00000 CI1FE1=0 Down Quadrature decoder mode 1 CI0FE0=1 Down TSCFG1[4:0]!= 5’b00000 CI0FE0=0...
Page 657: Figure 22-35. Quadrature Decoder Signal Disconnection Detection Block Diagram
GD32H75E User Manual jump edges (rising or falling) of the CI0 and CI1 signals occur at the same time. When DECJDEN =1, if the level transitions of the two quadrature signals CI0 and CI1 occur simultaneously, the interrupt flag DECJIF is set, if DECJIE=1, the corresponding interrupt is generated.
Page 658: Figure 22-37. Example Of Counter Operation In Non-Quadrature Decoder Mode 1 With Ch0P=0
GD32H75E User Manual CH1P=0 When the non-quadrature decoder mode 1 is enabled, the CI0 signal is used as the count pulse (with the CH0P is used to select the counter edge) and the CI1 signal is used as the count direction selection. The more details is shown in Table 22-8.
Page 659: Figure 22-38. Hall Sensor Is Used For Bldc Motor
GD32H75E User Manual Hall sensor function Hall sensor is generally used to control BLDC motor; the advanced timer supports this function. Figure 22-38. Hall sensor is used for BLDC motor shows how to connect the timer and the motor. And two timers are needed. TIMER_in(Advanced/General L0 TIMER） is used to accept three rotor position signals of motor from hall sensors.
Page 660: Figure 22-39. Hall Sensor Timing Between Two Timers
GD32H75E User Manual Figure 22-39. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O MCH0_O CH1_O MCH1_O CH2_O MCH2_O Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode and so on, which is selected by the TSCFGy[4:0] (y=3..7) in...
Page 661: Figure 22-40. Restart Mode
GD32H75E User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 01000: ETIFP trigger input ETI) is used 01001: CI2FE2 selected as the trigger configuring ETFC and 01010: CI3FE3 source, configure the prescaler can be used 01011: MCI0FEM0 polarity by configuring ETPSC.
Page 662: Figure 22-41. Pause Mode
GD32H75E User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 22-41. Pause mode Event mode ETPSC = 1, ETI is The counter will start to TSCFG5[4:0] ETP = 0, the polarity of divided by 2. =5’b01000, count when a rising ETI does not change.
Page 663: Figure 22-43. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X60
GD32H75E User Manual pulse mode, the OxCPRE signal will immediately be forced to the state which the OxCPRE/ MOxCPRE signals will change to, as the compare match event occurs without taking the comparison result into account. Single pulse mode is also applicable to composite PWM mode (CHxCPWMEN = 1’b1 and CHxMS[2:0] = 3’b000).
Page 664: Figure 22-44. Delayable Single Pulse Mode With Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32H75E User Manual Note: 1) The center-aligned counting mode cannot be used in this mode and the CAM[1:0] = 2’b00( in TIMERx_CTL0 register); 2) When counter counting up (DIR = 0 in TIMERx_CTL0 register), the value of TIMERx_CHxCV/ TIMERx_MCHxCV should be set to 0; When counting down (DIR =1 in TIMERx_CTL0 register), the value of TIMERx_CHxCV/ TIMERx_MCHxCV should be greater than or equal to the value of TIMERx_CAR register.
Page 665: Figure 22-45. Trigger Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32H75E User Manual value with the divided internal clock after being triggered by TIMER2 enable signal output. When TIMER0 receives the trigger signal, its CEN bit is set automatically and the counter counts until TIMER0 is disabled. Both clock frequency of the counters is divided by 3 from TIMER_CK (f /3).
Page 666: Figure 22-46. Trigger Mode Of Timer0 Controlled By Update Signal Of Timer2
GD32H75E User Manual Figure 22-46. Trigger mode of TIMER0 controlled by update signal of TIMER2 TIMER2 TIMER_CK CNT_REG TIMER0 TRGIF CNT_REG  Enable TIMER0 to count with the enable/O0CPRE signal of TIMER2. In this example, TIMER0 is enabled with the enable signal of TIMER2. Refer to Figure 22-47.
Page 667: Figure 22-48. Pause Mode Of Timer0 Controlled By O0Cpre Signal Of Timer2
GD32H75E User Manual TIMER2_CTL1 register). 2. Configure the TIMER2 O0CPRE waveform (TIMER2_CHCTL0 register). 3. Configure TIMER0 in pause mode and select the TIMER2 as TIMER0 input trigger source (TRCFG4[4:0] = 5b’00011 in the_SYSCFG_TIMER0CFG0 register). 4. Enable TIMER0 by writing ‘1’ to the CEN bit (TIMER0_CTL0 register).
Page 668: Figure 22-49. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32H75E User Manual Figure 22-49. Trigger TIMER0 and TIMER2 by the CI0 signal of TIMER2 TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB.
Page 669 GD32H75E User Manual and interrupt processing. Timer debug mode ® When the Cortex -M7 is halted, and the TIMERx_HOLD configuration bit in DBG_CTL register is set to 1, the TIMERx counter stops.
Page 670 GD32H75E User Manual Registers definition (TIMERx, x=0, 7) 22.1.5. TIMER0 base address: 0x4001 0000 TIMER7 base address: 0x4001 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved...
Page 671 GD32H75E User Manual TIMERx_CHCTL0 register). Only when the counter is counting down, compare interrupt flag of channels can be set. 10: Center-aligned and counting up assert mode. The counter counts in center- aligned mode and channel is configured in output mode (CHxMS = 3’b000 in TIMERx_CHCTL0 register).
Page 672 GD32H75E User Manual pause mode or decoder mode. While in event mode, the hardware can set the CEN bit automatically. Control register 1 (TIMERx_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 673 GD32H75E User Manual Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 19:16 Reserved Must be kept at reset value.
Page 674 GD32H75E User Manual CEN control bit is set or the trigger input in pause mode is high. There is a delay between the trigger input in pause mode and the TRGO0 output, except if the master-slave mode is selected. 010: Update. In this mode, the master mode controller selects the update event as TRGO0.
Page 675 GD32H75E User Manual When a channel does not have a complementary output, this bit has no effect. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1...
Page 676 GD32H75E User Manual An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample ETIFP signal and the length of the digital filter applied to ETIFP.
Page 677 GD32H75E User Manual 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode. CH2COMADDIE Channel 2 additional compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used in composite PWM mode. CH1COMADDIE Channel 1 additional compare interrupt enable...
Page 678 GD32H75E User Manual MCH3MSEL[1:0] = 2b’00). MCH2IE Multi mode channel 2 capture/compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MCH2MSEL[1:0] = 2b’00). MCH1IE Multi mode channel 1 capture/compare interrupt enable...
Page 679 GD32H75E User Manual CH2DEN Channel 2 capture/compare DMA request enable 0: Disabled 1: Enabled CH1DEN Channel 1 capture/compare DMA request enable 0: Disabled 1: Enabled CH0DEN Channel 0 capture/compare DMA request enable 0: Disabled 1: Enabled UPDEN Update DMA request enable...
Page 680 GD32H75E User Manual Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3COM CH2COM CH1COM CH0COM DECDISIF DECJIF MCH3OF MCH2OF MCH1OF MCH0OF MCH3IF MCH2IF MCH1IF MCH0IF Reserved ADDIF ADDIF...
Page 681 GD32H75E User Manual Refer to MCH0IF description MCH2IF Multi mode channel 2 capture/compare interrupt flag Refer to MCH0IF description MCH1IF Multi mode channel 1 capture/compare interrupt flag Refer to MCH0IF description MCH0IF Multi mode channel 0 capture/compare interrupt flag This flag is set by hardware and cleared by software.
Page 682 GD32H75E User Manual CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software.
Page 683 GD32H75E User Manual If channel 0 is in input mode, this flag is set when a capture event occurs. If channel 0 is in output mode, this flag is set when a compare event occurs. If channel 0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 684 GD32H75E User Manual Refer to MCH0G description. MCH2G Multi mode channel 2 capture or compare event generation. Refer to MCH0G description. MCH1G Multi mode channel 1 capture or compare event generation. Refer to MCH0G description. MCH0G Multi mode channel 0 capture or compare event generation.
Page 685 GD32H75E User Manual 1: Generate channel commutation update event CH3G Channel 3 capture or compare event generation Refer to CH0G description CH2G Channel 2 capture or compare event generation Refer to CH0G description CH1G Channel 1 capture or compare event generation...
Page 686 GD32H75E User Manual Bits Fields Descriptions CH1MS[2] Channel 1 I/O mode selection Refer to CH1MS[1:0]description CH0MS[2] Channel 0 I/O mode selection Refer to CH0MS[1:0] description CH1COMADDSEN Channel 1 additional compare output shadow enable Refer to CH0COMADDSEN description. CH0COMADDSEN Channel 0 additional compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0COMV_ADD register which updates at each update event will be enabled.
Page 687 GD32H75E User Manual 011: Channel 1 is configured as input, IS1 is connected to ITS. This mode is working only if an internal trigger input is selected (through TSCFG15[4:0] bit-field in SYSCFG_TIMERxCFG2(x=0,7) register). 100: Channel 1 is configured as input, IS1 is connected to MCI1FE1.
Page 688 GD32H75E User Manual the O0CPRE is active. The O0CPRE is inactive again at the next update event; When counting down, the O0CPRE is active. When a trigger event occurs, the O0CPRE is inactive. The O0CPRE is active again at the next update event.
Page 689 GD32H75E User Manual Bits Fields Descriptions CH1MS[2] Channel 1 I/O mode selection Same as output compare mode. CH0MS[2] Channel 0 I/O mode selection Same as output compare mode. 29:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description.
Page 690 GD32H75E User Manual Same as output compare mode. Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3COM CH2COM CH3COM CH2COM CH3MS CH2MS ADDSEN ADDSEN CTL[3] CTL[3] Reserved...
Page 691 GD32H75E User Manual Refer to CH2COMCTL[2:0] description CH3COMCEN Channel 3 output compare clear enable Refer to CH2COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH2COMCTL[2:0] description CH3COMSEN Channel 3 output compare shadow enable Refer to CH2COMSEN description Reserved Must be kept at reset value.
Page 692 GD32H75E User Manual counter matches the output compare register TIMERx_CH2CV. 0011: Toggle on match. O2CPRE toggles when the counter matches the output compare register TIMERx_CH2CV. 0100: Force low. O2CPRE is forced low level. 0101: Force high. O2CPRE is forced high level.
Page 693 GD32H75E User Manual This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP register is 11 and CH2MS bit-field is 000. Reserved Must be kept at reset value. CH2MS[1:0] Channel 2 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection.
Page 694 GD32H75E User Manual 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6. SAMP 0111: f /4, N=8. SAMP 1000: f /8, N=6. SAMP 1001: f /8, N=8. SAMP 1010: f /16, N=5. SAMP 1011: f /16, N=6.
Page 695 GD32H75E User Manual CH3P Channel 3 capture/compare polarity Refer to CH0P description. CH3EN Channel 3 capture/compare enable Refer to CH0EN description. MCH2P Multi mode channel 2 output polarity Refer to MCH0P description. MCH2EN Multi mode channel 2 output enable Refer to MCH0EN description.
Page 696 GD32H75E User Manual 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, these bits specifie the channel 0 input signal’s polarity. [MCH0P, CH0P] will select the active trigger or capture polarity for channel 0 input signals.
Page 697 GD32H75E User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock.
Page 698 GD32H75E User Manual Reserved Reserved CREP0[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP0[7:0] Counter repetition value 0 This bit-field specifies the update event generation rate. Each time the repetition counter counts down to zero, an update event will be generated. The update rate of the shadow registers is also affected by this bit-field when these shadow registers are enabled.
Page 699 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture/compare value of channel 1 When channel 1 is configured in input mode, this bit-field indicates the counter value at the last capture event.
Page 700 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture/compare value of channel 3 When channel 3 is configured in input mode, this bit-field indicates the counter value at the last capture event.
Page 701 GD32H75E User Manual Note: Every write operation to this bit needs a delay of 1 APB clock to active. BRK1REL BREAK1 input released Refer to BRK0REL description. BRK0REL BREAK0 input released This bit is cleared by hardware when the BREAK0 input is invalid.
Page 702 GD32H75E User Manual 1010: f /16, N=5 SAMP 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is...
Page 703 GD32H75E User Manual input is not active. This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK0P BREAK0 input signal polarity This bit specifies the polarity of the BREAK0 input signal. 0: BREAK0 input active low...
Page 704 GD32H75E User Manual 10: PROT mode 1. In addition to the registers in PROT mode 0, the CHxP/MCHxP bits in TIMERx_CHCTL2 register (if related channel is configured in output mode), the ROS/IOS bits in TIMERx_CCHP register and the ROS/IOS bits in TIMERx_FCCHPx (x = 0..3) register are writing protected.
Page 705 GD32H75E User Manual Refer to MCH0MS[1:0] description. 29:25 Reserved Must be kept at reset value. MCH1COMCTL Multi mode channel 1 compare output control. Refer to MCH0COMCTL[2:0] description. 23:17 Reserved Must be kept at reset value. MCH0COMCTL Multi mode channel 0 compare output control.
Page 706 GD32H75E User Manual O0CPRE which drives CH0_O and MCH0_O, while the active level of CH0_O and MCH0_O depends on CH0P and MCH0P bits. 0000: Timing mode. The MO0CPRE signal keeps stable, independent of the comparison between register TIMERx_MCH0CV counter TIMERx_CNT.
Page 707 GD32H75E User Manual updates at each update event will be enabled. 0: Multi mode channel 0 output compare shadow disabled 1: Multi mode channel 0 output compare shadow enabled The PWM mode can be used without validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set).
Page 708 GD32H75E User Manual 0010: f , N=4. SAMP CK_TIMER 0011: f , N=8. SAMP CK_TIMER 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6. SAMP 0111: f /4, N=8. SAMP 1000: f /8, N=6. SAMP 1001: f /8, N=8.
Page 709 GD32H75E User Manual Refer to MCH3MS[1:0]description. MCH2MS[2] Multi mode channel 0 I/O mode selection Refer to MCH2MS[1:0] description. 29:25 Reserved Must be kept at reset value. MCH3COMCTL Multi mode channel 3 compare output control. Refer to MCH2COMCTL[2:0] description. 23:17 Reserved Must be kept at reset value.
Page 710 GD32H75E User Manual Note: When multi mode channel 2 is configured in output mode, and the MCH2MSEL[1:0] = 2b’11, the CH2COMCTL[2:0] bit-field controls the behavior of O2CPRE which drives CH2_O and MCH2_O, while the active level of CH2_O and MCH2_O depends on CH2P and MCH2P bits.
Page 711 GD32H75E User Manual MCH2COMSEN Multi mode channel 2 output compare shadow enable When this bit is set, the shadow register of TIMERx_MCH2CV register, which updates at each update event will be enabled. 0: Multi mode channel 2 output compare shadow disabled...
Page 712 GD32H75E User Manual 0000: Filter disabled, f , N=1. SAMP 0001: f , N=2. SAMP CK_TIMER 0010: f , N=4. SAMP CK_TIMER 0011: f , N=8. SAMP CK_TIMER 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6.
Page 713 GD32H75E User Manual MCH3FP[1:0] Multi mode channel 3 capture/compare free polarity Refer to MCH0FP[1:0] description. MCH2FP[1:0] Multi mode channel 2 capture/compare free polarity Refer to MCH0FP[1:0] description. MCH1FP[1:0] Multi mode channel 1 capture/compare free polarity Refer to MCH0FP[1:0] description. MCH0FP[1:0]...
Page 714 GD32H75E User Manual 15:0 MCH0VAL[15:0] Capture/compare value of multi mode channel 0. When multi mode channel 0 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only. When multi mode channel 0 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 715 GD32H75E User Manual 31:16 Reserved Must be kept at reset value. 15:0 MCH2VAL[15:0] Capture/compare value of multi mode channel 2. When multi mode channel 2 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only.
Page 716 GD32H75E User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0COMVAL_ADD Additional compare value of channel 0 [15:0] When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 717 GD32H75E User Manual 31:16 Reserved Must be kept at reset value. 15:0 CH2COMVAL_ADD Additional compare value of channel 2 [15:0] When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 718 GD32H75E User Manual Bits Fields Descriptions CH3CPWMEN Channel 3 composite PWM mode enable 0: Disabled 1: Enabled CH2CPWMEN Channel 2 composite PWM mode enable 0: Disabled 1: Enabled CH1CPWMEN Channel 1 composite PWM mode enable 0: Disabled 1: Enabled CH0CPWMEN...
Page 719 GD32H75E User Manual 1: Quadrature decoder signal disconnection detection is enabled DECJDEN Quadrature decoder signal jump (the two signals jump at the same time) detection enable 0: Quadrature decoder signal jump detection is disabled 1: Quadrature decoder signal jump detection is enabled...
Page 720 GD32H75E User Manual CK_TIMER clock cycle. CH0OMPSEL[1:0] Channel 0 output match pulse select When the match events occur, this bit is used to select the output of O0CPRE which drives CH0_O. 00: The O0CPRE signal is output normal with the configuration of CH0COMCTL[2:0] bits.
Page 721 GD32H75E User Manual DTIENCH0 Dead time inserted enable for channel 0 Enables the deadtime insertion in the outputs of MCH0_O and CH0_O. 0: Disabled 1: Enabled Free complementary channel protection register 0 (TIMERx_FCCHP0) Address offset: 0x7C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 722 GD32H75E User Manual state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Reserved Must be kept at reset value. DTCFG[7:0] Dead time configure This bit-field controls the value of the dead-time, which is inserted before the output transitions.
Page 723 GD32H75E User Manual channel is output disabled. 1: “off-state” enabled. If the CH1EN or CH1NEN bit is reset, the corresponding channel is “off-state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode “off-state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off-state”...
Page 724 GD32H75E User Manual FCCHP2EN Free complementary channel protection register 2 enable 0: the ROS、IOS and DTCFG[7:0] bits in TIMERx_CCHP register is active 1: the ROS、IOS and DTCFG[7:0] bits in TIMERx_FCCHP2 register is active This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 725 GD32H75E User Manual This register is used to configure the outputs of CH3_O/MCH3_O. FCCHP3 Reserved Reserved Reserved DTCFG[7:0] Bits Fields Descriptions FCCHP3EN Free complementary channel protection register 0 enable 0: the ROS、IOS and DTCFG[7:0] bits in TIMERx_CCHP register is active 1: the ROS、IOS and DTCFG[7:0] bits in TIMERx_FCCHP3 register is active...
Page 726 GD32H75E User Manual DTCFG [7:5] =3’b10x: DTvalue = (64+DTCFG [5:0])xt DTCFG [7:5] =3’b110: DTvalue = (32+DTCFG [4:0])xt DTCFG [7:5] =3’b111: DTvalue = (32+DTCFG [4:0])xt *16. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 727 GD32H75E User Manual 24:19 Reserved Must be kept at reset value. BRK0IN2P BREAK0 BRKIN2 alternate function input polarity This bit is used to configure the BRKIN2 input polarity, and the specific polarity is determined by this bit and the BRK0P bit.
Page 728 GD32H75E User Manual 0: HPDF input disabled 1: HPDF input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is Reserved Must be kept at reset value. BRK0IN2EN BREAK0 BRKIN2 alternate function input enable 0: BRKIN2 alternate function input disabled...
Page 729 GD32H75E User Manual 0: CMP1 input signal will not be inverted (BRK1P =0, the input signal is active low; BRK1P =1, the input signal is active high) 1: CMP1 input signal will be inverted (BRK1P =0, the input signal is active high;...
Page 730 GD32H75E User Manual This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is 15:11 Reserved Must be kept at reset value. BRK1CMP1EN BREAK1 CMP1 enable 0: CMP1 input disabled 1: CMP1 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is...
Page 731 GD32H75E User Manual This register has to be accessed by word (32-bit). BRK0CMP BRK0CMP Reserved Reserved BRK0IN2P BRK0IN1P BRK0IN0P BRK0HPD BRK0IN2E BRK0IN1E BRK0IN0E BRK0CMP BRK0CMP Reserved Reserved Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. BRK0CMP1P BREAK0 CMP1 input polarity This bit is used to configure the CMP1 input polarity, and the specific polarity is determined by this bit and the BRK0P bit.
Page 732 GD32H75E User Manual BRK0IN1P BREAK0 BRKIN1 alternate function input polarity This bit is used to configure the BRKIN1 input polarity, and the specific polarity is determined by this bit and the BRK0P bit. 0: BRKIN1 input signal will not be inverted (BRK0P =0, the input signal is active low;...
Page 733 GD32H75E User Manual BRK0IN1EN BREAK0 BRKIN1 alternate function input enable 0: BRKIN1 alternate function input disabled 1: BRKIN1 alternate function input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK0IN0EN BREAK0 BRKIN0 alternate function input enable...
Page 734 GD32H75E User Manual 1: CMP0 input signal will be inverted (BRK1P =0, the input signal is active high; BRK1P =1, the input signal is active low) This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is 24:19 Reserved Must be kept at reset value.
Page 735 GD32H75E User Manual 1: CMP0 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK1HPDFEN BREAK1 HPDF input(hpdf_break[1]) enable 0: HPDF input disabled 1: HPDF input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is Reserved Must be kept at reset value.
Page 736 GD32H75E User Manual countius to count to this value, the counter will timeout and the interrupt flag DECDISIF is set. If DECDISIE=1, the corresponding interrupt is generated. Note: This register is just used in quadrature decoder signal disconnection detection function(with DECDISDEN =1).
Page 737 GD32H75E User Manual DMA. 6’b000000: transfer 1 time 6’b000001: transfer 2 times … 6’b100101: transfer 38 times Reserved Must be kept at reset value. DMATA[5:0] DMA transfer access start address This field defines the start address of accessing the TIMERx_DMATB register by DMA.
Page 738 GD32H75E User Manual Reserved CCUSEL CREPSEL CHVSEL OUTSEL Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CCUSEL Commutation control shadow register update select This bit is valid only when the CCUC[2:0] bit-field are set to 100, 101 and 110.
Page 739: Figure 22-50. General Level 0 Timer Block Diagram
GD32H75E User Manual General level0 timer (TIMERx, x=1,2,3,4,22,23) 22.2. Overview 22.2.1. The general level0 timer module (TIMER1/2/3/4/22/23) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level0 timer has a 16-bit or 32-bit counter that can be used as an unsigned counter.
Page 740: Clock Selection
GD32H75E User Manual Figure 22-50. General Level 0 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TIMERx_TRGO0 Trigger selector CH0_I Input Logic CH1_I Synchronizer&Filter Edge selector Prescaler CH2_I &Edge Detector CH3_I TIMERx_CHxCV Counter External Trigger Input logic On-chip ETI PSC_CLK sources Polarity selection TIMER_CK...
Page 741: Figure 22-51. Normal Mode, Internal Clock Divided By 1
GD32H75E User Manual Figure 22-51. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK 20 21 01 02 CNT_REG  TSCFG6[4:0] are setting to a nonzero value (external clock mode 0). External input pin is selected as timer clock source.
Page 742: Figure 22-52. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32H75E User Manual Figure 22-52. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 743: Figure 22-54. Timing Chart Of Up Counting, Change Timerx_Car Ongoing
GD32H75E User Manual Figure 22-53. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 22-54.
Page 744: Figure 22-55. Timing Chart Of Down Counting Mode, Psc=0/2
GD32H75E User Manual Down counting mode In this mode, the counter counts down continuously from the counter reload value, which is defined in the TIMERx_CAR register, in a count-down direction. Once the counter reaches 0, the counter restarts to count again from the counter reload value. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode.
Page 745: Figure 22-56. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32H75E User Manual Figure 22-56. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118...
Page 746: Figure 22-57. Timing Chart Of Center-Aligned Counting Mode
GD32H75E User Manual updated. Figure 22-57. Timing chart of center-aligned counting mode shows the example of the counter behavior when TIMERx_CAR=0x99, TIMERx_PSC=0x0. Figure 22-57. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11...
Page 747: Figure 22-58. Input Capture Logic
GD32H75E User Manual enabled when CHxIE=1. Figure 22-58. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling CI0F_ED Capture Clock CI1FE0 Register Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other...
Page 748: Figure 22-59. Output Compare Logic (X=0,1,2,3)
GD32H75E User Manual The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connects to CI0 input. Select CI0 as channel 0 capture signals by setting CH0MS to 3’b001 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 749: Figure 22-60. Output-Compare Under Three Modes
GD32H75E User Manual Step3: Interrupt/DMA-request enables configuration by CHxIE/CHxDEN. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed onging to meet the expected waveform. Step5: Start the counter by configuring CEN to 1. Figure 22-60. Output-compare under three modes shows the three compare modes toggle/set/clear.
Page 750 GD32H75E User Manual be always inactive in PWM mode 1 (CHxCOMCTL=4’b0111). Figure 22-61. Timing chart of EAPWM Figure 22-62. Timing chart of CAPWM CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CAM=2'b01 down only CHxIF CHxOF...
Page 751: Table 22-10.The Composite Pwm Pulse Width
GD32H75E User Manual If CHxCOMCTL = 4’b0111 (PWM mode 1) and DIR = 1’b0 (up counting mode), or CHxCOMCTL = 4’b0110 (PWM mode 0) and DIR = 1’b1 (down counting mode) the channel x output is forced high when the counter matches the value of CHxVAL. It is forced low when the counter matches the value of CHxCOMVAL_ADD.
Page 752: Figure 22-63. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32H75E User Manual between 0 and CARL. Figure 22-63. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal...
Page 753: Figure 22-66. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32H75E User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1...
Page 754: Figure 22-68. Four Channels Outputs In Composite Pwm Mode
GD32H75E User Manual CARL CHxVAL next counter next counter period period PWM MODE 1 OxCPRE PWM MODE 0 OxCPRE Interrupt signal CHxIF CHxCOMADDIF CHxCOMVAL_ADD match If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels.
Page 755: Figure 22-69. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel≠2'B00)
GD32H75E User Manual  CHxOMPSEL = 2’b00, the OxCPRE signal is output normally with the configuration of CHxCOMCTL[3:0] bits; CHxOMPSEL = 2’b01, only the counter is counting up, the OxCPRE signal is output a  pulse when the match events occur, and the pulse width is one CK_TIMER clock cycle.
Page 756 GD32H75E User Manual Channel output prepare signal As is shown in Figure 22-59. Output compare logic (x=0,1,2,3), when TIMERx is configured in compare match output mode, a middle signal which is OxCPRE signal (Channel x output prepare signal) will be generated before the channel outputs signal. The OxCPRE signal type is defined by configuring the CHxCOMCTL bit.
Page 757: Figure 22-71. Example Of Counter Operation In Decoder Interface Mode
GD32H75E User Manual Table 22-11. Counting direction in different quadrature decoder signals CI0FE0 CI1FE1 Counting mode Level Rising Falling Rising Falling CI1FE1=1 Down Quadrature decoder mode 0 TSCFG0[4:0]!= 5’b00000 CI1FE1=0 Down Quadrature decoder mode 1 CI0FE0=1 Down TSCFG1[4:0]!= 5’b00000 CI0FE0=0...
Page 758: Figure 22-73. Quadrature Decoder Signal Disconnection Detection Block Diagram
GD32H75E User Manual DECJDEN bit (in TIMERx_CTL2register) to 1, which can be used to detect whether the level jump edges (rising or falling) of the CI0 and CI1 signals occur at the same time. When DECJDEN =1, if the level transitions of the two quadrature signals CI0 and CI1 occur simultaneously, the interrupt flag DECJIF is set, if DECJIE=1, the corresponding interrupt is generated.
Page 759: Figure 22-75. Example Of Counter Operation In Non-Quadrature Decoder Mode 1 With Ch0P=0
GD32H75E User Manual CH1P=0 When the non-quadrature decoder mode 1 is enabled, the CI0 signal is used as the count pulse (with the CH0P is used to select the counter edge) and the CI1 signal is used as the count direction selection. The more details is shown in Table 22-12.
Page 760: Table 22-13. Examples Of Slave Mode
GD32H75E User Manual Hall sensor function Refer to Advanced timer (TIMERx, x=0, 7)Hall sensor function. Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode and so on, which is selected by the TSCFGy[4:0] (y=3..7) in SYSCFG_TIMERxCFG(x=1..4,22,23).
Page 761: Figure 22-76. Restart Mode
GD32H75E User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 22-76. Restart mode TIMER_CK CNT_REG 61 62 02 03 01 02 UPIF ITI0 Internal sync delay TRGIF Pause mode TI0S = 0 (Non-xor) The counter will be...
Page 762 GD32H75E User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler (1) The ETI signal can be input from an external ETI pin or provide by on-chip peripherals, please refer Trigger selection for TIMER1_ETI register (TRIGSEL_TIMER1ETI) for more details.
Page 763: Figure 22-79. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X60
GD32H75E User Manual Figure 22-79. Single pulse mode TIMERx_CHxCV = 0x04, TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O0CPRE Delayable single pulse mode Delayable single pulse mode is enabled by setting CHxCOMCTL[3:0] in TIMERx_CHCTLx registers. In this mode, the pulse width of OxCPRE signal is determined by the TIMERx_CAR register.
Page 764: Figure 22-80. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32H75E User Manual Figure 22-80. delayable single pulse mode TIMERx_CHxCV=0x00, TIMERx_CAR=0x60 TIMER_CK (CNT_CLK) 60 00 60 00 CNT_REG O0CPRE Timers interconnection Please refer to Advanced timer (TIMERx, x=0, 7)Timers interconnection Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative Corresponding registers are TIMERx_DMACFG and TIMERx_DMATB.
Page 765 GD32H75E User Manual register set to 1, the TIMERx counter stops.
Page 766 GD32H75E User Manual Registers definition (TIMERx, x=1,2,3,4,22,23) 22.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 TIMER22 base address: 0x4000 E000 TIMER23 base address: 0x4000 E400 Control register 0 (TIMERx_CTL0)
Page 767 GD32H75E User Manual 1: The shadow register for TIMERx_CAR register is enabled CAM[1:0] Counter align mode selection 00: No center-aligned mode (edge-aligned mode). The direction of the counter is specified by the DIR bit. 01: Center-aligned and counting down assert mode. The counter counts in center- aligned mode and channel is configured in output mode (CHxMS = 3’b000 in...
Page 768 GD32H75E User Manual and the prescaler are reinitialized if the UG bit is set or the slave mode controller generates a hardware reset event. Counter enable 0: Counter disable 1: Counter enable The CEN bit must be set by software when timer works in external clock mode, pause mode or decoder mode.
Page 769 GD32H75E User Manual 011: Capture/compare pulse. In this mode, the master mode controller generates a TRGO0 pulse when a capture or a compare match occurs in channel 0. 100: Compare. In this mode, the master mode controller selects the O0CPRE signal as TRGO0.
Page 770 GD32H75E User Manual The external clock input will be ETIFP if external clock mode 0 and external clock mode 1 are enabled at the same time. Note: External clock mode enable TSCFG6[4:0] bit-field SYSCFG_TIMERxCFG1 register. 13:12 ETPSC[1:0] External trigger prescaler The frequency of external trigger signal ETIFP must not be higher than 1/4 of TIMER_CK frequency.
Page 771 GD32H75E User Manual DMA and interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH3COM CH2COM CH1COM CH0COM Reserved DECDISIE DECJIE ADDIE ADDIE ADDIE ADDIE Reserved TRGDEN Reserved CH3DEN CH2DEN CH1DEN CH0DEN...
Page 772 GD32H75E User Manual Note: This bit just used for quadrature decoder signal jump detection is enabled (when DECJDEN =1). Reserved Must be kept at reset value. TRGDEN Trigger DMA request enable 0: Disabled 1: Enabled Reserved Must be kept at reset value.
Page 773 GD32H75E User Manual CH0IE Channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 774 GD32H75E User Manual enabled (when DECDISDEN =1). DECJIF Quadrature decoder signal jump (the two signals jump at the same time) interrupt flag 0: No quadrature decoder signal jump interrupt occurred 1: Quadrature decoder signal jump interrupt occurred Note: This bit just used for quadrature decoder signal jump detection is enabled (when DECJDEN =1).
Page 775 GD32H75E User Manual If channel 0 is in input mode, this flag is set when a capture event occurs. If channel 0 is in output mode, this flag is set when a compare event occurs. If channel 0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 776 GD32H75E User Manual This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_INTF register will be set, related interrupt or DMA transfer can occur if enabled. 0: No generate a trigger event...
Page 777 GD32H75E User Manual CH1COM CH1COM CH0COM CH0COM CH1COMCTL[2:0] Reserved CH0COMCTL[2:0] Reserved CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions CH1MS[2] Channel 1 I/O mode selection Refer to CH1MS[1:0]description CH0MS[2] Channel 0 I/O mode selection Refer to CH0MS[1:0] description...
Page 778 GD32H75E User Manual 010: Channel 1 is configured as input, IS1 is connected to CI0FE1. 011: Channel 1 is configured as input, IS1 is connected to ITS. This mode is working only if an internal trigger input is selected (through TSCFG15[4:0] bit-field in SYSCFG_TIMERxCFG2(x=1...4,22,23,30,31) register).
Page 779 GD32H75E User Manual Note: In the composite PWM mode (CH0CPWMEN = 1’b1 and CH0MS = 3’b000), the PWM signal output in channel 0 is composited by TIMERx_CH0CV and TIMERx_CH0COMV_ADD. Please refer to Composite PWM mode for more details. If configured in PWM mode, the O0CPRE level changes only when the output compare mode switches from “Timing”...
Page 780 GD32H75E User Manual Same as output compare mode. CH0CAPFLT[3:0] Channel 0 input capture filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample CI0 input signal and the length of the digital filter applied to CI0.
Page 781 GD32H75E User Manual CH3COM CH3COM CH2COM CH2COM CH3COMCTL[2:0] Reserved CH2COMCTL[2:0] Reserved CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions CH3MS[2] Channel 3 I/O mode selection Refer to CH3MS[1:0]description. CH2MS[2] Channel 2 I/O mode selection Refer to CH2MS[1:0] description.
Page 782 GD32H75E User Manual 01: Channel 3 is configured as input, IS3 is connected to CI3FE3. 10: Channel 3 is configured as input, IS3 is connected to CI2FE3. 11: Channel 3 is configured as input, IS3 is connected to ITS, this mode is working only if an internal trigger input is selected (through TSCFG15[4:0] bit-field in SYSCFG_TIMERxCFG2(x=1...4,22,23) register).
Page 783 GD32H75E User Manual 1010~1111: Reserved. Note: In the composite PWM mode (CH2CPWMEN = 1’b1 and CH2MS = 3’b000), the PWM signal output in channel 2 is composited by TIMERx_CH2CV and TIMERx_CH2COMV_ADD. Please refer to Composite PWM mode for more details.
Page 784 GD32H75E User Manual Same as output compare mode. CH2CAPFLT[3:0] Channel 2 input capture filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample CI2 input signal and the length of the digital filter applied to CI2.
Page 785 GD32H75E User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3NP Channel 3 complementary capture/compare polarity Refer to CH0NP description. Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description...
Page 786 GD32H75E User Manual 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0.
Page 787 GD32H75E User Manual Counter register (TIMERx_CNT) (TIMERx, x= 1,4,22,23) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CNT[31] CNT[30:16] UPIFBU rw /r CNT[15:0] UPIFBUEN = 0: Bits Fields Descriptions 31:0 CNT[31:0] This bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter.
Page 788 GD32H75E User Manual 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field will be loaded to the corresponding shadow register at every update event.
Page 789 GD32H75E User Manual When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event. Channel 1 capture/compare value register (TIMERx_CH1CV)
Page 790 GD32H75E User Manual 15:0 CH2VAL[15:0] Capture/compare value of channel 2 When channel 2 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only. When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 791 GD32H75E User Manual 31:16 CH0COMVAL_ADD Additional compare value of channel 0 (bit 16 to 31) [31:16] This bit-field only for TIMER1/ 4/ 22/ 23. 15:0 CH0COMVAL_ADD Additional compare value of channel 0 [15:0] When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 792 GD32H75E User Manual Bits Fields Descriptions 31:16 CH2COMVAL_ADD Additional compare value of channel 2 (bit 16 to 31) [31:16] This bit-field only for TIMER1/ 4/ 22/ 23. 15:0 CH2COMVAL_ADD Additional compare value of channel 2 [15:0] When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter.
Page 793 GD32H75E User Manual Bits Fields Descriptions CH3CPWMEN Channel 3 composite PWM mode enable 0: Disabled 1: Enabled CH2CPWMEN Channel 2 composite PWM mode enable 0: Disabled 1: Enabled CH1CPWMEN Channel 1 composite PWM mode enable 0: Disabled 1: Enabled CH0CPWMEN...
Page 794 GD32H75E User Manual 13:12 CH2OMPSEL[1:0] Channel 2 output match pulse select When the match events occur, this bit is used to select the output of O2CPRE which drives CH2_O. 00: The O2CPRE signal is output normal with the configuration of CH2COMCTL [2:0] bits.
Page 795 GD32H75E User Manual This register has to be accessed by word (32-bit). WDGPER[31:16] WDGPER[15:0] Bits Fields Descriptions 31:0 WDGPER[31:0] Watchdog counter period value This register contains the period of the two watchdog counter. When the counters continus to count to this value, the counter will timeout and the interrupt flag DECDISIF is set.
Page 796 GD32H75E User Manual specifies the address just accessed. And then the address of the second access to the TIMERx_DMATB register will be (start address + 0x4). 6’b000000: TIMERx_CTL0 6’b000001: TIMERx_CTL1 … In a word: start address = TIMERx_CTL0 + DMATA*4...
Page 797 GD32H75E User Manual CHVSEL Write CHxVAL register selection bit This bit-field is set and reset by software. 1: If the value to be written to the CHxVAL register is the same as the value of CHxVAL register, the write access is ignored.
Page 798: Figure 22-81. General Level3 Timer Block Diagram
GD32H75E User Manual General level3 timer (TIMERx, x=14,40,41,42,43,44) 22.3. Overview 22.3.1. The general level3 timer module (TIMER14/40/41/42/43/44) is a three-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level3 timer has a 16-bit counter that can be used as an unsigned counter.
Page 799 GD32H75E User Manual configuration of the general level3 timer. Figure 22-81. General level3 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TIMERx_TRGO0 Trigger selector CH0_I Input Logic Synchronizer & Filter Edge selector Prescaler CH1_I & Edge Detector TIMERx_CHxCV/ Counter TIMERx_MCHxCV PSC_CLK TIMER_CK DMA REQ/ACK...
Page 800: Figure 22-82. Normal Mode, Internal Clock Divided By 1
GD32H75E User Manual available value, the internal clock TIMER_CK is the counter prescaler driving clock source. Figure 22-82. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 ...
Page 801: Figure 22-83. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32H75E User Manual Figure 22-83. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 802: Figure 22-85. Timing Diagram Of Up Counting Mode, Change Timerx_Car On The Go
GD32H75E User Manual the counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Timing diagram of up counting mode, PSC=0/2 Figure 22-84. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2...
Page 803: Figure 22-86. Repetition Timechart For Up-Counter
GD32H75E User Manual Counter repetition The general timer has two repetitions counter TIMERx_CREP0/1, which can be selected by configuring the CPERSEL bit in the TIMERx_CFG register. The CPEP[7:0] bit-field is 8bits, the CPEP[31:0] bit-field is 32bits and can be read on the fly.
Page 804: Figure 22-87. Input Capture Logic For Channel 0
GD32H75E User Manual TIMERx_MCHxCV(x=0, 1) registers, at the same time the CHxIF/ MCHxIF(x=0, 1) bits are set and the channel interrupt is generated if it is enabled when CHxIE/ MCHxIE =1(x=0, 1). Figure 22-87. Input capture logic for channel 0...
Page 805: Figure 22-89. Output Compare Logic (When Mchxmsel = 2'00, X=0)
GD32H75E User Manual Based on the input signal and quality of requested signal, configure compatible CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits.
Page 806: Figure 22-90. Output Compare Logic (When Mchxmsel = 2'11, X=0)
GD32H75E User Manual Figure 22-89. Output compare logic (when MCHxMSEL = 2’00, x=0) OxCPRE/MOxCPRE Capture/ CNT>CHxCV/ Compare register MCHxCV CHxCV/MCHxCV Compare output Output enable and CNT=CHxCV/ CHx_O control polarity selector MCHxCV CHxCOMCTL/ CHxP,CHxEN/ CNT<CHxCV/ MCHx_O MCHxCOMCTL MCHxFP,MCHxEN MCHxCV Counter Figure 22-90. Output compare logic (when MCHxMSEL = 2’11, x=0) Figure 22-91.
Page 807 GD32H75E User Manual CHxEN/MCHxEN bits. Please refer to Figure 22-90. Output compare logic (when MCHxMSEL = 2’11, x=0). For examples (the MCHx_O output is independent from the CHx_O output): 3) Configure CHxP=0 (the active level of CHx_O is high, the same as OxCPRE), CHxEN=1 (the output of CHx_O is enabled): If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level;...
Page 808: Figure 22-92. Output-Compare In Three Modes
GD32H75E User Manual Figure 22-92. Output-compare in three modes CNT_CLK CNT_REG 03 04 03 04 Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the PWM output mode (by setting the CHxCOMCTL/ MCHxCOMCTL bit to 4’b0110 (PWM mode 0) or to 4’b0111(PWM mode 1)), the channel can generate PWM waveform according...
Page 809 GD32H75E User Manual Figure 22-93. PWM mode timechart CARL CHxVAL PWM MO DE0 OxCPRE PWM MO DE1 OxCPRE Interrupt signal CHxIF CHxOF Composite PWM mode In the Composite PWM mode (CHxCPWMEN = 1’b1, CHxMS[2:0] = 3’b000 and CHxCOMCTL = 4’b0110 or 4’b0111), the PWM signal output in channel x (x=0, 1) is composited by CHxVAL and CHxCOMVAL_ADD bits.
Page 810: Table 22-14.The Composite Pwm Pulse Width
GD32H75E User Manual Table 22-14.The Composite PWM pulse width Condition Mode PWM pulse width (CARL + 0x0001) + PWM mode 0 CHxVAL < CHxCOMVAL_ADD (CHxVAL – CHxCOMVAL_ADD) ≤ CARL PWM mode 1 (CHxCOMVAL_ADD – CHxVAL) PWM mode 0 (CHxVAL - CHxCOMVAL_ADD) CHxCOMVAL_ADD <...
Page 811: Figure 22-94. Channel X Output Pwm With (Chxval < Chxcomval_Add)
GD32H75E User Manual Figure 22-94. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF...
Page 812: Figure 22-97. Channel X Output Pwm With Chxval Or Chxcomval_Add Exceeds Carl
GD32H75E User Manual CHxVAL = CARL CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1...
Page 813: Figure 22-99. Chx_O Output With A Pulse In Edge-Aligned Mode (Chxompsel =2'B00)
GD32H75E User Manual CARL CHxVAL next counter next counter period period PWM MODE 1 OxCPRE PWM MODE 0 OxCPRE Interrupt signal CHxIF CHxCOMADDIF CHxCOMVAL_ADD match If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels.
Page 814 GD32H75E User Manual CARL CHxCOMVAL_ CHxVAL OxCPRE CHxOMPSEL=2b 01 Channel output prepare signal Figure 22-89. Output compare logic (when MCHxMSEL = 2’00, x=0), As is shown in Figure 22-90. Output compare logic (when MCHxMSEL = 2’11, x=0) Figure 22-91. Output compare logic...
Page 815 GD32H75E User Manual Outputs complementary The outputs of CHx_O and MCHx_O have two situations:  MCHxMSEL=2’b00: The MCHx_O output is independent from the CHx_O output;  MCHxMSEL=2’b11: The outputs of MCHx_O and CHx_O are complementary and the MCHxOMCTL bits are not used in the generation of the MCHx_O output.
Page 816: Table 22-15. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32H75E User Manual Table 22-15. Complementary outputs controlled by parameters (MCHxMSEL =2’b11) Complementary Parameters Output Status POEN ROS CHxEN MCHxEN CHx_O MCHx_O CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 817: Figure 22-100. Complementary Output With Dead-Time Insertion
GD32H75E User Manual Dead time insertion The dead time insertion is enabled when MCHxMSEL=2’b11 and both CHxEN and MCHxEN are configured to 1’b1, it is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for all channels. Refer to the...
Page 818: Figure 22-101. Break0 Function Logic Diagram
GD32H75E User Manual configured by the BRK0P bit in TIMERx_CCHP register, the input is active on level. In BREAK0 function, CHx_O and MCHx_O are controlled by the POEN, OAEN, IOS and ROS bits in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register.
Page 819 GD32H75E User Manual high active and IOS=1) BREAK0 OxCPRE CHx_O = ISOx CHxEN: 1 MCHxEN: 1 CHxP : 0 MCHxP : 0 ISOx = ~ISOxN MCHx_O = ISOxN = ISOx CHxEN: 1 MCHxEN: 0 CHx_O CHxP: 0 MCHxP : 0...
Page 820: Figure 22-103. Brkin0 Pin Logic With Break0 Function
GD32H75E User Manual break function is released. The break events are still active, because the break input sources are still active.  POEN=1: when the channel outputs are enabled, the BRKIN0 pin cannot be released even if the BRK0REL is set.
Page 821: Figure 22-104. Restart Mode
GD32H75E User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler y=4: pause mode 00001: ITI0 MCIxFEMx(x=0), For the CIx/ MCIx, configure y=5: event mode 00010: ITI1 configure the CHxP, Filter CHxCAPFLT/ y=6: external clock 00011: ITI2 MCHxP and MCHxFP...
Page 822: Figure 22-106. Event Mode
GD32H75E User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler =5’b01000, counter will ETI does not change. by 2. start to count when ETIFP is selected. ETFC = 0, ETI does not a rising edge of filter. trigger input comes.
Page 823: Figure 22-107. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32H75E User Manual Figure 22-107. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O0CPRE Delayable single pulse mode Delayable single pulse mode is enabled by setting CHxCOMCTL[3:0]/ MCHxCOMCTL[3:0] in TIMERx_CHCTLx/ TIMERx_MCHCTLx registers. In this mode, the pulse width of OxCPRE/ MOxCPRE signal is determined by the TIMERx_CAR register.
Page 824: Figure 22-108. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
GD32H75E User Manual greater than or equal to the value of TIMERx_CAR register. Figure 22-108. delayable single pulse mode TIMERx_CHxCV=0x00, TIMERx_CAR=0x60 TIMER_CK (CNT_CLK) 60 00 60 00 CNT_REG O0CPRE Timers interconnection Please refer to Advanced timer (TIMERx, x=0, 7)Timers interconnection Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module.
Page 825 GD32H75E User Manual set to 1, the TIMERx counter stops. Register definition (TIMERx, x=14,40,41,42,43,44) 22.3.5. TIMER14 base address: 0x4001 4000 TIMER40 base address: 0x4001 D000 TIMER41 base address: 0x4001 D400 TIMER42 base address: 0x4001 D800 TIMER43 base address: 0x4001 DC00...
Page 826 GD32H75E User Manual 0: The shadow register for TIMERx_CAR register is disabled 1: The shadow register for TIMERx_CAR register is enabled Reserved Must be kept at reset value. Single pulse mode 0: Single pulse mode is disabled. Counter continues after an update event.
Page 827 GD32H75E User Manual Reserved ISO1 ISO0N ISO0 TI0S MMC0[2:0] DMAS CCUC[0] Reserved CCSE Bits Fields Descriptions 31:30 CCUC[2:1] Commutation control shadow register update control Refer to CCUC [0] description. 29:11 Reserved Must be kept at reset value. ISO1 Idle state of channel 1 output...
Page 828 GD32H75E User Manual 101: Compare. In this mode, the master mode controller selects the O1CPRE signal as TRGO0. 110: Reserved. 111: Reserved. DMAS DMA request source selection 0: DMA request of CHx/MCHx is sent when capture/compare event occurs. 1: DMA request of channel CHx/MCHx is sent when update event occurs.
Page 829 GD32H75E User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. Master-slave mode This bit can be used to synchronize the selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected.
Page 830 GD32H75E User Manual 23:21 Reserved Must be kept at reset value. MCH0IE Multi mode channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MMCH0SEL[1:0] = 2b’00). 19:15 Reserved Must be kept at reset value.
Page 831 GD32H75E User Manual 0: Disabled 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1COM CH0COM Reserved Reserved MCH0OF...
Page 832 GD32H75E User Manual If multi mode channel 0 is in input mode, this flag is set when a capture event occurs. If multi mode channel 0 is in output mode, this flag is set when a compare event occurs. If multi mode channel 0 is set to input mode, this bit will be reset by reading TIMERx_MCH0CV.
Page 833 GD32H75E User Manual If channel 0 is in input mode, this flag is set when a capture event occurs. If channel 0 is in output mode, this flag is set when a compare event occurs. If channel 0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 834 GD32H75E User Manual enabled. In addition, if multi mode channel 0 is configured in input mode, the current value of the counter is captured to TIMERx_MCH0CV register, and the MCH0OF flag is set if the MCH0IF flag has been set.
Page 835 GD32H75E User Manual counter is cleared at the same time. 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 836 GD32H75E User Manual 23:17 Reserved Must be kept at reset value. CH0COMCTL[3] Channel 0 compare output control Refer to CH0COMCTL[2:0] description Reserved Must be kept at reset value. 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL[2:0] description CH1COMSEN...
Page 837 GD32H75E User Manual 0101: Force high. O0CPRE is forced high level. 0110: PWM mode 0. When counting up, O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV, otherwise it is inactive. When counting down, O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV, otherwise it is active.
Page 838 GD32H75E User Manual CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. The CH0MS[2:0] bit-field is writable only when the channel is not active (When MCH0MSEL[1:0] = 2b’00, the CH1EN bit in TIMERx_CHCTL2 register is reset;...
Page 839 GD32H75E User Manual 1001: f /8, N=8. SAMP 1010: f /16, N=5. SAMP 1011: f /16, N=6. SAMP 1100: f /16, N=8. SAMP 1101: f /32, N=5. SAMP 1110: f /32, N=6. SAMP 1111: f /32, N=8. SAMP CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input.
Page 840 GD32H75E User Manual When Multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2b’11, this bit specifies the MCH0_O output signal polarity. 0: Multi mode channel 0 output active high 1: Multi mode channel 0 output active low When CH0 is configured in input mode, in conjunction with CH0P, this bit is used to define the polarity of CH0.
Page 841 GD32H75E User Manual UPIFBU Reserved CNT[15:0] Bits Fields Descriptions UPIFBU UPIF bit backup This bit is a backup of UPIF bit in TIMERx_INTF register, and read-only. This bit is only valid when UPIFBUEN = 1. If the UPIFBUEN =0, this bit is reserved and read the result is 0.
Page 842 GD32H75E User Manual Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter. Counter repetition register 0 (TIMERx_CREP0) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 843 GD32H75E User Manual CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture/compare value of channel 0 When channel 0 is configured in input mode, this bit-field indicates the counter value at the last capture event. And this bit-field is read-only.
Page 844 GD32H75E User Manual POEN OAEN BRK0P BRK0EN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value. BRK0LK BREAK0 input locked 0: BREAK0 input in input mode 1: BREAK0 input in locked mode When the BRK0LK is set to 1, the BREAK0 input is configured in open drain output mode.
Page 845 GD32H75E User Manual 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is POEN Primary output enable This bit is set by software or automatically set by hardware depending on the OAEN bit.
Page 846 GD32H75E User Manual channel is “off-state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode “off-state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off-state” for the channels which has been configured in output mode.
Page 847 GD32H75E User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). MCH0CO MCH0 Reserved Reserved MCTL[3] MS[2] Reserved MCH0CO Reserved MCH0COMCTL[2:0] Reserved MSEN Reserved MCH0MS[1:0] MCH0CAPPSC MCH0CAPFLT[3:0] [1:0] Output compare mode: Bits Fields Descriptions Reserved Must be kept at reset value.
Page 848 GD32H75E User Manual 0101: Force high. MO0CPRE is forced high level. 0110: PWM mode 0. When counting up, MO0CPRE is active as long as the counter is smaller than TIMERx_MCH0CV, otherwise it is inactive. When counting down, MO0CPRE is inactive as long as the counter is larger than TIMERx_MCH0CV, otherwise it is active.
Page 849 GD32H75E User Manual TIMERx_CHCTL2 register is reset). 000: Multi mode channel 0 is configured as output. 001: Multi mode channel 0 is configured as input, MIS0 is connected to MCI0FEM0. 010: Reserved. 011: Multi mode channel 0 is configured as input, MIS0 is connected to ITS, this mode is working only if an internal trigger input is selected (through TSCFG15[4:0] bit-field in SYSCFG_TIMERxCFG2(x=14,40,41,42,43,44) register).
Page 850 GD32H75E User Manual 11: Capture is done every 8 channel input edges. MCH0MS[1:0] Multi mode channel 0 I/O mode selection Same as output compare mode Multi mode channel control register 2 (TIMERx_MCHCTL2) Address offset: 0x50 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit).
Page 851 GD32H75E User Manual Multi mode channel 0 capture/compare value register (TIMERx_MCH0CV) Address offset: 0x54 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved MCH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 852 GD32H75E User Manual Channel 1 additional compare value register (TIMERx_CH1COMV_ADD) Address offset: 0x68 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH1COMVAL_ADD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0...
Page 853 GD32H75E User Manual 1: Enabled 27:22 Reserved Must be kept at reset value. 21:20 MCH0MSEL[1:0] Multi mode channel 0 mode select 00: Independent mode, MCH0 is independent of CH0 01: Reserved 10: Reserved 11: Complementary mode, only the CH0 is valid for input, and the outputs of MCH0...
Page 854 GD32H75E User Manual BRK0HPD BRK0IN0E BRK0CMP BRK0CMP Reserved Reserved Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. BRK0CMP1P BREAK0 CMP1 input polarity This bit is used to configure the CMP1 input polarity, and the specific polarity is determined by this bit and the BRK0P bit.
Page 855 GD32H75E User Manual BRK0CMP0EN BREAK0 CMP0 enable 0: CMP0 input disabled 1: CMP0 input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is BRK0HPDFEN BREAK0 HPDF input(hpdf_break[x], please refer to Table 34-2. HPDF internal signal) enable...
Page 856 GD32H75E User Manual DMA configuration register (TIMERx_DMACFG) Address offset: 0xE0 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DMATC[5:0] Reserved DMATA[5:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8...
Page 857 GD32H75E User Manual DMATB[15:0] Bits Fields Descriptions 31:0 DMATB[31:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address ranges from (start address) to (start address + transfer count * 4) will be accessed.
Page 858 GD32H75E User Manual This bit-field is set and reset by software. 1: If POEN bit and IOS bit are 0, the output is disabled. 0: No effect.
Page 859: Figure 22-109. General Level4 Timer Block Diagram
GD32H75E User Manual General level4 timer (TIMERx, x=15,16) 22.4. Overview 22.4.1. The general level4 timer module (TIMER15/16) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 860 GD32H75E User Manual configuration of the general level4 timer. Figure 22-109. General level4 timer block diagram Input Logic Synchronizer&Filter Edge selector Prescaler CH0_I &Edge Detector MCH0_I TIMERx_CHxCV/ CK_TIMER Counter TIMERx_MCHxCV PSC_CLK Counter Control TIMER_CK DMA REQ/ACK DMA controller TIMERx_CH0 TIMERx_UP...
Page 861: Figure 22-110. Normal Mode, Internal Clock Divided By 1
GD32H75E User Manual Figure 22-110. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 Prescaler The prescaler can divide the timer clock (TIMER_CK) to a counter clock (PSC_CLK) by any factor between 1 and 65536.
Page 862: Figure 22-112. Timing Diagram Of Up Counting Mode, Psc=0/2
GD32H75E User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts from 0. If the repetition counter is set, the update events will be generated after (TIMERx_CREP0/1+1) times of overflow.
Page 863: Figure 22-113. Timing Diagram Of Up Counting Mode, Change Timerx_Car On The Go
GD32H75E User Manual Timing diagram of up counting mode, Figure 22-113. change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG...
Page 864: Figure 22-114. Repetition Timechart For Up-Counter
GD32H75E User Manual Figure 22-114. Repetition timechart for up-counter TIMER_CK CNT_CLK 61 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 CNT_REG 62 63 00 01 Underflow Overflow TIMERx_CREP0 = 0x0...
Page 865: Figure 22-115. Input Capture Logic For Channel 0
GD32H75E User Manual Figure 22-115. Input capture logic for channel 0 Edge Detector Synchronizer Edge selector &inverter Based on CH0P&MCH0P TIMER_CK CI0FE0 Rising/Falling Capture Clock Register MCI0FE0 Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channals Figure 22-116.
Page 866: Figure 22-117. Output Compare Logic (When Mchxmsel = 2'00, X=0)
GD32H75E User Manual CHxCAPFLT or MCHxCAPFLT bit. Step2: Edge selection (CHxP and MCHxP bits in TIMERx_CHCTL2 register, MCHxFP[1:0] bits in TIMERx_MCHCTL2 register). Rising edge or falling edge, choose one by configuring CHxP and MCHxP bits or MCHxFP[1:0] bits. Step3: Capture source selection (CHxMS bit in TIMERx_CHCTL0 register, MCHxMS bit in TIMERx_MCHCTL0 register).
Page 867 GD32H75E User Manual Figure 22-118. Output compare logic (when MCHxMSEL = 2’11, x=0) The relationship between the channel output signal CHx_O/MCHx_O and the OxCPRE/ MOxCPRE signal (more details refer to Channel output prepare signal) is described as blew(the active level of OxCPRE is high and the active level of MOxCPRE is high).
Page 868: Figure 22-119. Output-Compare In Three Modes
GD32H75E User Manual counter reaches the value in the TIMERx_CHxCV/ TIMERx_MCHxCV register, the CHxIF/ MCHxIF bit will be set and the channel (n) interrupt is generated if CHxIE/ MCHxIE = 1. And the DMA request will be asserted, if CHxDEN/ MCHxDEN =1.
Page 869: Figure 22-118. Output Compare Logic (When Mchxmsel = 2'11, X=0)
GD32H75E User Manual The EAPWM’s period is determined by TIMERx_CAR and the duty cycle is determined by TIMERx_CHxCV/ TIMERx_MCHxCV. Figure 22-120. PWM mode timechart shows the EAPWM output and interrupts waveform. In up counting mode, if the value of TIMERx_CHxCV/ TIMERx_MCHxCV is greater than the value of TIMERx_CAR, the output will be always active in PWM mode 0 (CHxCOMCTL/ MCHxCOMCTL =4’b0110).
Page 870: Table 22-18. Complementary Outputs Controlled By Parameters (Mchxmsel =2'B11)
GD32H75E User Manual and the TIMERx_CHxCV content. Refer to the definition of relative bit for more details. Another special function of the OxCPRE signal is forced output which can be achieved by configuring the CHxCOMCTL field to 0x04/ 0x05. The output can be forced to an inactive/active level irrespective of the comparison condition between the values of the counter and the TIMERx_CHxCV.
Page 871 GD32H75E User Manual Complementary Parameters Output Status POEN ROS CHxEN MCHxEN CHx_O MCHx_O MCHx_O=OxCPRE⊕ CHx_O = LOW MCHxP CHx_O output disable. MCHx_O output enable. MCHx_O = LOW CHx_O=OxCPRE⊕CHxP CHx_O output enable. MCHx_O output disable. ⊕ MCHx_O = (! OxCPRE) CHx_O=OxCPRE⊕CHxP MCHxP.
Page 872: Figure 22-121. Complementary Output With Dead-Time Insertion
GD32H75E User Manual Sometimes, we can see corner cases about the dead time insertion. For example: the dead time delay is greater than or equal to the duty cycle of the CHx_O signal, then the CHx_O signal is always inactive (As shown in Figure 22-121.
Page 873: Figure 22-122. Break0 Function Logic Diagram
GD32H75E User Manual Figure 22-122. BREAK0 function logic diagram CKM clock monitor LVD lock event LOCKUP_LOCK event BRK0G SRAM parity error event BRK0EN BRKIN0 pin BRK0INEN Output BRK0INP Logic CMP0_OUT BRK0CMP0EN BRK0CMP0P Digital Filter CMP1_OUT BRK0CMP1EN BRK0CMP1P BRK0P HPDF_OUT BRK0F...
Page 874: Table 22-19. Break Function Input Pins Locked/ Released Conditions
GD32H75E User Manual Locked break function The BRKIN0 input pin of general timer have the locked break function, this function can be enabled by setting the BRK0LK bit in the TIMERx_CCHP register. When the locked break function is enabled, the BRKIN0 pins need to be configured to open- drain output mode with low level active (BRK0P=0 and BRK0IN0P=0).
Page 875: Figure 22-124. Brkin0 Pin Logic With Break0 Function
GD32H75E User Manual Figure 22-124. BRKIN0 pin logic with BREAK0 function CKM clock monitor LVD lock event LOCKUP_LOCK event SYSBIF BRK0G SRAM parity error event System source Flash ECC error requests BRK0EN HPDF_OUT BRK0HPDFEN Output Logic CMP0_OUT BRK0CMP0EN BRK0CMP0P Digital...
Page 876 GD32H75E User Manual Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Of course, you have to enable a DMA request which will be asserted by some internal event. When the interrupt event was asserted, TIMERx will send a request to DMA, which is configured to M2P mode and PADDR is TIMERx_DMATB, then DMA will access the TIMERx_DMATB.
Page 877 GD32H75E User Manual Register definition (TIMERx, x=15,16) 22.4.5. TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved UPIFBUE...
Page 878 GD32H75E User Manual counter stops at next update event. Update source This bit is used to select the update event sources by software. 0: Any of the following events generates an update interrupt or a DMA request: – The UPG bit is set.
Page 879 GD32H75E User Manual 29:10 Reserved Must be kept at reset value. ISO0N Idle state of multi mode channel 0 complementary output 0: When POEN bit is reset, MCH0_O is set low. 1: When POEN bit is reset, MCH0_O is set high.
Page 880 GD32H75E User Manual MCH0 Reserved Reserved MCH0IE Reserved Reserved CH0DEN UPDEN BRKIE Reserved CMTIE Reserved CH0IE UPIE Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. MCH0DEN Multi mode channel 0 capture/compare DMA request enable 0: Disabled 1: Enabled Note: This bit just used for channel input and output independent mode (when MMCH0SEL[1:0] = 2b’00).
Page 881 GD32H75E User Manual 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved MCH0OF Reserved MCH0IF Reserved rc_w0 rc_w0...
Page 882 GD32H75E User Manual 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRK0IF BREAK0 interrupt flag This flag is set by hardware when the BREAK0 input is active, and cleared by software if the BREAK0 input is not at active level.
Page 883 GD32H75E User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. MCH0G Multi mode channel 0 capture or compare event generation. This bit is set by software to generate a capture or compare event in multi mode channel 0, it is automatically cleared by hardware.
Page 884 GD32H75E User Manual 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH0COM Reserved CH0MS[2] Reserved Reserved...
Page 885 GD32H75E User Manual counter matches the output compare register TIMERx_CH0CV. 0011: Toggle on match. O0CPRE toggles when the counter matches the output compare register TIMERx_CH0CV. 0100: Force low. O0CPRE is forced low level. 0101: Force high. O0CPRE is forced high level.
Page 886 GD32H75E User Manual 011: Reserved 100: Channel 0 is configured as input, IS0 is connected to MCI0FE0. 101~111: Reserved. Input capture mode: Bits Fields Descriptions Reserved Must be kept at reset value. CH0MS[2] Channel 0 I/O mode selection Refer to CH0MS[1:0] description.
Page 887 GD32H75E User Manual Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved MCH0P MCH0EN CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value.
Page 888 GD32H75E User Manual 11: Noninverted/both channel 0 input signal’s edges. This bit cannot be modified when PROT[1:0] bit-field in TIMERx_CCHP register is 11 or 10. CH0EN Channel 0 capture/compare enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state.
Page 889 GD32H75E User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field will be loaded to the corresponding shadow register at every update event.
Page 890 GD32H75E User Manual CREP0[7:0] Counter repetition value 0 This bit-field specifies the update event generation rate. Each time the repetition counter counts down to zero, an update event will be generated. The update rate of the shadow registers is also affected by this bit-field when these shadow registers are enabled.
Page 891 GD32H75E User Manual 31:29 Reserved Must be kept at reset value. BRK0LK BREAK0 input locked 0: BREAK0 input in input mode 1: BREAK0 input in locked mode When the BRK0LK is set to 1, the BREAK0 input is configured in open drain output mode.
Page 892 GD32H75E User Manual POEN Primary output enable This bit is set by software or automatically set by hardware depending on the OAEN bit. It is cleared asynchronously by hardware as soon as the break input is active. When one of channels is configured in output mode, setting this bit enables the channel outputs (CHx_O and MCHx_O) if the corresponding enable bits (CHxEN, MCHxEN in TIMERx_CHCTL2 register) have been set.
Page 893 GD32H75E User Manual the channels which has been configured in output mode. Please refer to Table 22-15. Complementary outputs controlled by parameters (MCHxMSEL =2’b11). 0: “off-state” disabled. If the CHxEN/CHxNEN bits are both reset, the channels are output disabled. 1: “off-state” enabled. No matter the CHxEN/CHxNEN bits, the channels are “off- state”.
Page 894 GD32H75E User Manual Reserved MCH0CO Reserved MCH0COMCTL[2:0] Reserved MSEN Reserved MCH0MS[1:0] MCH0CAPPSC MCH0CAPFLT[3:0] [1:0] Output compare mode: Bits Fields Descriptions Reserved Must be kept at reset value. MCH0MS[2] Multi mode channel 0 I/O mode selection Refer to MCH0MS[1:0] description. 29:17 Reserved Must be kept at reset value.
Page 895 GD32H75E User Manual 0111: PWM mode 1. When counting up, MO0CPRE is inactive as long as the counter is smaller than TIMERx_MCH0CV, otherwise it is active. When counting down, MO0CPRE is active as long as the counter is larger than TIMERx_MCH0CV, otherwise it is inactive.
Page 896 GD32H75E User Manual An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample MCI0 input signal and the length of the digital filter applied to MCI0.
Page 897 GD32H75E User Manual 31:2 Reserved Must be kept at reset value. MCH0FP[1:0] Multi mode channel 0 capture/compare free polarity When multi mode channel 0 is configured in output mode, and the MCH0MSEL[1:0] = 2b’00, these bits specifie the multi mode channel 0 output signal polarity.
Page 898 GD32H75E User Manual enabled, the shadow register updates by every update event. Control register 2 (TIMERx_CTL2) Address offset: 0x74 Reset value: 0x0030 0000 This register has to be accessed by word (32-bit). MCH0MSEL[1:0] Reserved Reserved Reserved Bits Fields Descriptions 31:22 Reserved Must be kept at reset value.
Page 899 GD32H75E User Manual BRK0CMP1P BREAK0 CMP1 input polarity This bit is used to configure the CMP1 input polarity, and the specific polarity is determined by this bit and the BRK0P bit. 0: CMP1 input signal will not be inverted (BRK0P =0, the input signal is active low;...
Page 900 GD32H75E User Manual signal) enable 0: HPDF input disabled 1: HPDF input enabled This bit can be modified only when PROT[1:0] bit-field in TIMERx_CCHP register is Reserved Must be kept at reset value. BRK0IN0EN BREAK0 BRKIN0 alternate function input enable...
Page 901 GD32H75E User Manual Reserved DMATC[5:0] Reserved DMATA[5:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 DMATC[5:0] DMA transfer count This field defines the times of accessing(R/W) the TIMERx_DMATB register by DMA. 6’b000000: transfer 1 time 6’b000001: transfer 2 times …...
Page 902 GD32H75E User Manual The transfer count is calculated by hardware, and ranges from 0 to DMATC. Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CCUSEL CREPSEL CHVSEL OUTSEL...
Page 903: Figure 22-126. Basic Timer Block Diagram
GD32H75E User Manual Basic timer (TIMERx, x=5,6,50,51) 22.5. Overview 22.5.1. The basic timer module(TIMER5/6/50/51) has a 32-bit or 64-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate a DMA request and a TRGO0 to connect to DAC.
Page 904: Figure 22-127. Normal Mode, Internal Clock Divided By 1
GD32H75E User Manual Figure 22-127. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG 20 21 01 02 Prescaler The prescaler can divide the timer clock (TIMER_CK) to a counter clock (PSC_CLK) by any factor ranging from 1 to 65536.
Page 905: Figure 22-129. Timing Chart Of Up Counting Mode, Psc=0/2 (Timerx, X=5,6)
GD32H75E User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR/ TIMERx_CARL/ TIMERx_CARH register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts from 0. The update event is generated each time when counter overflows.
Page 906 GD32H75E User Manual (TIMERx, x=5,6) TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 907 GD32H75E User Manual Registers definition (TIMERx, x=5,6,50,51) 22.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 TIMER50 base address: 0x4000 F000 TIMER51 base address: 0x4000 F400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 908 GD32H75E User Manual This bit is used to select the update event sources by software. 0: When enabled, any of the following events generates an update interrupt or a DMA request: – The UPG bit is set – The counter generates an overflow event –...
Page 909 GD32H75E User Manual slave timer for synchronization function. 000: Reset. When the UPG bit in the TIMERx_SWEVG register is set or a reset is generated by the slave mode controller, a TRGO0 pulse occurs. And in the latter case, the signal on TRGO0 is delayed compared to the actual reset.
Page 910 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved UPIF rc_w0 Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. UPIF Update interrupt flag This bit is set by hardware when an update event occurs and cleared by software.
Page 911 GD32H75E User Manual UPIFBU rw/ r CNT[15:0] UPIFBUEN = 0: Bits Fields Descriptions 31:0 CNT[31:0] This bit-field indicates the current counter value. Writing to this bit-field can change the value of the counter. UPIFBUEN = 1: Bits Fields Descriptions UPIFBU UPIF bit backup This bit is a backup of UPIF bit in TIMERx_INTF register, and read-only.
Page 912 GD32H75E User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-field will be loaded to the corresponding shadow register at every update event.
Page 913 GD32H75E User Manual Bits Fields Descriptions 31:0 CARLL[31:0] Counter auto reload low value This bit-field specifies the auto reload low value of the counter. Counter high register (TIMERx_CNTH) (TIMERx, x=50,51) Address offset: 0xD0 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 914 GD32H75E User Manual Bits Fields Descriptions 31:0 CARLH[63:32] Counter auto reload high value This bit-field specifies the auto reload high value of the counter.
Page 915: Universal Synchronous / Asynchronous Receiver
GD32H75E User Manual Universal synchronous / asynchronous receiver / transmitter (USART) Overview 23.1. The Universal Synchronous / Asynchronous Receiver / Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (CK_APBx, CK_AHB, CK_LXTAL or CK_IRC64MDIV) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 916 GD32H75E User Manual  Parity control: Transmits parity bit. – Checks parity of received data byte. – LIN break generation and detection.   IrDA support.  Synchronous mode and transmitter clock output for synchronous transmission.  ISO 7816-3 compliant smartcard interface: Character mode (T = 0).
Page 917: Function Overview
GD32H75E User Manual Function overview 23.3. The interface is externally connected to another device by the main pins listed in Table 23-1. Description of USART important pins. Table 23-1. Description of USART important pins Type Description Input Receive Data Output I/O (single-wire / Transmit Data.
Page 918: Figure 23-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32H75E User Manual register. Figure 23-2. USART character frame (8 bits data and 1 stop bit) CLOCK Data frame or parity bit Start bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 Start Stop Idle frame Start Stop Stop Start Break frame In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register.
Page 919: Usart Transmitter
GD32H75E User Manual USARTDIV = 33 + 13 / 16 = 33.81. Get the value of USART_BAUD by calculating the value of USARTDIV: If USARTDIV = 30.37, then INTDIV = 30 (0x1E). 16*0.37 = 5.92, the nearest integer is 6, so FRADIV = 6 (0x6).
Page 920: Figure 23-3. Usart Transmit Procedure
GD32H75E User Manual Figure 23-3. USART transmit procedure It is necessary to wait for the TC bit to be asserted before disabling the USART or entering the power saving mode. The TC bit can be cleared by set the TCC bit in USART_INTC register.
Page 921: Figure 23-4. Oversampling Method Of A Receive Frame Bit (Osb = 0)
GD32H75E User Manual bit in USART_CTL2 register is set. If the OSB bit in USART_CTL2 register is set, the receiver gets only one sample to evaluate a bit value. In this situation, no noisy error will be detected. Figure 23-4. Oversampling method of a receive frame bit (OSB = 0)
Page 922: Figure 23-5. Configuration Step When Using Dma For Usart Transmission
GD32H75E User Manual and the DENR bit in USART_CTL2 is used to enable the DMA reception. When DMA is used for USART transmission, DMA transfers data from internal SRAM to the transmit data buffer of the USART. The configuration step are shown in Figure 23-5.
Page 923: Figure 23-6. Configuration Step When Using Dma For Usart Reception
GD32H75E User Manual Figure 23-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA...
Page 924: Figure 23-8. Hardware Flow Control
GD32H75E User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full.
Page 925: Lin Mode
GD32H75E User Manual The idle frame wake up method is selected by default. If the RWU bit is reset, an idle frame is detected on the RX pin, the IDLEF bit in USART_STAT will be set. If the RWU bit is set, an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode.
Page 926: Figure 23-9. Break Frame Occurs During Idle State
GD32H75E User Manual by 1 stop bit. The break detection function is totally independent of the normal USART receiver. So a break frame can be detected during the idle state or during a frame. The expected length of a break frame can be selected by configuring LBLEN in USART_CTL1.
Page 927: Figure 23-11. Example Of Usart In Synchronous Mode
GD32H75E User Manual The clock is synchronized with the data transmitted. The receiver in synchronous mode samples the data on the transmitter clock without any oversampling. Figure 23-11. Example of USART in synchronous mode Data output Data input USART Device...
Page 928: Figure 23-13. Irda Sir Endec Module
GD32H75E User Manual Figure 23-13. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 929: Figure 23-15. Iso7816-3 Frame Format
GD32H75E User Manual Half-duplex communication mode 23.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 930 GD32H75E User Manual can automatically resend data according to the protocol for SCRTNUM times. An interframe gap of 2.5 bits time will be inserted before the start of a resented frame. At the end of the last repeated character the TC bit is set immediately without guard time. The USART will stop transmitting and assert the frame error status if it still receives the NACK signal after the programmed number of retries.
Page 931: Direct And Inverse Convention
GD32H75E User Manual third character. The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set). The RT interrupt may occur in case of an error in the block length.
Page 932: Figure 23-16. Usart Receive Fifo Structure
GD32H75E User Manual an interrupt is generated if the RFTIE bit is set. An interrupt will be generated when receive FIFO is not empty if RFNEIE bit is set. Figure 23-16. USART receive FIFO structure If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out.
Page 933: Usart Interrupts
GD32H75E User Manual The UESM bit must be set and the USART clock must be set to CK_IRC64MDIV or CK_LXTAL (refer to the reset and clock unit RCU section). When using the standard RBNE interrupt, the RBNEIE bit must be set before entering deep- sleep mode.
Page 934: Figure 23-18. Usart Interrupt Mapping Diagram
GD32H75E User Manual Interrupt event Event flag Enable Control bit overrun error, framing error) ADDR0 match AMF0 AMIE0 ADDR1 match AMF1 AMIE1 Receiver timeout error RTIE End of Block EBIE Wakeup from Deep-sleep WUIE mode All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time.
Page 935: Register Definition
GD32H75E User Manual Register definition 23.4. USART0 base address: 0x4001 1000 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 USART5 base address: 0x4001 1400 UART6 base address: 0x4000 7800...
Page 936 GD32H75E User Manual 0: End of block interrupt is disabled 1: End of block interrupt is enabled This bit is reserved in UART3 / UART4 / UART6 / UART7. RTIE Receiver timeout interrupt enable 0: Receiver timeout interrupt is disabled 1: Receiver timeout interrupt is enabled This bit is reserved in UART3 / UART4 / UART6 / UART7.
Page 937 GD32H75E User Manual This bit field cannot be written when the USART is enabled (UEN = 1). Parity mode 0: Even parity 1: Odd parity This bit field cannot be written when the USART is enabled (UEN = 1). PERRIE...
Page 938 GD32H75E User Manual 1: Receiver is enabled and begins searching for a start bit UESM USART enable in Deep-sleep mode 0: USART not able to wake up the MCU from Deep-sleep mode. 1: USART able to wake up the MCU from Deep-sleep mode. Providing that the clock source for the USART must be CK_IRC64MDIV or CK_LXTAL.
Page 939 GD32H75E User Manual 0: Data is transmitted / received with the LSB first 1: Data is transmitted / received with the MSB first This bit field cannot be written when the USART is enabled (UEN = 1). DINV Data bit level inversion...
Page 940 GD32H75E User Manual This bit field cannot be written when the USART is enabled (UEN = 1). Clock phase 0: The first clock transition is the first data capture edge in synchronous mode 1: The second clock transition is the first data capture edge in synchronous mode This bit field cannot be written when the USART is enabled (UEN = 1).
Page 941 GD32H75E User Manual ADDR1[7:0] ADDM1 WUIE WUM[1:0] SCRTNUM[2:0] AMEN1 DDRE OVRD CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields Descriptions 31:24 ADDR1[7:0] Address 1 of the USART terminal These bits give the address 1 of the USART terminal.
Page 942 GD32H75E User Manual 19:17 SCRTNUM[2:0] Smartcard auto-retry number In smartcard mode, these bits specify the number of retries in transmission and reception. In transmission mode, a transmission error (FERR bit set) will occur after this number of automatic retransmission retries.
Page 943 GD32H75E User Manual overwrites the previous content of the USART_RDATA register. When FIFO mode is enabled, the data is written in USART_RDATA directly and Receive FIFO is bypassed. Even if FIFO is enabled, the RBNE bit is to be used.
Page 944 GD32H75E User Manual This bit field cannot be written when the USART is enabled (UEN = 1). IRLP IrDA low-power 0: Normal mode 1: Low-power mode This bit field cannot be written when the USART is enabled (UEN = 1).
Page 945 GD32H75E User Manual Reset value: 0x0000 0000 This register cannot be written when the USART is enabled (UEN = 1). This register is reserved in UART3 / UART4 / UART6 / UART7. This register has to be accessed by word (32-bit).
Page 946 GD32H75E User Manual BL[7:0] RT[23:16] RT[15:0] Bits Fields Descriptions 31:24 BL[7:0] Block Length These bits specify the block length in smartcard T=1 reception. Its value equals the number of information characters + the length of the Epilogue Field (1 - LEC / 2- CRC) - 1.
Page 947 GD32H75E User Manual 31:5 Reserved Must be kept at reset value. TXFCMD Transmit data flush request When FIFO is disabled, Writing 1 to this bit sets the TBE flag, to discard the transmit data. When FIFO is enabled, Writing 1 to this bit flushes the whole Transmit FIFO and sets TFE flag in USART_FCS.
Page 948 GD32H75E User Manual 1: The USART core receiving logic has been enabled Transmit enable acknowledge flag This bit, which is set / reset by hardware, reflects the transmit enable state of the USART core logic. 0: The USART core transmitting logic has not been enabled...
Page 949 GD32H75E User Manual 0: ADDR1 character does not match the received character 1: ADDR1 character matches the received character, an interrupt is generated if AMIE1 = 1 in the USART_CTL0 register. Set by hardware, when the character defined by ADDR1[7:0] is received.
Page 950 GD32H75E User Manual When FIFO is disabled: Transmit data register empty 0: Data is not transferred to the shift register 1: Data is transferred to the shift register. An interrupt will occur if the TBEIE bit is set in USART_CTL0...
Page 951 GD32H75E User Manual USART_CMD. IDLEF IDLE line detected flag 0: No Idle line is detected 1: Idle line is detected. An interrupt will occur if the IDLEIE bit is set in USART_CTL0 Set by hardware when an Idle line is detected. It will not be set again until the RBNE bit or RFNE bit has been set itself.
Page 952 GD32H75E User Manual 1: Parity error flag is detected. An interrupt will occur if the PERRIE bit is set in USART_CTL0. Set by hardware when a parity error occurs in receiver mode. Cleared by writing 1 to PEC bit in USART_INTC register.
Page 953 GD32H75E User Manual Writing 1 to this bit clears the CTSF bit in the USART_STAT register. LBDC LIN break detected clear Writing 1 to this bit clears the LBDF flag in the USART_STAT register. This bit is reserved in UART3 / UART4 / UART6 / UART7.
Page 954 GD32H75E User Manual the USART_CTL0 register). Transmit data register (USART_TDATA) 23.4.11. Address offset: 0x28 Reset value: Undefined This register has to be accessed by word (32-bit). Reserved Reserved TDATA[9:0] Bits Fields Descriptions 31:10 Reserved Must be kept at reset value...
Page 955 GD32H75E User Manual 1: Parity error is detected. Reserved Must be kept at reset value. Hardware flow control coherence mode 0: nRTS signal equals to the RBNE in status register 1: nRTS signal is set when the last data bit (parity bit when pce is set) has been sampled.
Page 956 GD32H75E User Manual TFTIF Transmit FIFO threshold interrupt flag The bit is valid when TFTIE bit is set. 0: Transmit FIFO does not reach the programmed threshold 1: Transmit FIFO reached the programmed threshold TFEIF Transmit FIFO empty interrupt flag The bit is valid when TFEIE bit is set.
Page 957 GD32H75E User Manual Receive FIFO empty flag 0: Receive FIFO is not empty 1: Receive FIFO is empty. RFFIE Receive FIFO full interrupt enable If this bit is set, an interrupt occurs when the RFF bit is set. 0: Receive FIFO full interrupt is disable...
Page 958 GD32H75E User Manual These bits and RFCNT[2:0] bits determine the eceive FIFO counter number. ELNACK Early NACK when smartcard mode is selected. The NACK pulse occurs 1/16 bit time earlier when the parity error is detected. 0:Early NACK disable when smartcard mode is selected 1:Early NACK enable when smartcard mode is selected This bit is reserved in UART3 / UART4 / UART6 / UART7.
Page 959: Inter-Integrated Circuit Interface (I2C)
GD32H75E User Manual Inter-integrated circuit interface (I2C) Overview 24.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL.
Page 960: Table 24-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32H75E User Manual Figure 24-1. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Register Digital Noise...
Page 961: Figure 24-2. Data Validation
GD32H75E User Manual  < ( t ) /4 I2CCLK filters  <t I2CCLK HIGH with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter.
Page 962: Figure 24-3. Start And Stop Condition
GD32H75E User Manual signal. Figure 24-3. START and STOP condition START STOP Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device.
Page 963: Figure 24-5. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32H75E User Manual Figure 24-5. I2C communication flow with 7-bit address (Master Transmit) Start Slave address …… W(0) DATA0 DATAN Stop data transfer (N+1 bytes) From master to slave From slave to master Figure 24-6. I2C communication flow with 7-bit address (Master Receive) In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent.
Page 964: Noise Filter
GD32H75E User Manual Noise filter 24.3.3. The noise filters must be configured before setting the I2CEN bit in I2C_CTL0 register if it is necessary. The analog noise filter is disabled by setting the ANOFF bit in I2C_CTL0 register and enabled when ANOFF is 0. It can suppress spikes with a pulse width up to 130ns in fast mode and fast mode plus.
Page 965: Figure 24-10. Data Setup Time
GD32H75E User Manual Figure 24-10. Data setup time SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t = SDADELY * t where t = (PSC+1) * t SDADELY...
Page 966: Table 24-2. Data Setup Time And Data Hold Time
GD32H75E User Manual Table 24-2. Data setup time and data hold time Standard Fast mode Fast mode SMBus Symbol Parameter mode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of...
Page 967: Figure 24-11. Data Transmission
GD32H75E User Manual Figure 24-11. Data transmission SCL Stretch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA Data Reception When receiving data, the data will be received in the shift register first. If RBNE is 0, the data in the shift register will move into I2C_RDATA register.
Page 968: I2C Slave Mode
GD32H75E User Manual Working mode Action Slave receiver mode ACK control SMBus mode PEC generation/checking The number of bytes to be transferred is configured by BYTENUM[7:0] in I2C_CTL1 register. If BYTENUMis greater than 255, or in slave byte control mode, the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register.
Page 969: Slave Byte Control Mode
GD32H75E User Manual before the first data byte writing to the I2C_TDATA register. Or the SCL will be stretched before the new data is written to the I2C_TDATA register after the previous data transmission is completed. In slave receiving mode, a new reception is completed but the data in I2C_RDATA ...
Page 970: Figure 24-13. I2C Initialization In Slave Mode
GD32H75E User Manual Only when the ADDSEND=1 or TCR=1, the RELOAD bit can be modified. Figure 24-13. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0...
Page 971: Figure 24-14. Programming Model For Slave Transmitting When Ss=0
GD32H75E User Manual configured in the ADDSEND interrupt service routine. And the number of TI events is equal to the value of BYTENUM[7:0]. When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set. In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine.
Page 972: Figure 24-15. Programming Model For Slave Transmitting When Ss=1
GD32H75E User Manual Figure 24-15. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in...
Page 973: Figure 24-16. Programming Model For Slave Receiving
GD32H75E User Manual Figure 24-16. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND...
Page 974: Figure 24-17. I2C Initialization In Master Mode
GD32H75E User Manual configured in I2C_CTL1 register. When the addressing mode is 10-bit in master receiving mode, the HEAD10R bit must be configured to decide whether the complete address sequence must be executed, or only the header to be sent. The number of bytes to be transferred should be configured in BYTENUM[7:0] in I2C_CTL1 register.
Page 975: Figure 24-18. Programming Model For Master Transmitting (N<=255)
GD32H75E User Manual  If data of BYTENUM[7:0] bytes have been transferred and RELOAD=0, the AUTOEND bit in I2C_CTL1 can be set to generate a STOP signal automatically. When AUTOEND is 0, the TC bit in I2C_STAT register will be set and the SCL is stretched. In this case, the master can generate a STOP signal by setting the STOP bit in the I2C_CTL1 register.
Page 976: Figure 24-19. Programming Model For Master Transmitting (N>255)
GD32H75E User Manual Figure 24-19. Programming model for master transmitting (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to...
Page 977: Figure 24-20. Programming Model For Master Receiving (N<=255)
GD32H75E User Manual Figure 24-20. Programming model for master receiving (N<=255) I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 978: Figure 24-21. Programming Model For Master Receiving (N>255)
GD32H75E User Manual Figure 24-21. Programming model for master receiving (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge...
Page 979: Address Resolution Protocol
GD32H75E User Manual Configuration and Power Management Interface (abbreviated to ACPI) specifications. Address resolution protocol The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’...
Page 980: Packet Error Checking
GD32H75E User Manual The BUSTOB[11:0] is used to check the t of the slave and the t of the LOW:SEXT LOW:MEXT master. The timer can be enabled by setting the EXTOEN bit in the I2C_TIMEOUT register, after the EXTOEN bit is set, the BUSTOB[11:0] cannot be changed. If the SCL stretching time...
Page 981: Smbus Slave Mode
GD32H75E User Manual check in order to obtain the t parameter. To detect SCL and SDA high level timeouts, the IDLE TOIDLE bit must be set. Then setting the TOEN bit in the I2C_TIMEOUT register to enable the timer, after the TOEN bit is set, the BUSTOA[11:0] bit and the TOIDLE bit cannot be changed.
Page 982: Figure 24-22. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32H75E User Manual Figure 24-22. SMBus master transmitter and slave receiver communication flow Start Slave address …… W(0) DATA0 DATA N-1 Stop data transfer (N+1 bytes) From master to slave From slave to master SMBus master receiver and slave transmitter If the SMBus master is required to receive PEC at the end of bytes transfer, automatic end mode can be enabled.
Page 983: Table 24-4. I2C Error Flags
GD32H75E User Manual clears the ADDSEND flag and the transmission proceeds normally. If the detected address does not match, IRC64M will be closed again and the MCU will not be wake up. Only an address match interrupt (ADDMIE = 1) can wakeup the MCU. If the clock source of I2C is the system clock, or WUEN = 0, IRC64M will not switched on after receiving start signal.
Page 984: I2C Debug Mode
GD32H75E User Manual nterrupt event Event flag Enable control bit Address match ADDSEND ADDMIE Not acknowledge received NACK NACKIE Bus error BERR Arbitration Lost LOSTARB Overrun/Underrun error OUERR ERRIE PEC error PECERR Timeout error TIMEOUT SMBus Alert SMBALT I2C debug mode 24.3.14.
Page 985: Register Definition
GD32H75E User Manual Register definition 24.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 I2C2 base address: 0x4000 C000 I2C3 base address: 0x4000 5C00 Control register 0 (I2C_CTL0) 24.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 986 GD32H75E User Manual 1: Host address is enabled, address 0b0001000x will be acknowledged. GCEN Whether or not to response to a General Call (0x00) 0: Slave won’t response to a General Call 1: Slave will response to a General Call...
Page 987 GD32H75E User Manual or SMBALT bit is set, an interrupt will be generated. TCIE Transfer complete interrupt enable 0: Transfer complete interrupt is disabled 1: Transfer complete interrupt is enabled STPDETIE Stop detection interrupt enable 0: Stop detection (STPDET) interrupt is disabled...
Page 988 GD32H75E User Manual PECTRANS PEC Transfer Set by software. Cleared by hardware in the following cases: When PEC byte is transferred or ADDSEND bit is set or STOP signal is detected or I2CEN=0. 0: Don’t transfer PEC value 1: Transfer PEC Note: This bit has no effect when RELOAD=1, or SBCTL=0 in slave mode.
Page 989 GD32H75E User Manual 0: START will not be sent 1: START will be sent HEAD10R 10-bit address header executes read direction only in master receive mode 0: The 10 bit master receive address sequence is START + header of 10-bit address (write) + slave address byte 2 + RESTART + header of 10-bit address (read).
Page 990 GD32H75E User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ADDRESSEN I2C address enable 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave...
Page 991 GD32H75E User Manual 10:8 ADDMSK2[2:0] ADDRESS2[7:1] mask Defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don’t care). 000: No mask, all the bits must be compared. n(001~110): ADDRESS2[n:0] is masked. Only ADDRESS2[7:n+1] are compared.
Page 992 GD32H75E User Manual configuring these bits. And during t , the SCL line is stretched low in master SDADELY mode and in slave mode when SS = 0. = SDADELY x t SDADELY 15:8 SCLH[7:0] SCL high period SCL high period can be generated by configuring these bits.
Page 993 GD32H75E User Manual than t when TOIDLE =1, a timeout error is detected. IDLE 0: SCL timeout detection is disabled 1: SCL timeout detection is enabled 14:13 Reserved Must be kept at reset value. TOIDLE Idle clock timeout detection 0: BUSTOA is used to detect SCL low timeout 1: BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle Note: This bit can be written only when TOEN =0.
Page 994 GD32H75E User Manual 1: I2C communication active. Reserved Must be kept at reset value. SMBALT SMBus Alert When SMBHAEN=1, SMBALTEN=1, and a SMBALERT event (falling edge) is detected on SMBA pin, this bit will be set by hardware. It is cleared by software by setting the SMBALTC bit.
Page 995 GD32H75E User Manual zero value. 0: When RELOAD=1, transfer of BYTENUM[7:0] bytes is not completed 1: When RELOAD=1, transfer of BYTENUM[7:0] bytes is completed Transfer complete in master mode This bit is set by hardware when RELOAD=0, AUTOEND=0 and data of BYTENUM[7:0] bytes have been transferred.
Page 996 GD32H75E User Manual set by software in order to empty the I2C_TDATA register. 0: I2C_TDATA is not empty 1: I2C_TDATA is empty Status clear register (I2C_STATC) 24.4.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 997 GD32H75E User Manual Software can clear the ADDSEND bit of I2C_STAT by writing 1 to this bit. Reserved Must be kept at reset value. PEC register (I2C_PEC) 24.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 998 GD32H75E User Manual This register has to be accessed by word (32-bit). Reserved Reserved TDATA [7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value Control register 2 (I2C_CTL2) 24.4.12. Address offset: 0x90 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 999: Serial Peripheral Interface/Inter-Ic Sound (Spi/I2S)
GD32H75E User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) Overview 25.1. The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 1000: Spi Block Diagram
GD32H75E User Manual  Four I2S standards supported: Philips, MSB justified, LSB justified and PCM standard.  Data length can be 16 bits, 24 bits or 32 bits.  Channel length can be 16 bits or 32 bits.  Bit order can be LSB or MSB.

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