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Advantech PCIE-1812 User Manual

Advantech PCIE-1812 User Manual

16-bit multifunction card with pci express bus
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PCIE-1812
16-bit Multifunction Card with
PCI Express Bus

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Summary of Contents for Advantech PCIE-1812

  • Page 1 User Manual PCIE-1812 16-bit Multifunction Card with PCI Express Bus...

  • Page 2: Product Warranty (2 Years)

    No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. The information provided in this manual is intended to be accurate and reliable.

  • Page 3: Technical Support And Assistance

    This product has passed the CE test for environmental specifications when shielded cables are used for external wiring. We recommend the use of shielded cables. This type of cable is available from Advantech. Please contact your local supplier for ordering information.
  • Page 4 PCIE-1812 User Manual...

  • Page 5: Table Of Contents

    Figure 2.13Counter output signal connection ......16 2.3.8 Pin Assignment (CN4) ..............17 Figure 2.14Pin assignment ............17 Table 2.5: Pin assignment ............18 Grounding Considerations ..............19 2.4.1 Signal Source Type..............19 Figure 2.15Signal source type ............ 19 PCIE-1812 User Manual...
  • Page 6 Figure 3.27Quadrature x2 mode, counter B leads counter A ..38 Figure 3.28Quadrature x4 mode, counter A leads counter B ..39 Figure 3.29Quadrature x4 mode, counter B leads counter A ..39 Figure 3.30Two pulse (clockwise/counter-clockwise) mode..39 PCIE-1812 User Manual...
  • Page 7 Figure 3.67Firmware/FPGA code download utility ..... 58 Appendix A Specifications ........59 Function Block Diagram ................60 Figure A.1 Function Block ............60 Analog Input .................... 61 Table A.1: -3 dB Bandwidth ............61 Table A.2: Accuracy..............61 PCIE-1812 User Manual...
  • Page 8 Multi-Device Synchronization Interface (MDSI) ........67 Counter ....................67 A.10 FPGA Code Update ................68 A.11 General Specifications ................68 A.11.1 Power Requirements ..............68 A.11.2 Power Supply Output..............68 A.11.3 Physical ..................69 A.11.4 Environmental................69 PCIE-1812 User Manual viii...

  • Page 9: Chapter 1 Start Using Pcie-1812

    Chapter Start Using PCIE-1812...

  • Page 10: Product Overview

    (except for 0) for hardware devices with the same model name. Refer to the device specifications for the configuration of the board ID. If changed, the new board ID value takes effect only after a cold reset of the device. PCIE-1812 User Manual...

  • Page 11: Driver Installation

    DAQ devices. All these software packages are available on Advantech website: http://www.advantech.com/. The Advantech Navigator is a utility that allows you to set up, configure and test your device, and later store your settings in a proprietary database.

  • Page 12: Software Development Using Daqnavi Sdk

    FPGA Code Updates The FPGA can also be updated via the interface in Navigator. However, it is not advised to update FPGA without first doing some research. Advantech strongly sug- gests you consult your technical support before starting an FPGA update.

  • Page 13: Chapter 2 Installation Guide

    Chapter Installation Guide...

  • Page 14: Initial Unpacking Check

    PCIE-1812 card  Startup Manual  Hardware Installation and Configuration 2.2.1 Installation Before you install your PCIE-1812, please make sure you have the following compo- nents: PCIE-1812 card  PCIE-1812 User Manual  Advantech DAQNavi SDK and its corresponding device driver ...

  • Page 15: Configuration - Board Id (Sw1)

    2.2.3 Configuration - DI/O Control Selection (JP2 ~ JP9) Table 2.2: Configuration - DI/O Control Selection (JP2 ~ JP9) Jumper Setting Description DI/O channel direction is software configurable.* DI/O channels are fixed at output * Default setting. PCIE-1812 User Manual...
  • Page 16 * Default setting. 2.2.4 Multi-Device Synchronization Interface (CN2 ~ CN3) Table 2.4: Multi-Device Synchronization Interface (CN2 ~ CN3) Connector Description MDSI input. MDSI output. Note! Refer to “3.7 Synchronize by MDSI Cables/Table 3.1” for description of these connectors. PCIE-1812 User Manual...

  • Page 17: Signal Connection And Pin Assignment

    Analog input signal connection and internal functional block diagram is shown in Fig- ure 2. 1. Figure 2.1 Analog input signal connection   PCIE-1812 User Manual...

  • Page 18: Analog Output Signal Connection

    In this configuration, however, the output voltage is not calibrated, and the accuracy of the output voltage depends on the accuracy of the external reference voltage. Users can perform calibration through the calibration utility in the Advantech Navigator by themselves.

  • Page 19: Trigger Input Signal Connection

    And another trigger occurs only if the signal has crossed the voltage specified by the threshold level minus the hysteresis value from above before it crosses the threshold level from below again. This is shown in Figure 2. 5. Figure 2.5 Rising edge active analog trigger PCIE-1812 User Manual...

  • Page 20: Digital Input Signal Connection

    OFF. Additionally, avoid applying a voltage that exceeds the maximum allowable ON state value or falls below the minimum allowable OFF state value, as this may cause damage to the device. Please refer to the device specifications for the exact ON and OFF voltage ranges. PCIE-1812 User Manual...
  • Page 21 Figure 2. 9. Be sure the voltage of the external source is within the allowable range of the ON state as specified in the device specifications. Figure 2.8 Digital input signal connection using a switch with internal pull-up resistor Figure 2.9 Digital input signal connection using a switch with internal pull- down resistor PCIE-1812 User Manual...

  • Page 22: Digital Output Signal Connection

    Each digital output channel can source or sink only finite amount of current. If this limit is exceeded, the output voltage will not stay in the specified voltage logic level. Refer to the device specifications for the maximum source and skin current values. PCIE-1812 User Manual...

  • Page 23: Counter Input Signal Connection

    ON state or lower than the minimum allowable value of the OFF state. The device may be damaged under such circumstance. Refer to the device specifications for ON and OFF state voltage ranges. PCIE-1812 User Manual...

  • Page 24: Counter Output Signal Connection

    Each counter output channel can source or sink only finite amount of current. If this limit is exceeded, the output voltage will not stay in the specified voltage logic level. Refer to the device specifications for the maximum source and skin current values. PCIE-1812 User Manual...

  • Page 25: Pin Assignment (Cn4)

    2.3.8 Pin Assignment (CN4) Figure 2.14 Pin assignment PCIE-1812 User Manual...
  • Page 26 Counter sample clock/latch CNT<0..3>_SCLK/L I 3, 8, 53, 58 input terminals. CNT<0..3>_OUT Counter output terminals. 2, 7, 52, 57 Ground terminals for digital sig- DGND 12, 29, 62, 79 nals. +12V +12 V supply output. +5 V supply output. PCIE-1812 User Manual...

  • Page 27: Grounding Considerations

    This is shown in Figure 2. 16. Figure 2.16 Ground loop effect If differential (ungrounded) input configuration is used instead, the high input imped- ance of the negative input terminal prevents ground loop current from flowing, and therefore rejects the common-mode noise. PCIE-1812 User Manual...

  • Page 28: Measuring An Ungrounded (Floating) Signal Source

    However, this will lead to an unbalanced system if the source impedance is relatively high. A balanced system is desirable from a noise immunity point of view. PCIE-1812 User Manual...

  • Page 29: Field Wiring Considerations

    Route signal lines at right angles to noise generating cables.  Use differential input configuration to reduce common-mode noise.  For externally powered modules, use separate power sources for modules and  other noise generating equipment. PCIE-1812 User Manual...
  • Page 30 PCIE-1812 User Manual...

  • Page 31: Chapter 3 Functions Details

    Chapter Functions Details...

  • Page 32: Analog Input

    Figure 3. Figure 3.1 Instant (software-timed) analog input acquisition The advantage of instant acquisition is low latency. It is typically used for reading a single sample of analog input. PCIE-1812 User Manual...

  • Page 33: Buffered (Hardware-Timed) Analog Input Acquisition

    Buffered acquisition is also called hardware-timed acquisition. The advantages of buffered acquisition over instant acquisition include: The sample rate can be much higher.  The time of sample is deterministic.  Hardware triggers can be used.    PCIE-1812 User Manual...

  • Page 34: Analog Output

    Figure 3. 4. For synchronous update, however, the values to be updated are first stored in the device, and all analog output channels are updated synchronously when the synchronous write command is sent. This is shown in Figure 3. 5. Figure 3.4 Analog output asynchronous update PCIE-1812 User Manual...

  • Page 35: Buffered (Hardware-Timed) Analog Output Generation

    (DMA) engine, and converted by the DAC one sample at a time. A buffer is a block of memory in the PC for temporarily storing the data to be transferred to the onboard FIFO. Because the data is moved in large PCIE-1812 User Manual...

  • Page 36: Digital Input

    Figure 3. 7. Figure 3.7 Instant (software-timed) digital input acquisition The advantage of instant acquisition is low latency. It is typically used for reading a single sample of digital input. PCIE-1812 User Manual...

  • Page 37: Buffered (Hardware-Timed) Digital Input Acquisition

    Buffered acquisition is also called hardware-timed acquisition. The advantages of buffered acquisition over instant acquisition include: The sample rate can be much higher.  The time of sample is deterministic.  Hardware triggers can be used.  PCIE-1812 User Manual...

  • Page 38: Digital Output

    Figure 3.10 Buffered (hardware-timed) digital output generation The samples to be generated are provided by the application. They are first stored in the buffer of the PC, moved to the onboard first-in-first-out (FIFO) memory of the PCIE-1812 User Manual...

  • Page 39: Counter

    Figure 3. 11 and Figure 3. 12, respectively. Figure 3.11 Rising edge event counting Figure 3.12 Falling edge event counting Counting may be temporarily paused by the counter gate signal as shown in Figure 3. 13. Figure 3.13 Event counting with pause gate PCIE-1812 User Manual...
  • Page 40 Figure 3. 15.The sample clock can be generated internally on the device or be provided externally. Refer to the device specifications for supported sample clock sources and the maximum allowable fre- quency of sample clock. Figure 3.15 Buffered (hardware-timed) event counting PCIE-1812 User Manual...

  • Page 41: Frequency Measurement

    The frequency of the signal is then calculated by dividing this number by the time duration. This is shown in Figure 3. 17 and by the following equation. Figure 3.17 Frequency measurement by counting number of pulses in fixed duration PCIE-1812 User Manual...
  • Page 42 Refer to the device specifications for supported sample clock sources and the maximum allowable frequency of sample clock. Figure 3.19 Buffered (hardware-timed) frequency measurement PCIE-1812 User Manual...

  • Page 43: Pulse Width Measurement

    Figure 3. 21. Figure 3.21 Instant (software-timed) pulse width measurement The advantage of instant pulse width measurement is low latency. It is typically used for reading a single sample of counter value. PCIE-1812 User Manual...
  • Page 44 Buffered pulse width measurement is also called hard- ware-timed pulse width measurement. The advantages of buffered pulse width measurement over instant pulse width mea- surement include: The sample rate can be much higher.  The time of sample is deterministic.  PCIE-1812 User Manual...

  • Page 45: Surement

    A signal by 90 degrees, the counter value is decrease by 1 for each pulse period. They are shown in Figure 3. 24 and Figure 3. 25, respectively. Figure 3.24 Quadrature x1 mode, counter A leads counter B PCIE-1812 User Manual...
  • Page 46 A signal by 90 degrees, the counter value is decrease by 2 for each pulse period. They are shown in Figure 3. 26 and Figure 3. 27, respectively. Figure 3.26 Quadrature x2 mode, counter A leads counter B Figure 3.27 Quadrature x2 mode, counter B leads counter A PCIE-1812 User Manual...
  • Page 47 In two pulse (or clockwise/counter-clockwise) mode, the counter value is increased by 1 for each pulse of counter A signal, and is decreased by 1 for each pulse of counter B signal. This is shown in Figure 3. 30. Figure 3.30 Two pulse (clockwise/counter-clockwise) mode PCIE-1812 User Manual...
  • Page 48 In position measurement, the counter value can be reset to a specified value either by the software or by the counter Z signal. Figure 3. 32 shows an example of reset by counter Z signal. Figure 3.32 Position reset to 0 by counter Z signal PCIE-1812 User Manual...
  • Page 49 Because the data is moved in large blocks instead of one point at a time, buffered position measurement typically allow much higher transfer rates. Buffered position measurement is also called hardware-timed position measurement. PCIE-1812 User Manual...

  • Page 50: Position Comparison

    This is shown in Figure 3. 36. Figure 3.36 Instant position comparison The advantage of instant position comparison is that the next compare value can be decided on the fly. PCIE-1812 User Manual...
  • Page 51 When the counter sample clock rises, the counter value at that time is latched, offset by a specified value, and stored as the next compare value. An exam- ple is shown in Figure 3. 38. Figure 3.38 Offset position comparison with offset value of “+2” PCIE-1812 User Manual...
  • Page 52 The output can be gated. If counter gate is in active level, pulses are output normally. On the other hand, if counter gate is in inactive level, output is disabled. Figure 3. 41 shows an example of active high gate. Figure 3.41 Gated timer/pulse output PCIE-1812 User Manual...
  • Page 53 Each time a rising edge of sample clock is detected, the first sample in the FIFO is used to update the output pulse frequency, and then the sam- ple is discarded. Buffered timer/pulse is also called hardware-timed timer/pulse. PCIE-1812 User Manual...
  • Page 54 Figure 3.46 Infinite pulse generation The output can be gated. If counter gate is high, pulses are output normally. On the other hand, if counter gate is low, output is disabled. This is shown in Figure 3. 47. PCIE-1812 User Manual...
  • Page 55 Whenever the software sends an update command, the width of output pulse is updated to the specified value after current pulse is completed as shown in Figure 3. 48. Figure 3.48 Static (software-timed) timer/pulse PCIE-1812 User Manual...
  • Page 56 Buffered PWM output is also called hardware-timed PWM output. The advantages of buffered PWM output over static PWM output include: The time of sample is deterministic.  The time of sample can be controlled by an external signal.  PCIE-1812 User Manual...

  • Page 57: Timing Signals

    A digital trigger can be configured as rising edge active or falling edge active, as shown in Figure 3. 51 and Figure 3. 52, respectively. Figure 3.51 Rising edge active digital trigger Figure 3.52 Falling edge active digital trigger PCIE-1812 User Manual...
  • Page 58 For external clock, on the other hand, clock frequency can be controlled by the external source in real time. PCIE-1812 User Manual...
  • Page 59 One of the devices is selected as the primary device, and others as secondary devices. The primary device sends the required tim- ing signals to all the secondary devices for synchronized acquisition. Figure 3.55 MDSI Layout PCIE-1812 User Manual...
  • Page 60 Signal synchronization can be achieved through external wiring as shown in Figure 3.56 and Figure 3.57. This method requires additional wiring boards for the connec- tions. Figure 3.56 Synchronize by External Cables Figure 3.57 Signal Connection Synchronize by External Cables PCIE-1812 User Manual...
  • Page 61 To use MDSI cable for synchronization, connect each cable between MDSI OUT of one device to MDSI IN of the next device as shown in Figure 3.58 and Figure 3.59. Figure 3.58 Synchronize by MDSI Cables Figure 3.59 Signal Connection of MDSI Synchronize by MDSI Cables PCIE-1812 User Manual...
  • Page 62 With Synchronized-MDSI acquisition, The ADCs of all acquisition enabled channels simultaneously begin to convert the analog input voltage at each rising edge of the sample clock. Figure 3.60 shows an example of Synchronized-MDSI acquisition which AI0, AI1, and AI2 are enabled. PCIE-1812 adopts Synchronized-MDSI. Figure 3.60 Synchronized-MDSI 3.7.3.2...
  • Page 63 The following sections will explain the setup for both the primary and secondary devices. 3.7.4.1 Primary Device In the Navigator, click on 'Settings,' then select 'Conversion.' Choose 'Internal Clock' as the conversion clock source. Figure 3.62 Setting for Primary Device PCIE-1812 User Manual...
  • Page 64 Figure 3.64 Trigger Setting for Secondary Device Once all the settings are completed, the primary and secondary devices will operate synchronously. Use the Data Logger to verify whether MDSI is functioning properly. Figure 3.65 illustrates an example of synchronization. PCIE-1812 User Manual...
  • Page 65 Figure 3.65 Data Logger for synchronization Calibration The Navigator of Advantech DAQNavi provides the calibration utility to calibrate the analog input and analog output circuitry of the device. Figure 3. 66 shows the inter- face of the calibration utility. Follow the instructions shown to calibration the device.
  • Page 66 “Load factory default” button. Firmware/FPGA Code Update The Navigator of Advantech DAQNavi provides the firmware/FPGA code download utility. User can use this utility to update the firmware/FPGA code of the device. Figure 3. 67 shows the interface of the firmware/FPGA code download utility. To update the firmware/FPGA code, first click “Browser”...
  • Page 67 Appendix Specifications...

  • Page 68: Function Block Diagram

    Function Block Diagram Figure A.1 Function Block PCIE-1812 User Manual...
  • Page 69 ±0.05 % ±0.05 % Range 0 ~ 10 V 0 ~ 5 V 0 ~ 2.5 V 0 ~ 1.25 V Accuracy ±0.05 % ±0.05 % ±0.05 % ±0.05 % Common-mode rejection ratio (CMRR): 70 dB  PCIE-1812 User Manual...

  • Page 70: Amplitude)

    -94.09 dB -89.36 dB -89.39 dB -89.95 dB ±2.5 V -87.96 dB -85.20 dB -82.90 dB -82.78 dB ±1.25 V -84.11 dB -82.33 dB -80.11 dB -81.45 dB ±0.625 V -81.16 dB -77.97 dB -77.25 dB -77.64 dB PCIE-1812 User Manual...

  • Page 71: Dbfs Amplitude)

    75.43 dB 74.22 dB 73.88 dB 74.04 dB ±2.5 V 67.88 dB 68.43 dB 68.37dB 67.55 dB ±1.25 V 65.17 dB 65.17 dB 65.29 dB 65.55 dB ±0.625 V 61.80 dB 61.92 dB 62.27 dB 62.46 dB PCIE-1812 User Manual...

  • Page 72: Analog Output

    Enable channel combination: Each channel can be enabled/disabled inde- pendently by software – Update clock rate: 3 MHz max. per channel, software configurable – Update clock source: Internal or external – Internal data buffer (FIFO) size: 8,192 samples PCIE-1812 User Manual...

  • Page 73: Bi-Directional Digital Input/Output

    – Update clock rate: 250 kHz max. for all ports, simultaneous updating – Update clock source: Internal or external, software configurable – Internal data buffer (FIFO) size: 4,096 samples Initial output value: Configurable by software  PCIE-1812 User Manual...

  • Page 74: Trigger

    Output type: 5 V TTL  Output logic level:  – Logic high: 4.0 V min. @ 2 mA source/5.2 V max. – Logic low: 0.4 V max. @ 2 mA sink Load current: 8 mA max.  PCIE-1812 User Manual...

  • Page 75: Multi-Device Synchronization Interface (Mdsi)

    ○ Measuring type: Instant or sample clock buffered, software configurable Counter output function:  – One shot ○ Internal clock source frequency: 40 MHz ○ Internal clock accuracy: 50 ppm ○ External clock source frequency: 10 MHz max. PCIE-1812 User Manual...

  • Page 76: Fpga Code Update

    Sample clock rate: 250 kHz max. – Sample clock source: External or analog input sample clock, software config- urable A.10 FPGA Code Update FPGA code update function: Yes, through Advantech Navigator utility  A.11 General Specifications A.11.1 Power Requirements Power consumption: ...

  • Page 77: Physical

    Operating temperature: 0 °C to 60 °C (32 °F to 140 °F)  Storage temperature: -40°C to 70°C (-40°F to 158°F)  Operating humidity: 10% to 90% RH, non-condensing  Storage humidity: 5% to 95% RH, non-condensing  PCIE-1812 User Manual...
  • Page 78 No part of this publication may be reproduced in any form or by any means, such as electronically, by photocopying, recording, or otherwise, without prior written permission from the publisher. All brand and product names are trademarks or registered trademarks of their respective companies. © Advantech Co., Ltd. 2025...

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