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Summary of Contents for GOWIN DK USB GW5ART-LV15MG132P V1.1
- Page 1 DK_USB_GW5ART-LV15MG132P_V1.1 User Guide DBUG1279-1.0E, 01/17/2025...
- Page 2 Copyright © 2025 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is the trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 01/17/2025 1.0E Initial version published.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 2 1.4 Support and Feedback ....................... 2 2 Development Board Introduction .............. - Page 5 Contents 3.4.1 Introduction ........................10 3.4.2 Pin Distribution ....................... 11 3.5 I2C Interface ........................11 3.5.1 Introduction ........................11 3.5.2 Pin Distribution ....................... 12 3.6 MIPI Interface ........................12 3.6.1 Introduction ........................12 3.6.2 Pin Distribution ....................... 13 3.7 HDMI Interface ........................17 3.7.1 Introduction ........................
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Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_USB_GW5ART-LV15MG132P_V1.1 Development Board ......... 3 Figure 2-2 A Development Board Kit ..................4 Figure 2-3 PCB Components...................... 5 Figure 2-4 System Block Diagram ....................5 Figure 3-1 Power Distribution Diagram ..................9 Figure 3-2 Connection Diagram of Download ................ - Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ................... 2 Table 3-1 JTAG Pin Distribution ....................10 Table 3-2 Clock Pin Distribution ....................11 Table 3-3 Pin Distribution of I2C Interface .................. 12 Table 3-4 Pin Distribution of MIPI CPHY & DPHY Hard core Interface ........13 Table 3-5 Pin Distribution of MIPI DPHY Soft Core/LVDS Interface ...........
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Page 8: About This Guide
1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK_USB_GW5ART-LV15MG132P_V1.1 development board (hereinafter referred to as “the development board”) user guide consists of following three parts: A brief introduction to the features of the development board ... -
Page 9: Terminology And Abbreviations
SubMiniature version A Connector Serial Peripheral Interface 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com... -
Page 10: Development Board Introduction
Development Board Introduction 2.1 Overview Figure 2-1 DK_USB_GW5ART-LV15MG132P_V1.1 Development Board Gowin GW5ART series of FPGA products are the 5 series products of Arora family, with abundant internal resources, high-performance DSP with a new architecture that supports AI operations, high-speed LVDS interface and abundant BSRAM resources. -
Page 11: A Development Board Kit
2 Development Board Introduction 2.2 A Development Board Kit verification, and software learning and debugging, etc. The development board adopts Gowin GW5ART-LV15MG132P FPGA device. For the internal resources of the chip, see DS1118, GW5ART series of FPGA Products Data Sheet. -
Page 12: Pcb Components
2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 50MHz SMA_TX MIPI CPHY&DPHY MIPI DPHY 3.3V SMA_RX HardCore SoftCore SDI-IN_2 Power Socket SDI-IN_1 Power Switch FPGA Type-C 1.8V 148.5MHz INA3221 200MHz SDI-OUT_2 0.9V 0.9V Reset Button 2.5V HDMI-IN... -
Page 13: Features
2.5 Features 2.5 Features The key features are as follows: FPGA Device Gowin GW5ART-LV15MG132P FPGA Download and Boot Integrate USB download circuit on the development board, download through Mini USB-B interface External SPI Flash for storing FPGA configuration file ... - Page 14 2 Development Board Introduction 2.5 Features Lead out 1-lane SerDes signal I2C Interface One I2C interface Key 1 low-level reset key DBUG1279-1.0E 7(22)
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Page 15: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Development Board Circuit 3.1 FPGA 3.1.1 Overview For the resources of GW5ART series of FPGA Products, refer to DS1118, GW5ART series of FPGA Products Data Sheet. 3.1.2 I/O BANK Introduction For the I/O BANK, package, and pinout information, see UG1233, GW5ART series of FPGA Products Package and Pinout User Guide more details. -
Page 16: Power Distribution
3 Development Board Circuit 3.2 Power Supply 3.2.2 Power Distribution Figure 3-1 Power Distribution Diagram TPS82130 Type-C DC12V 5V/1.5A 200MHz 3.3V TPS82130 148.5MHz 3.3V/1A SPI FLASH INA3221 HDMI-IN USB to JTAG (FT232HQ) MIPI Connecror SDI-IN SID-OUT VCC3P3_F 2.5V Current TPS82130 2.5V VCC2P5_F 2.5V/2A... -
Page 17: Download Module
3 Development Board Circuit 3.3 Download Module 3.3 Download Module 3.3.1 Introduction The development board includes a Mini USB-B download port (J10) designed to program the programs to external SPI FLASH or SRAM. The download connection diagram is show in Figure 3-2. Figure 3-2 Connection Diagram of Download 3.3.2 Pin Distribution Table 3-1 JTAG Pin Distribution... -
Page 18: Pin Distribution
3 Development Board Circuit 3.5 I2C Interface 3.4.2 Pin Distribution Table 3-2 Clock Pin Distribution Signal Name FPGA Pin No. BANK I/O Level Description 50 MHz single-ended CLK_50M 1.8V clock 200 MHz differential Q0_200MHz_P clock 200 MHz differential Q0_200MHz_N clock 148.5 MHz differential Q0_148p5MHz_P clock... -
Page 19: Pin Distribution
3 Development Board Circuit 3.6 MIPI Interface 3.5.2 Pin Distribution Table 3-3 Pin Distribution of I2C Interface J2 Pin No. Signal Name I/O Level Description INA3221_SCL 3.3V Serial bus clock line INA3221_SDA 3.3V Serial bus data line 3.6 MIPI Interface 3.6.1 Introduction The development board provides one MIPI CPHY hard core interface, one MIPI DPHY hard core interface, and one MIPI DPHY soft core... -
Page 20: Pin Distribution
3 Development Board Circuit 3.6 MIPI Interface 3.6.2 Pin Distribution Table 3-4 Pin Distribution of MIPI CPHY & DPHY Hard core Interface FPGA Signal Name BANK Description Pin No. Pin No. Level M0_DPHY_D0N MIPI MIPI DPHY data signal VCC1P2 1.2V Power M0_DPHY_D0P MIPI... - Page 21 3 Development Board Circuit 3.6 MIPI Interface FPGA Signal Name BANK Description Pin No. Pin No. Level Floating M0_DPHY_D3P MIPI MIPI DPHY data signal Floating Floating M1_CPHY_D1A MIPI MIPI CPHY data signal Floating M1_CPHY_D1B MIPI MIPI CPHY data signal Floating M1_CPHY_D1C MIPI MIPI CPHY data signal...
- Page 22 3 Development Board Circuit 3.6 MIPI Interface FPGA Signal Name BANK Description Pin No. Pin No. Level M1_CPHY_D0C MIPI MIPI CPHY data signal Floating Floating M1_CPHY_D2A MIPI MIPI CPHY data signal Floating M1_CPHY_D2B MIPI MIPI CPHY data signal Floating M1_CPHY_D2C MIPI MIPI CPHY data signal Floating...
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Page 23: Table 3-5 Pin Distribution Of Mipi Dphy Soft Core/Lvds Interface
3 Development Board Circuit 3.6 MIPI Interface Table 3-5 Pin Distribution of MIPI DPHY Soft Core/LVDS Interface FPGA Signal Name BANK I/O Level Description Pin No. Pin No. DPHY_LVDS_D3P 1.8V MIPI/LVDS data DPHY_LVDS_D3N 1.8V MIPI/LVDS data DPHY_LVDS_D2P 1.8V MIPI/LVDS data DPHY_LVDS_D2N 1.8V MIPI/LVDS data... -
Page 24: Hdmi Interface
3 Development Board Circuit 3.7 HDMI Interface 3.7 HDMI Interface 3.7.1 Introduction The development board provides an HDMI input interface, enabling HDMI signal reception through an internal FPGA IP. The interface connection diagram is shown in Figure 3-7. Figure 3-7 Connection Diagram of HDMI-RX Interface 3.7.2 Pin Distribution Table 3-6 Pin Distribution of HDMI-RX Signal Name... -
Page 25: Spi Interface
FPGA through a Type-C dual-role port controller, which handles the switching of high-speed differential lines. USB 3.0 is implemented using the Gowin USB 3.0 PHY IP solution. The management interface of the Type-C dual-role port controller is led out via J20 and can be jumpered to the SPI interface (J4) to enable DBUG1279-1.0E... -
Page 26: Pin Distribution
3 Development Board Circuit 3.10 SDI Interface data interaction between the FPGA and the Type-C dual-role port controller. The enable signal (EN_N) for the Type-C dual-role port controller is multiplexed with the SPI clock signal (SPI_CK). Figure 3-9 Connection Diagram of Type-C Interface TYPEC_CC1 OUT1 TYPEC_CC2... -
Page 27: Pin Distribution
3 Development Board Circuit 3.10 SDI Interface The connection diagram of SDI interface is shown in Figure 3-10. Figure 3-10 Connection Diagram of SDI Interface SDI-OUT-1 SDI_SDA SDI_SCL SDI_1_OUT_DP SDI_1_OUT_DN MH1218 SDI-OUT-2 SDI_2_OUT_DP SDI_2_OUT_DN LMH1218 SDI-IN-1 SDI_1_IN_DP SDI_1_IN_DN LMH1219 SDI-IN-2 SDI_2_IN_DP SDI_2_IN_DN LMH1219... -
Page 28: Key
3 Development Board Circuit 3.11 Key Signal Name FPGA Pin No. BANK I/O Level Description SDI_1_OUT_P SerDes Q0 LMH1218 IN0+ SDI_1_OUT_N SerDes Q0 LMH1218 IN0- SDI_2_IN_P SerDes Q0 LMH1219 OUT0+ SDI_2_IN_N SerDes Q0 LMH1219 OUT0- SDI_1_IN_P SerDes Q0 LMH1219 OUT0+ SDI_1_IN_N SerDes Q0 LMH1219 OUT0-... -
Page 29: Sma Interface
3 Development Board Circuit 3.12 SMA Interface 3.12 SMA Interface 3.12.1 Introduction The development board leads out two pairs of SMA differential signals, including transmitting signal and receiving signal, which are connected to FPGA SerDes pins. The connection diagram is shown in Figure 3-12.
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