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GOWIN GW1NSER Series User Manual

Securefpga package & pinout
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GW1NSER series of SecureFPGA
Package & Pinout User Guide
UG884-1.01E, 04/16/2020

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Summary of Contents for GOWIN GW1NSER Series

  • Page 1 GW1NSER series of SecureFPGA Package & Pinout User Guide UG884-1.01E, 04/16/2020...
  • Page 2 Copyright © 2020 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , LittleBee, and GOWIN are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 10/8/2019 1.0E Initial version published. 04/16/2020 1.01E Quantity of GW1NSER-4C QN48P/QN48G Pins modified.

  • Page 4: Table Of Contents

    Contents Contents Contents ......................... i List of Figures ..................... ii List of Tables ...................... iii 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 2 1.4 Support and Feedback ....................... 2 2 Overview ......................

  • Page 5: List Of Figures

    List of Figures List of Figures Figure 2-1 GW1NSER series of SecureFPGA products I/O Bank Distribution ......... 9 Figure 3-1 View of GW1NSER-4C QN48P Pins Distribution (Top View) ........... 11 Figure 3-2 View of GW1N-4 QN48G Pins Distribution (Top View) ............ 12 Figure 4-1 Package Outline of QN48P / QN48G ................
  • Page 6 Table 2-2 GW1NSER Power Pins ...................... 4 Table 2-3 Quantity of GW1NSER-4CPins ..................5 Table 2-4 Definition of the Pins in the GW1NSER series of SecureFPGA products ......6 Table 3-1 Other pins in GW1NSER-4C QN48P ................. 11 Table 3-2 Other pins in GW1NSER-4C QN48G ................12...

  • Page 7: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose This manual contains an introduction to the GW1NSER series of SecureFPGA products together with a definition of the pins, list of pin numbers, distribution of pins, and package diagrams. 1.2 Related Documents The user guides are available on the GOWINSEMI Website.

  • Page 8: Terminology And Abbreviations

    Gowin Programmable IO QN48P QFN48P QN48G QFN48G 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail:support@gowinsemi.com UG884-1.01E...

  • Page 9: Overview

    IoT, edge, and server management applications. 2.1 PB-Free Package The GW1NSER series of SecureFPGA products are PB free in line with the EU ROHS environmental directives. The substances used in the GW1NSER series of SecureFPGA products are in full compliance with the IPC-1752 standards.

  • Page 10: Package And Max. User I/O Information

    2 Overview 2.2 Package and Max. User I/O Information 2.2 Package and Max. User I/O Information Table 2-1 Package, Max. User I/O Information, and LVDS Paris Package Pitch (mm) Size (mm) GW1NSER-4C QN48P 6 x 6 38(4) QN48G 6 x 6 38(4) Note! In this manual, abbreviations are employed to refer to the package types.

  • Page 11: Pin Quantity

    2 Overview 2.4 Pin Quantity 2.4 Pin Quantity 2.4.1 Quantity of GW1NSER-4C Pins Table 2-3 Quantity of GW1NSER-4CPins GW1NSER-4C Pin Type QN48P QN48G BANK0 8/4/0 8/4/0 BANK1 10/5/0 10/5/0 I/O Single end / Differential pair BANK2 9/4/4 9/4/4 BANK3 11/5/0 11/5/0 Max.

  • Page 12: Pin Definitions

    Table 2-4 provides a detailed overview of user I/O, multi-function pins, dedicated pins, and other pins. Table 2-4 Definition of the Pins in the GW1NSER series of SecureFPGA products Pin Name Description Max. User I/O...
  • Page 13 2 Overview 2.5 Pin Definitions Pin Name Description MISO in MSPI mode: Master data output/Slave data SI /D2 input Data port D2 in CPU mode I, internal weak Serial mode input in JTAG mode pull-up Serial clock input in JTAG mode, which needs to be connected with 4.7 K drop-down resistance on PCB I, internal weak Serial data input in JTAG mode...
  • Page 14 2 Overview 2.5 Pin Definitions Pin Name Description REXT 12.7K high-accuracy resistance Crystal input signals XOUT Crystal oscillator signals IDPAD ID signal VBUSPAD VBUS signal VDDA Analog power supply voltage, VDDA=3.3V VDDAUSB Analog power supply pin (3.3V) VDDDUSB Analog power supply pin (3.3V) VDDPL Power supply pin for driver (1.2V) UG884-1.01E...

  • Page 15: I/O Bank Introduction

    Figure 2-1 GW1NSER series of SecureFPGA products I/O Bank Distribution This manual provides an overview of the distribution view of the pins in the GW1NSER series of SecureFPGA products. The four I/O Banks in the GW1NSER series of SecureFPGA products are marked with four different colors.

  • Page 16: View Of Pin Distribution

    3 View of Pin Distribution 3.1 View of GW1NSER-4C Pins Distribution View of Pin Distribution 3.1 View of GW1NSER-4C Pins Distribution UG884-1.01E 10(14)

  • Page 17: View Of Qn48P Pins Distribution

    3 View of Pin Distribution 3.1 View of GW1NSER-4C Pins Distribution 3.1.1 View of QN48P Pins Distribution Figure 3-1 View of GW1NSER-4C QN48P Pins Distribution (Top View) Table 3-1 Other pins in GW1NSER-4C QN48P 11,37 VCCO0 VCCO1 VCCO2 VCCO3 12,24 VCCX UG884-1.01E 11(14)

  • Page 18: View Of Qn48G Pins Distribution

    3 View of Pin Distribution 3.1 View of GW1NSER-4C Pins Distribution 3.1.2 View of QN48G Pins Distribution Figure 3-2 View of GW1N-4 QN48G Pins Distribution (Top View) Table 3-2 Other pins in GW1NSER-4C QN48G 11,37 VCCO0 VCCO1 VCCO2 VCCO3 12,24 VCCX UG884-1.01E 12(14)

  • Page 19: Package Diagrams

    4 Package Diagrams Package Diagrams UG884-1.01E 13(14)

  • Page 20: Qn48P / Qn48G Package Outline (6Mm X 6Mm)

    4 Package Diagrams 4.1 QN48P / QN48G Package Outline (6mm x 6mm) 4.1 QN48P / QN48G Package Outline (6mm x 6mm) Figure 4-1 Package Outline of QN48P / QN48G EXPOSED THERMAL PAD ZONE BOTTOM VIEW MILLIMETER SYMBOL 0.75 0.85 0.05 0.15 0.25 0.20...

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