GOWIN DK START GW2AR18 V1.1 User Manual
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GOWIN DK START GW2AR18 V1.1 User Manual

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DK_START_GW2AR18_V1.1
User Guide
DBUG359-1.2E, 09/03/2021

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Summary of Contents for GOWIN DK START GW2AR18 V1.1

  • Page 1 DK_START_GW2AR18_V1.1 User Guide DBUG359-1.2E, 09/03/2021...
  • Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 01/15/2019 1.0E Initial version published. 09/12/2019 1.1E One precaution added.  The Quick Start in 2.2 A Development Board Suite removed; 09/03/2021 1.2E  The chapter 6 Quick Start added.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 2 2 Development Board Description ..............
  • Page 5 3.9.1 Overview ........................21 3.9.2 LVDS Circuit ........................21 3.9.3 Pinout ..........................21 3.10 Ethernet .......................... 23 3.10.1 Overview ........................23 3.10.2 Ethernet Circuit ......................23 3.10.3 Pinout ........................... 23 4 Considerations....................25 5 Gowin Software....................26 6 Quick Start ..................... 27 DBUG359-1.2E...

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 2-1 DK_START_GW2AR18_V1.1 Development Board ............3 Figure 2-2 A Development Board Suite ..................... 4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Architecture ......................5 Figure 3-1 GW2AR I/O Bank Distribution ..................10 Figure 3-2 View of GW2AR-18 EQ144 Pinout (Top View) ..............
  • Page 7 List of Tables List of Tables Table 1-1 Abbreviations and Terminology ..................2 Table 2-1 Development Board Specification ..................7 Table 3-1 GW2AR-18 FPGA Resources List ..................9 Table 3-2 FPGA I/O Pinout ......................... 11 Table 3-3 FPGA Download and Pinout ....................12 Table 3-4 FPGA Power Pinout ......................

  • Page 8: About This Guide

    1. DS226, GW2AR series of FPGA Products Data Sheet 2. UG229, GW2AR series of FPGA Products Package and Pinout 3. U115, GW2AR-18 Pinout 4. UG290, Gowin FPGA Products Programming and Configuration User Guide 5. SUG100, Gowin Software User Guide 1.3 Abbreviations and Terminology The abbreviations and terminology used in this manual are as shown in Table 1-1 below.

  • Page 9: Support And Feedback

    Phase-locked Loop Delay-locked Loop EQ144 EQFP144 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 10: Development Board Description

    2 Development Board Description 2.1 Overview Development Board Description 2.1 Overview Figure 2-1 DK_START_GW2AR18_V1.1 Development Board DK-START-GW2AR18 adopts the GW2AR-18 device. 64Mbit PSRAM is embedded in this device. The GW2AR series of FPGA products are the first generation products of the Arora family. They offer one form of SIP chip. The main difference between the GW2A series and the GW2AR series is that the GW2AR series integrates abundant memories.

  • Page 11: A Development Board Suite

    2 Development Board Description 2.2 A Development Board Suite 2.2 A Development Board Suite A development board suite includes the following items: DK_START_GW2AR18_V1.1 development board  USB cable  Figure 2-2 A Development Board Suite ① DK_START_GW2AR18_V1.1 development board ② USB Cale DBUG359-1.2E 4(27)

  • Page 12: Pcb Components

    2 Development Board Description 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components Mode GPIO GPIO 1.0V 1.8V Control Power GPIO ON/OFF 5V IN FPGA Download 3.3V LVDS FPGA Ethernet Switch LVDS Ethernet GPIO GPIO Reset FLASH 2.4 System Architecture Figure 2-4 System Architecture 2*BUTTON 2*SWITCH...

  • Page 13: Features

    2 Development Board Description 2.5 Features 2.5 Features The structure and features of the development board are as follows: 1. FPGA EQFP144 package  Up to 120 user I/O  Abundant LUT4 resources  Multiple modes and capacities of B-SRAM ...

  • Page 14: Development Board Specification

    2 Development Board Description 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functions Technical Conditions Note – – FPGA Core chip Support an USB interface; Support – Download USB-JTAG module on board JTAG, MSPI, and Multi BOOT ...
  • Page 15 2 Development Board Description 2.6 Development Board Specification Item Functions Technical Conditions Note between positive and negative anodes of power outlet;  2A self-recovery fuses are connected at power inlet – – Voltage Input Voltage: 5V – – Humidity – Operating range: –20°...

  • Page 16: Development Board Circuit

    3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module 3.1.1 Overview The resources of GW2AR series of FPGA products are set out in Table 3-1. Table 3-1 GW2AR-18 FPGA Resources List Device GW2AR-18 LUT4 20,736 Flip-Flop (FF) 15,552 Shadow SRAM 41,472...

  • Page 17: I/O Bank Introduction

    3 Development Board Circuit 3.1 FPGA Module 3.1.2 I/O BANK Introduction There are four I/O Banks in the GW2AR series of FPGA products, as shown in Figure 3-1. Figure 3-1 GW2AR I/O Bank Distribution Figure 3-2 View of GW2AR-18 EQ144 Pinout (Top View) DBUG359-1.2E 10(27)

  • Page 18: Download

    3 Development Board Circuit 3.2 Download Table 3-2 FPGA I/O Pinout I/O BANK No. Signals Pins used for download mode selection LVDS differential input I/O BANK0 LED&Reset&Slide switch&Key switch GPIO LVDS differential input I/O BANK1 LVDS differential output JTAG I/O BANK2 GPIO DONE&RECONFIG_N&READY I/O BANK3...

  • Page 19: Download Flow

    3 Development Board Circuit 3.3 Power Supply 3.2.3 Download Flow 1. FPGA SRAM Download Mode: Plug the USB cable to the USB interface (J26) on the development board. Power on. Open the Programmer, select SRAM mode, and then select the bitstream file you required. 2.

  • Page 20: Power System Distribution

    3 Development Board Circuit 3.3 Power Supply 3.3.2 Power System Distribution Figure 3-4 Power System Distribution DC5V USB-JTAG （FT2232） LED&SWTICH&BUTTON TPS7A7001 3.3V FPGA VCCO0&VCCO1 &VCCO3&VCCO4 &VCCO5&VCCO6&VCCX Ethernet FPGA TPS7A7001 VCCO2&VCCO7 (PSRAM) 1.8V TPS7A7001 FPGA VCC 1.0V 3.3.3 FPGA Power Pinout Table 3-4 FPGA Power Pinout Signal Name Pin No.

  • Page 21: Clock, Reset

    3 Development Board Circuit 3.4 Clock, Reset Signal Name Pin No. BANK Description VCCPLLL0 PLLL0 power 1.0V VCCPLLR0 PLLR0 power 1.0V VCCPLLR1 PLLR1 power 1.0V PLLL1 power VCCPLL1 1.0V is internally short-circuited. Auxiliary voltage The auxiliary voltage and VCCX 31, 55 3.3V VCCO4, VCCO6 are internally short-circuited.

  • Page 22: Pinout

    3 Development Board Circuit 3.5 LED 3.4.3 Pinout Table 3-5 FPGA Clock and Reset Pinout Signal Name Pin No. BANK Description FPGA_CLK 50MHz crystal oscillator Input 3.3V FPGA_RST_N Reset signal, active low 1.8V 3.5 LED 3.5.1 Overview Four green LEDs are incorporated into the development board and are used to display the required status.

  • Page 23: Switches

    3 Development Board Circuit 3.6 Switches 3.6 Switches 3.6.1 Overview Two Slide switches are incorporated into the development board. These are used to input the 0/1 signal during testing. 3.6.2 Switch Circuit Figure 3-7 Switch Circuit 3.6.3 Pinout Table 3-7 Clock Circuit Pinout Signal Name Pin No.

  • Page 24: Key Circuit

    3 Development Board Circuit 3.8 GPIO 3.7.2 Key Circuit Figure 3-8 Key Circuit 3.7.3 Pinout Table 3-8 Key Pinout Signal Name Pin No. BANK Description F_KEY1 KEY1 3.3V F_KEY2 KEY2 3.3V 3.8 GPIO 3.8.1 Overview Two 2.54mm DC3-10P sockets, one 2.54mm DC3-20P socket, and one 2.54mm DC3-26P socket are reserved on the development board for user function extension and testing purposes.

  • Page 25: Gpio Circuit

    3 Development Board Circuit 3.8 GPIO 3.8.2 GPIO Circuit Figure 3-9 GPIO Circuit H_B_IO0 H_B_IO1 H_A_IO0 H_B_IO2 H_B_IO3 H_A_IO2 H_A_IO1 H_B_IO5 H_B_IO4 H_A_IO4 H_A_IO3 H_B_IO6 H_B_IO7 H_A_IO6 H_A_IO5 VCC3P3 VCC5P0 H_B_IO8 H_B_IO9 H_A_IO8 H_A_IO7 H_B_IO10 H_B_IO11 H_A_IO10 H_A_IO9 H_B_IO12 H_A_IO12 H_A_IO11 H_B_IO13 H_B_IO14...

  • Page 26: Table 3-10 J14 Gpio Pinout

    3 Development Board Circuit 3.8 GPIO Signal Name Pin No. Socket Pin No. BANK Description H_A_IO2 General I/O 1.8V H_A_IO1 General I/O 1.8V H_A_IO4 General I/O 1.8V H_A_IO3 General I/O 1.8V H_A_IO6 General I/O 3.3V H_A_IO5 General I/O 1.8V Table 3-10 J14 GPIO Pinout Signal Name Pin No.

  • Page 27: Table 3-11 J2 Gpio Pinout

    3 Development Board Circuit 3.8 GPIO Table 3-11 J2 GPIO Pinout Signal Name Pin No. Socket Pin No. BANK Description H_B_IO0 General I/O 1.8V H_B_IO1 General I/O 1.8V H_B_IO2 General I/O 1.8V H_B_IO3 General I/O 1.8V H_B_IO4 General I/O 1.8V H_B_IO5 General I/O 1.8V...

  • Page 28: Lvds

    3 Development Board Circuit 3.9 LVDS 3.9 LVDS 3.9.1 Overview Two 2.0 mm DC3-20P sockets are reserved on the development board for LVDS input/output testing and data communication. 3.9.2 LVDS Circuit Figure 3-10 LVDS Circuit F_LVDS_A1_P F_LVDS_A1_N F_LVDS_B1_P F_LVDS_B1_N F_LVDS_A2_P F_LVDS_A2_N F_LVDS_B2_P F_LVDS_B2_N...

  • Page 29: Table 3-14 J4 Fpga Pinout

    3 Development Board Circuit 3.9 LVDS Signal Name Pin No. Socket Pin No. BANK Description F_LVDS_A4_P A Channel 4+ 3.3V F_LVDS_A4_N A Channel 4– 3.3V F_LVDS_A5_P A Channel 5+ 3.3V F_LVDS_A5_N A Channel 5– 3.3V Table 3-14 J4 FPGA Pinout Signal Name Pin No.

  • Page 30: Ethernet

    3 Development Board Circuit 3.10 Ethernet 3.10 Ethernet 3.10.1 Overview Two Ethernet interfaces are reserved for FPGA to communicate with PC or the other external devices. 3.10.2 Ethernet Circuit Figure 3-11 Ethernet Download Connection PHY_MDC PHY_MDIO PHY1_GTCLK PHY1_TXD0 PHY1_TXD1 PHY1_TXD2 PHY1_TXD3 RJ45 PHY1_TXEN...

  • Page 31: Table 3-16 Ethernet2 Pinout

    3 Development Board Circuit 3.10 Ethernet Signal Name Pin No. BANK Description PHY1_TXD1 RGMII/MII transmitter data 3.3V PHY1_TXD2 RGMII/MII transmitter data 3.3V PHY1_TXD3 RGMII/MII transmitter data 3.3V PHY1_TXEN RGMII/MII transmitting enable 3.3V PHY1_RXC RGMII/MII receive clock 3.3V PHY1_RXD0 RGMII/MII receive data 3.3V PHY1_RXD1 RGMII/MII receive data...

  • Page 32: Considerations

    1. Handle with care and pay attention to electrostatic protection; 2. When you program the external FLASH, please refer to the MODE value in Gowin FPGA products programming and configuration Guide； 3. When the LVDS differential signal is used as input, the built-in 100Ω...

  • Page 33: Gowin Software

    5 Gowin Software Gowin Software Please refer to SUG100, Gowin Software User Guide for details. DBUG359-1.2E 26(27)

  • Page 34: Quick Start

    6 Quick Start Quick Start See TN431, DK_START_GW2AR18_V1.1 Development Board Quick Start User Guide for details. DBUG359-1.2E 27(27)

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