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Summary of Contents for GOWIN DK START GW1NZ-LV1FN32C6I5
- Page 1 DK_START_GW1NZ-LV1FN32C6I5_V3.1 User Guide DBUG393-1.0E, 07/22/2021...
- Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin ， Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 07/22/2021 1.0E Initial version published.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 1 1.4 Support and Feedback ....................... 2 2 Introduction ...................... - Page 5 3.6 Switches Module ....................... 12 3.6.1 Overview ........................12 3.6.2 Switches Circuit ......................12 3.6.3 Pinout ..........................12 3.7 GPIO ..........................13 3.7.1 Overview ........................13 3.7.2 GPIO Circuit ........................13 3.7.3 Pinout ..........................13 4 Considerations....................15 5 Gowin Software....................16 DBUG393-1.0E...
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Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_START_GW1NZ-LV1FN32C6I5_V3.1 Development Board ........3 Figure 2-2 A Development Kit ......................4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Block Diagram ..................... 5 Figure 3-1 FPGA USB Download Diagram ..................9 Figure 3-2 Clock, Reset ........................ - Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................1 Table 2-1 Development Board Description ..................7 Table 3-1 FPGA Download Pinout ..................... 9 Table 3-2 FPGA Clock and Reset Pinout ................... 10 Table 3-3 LED Pinout ......................... 11 Table 3-4 Switches Pinout ........................
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Page 8: About This Guide
2. UG843, GW1NZ series of FPGA Products Package and Pinout User Guide 3. UG842, GW1NZ-1 Pinout 4. UG290, Gowin FPGA Products Programming and Configuration Guide 5. SUG100, Gowin Software User Guide 1.3 Terminology and Abbreviations The terminology and abbreviations used in this manual are as shown in Table 1-1. -
Page 9: Support And Feedback
System Power Management Interface FN32 QFN32 package 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com... -
Page 10: Introduction
2 Introduction 2.1 Overview Introduction 2.1 Overview Figure 2-1 DK_START_GW1NZ-LV1FN32C6I5_V3.1 Development Board This development board adopts the GW1NZ-1 series of FPGA device. The GW1NZ series of FPGA products are the first generation products in ® the LittleBee family. It has the characteristics of low power consumption, instant on, low cost, non-volatile, high security, various packages, and flexible usage. -
Page 11: Development Kit
2 Introduction 2.2 Development Kit development environment that supports FPGA synthesis, placement & routing, bitstream generation and download, etc. The development board offers USB download interface, GPIO interfaces, SPMI, keys, LEDs, etc., which is useful for both developers and learners. 2.2 Development Kit The development board kit includes the following items: DK_START_GW1NZ-LV1FN32C6I5_V3.1 development board... -
Page 12: Pcb Components
2Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components USB-to-JTAG Chip Power Chip*3 Power Outlet Download Power Switch Level Conversion Voltage Chip Selection GPIO SPMI/JTAG Selection SPMI Test Pin Reset Dial Switch FPGA LED*2 DONE 2.4 System Block Diagram Figure 2-4 System Block Diagram Dial Slide... -
Page 13: Features
2Introduction 2.5Features 2.5 Features The structure and features of the development board are as follows: 1. FPGA QFN32 package 25 user I/Os Embedded flash, data not easily lost if power down Abundant LUT4 resources Multiple modes and capacities of SSRAM ... -
Page 14: Development Board Description
2Introduction 2.6Development Board Description 2.6 Development Board Description Table 2-1 Development Board Description Name Functional Description Technical Condition Note FPGA Core chip – – Supports JTAG and Download USB download interface – AUTOBOOT Input power: 5V Provides power for download circuit and other circuits via the 5V to 3.3 V Provides 5V input;... -
Page 15: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW1NZ series of FPGA Products, see DS841, GW1NZ Series of FPGA Products Data Sheet. I/O BANK Introduction For the I/O BANK, package, and pinout information, see UG843, GW1NZ Series of FPGA Products Package and Pinout User Guide. -
Page 16: Usb Download Circuit
3 Development Board Circuit 3.3 Power Supply 3.2.2 USB Download Circuit Figure 3-1 FPGA USB Download Diagram 3.2.3 Download Flow 1. SRAM: Scan the device and download bitstream after power on. When Done is on, it indicates it is successful. 2. -
Page 17: Clock, Reset
3 Development Board Circuit 3.4 Clock, Reset 3.4 Clock, Reset 3.4.1 Overview The development board provides a 12MHz/50MHz 1 crystal oscillator connected to the GCLK input pin. This can be employed as the global clock. Frequency division and multiplication of PLL can provide clocks required by users. -
Page 18: Led
3 Development Board Circuit 3.5 LED 3.5 LED 3.5.1 Overview There are two green LEDs on the development board. You can test and verify the development board through LEDs. To use them, the LED1 and LED2 of S1 must be set to ON. You can test the LEDs in the following ways: When the FPGA corresponding pin output signal is logic low , the LED ... -
Page 19: Switches Module
3 Development Board Circuit 3.6 Switches Module 3.6 Switches Module 3.6.1 Overview There are four slide switches on the development board available for SPMI test. Set to SPMI, JTAG is multiplexed to SPMI; Set to JTAG, it is JTAG download. 3.6.2 Switches Circuit Figure 3-4 Switches Circuit 3.6.3 Pinout... -
Page 20: Gpio
3Development Board Circuit 3.7 GPIO 3.7 GPIO 3.7.1 Overview One 2.54mm DC3-20P socket is reserved on the development board for function extension and testing 3.7.2 GPIO Circuit Figure 3-5 GPIO Circuit 3.7.3 Pinout Table 3-5 GPIO Pinout Signal Name Pin No. 20P Socket BANK Description... - Page 21 3Development Board Circuit 3.7 GPIO Signal Name Pin No. 20P Socket BANK Description I/O Level Pin No. H_A_IO6 General I/O 1.8V/3.3V H_A_IO7 General I/O 1.8V/3.3V H_A_IO8 General I/O 1.8V/3.3V H_A_IO9 General I/O 1.8V/3.3V H_A_IO10 General I/O 1.8V/3.3V H_A_IO11 General I/O 1.8V/3.3V H_A_IO12 General I/O...
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Page 22: Considerations
4 Considerations Considerations Considerations for the use of development board: 1. Handle with care and pay attention to electrostatic protection; 2. If you use SPMI, set SW2, SW3, SW4, SW5 to JTAG. Download .fs file, then power off. Set to SPMI, power on again to test and debug; 3. -
Page 23: Gowin Software
5 Gowin Software Gowin Software See SUG100, Gowin Software User Guide for details. DBUG393-1.0E 16(16)
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