GOWIN DK-START-GW2A55-PG484 User Manual
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GOWIN DK-START-GW2A55-PG484 User Manual

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DK-START-GW2A55-PG484 V1.3
Development
User Guide
BoardDK-START-GW2A55-PG484 V1.3
Development Board
DBUG375-1.0E, 04/22/2020

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Summary of Contents for GOWIN DK-START-GW2A55-PG484

  • Page 1 DK-START-GW2A55-PG484 V1.3 Development User Guide BoardDK-START-GW2A55-PG484 V1.3 Development Board DBUG375-1.0E, 04/22/2020...
  • Page 2 Copyright© 2020 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer ®...
  • Page 3 Revision History Date Version Description 04/22/2020 1.0E Initial version published.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iv List of Tables ...................... vi 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Supported Products ......................1 1.3 Related Documents ......................1 1.4 Terminology and Abbreviations ................... 2 1.5 Support and Feedback .......................
  • Page 5 Contents 3.5 DDR3 ..........................13 3.5.1 Introduction ........................13 3.5.2 Pinout ..........................13 3.6 Ethernet ..........................15 3.6.1 Introduction ........................15 3.6.2 Pinout ..........................16 3.7 LVDS Interfaces ........................ 16 3.7.1 Introduction ........................16 3.7.2 Pinout ..........................17 3.8 MIPI DSI ........................... 20 3.8.1 Introduction ........................
  • Page 6 Contents 3.15.2 Pinout ........................... 30 3.16 Industry Screen Interface ....................32 3.16.1 Introduction ........................32 3.16.2 Pinout ........................... 33 3.17 LED Module ........................34 3.17.1 Introduction ........................34 3.17.2 Pinout ........................... 34 3.18 Keys Module ........................35 3.18.1 Introduction ........................35 3.18.2 Pinout ...........................

  • Page 7: List Of Figures

    List of Figures List of Figures Figure 2-1 DK-START-GW2A55-PG484 V1.3 ................... 3 Figure 2-2 Development Kit ....................... 4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Block Diagram ..................... 6 Figure 3-1 Connection Diagram of FPGA Downloading and Configuration ........10 Figure 3-2 Asynchronous FIFO Connection Diagram ................
  • Page 8 List of Figures Figure 4-2 Process Window ....................... 38 Figure 4-3 Build Completed ....................... 38 Figure 4-4 Programmer Window ......................39 Figure 4-5 Device Configure Window ....................39 Figure 4-6 Click Program/Configure ....................40 DBUG375-1.0E...
  • Page 9 List of Tables List of Tables Table 1-1 Abbreviations and Terminology ..................2 Table 3-1 FPGA Download and Pinout ....................10 Table 3-2 Asynchronous FIFO Pinout ....................11 Table 3-3 Clock and Reset Pinout...................... 13 Table 3-4 DDR3 Pinout ........................13 Table 3-5 Ethernet Pinout ........................

  • Page 10: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK-START-GW2A55-PG484 V1.3 development board (hereinafter referred to development board) user guide consists of following three parts: 1. A brief introduction to the features of the development board; 2. An introduction to the development board system architecture and hardware resources;...

  • Page 11: Terminology And Abbreviations

    Low-Voltage Differential Signaling S-SRAM Shadow Static Random Access Memory 1.5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com...

  • Page 12: Introduction

    Introduction 2.1 Overview Figure 2-1 DK-START-GW2A55-PG484 V1.3 DK-START-GW2A55-PG484 V1.3 applies to high speed data storage based on DDR3, high-speed communication test based on MIPI, LVDS and GbE, 55k series of FPGA products functions evaluation, the verification of hardware reliability, software learning and debugging, etc.

  • Page 13: Development Kit

    2 Introduction 2.2 Development Kit which is the first generation product of Gowin Arora family. The GW2A series of FPGA products offer a range of features and rich resources like high-performance DSP, high-speed LVDS interface and BSRAM. These embedded resources combine a streamlined FPGA architecture with a 55nm process to make the GW2A series of FPGA products ideal for high-speed and low-cost applications.

  • Page 14: Pcb Components

    2 Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 1.0V Power 3.3V Power Button Cell 1.8V Power 1.5V Power 1.2V Power 2.5V Power WIFI Power Socket Power Switch Ethernet1 AD/DA DDR3 Ethernet2 Bank4 Level Selection LED*4 CAN Interface MINI B Dip switch 40PIN...

  • Page 15: System Block Diagram

    Figure 2-4 System Block Diagram 2.5 Features The key features are as follows: 1. The FPGA device  Gowin GW2A-LV55PG484 FPGA  Max. user I/O 319 2. Download and Boot  Integrates the download module and can be downloaded with USB Mini B cable ...
  • Page 16 2 Introduction 2.5 Features  The development board generates 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, 1.0v, 0.75v and the power needed by LCD interface and MIPI interface. 4. Clock system  50MHz crystal oscillator input 5. Memory Device  2Gbit DDR3 SDRAM ...
  • Page 17 2 Introduction 2.5 Features supply or button cell.  The communication interface with FPGA is I2C. 12. AD/DA  ADI AD5593R chip is used.  Supports 12-bit A/D and D/A converters, and 8-channel interface can be configured to any combination of ADC/DAC/GPIO. ...

  • Page 18: Development Board Circuit

    3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW2A-LV55PG484 FPGA products, see DS102, GW2A Series of FPGA Products. I/O BANK Introduction For the I/O BANK, package and pinout information, see UG111, GW2A Series of FPGA Products Package and Pinout User Guide.

  • Page 19: Pinout

    3 Development Board Circuit 3.2 Download Module Figure 3-1 Connection Diagram of FPGA Downloading and Configuration JTAG_TCK USB_D+ JTAG_TDO USB_D- USB to JTAG_TDI JTAG chip JTAG_TMS FLASH_SPI_MISO FLASH_SPI_MOSI Configure FLASH_SPI_CS_N FLASH FLASH_SPI_CLK By configuring EEPROM chip, the B channel of FT2232 can be configured as an asynchronous FIFO interface.

  • Page 20: Power Supply

    3 Development Board Circuit 3.3 Power Supply Name FPGA Pin No. BANK I/O Level Description FLASH_SPI_MISO 1.5V Configure FLASH Signal FLASH_SPI_MOSI 1.5V Configure FLASH Signal FLASH_SPI_CS_N 1.5V Configure FLASH Signal FLASH_SPI_CLK 1.5V Configure FLASH Signal Table 3-2 Asynchronous FIFO Pinout Name FPGA Pin No.

  • Page 21: Clock And Reset

    3 Development Board Circuit 3.4 Clock and Reset Three NCP3170ADR2G DC-DC power supply chips are used to generate 3.3v, 1.5v and 1.0v, and the maximum output current is 3A. Three TPS7A7001 LDO power supply chips are used to generate 2.5v, 1.8v and 1.2v, and the maximum output current is 2A.

  • Page 22: Pinout

    3 Development Board Circuit 3.5 DDR3 3.4.2 Pinout Table 3-3 Clock and Reset Pinout Name FPGA Pin No. BANK I/O Level Description CLK_G 3.3V 50MHz crystal oscillator input RST_N 2.5V Reset Signal, active Low 3.5 DDR3 3.5.1 Introduction The development board includes a DDR3 chip with 2Gbit,16-bit bus width, and the highest data rate is 1600MT/s.
  • Page 23 3 Development Board Circuit 3.5 DDR3 Name FPGA Pin No. BANK I/O Level Description Address DDR3_A3 1.5V Address DDR3_A4 1.5V Address DDR3_A5 1.5V Address DDR3_A6 AA22 1.5V Address DDR3_A7 1.5V Address DDR3_A8 AB22 1.5V Address DDR3_A9 1.5V Address DDR3_A10 1.5V Address DDR3_A11 AA21...

  • Page 24: Ethernet

    3 Development Board Circuit 3.6 Ethernet Name FPGA Pin No. BANK I/O Level Description Data input mask DDR3_LDM 1.5V Data strobe DDR3_LDQSn 1.5V Data strobe DDR3_LDQSp 1.5V On-Die Termination DDR3_ODT 1.5V Enable Row address DDR3_RASn 1.5V strobe Reset DDR3_RSTn 1.5V Data input mask DDR3_UDM 1.5V...

  • Page 25: Pinout

    3 Development Board Circuit 3.7 LVDS Interfaces 3.6.2 Pinout Table 3-5 Ethernet Pinout Name FPGA Pin No. BANK I/O Level Description PHY_MDC 3.3V Manage channel clock PHY_MDIO 3.3V Manage channel data PHY1_GTCLK 3.3V PHY1 Transmit Clock PHY1_TXD0 3.3V PHY1 transmitting data channel 0 PHY1_TXD1 3.3V PHY1 transmitting data channel 1...

  • Page 26: Pinout

    3 Development Board Circuit 3.7 LVDS Interfaces to 2.5V when LVDS is used. Figure 3-6 LVDS TX Interface LVDS_B6_P LVDS_B6_N LVDS_B1_P LVDS_B1_N LVDS_B7_P LVDS_B7_N LVDS_B2_P LVDS_B2_N LVDS_B8_P LVDS_B8_N LVDS_B3_P LVDS_B3_N LVDS_B9_P LVDS_B9_N LVDS_B4_P LVDS_B4_N LVDS_B10_P LVDS_B10_N LVDS_B5_P LVDS_B5_N Figure 3-7 LVDS RX Interface LVDS_A1_P LVDS_A1_N LVDS_A6_P...

  • Page 27: Table 3-7 Lvds Tx2 Pinout

    3 Development Board Circuit 3.7 LVDS Interfaces Pins Number Name FPGA Pin No. BANK I/O Level Description Channel 2- 2.5V Differential LVDS_B3_P Channel 3+ 2.5V Differential LVDS_B3_N Channel 3- 2.5V Differential LVDS_B4_P AA17 Channel 4+ 2.5V Differential LVDS_B4_N Channel 4- 2.5V Differential LVDS_B5_P...

  • Page 28: Table 3-9 Lvds Tx2 Pinout

    3 Development Board Circuit 3.7 LVDS Interfaces Pins Number Name FPGA Pin No. BANK I/O Level Description 2.5V Differential LVDS_A1_N Channel 1- 2.5V Differential LVDS_A2_P Channel 2+ 2.5V Differential LVDS_A2_N Channel 2- 2.5V Differential LVDS_A3_P AB19 Channel 3+ 2.5V Differential LVDS_A3_N AB20 Channel 3-...

  • Page 29: Mipi Dsi

    3 Development Board Circuit 3.8 MIPI DSI 3.8 MIPI DSI 3.8.1 Introduction The DSI interface uses the 30-contact stacked board connector, which channels to 5 pairs of differential signals, including one for clock and four for data, corresponding to TXD T550UZPA-75 mobile phone screen interface.

  • Page 30: Pinout

    3 Development Board Circuit 3.8 MIPI DSI 3.8.2 Pinout Table 3-10 MIPI DSI Pinout Name FPGA Pin No. BANK I/O Level Description DSI_D0n 2.5V HS differential data 0- HS differential data DSI_D0p 2.5V DSI_D1n 2.5V HS differential data 1 HS differential data DSI_D1p 2.5V DSI_CLKn...

  • Page 31: Mipi Csi

    3 Development Board Circuit 3.9 MIPI CSI Name FPGA Pin No. BANK I/O Level Description signal Tearing effect output DSI_TE 2.5V signal 3.9 MIPI CSI 3.9.1 Introduction MIPI CSI uses 15pin connector with 1mm pitch. The interface includes 3 pairs of differential signals, among which one for clock and two for data. Differential signals of three lanes are simultaneously channeled to the double rows pin of 20pin with 2.00mm pitch.

  • Page 32: Pinout

    3 Development Board Circuit 3.9 MIPI CSI Figure 3-9 Connection Diagram of MIPI CSI CSI_LP_D0n CSI_D0n CSI_D0n CSI_D0p CSI_LP_D0p CSI_D0p CSI_D1n CSI_D1p CSI_LP_D1n CSI_D1n CSI_CLKn CSI_CLKp CSI_LP_D1p CSI_D1p 3.3V CSI_RESET CSI_CLK CSI_LP_CLKn CSI_SCL CSI_CLKn CSI_SDA CSI_LP_CLKp CSI_CLKp CSI_D0p CSI_D0n CSI_D1p CSI_D1n CSI_CLKp CSI_CLKn...

  • Page 33: Sd Card

    3 Development Board Circuit 3.10 SD Card Name FPGA Pin No. BANK I/O Level Description CSI_D1p 2.5V HS differential data CSI_CLKn 2.5V HS Differential clock- CSI_CLKp 2.5V HS Differential clock+ CSI_LP_D0n 1.2V LP single-ended data CSI_LP_D0p 1.2V LP single-ended data CSI_LP_D1n 1.2V LP single-ended data...

  • Page 34: Pinout

    3 Development Board Circuit 3.11 RTC 3.10.2 Pinout Table 3-12 SD Card Pinout Name FPGA Pin No. BANK I/O Level Description SD_D0 3.3V Data bit 0 SD_D1 3.3V Data bit 1 SD_D2 3.3V Data bit 2 SD_CD/D3 3.3V Card detection/Data bit 3 SD_CMD 3.3V...

  • Page 35: Ad/Da

    3 Development Board Circuit 3.12 AD/DA Name FPGA Pin No. BANK I/O Level Description IIC_SCL 2.5V I2C signal IIC_SDA 2.5V I2C signal 3.12 AD/DA 3.12.1 Introduction The AD/DA module uses ADI AD5593R chip. It is a 12-bit A/D and D/A converter with configurable 8-channel interface, which can be configured as any combination of ADC/DAC/GPIO and shares the I2C bus with the RTC module.

  • Page 36: Can

    3 Development Board Circuit 3.13 CAN 3.13 CAN 3.13.1 Introduction There is one CAN interface and NXP TJA1050 transceiver chip is used. The FPGA communicates with the transceiver via the UART interface, and the maximum transmission rate is 1Mbps. The connection diagram is as follows: Figure 3-13 Connection Diagram of CAN CAN_TXD...

  • Page 37: Pinout

    3 Development Board Circuit 3.15 GPIO Figure 3-14 Connection Diagram of WIFI WIFI_SPI_CLK WIFI_SPI_MISO WIFI_SPI_MOSI WIFI WIFI_SPI_CS Module WIFI_TX WIFI_RX 3.14.2 Pinout Table 3-16 WIFI Pinout Name FPGA Pin No. BANK I/O Level Description WIFI_SPI_CLK 1.2V SPI clock WIFI_SPI_MISO A10 1.2V SPI data WIFI_SPI_MOSI B8...

  • Page 38: Figure 3-15 40Pin Diagram

    3 Development Board Circuit 3.15 GPIO Figure 3-15 40pin Diagram 3.3V H_GPIO_01 H_GPIO_02 H_GPIO_04 H_GPIO_03 H_GPIO_05 H_GPIO_06 H_GPIO_07 H_GPIO_08 H_GPIO_09 H_GPIO_10 H_GPIO_11 H_GPIO_12 H_GPIO_13 H_GPIO_14 H_GPIO_15 H_GPIO_16 H_GPIO_18 H_GPIO_17 H_GPIO_19 H_GPIO_20 H_GPIO_22 H_GPIO_21 H_GPIO_23 H_GPIO_24 H_GPIO_25 H_GPIO_26 H_GPIO_27 H_GPIO_28 H_GPIO_29 H_GPIO_30 H_GPIO_31 H_GPIO_32...

  • Page 39: Pinout

    3 Development Board Circuit 3.15 GPIO Figure 3-16 20pin Diagram 3.3V H_GPIO_01 H_GPIO_11 H_GPIO_02 H_GPIO_03 H_GPIO_04 H_GPIO_12 H_GPIO_05 H_GPIO_13 H_GPIO_06 H_GPIO_14 H_GPIO_07 H_GPIO_15 H_GPIO_08 H_GPIO_16 H_GPIO_09 H_GPIO_10 5.0V 3.15.2 Pinout Table 3-17 40pin Interface Pinout Pins Number Name FPGA Pin No. BANK I/O Level Description...

  • Page 40: Table 3-18 20Pin Interface Pinout

    3 Development Board Circuit 3.15 GPIO Pins Number Name FPGA Pin No. BANK I/O Level Description 3.3V General I/O H_GPIO_17 3.3V General I/O H_GPIO_18 3.3V General I/O H_GPIO_19 3.3V General I/O H_GPIO_20 3.3V General I/O H_GPIO_21 3.3V General I/O H_GPIO_22 3.3V General I/O H_GPIO_23...

  • Page 41: Industry Screen Interface

    3 Development Board Circuit 3.16 Industry Screen Interface 3.16 Industry Screen Interface 3.16.1 Introduction This interface uses 50pin FPC connector with 0.5mm pitch. The pin definition conforms to the industry screen of AT070TN92 model, and all I/O and 40PIN multiplex GPIO of FPGA. Figure 3-17 50pin FPC Interface Diagram LED+ LED+...

  • Page 42: Pinout

    3 Development Board Circuit 3.16 Industry Screen Interface 3.16.2 Pinout Table 3-19 50pin FPC Interface Pinout Pins Number Name FPGA Pin No. BANK I/O Level Description LCD_MODE 3.3V DE or SYNC mode selection LCD_DE 3.3V Data input enable LCD_VS 3.3V Column synchronization signal...

  • Page 43: Led Module

    3 Development Board Circuit 3.17 LED Module Table 3-20 LCD Screen Brightness Control Pinout Power chip Pin No. Name FPGA Pin No. BANK I/O Level Description LCD_C LCD screen 1.2V brightness control 3.17 LED Module 3.17.1 Introduction There are four blue LED lights on the development board, which can be used for demo.

  • Page 44: Keys Module

    3 Development Board Circuit 3.18 Keys Module 3.18 Keys Module 3.18.1 Introduction The development board has four keys that can be used to control input during testing. When the key is pressed, the input is low. The diagram is as shown in Figure 3-19.

  • Page 45: Pinout

    3 Development Board Circuit 3.19 Switches Module Figure 3-20 Switch Circuit Diagram 1.5V AB21 3.19.2 Pinout Table 3-23 Switches Module Pinout Name FPGA Pin No. BANK I/O Level Description 1.5V Switch1 1.5V Switch2 AB21 1.5V Switch3 1.5V Switch4 DBUG375-1.0E 36(40)

  • Page 46: Quick Start

    4 Quick Start 4.1 Install Software Quick Start 4.1 Install Software Install Gowin EDA software (Gowin Software) to create, build and download FPGA Demo program. Download the EDA software, apply for a license, and obtain software user guide at GOWINSEMI website https://www.gowinsemi.com/en/support/home/.

  • Page 47: Download And Run

    4 Quick Start 4.4 Download and Run Figure 4-1 Design Window 2. Right click "Place & Route" in the "Process" window and select "Rerun All"; Figure 4-2 Process Window 3. After building, the following information will be displayed. The generated bitstream file is saved in: ..LED_test\impl\pnr\LED_test.fs. Figure 4-3 Build Completed 4.4 Download and Run 1.

  • Page 48: Figure 4-4 Programmer Window

    4 Quick Start 4.4 Download and Run switch on the power. Double click "Program Device" in the "Process" window, and the "Programmer" window will pop up. Right click the device list, and select "Configure Device". The Device configuration dialog box will pop up. Figure 4-4 Programmer Window 2.

  • Page 49: Figure 4-6 Click Program/Configure

    4 Quick Start 4.4 Download and Run Figure 4-6 Click Program/Configure DBUG375-1.0E 40(40)

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