1. Manuals
  2. Brands
  3. GOWIN Manuals
  4. Motherboard
  5. GW1N-LV9LQ144C6I5 V1.1
  6. User manual

GOWIN GW1N-LV9LQ144C6I5 V1.1 User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
DK_START_GW1N-LV9LQ144C6I5_V1.1
User Guide
DBUG398-1.1E, 08/13/2021

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the GW1N-LV9LQ144C6I5 V1.1 and is the answer not in the manual?

Questions and answers

Related Manuals for GOWIN GW1N-LV9LQ144C6I5 V1.1

Summary of Contents for GOWIN GW1N-LV9LQ144C6I5 V1.1

  • Page 1 DK_START_GW1N-LV9LQ144C6I5_V1.1 User Guide DBUG398-1.1E, 08/13/2021...
  • Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 08/13/2021 1.0E Initial version published.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide .................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 2 2 Development Board Description ..............
  • Page 5 3.8.1 Overview ........................16 3.8.2 GPIO Circuit ........................17 3.8.3 Pinout ..........................17 3.9 LVDS ..........................20 3.9.1 Overview ........................20 3.9.2 LVDS Circuit ........................20 3.9.3 Pinout ..........................21 4 Considerations ....................23 5 Gowin Software ..................... 25 DBUG398-1.1E...

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 2-1 DK_START_GW1N-LV9LQ144C6I5_V1.1 Development Board ........3 Figure 2-2 A Development Board Kit ....................4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Architecture ......................5 Figure 3-1 Connection Diagram of FPGA USB Downloading and Configuration ......10 Figure 3-2 Power System Distribution ....................
  • Page 7 List of Tables List of Tables Table 1-1 Abbreviations and Terminologies ..................2 Table 2-1 Development Board Specification ..................7 Table 3-1 FPGA Download and Pinout ....................11 Table 3-2 GW1N-9 FPGA Power Pinout .................... 12 Table 3-3 FPGA Clock and Reset Pinout ................... 13 Table 3-4 LED Pinout .........................

  • Page 8: About This Guide

    DS100, GW1N series of FPGA Products Data Sheet  UG103, GW1N series of FPGA Products Package and Pinout  UG114, GW1N-9 Pinout  UG290, Gowin FPGA Products Programming and Configuration User  Guide SUG100, Gowin Software User Guide  1.3 Abbreviations and Terminology The abbreviations and terminology used in this manual are set out in Table 1-1.

  • Page 9: Support And Feedback

    Delay-locked Loop Digital Signal Processing LQ144 LQFP144 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 10: Development Board Description

    2 Development Board Description 2.1 Overview Development Board Description 2.1 Overview Figure 2-1 DK_START_GW1N-LV9LQ144C6I5_V1.1 Development Board The Development board adopts the GW1N-LV9LQ144C6I5 devices of the GW1N-9 series of FPGA products. It features a range of advanced features including low power consumption, instant start-up, high security, low-cost, and flexible extensions, all of which can effectively reduce the learning cost and help users quickly design and develop programmable logic devices.

  • Page 11: A Development Board Suite

    2 Development Board Description 2.2 A Development Board Suite slide switches, key switches, a clock, and LEDs, all of which are useful for both developers and hobbyists alike. With abundant GPIO resources, the development board can be used as the main board to design an image-sampling system and the other related systems by combining video daughter boards.

  • Page 12: Pcb Components

    2 Development Board Description 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 36 PIN FPGA MODE Selection*2 Key*4 GPIO Pin Power Switch Power Socket 3.3V LVDS Power LED*4 1.2V SMA External Power Clock Source 2.5V Power LVDS Slide USB-to- Switch*4 JTAG Chip...

  • Page 13: Features

    2 Development Board Description 2.5 Features 2.5 Features The structure and features of the development board are as follows: 1. FPGA LQFP144 package  Embedded flash, data not easily lost if power down  Abundant LUT4 resources  Multiple modes and capacities of BSRAM ...

  • Page 14: Development Board Specification

    2 Development Board Description 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functional Description Technical Condition Note – – FPGA Core chip Supports USB interface; Download USB-JTAG module on – Supports JTAG, Interface board AUTOBOOT, MSPI Input power: 5V Provides power for...
  • Page 15 2 Development Board Description 2.6 Development Board Specification Item Functional Description Technical Condition Note connected between positive and negative anodes of power outlet; 2A self-recovery fuses are connected at power inlet – – Voltage Input range: 2.7V~5.5V – – Humidity Operating range: –...

  • Page 16: Fpga Circuits

    3 FPGA Circuits 3.1 FPGA Module FPGA Circuits 3.1 FPGA Module Overview For the resources of GW1N series of FPGA Products, please refer to DS100, GW1N series of FPGA Products Data Sheet. I/O BANK Introduction For the I/O BANK, package and pinout information, please refer to UG103, GW1N series of FPGA Products Package and Pinout.

  • Page 17: Usb Download Circuit

    3 FPGA Circuits 3.2 Download Interface 3.2.2 USB Download Circuit Figure 3-1 Connection Diagram of FPGA USB Downloading and Configuration USB_D+ USB_D- USB to JTAG Chip TDO_A MSPI_CK_A MSPI_CS_A FLASH MSPI_DI_A Configuration MSPI_DO 3.2.3 Downloading the Data Stream The data stream file can be downloaded in the following ways: 1.

  • Page 18: Pinout

    3 FPGA Circuits 3.3 Power Supply 3.2.4 Pinout Table 3-1 FPGA Download and Pinout Signal Name Pin No. BANK Description JTAG Signal VCCO3 JTAG Signal VCCO3 JTAG Signal VCCO3 TDO_A JTAG Signal VCCO3 MSPI_CK_A FLASH signals configuration VCCO1 MSPI_CS_A FLASH signals configuration VCCO1 MSPI_DI_A FLASH signals configuration...

  • Page 19: Power System Distribution

    3 FPGA Circuits 3.3 Power Supply 3.3.2 Power System Distribution Figure 3-2 Power System Distribution 40PIN GPIO 5V 2A Power Adapter 40PIN GPIO VCCX (FPGA) FLASH Configuration TPS7A7001 (W25Q64) 3.3V 2A USB to JTAG （FT2232） VCCO0 (FPGA) TPS7A7001 Key&Switch 2.5V 2A VCCO1 (FPGA) VCCO2...

  • Page 20: Clock, Reset

    3 FPGA Circuits 3.4 Clock, Reset 3.4 Clock, Reset 3.4.1 Overview A 50MHz crystal oscillator is provided in the development board that connects to the PLL input pin. This can be employed as the input clock for the PLL in FPGA, and the output clock as needed via multiplication and division of the PLL frequency.

  • Page 21: Led Circuit

    3 FPGA Circuits 3.6 Switches signify power supply and FPGA loading status. Users can test the LEDs in the following ways: If the output signal of related pins is logic low, LED is on;  If logic is high, LED is off. ...

  • Page 22: Key Switch Circuit

    3 FPGA Circuits 3.7 Key 3.6.2 Key Switch Circuit Figure 3-5 Key Switch Circuit 3.6.3 Pinout Table 3-5 Clock Circuit Pinout Signal Name Pin No. BANK Description F_SW1 Slide Switch1 3.3V, 2.5V, 1.2V F_SW2 Slide Switch2 3.3V, 2.5V, 1.2V F_SW3 Slide Switch3 3.3V, 2.5V F_SW4...

  • Page 23: Key Circuit

    3 FPGA Circuits 3.8 GPIO 3.7.2 Key Circuit Figure 3-6 Key Circuit Diagram 3.7.3 Pinout Table 3-6 Key Pinout Signal Name Pin No. BANK Description F_KEY1 KEY1 3.3V, 2.5V, 1.2V F_KEY2 KEY2 3.3V, 2.5V, 1.2V F_KEY3 KEY3 3.3V, 2.5V, 1.2V F_KEY4 KEY4 3.3V, 2.5V, 1.2V...

  • Page 24: Gpio Circuit

    3 FPGA Circuits 3.8 GPIO 3.8.2 GPIO Circuit Figure 3-7 GPIO Circuit VCC3P3 VCC3P3 H_B_IO1 H_B_IO2 H_A_IO1 H_A_IO2 H_B_IO3 H_B_IO4 H_A_IO3 H_A_IO4 H_B_IO5 H_B_IO6 H_A_IO5 H_A_IO6 H_B_IO8 H_B_IO7 H_A_IO8 H_A_IO7 H_B_IO10 H_B_IO9 H_A_IO10 H_A_IO9 H_B_IO11 H_B_IO12 H_A_IO11 H_A_IO12 H_B_IO13 H_B_IO14 H_A_IO13 H_A_IO14 H_B_IO15...
  • Page 25 3 FPGA Circuits 3.8 GPIO Signal Name Pin No. 40P Socket Pin No. BANK Description H_A_IO5 General I/O VCCO0 H_A_IO6 General I/O VCCO0 H_A_IO7 General I/O VCCO0 H_A_IO8 General I/O VCCO0 H_A_IO9 General I/O VCCO0 H_A_IO10 General I/O VCCO0 H_A_IO11 General I/O VCCO0 H_A_IO12...

  • Page 26: Table 3-8 J9 Fpga Pinout

    3 FPGA Circuits 3.8 GPIO Table 3-8 J9 FPGA Pinout Signal Name Pin No. 40P Socket Pin No. BANK Description VCC3P3 3.3V H_B_IO1 General I/O VCCO0 H_B_IO2 General I/O VCCO0 H_B_IO3 General I/O VCCO0 H_B_IO4 General I/O VCCO0 H_B_IO5 General I/O VCCO0 H_B_IO6 General I/O...

  • Page 27: Lvds

    3 FPGA Circuits 3.9 LVDS Signal Name Pin No. 40P Socket Pin No. BANK Description H_B_IO33 General I/O VCCO1 H_B_IO34 General I/O VCCO1 H_B_IO35 General I/O VCCO1 H_B_IO36 General I/O VCCO1 VCC5 Note! The VCCO1 of GW1N-9 can only be supplied with 3.3V. 3.9 LVDS 3.9.1 Overview Two 2 mm DC3-20P sockets are reserved on the development board...

  • Page 28: Pinout

    3 FPGA Circuits 3.9 LVDS 3.9.3 Pinout Table 3-9 J10 FPGA Pinout 40P Socket Signal Name Pin No. BANK Description Pin No. F_LVDS_A1_P Differential Channel 1+ 2.5V F_LVDS_A1_N Differential Channel 1- 2.5V F_LVDS_A2_P Differential Channel 2+ 2.5V F_LVDS_A2_N Differential Channel 2- 2.5V F_LVDS_A3_P Differential Channel 3+...
  • Page 29 3 FPGA Circuits 3.9 LVDS 40P Socket Signal Name Pin No. BANK Description Pin No. F_LVDS_B3_N Differential Channel 3- 2.5V F_LVDS_B4_P Differential Channel 4+ 2.5V F_LVDS_B4_N Differential Channel 4- 2.5V F_LVDS_B5_P Differential Channel 5+ 2.5V F_LVDS_B5_N Differential Channel 5- 2.5V Note! The pin 72 and pin 75 of GW1N-9 are the none-TLVDS differential output pins.

  • Page 30: Considerations

    2. When downloading bitstream files to internal flash or external flash, set the MODE pin state to the correct configuration value, please refer to UG290, Gowin FPGA Products Programming and Configuration User Guide 3. 100 ohm terminating resistors are welded into the LVDS Port. As the output port, the corresponding terminating resistors are removed in the LVDS interface.
  • Page 31 4 Considerations 6. VCCO of four FPGA Banks can select the voltage between 3.3V, 2.5V, and 1.2V through J3 to J6 pins using jumpers.  For GW1N-9 chip, VCCO1 is 3V, i.e., J5 jumper should be set as 3.3V;  VCCO0, VCCO2 and VCCO3 can be set as 3.3V, 2.5V and 1.2V using jumpers.

  • Page 32: Gowin Software

    5 Gowin Software Gowin Software Please refer to SUG100, Gowin Software User Guide. DBUG398-1.1E 25(25)

Table of Contents