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GOWIN DK VIDEO GW5AT-LV60UG225 V1.0 User Manual

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DK_VIDEO_GW5AT-LV60UG225_V1.0
User Guide
DBUG1281-1.0E, 03/07/2025

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Summary of Contents for GOWIN DK VIDEO GW5AT-LV60UG225 V1.0

  • Page 1 DK_VIDEO_GW5AT-LV60UG225_V1.0 User Guide DBUG1281-1.0E, 03/07/2025...
  • Page 2 Copyright © 2025 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 03/07/2025 1.0E Initial version published.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iv List of Tables ....................... v 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 1 1.4 Support and Feedback ....................... 2 2 Development Board Introduction ..............
  • Page 5 Contents 3.2.2 Power System Distribution .................... 11 3.3 Download Module ......................11 3.3.1 Introduction ........................11 3.3.2 Pin Distribution ....................... 12 3.4 Clock ..........................12 3.4.1 Introduction ........................12 3.4.2 Pin Distribution ....................... 12 3.5 DDR3 ..........................12 3.5.1 Introduction ........................12 3.5.2 Pin Distribution .......................
  • Page 6 Contents 4.5.2 Pin Distribution ....................... 30 4.6 LVDS Interface ........................30 4.6.1 Introduction ........................30 4.6.2 Pin Distribution ....................... 31 4.7 MIPI Interface ........................33 4.7.1 Introduction ........................33 4.7.2 Pin Distribution ....................... 35 5 Demo ....................... 40 DBUG1281-1.0E...

  • Page 7: List Of Figures

    List of Figures List of Figures Figure 2-1 DK_VIDEO_GW5AT-LV60UG225_V1.0 Development Board .......... 3 Figure 2-2 DK_VIDEO_GW5AT-LV60UG225_V1.0 Core Board ............4 Figure 2-3 DK_VIDEO_GW5AT-LV60UG225_V1.0 Carrier Board ............ 5 Figure 2-4 A Development Board Kit ....................6 Figure 2-5 PCB Components ......................7 Figure 2-6 PCB Components ......................
  • Page 8 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................1 Table 3-1 JTAG Pin Distribution ......................12 Table 3-2 Clock Pin Distribution ......................12 Table 3-3 DDR3 Configuration ......................13 Table 3-4 DDR3 Pin Distribution ......................13 Table 3-5 Pin Distribution of Key ......................

  • Page 9: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK_VIDEO_GW5AT-LV60UG225_V1.0 development board (hereinafter referred to as “the development board”) user guide consists of following three parts:  A brief introduction to the features of the development board. ...

  • Page 10: Support And Feedback

    Mobile Industry Processor Interface Universal Asynchronous UART Receiver/Transmitter 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 11: Development Board Introduction

    2 Development Board Introduction 2.1 Overview Development Board Introduction 2.1 Overview Figure 2-1 DK_VIDEO_GW5AT-LV60UG225_V1.0 Development Board DK_VIDEO_GW5AT- LV60UG225_V1.0 development board applies to high-speed data storage based on DDR3, high-speed communication based on MIPI, SerDes, supporting MIPI C-PHY and MIPI D-PHY function evaluation, hardware verification, and software learning and debugging, etc.

  • Page 12: Core Board

    DDR3 and SerDes supporting multiple protocols and provides a variety of packages. It is suitable for applications such as low power, high performance and compatibility design. The core board adopts Gowin GW5AT-LV60UG225 FPGA device. For the internal resources of the chip, see DS981, GW5AT series of FPGA Products Data Sheet.

  • Page 13: Carrier Board

    2 Development Board Introduction 2.2 A Development Board Kit 2.1.2 Carrier Board Figure 2-3 DK_VIDEO_GW5AT-LV60UG225_V1.0 Carrier Board The carrier board needs to be used with the DK_VIDEO_GW5AT- LV60UG225_V1.0 core board, integrated multiple interfaces, including LVDS, DP, HDMI, MIPI CPHY, MIPI DPHY, MIPI DPHY DSI, etc. 2.2 A Development Board Kit The development board kit includes the following items: 1.

  • Page 14: Figure 2-4 A Development Board Kit

    2 Development Board Introduction 2.2 A Development Board Kit Figure 2-4 A Development Board Kit ① DK_VIDEO_GW5AT- LV60UG225_V1.0 core board ② DK_VIDEO_GW5AT- LV60UG225_V1.0 carrier board ③ 1080*1920 MIPI LCD ④ 1024*600 LVDS/RGB LCD ⑤ SC130GS module with 1.3 MP MIPI global shutter black and white exposure ⑥...

  • Page 15: Pcb Components

    2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components 2.3.1 Core Board Figure 2-5 PCB Components of Core Board 2.3.2 Carrier Board Figure 2-6 PCB Components of Carrier Board Backup CPHY Hard DPHY Soft Power DP_RX DP_TX Connector Connector DPHY HDMI_TX Hard...

  • Page 16: System Block Diagram

    Figure 2-7 System Block Diagram 2.5 Features The key features are as follows:  FPGA Device Gowin GW5AT-LV60UG225 FPGA  Download and Boot The core board integrates a JTAG interface and supports downloading via a USB downloader. External Flash boot The DONE light is on after loading ...
  • Page 17 2 Development Board Introduction 2.5 Features  HDMI Interface 1-channel HDMI interface  DP Interface 1-channel DP-TX interface 1-channel DP-RX interface Display Port connector  MIPI Interface 1-channel MIPI CPHY hard core, including 3*trios data 1-channel MIPI DPHY hard core, including 4 data + 1 clk 1-channel MIPI-DPHY soft core, including 4 data + 1 clk 1-channel MIPI DPHY DSI, including 4 data+1 clk ...

  • Page 18: Core Board Circuit

    3 Core Board Circuit 3.1 FPGA Core Board Circuit 3.1 FPGA 3.1.1 Overview For the resources of GW5AT series of FPGA products, refer to DS981, GW5AT series of FPGA Products Data Sheet. 3.1.2 I/O BANK Description For the I/O BANK, package, and pinout information, see UG983, GW5AT series of FPGA Products Package and Pinout User Guide more details.

  • Page 19: Power System Distribution

    3 Core Board Circuit 3.3 Download Module 3.2.2 Power System Distribution Figure 3-1 Power Supply System Distribution DC-DC 25MHz 1.8V [ MT3410L Connector /H9008] 1.8V (Input) Connector DC-DC [ MT3410L /H9008] 1.0V 1.0V DC-DC 1.0V [ M0503DLBGP] 1.0V GW5AT- LV60UG225 1.2V 3.3V [ XC6206P122MR]...

  • Page 20: Pin Distribution

    3 Core Board Circuit 3.4 Clock 3.3.2 Pin Distribution Table 3-1 JTAG Pin Distribution Signal Name FPGA Pin No. BANK I/O Level Description C15/IOR1A/TCK 3.3V JTAG signal D15/IOR3B/TDO 3.3V E15/IOR3A/TMS 3.3V B15/IOR1B/TDI 3.3V 3.4 Clock 3.4.1 Introduction The core board provides 1-channel 25 MHz single-ended clock. Figure 3-3 Clock Connection Diagram 3.4.2 Pin Distribution Table 3-2 Clock Pin Distribution...

  • Page 21: Pin Distribution

    3 Core Board Circuit 3.5 DDR3 Table 3-3 DDR3 Configuration Designator Capacity 256M x 16bit The hardware connection diagram of DDR3 is shown in Figure 3-4. Figure 3-4 Hardware Connection Diagram of DDR3 3.5.2 Pin Distribution Table 3-4 DDR3 Pin Distribution Signal Name FPGA Pin No.
  • Page 22 3 Core Board Circuit 3.5 DDR3 Signal Name FPGA Pin No. BANK I/O Level Description DDR3_A14 1.5V Address DDR3_BA0 1.5V Bank address DDR3_BA1 1.5V Bank address DDR3_BA2 1.5V Bank address DDR3_CS# 1.5V Chip select Column address DDR3_CAS# 1.5V strobe DDR3_CKE 1.5V Clock Enable On-Die...

  • Page 23: Reset Key

    3 Core Board Circuit 3.6 Reset Key Signal Name FPGA Pin No. BANK I/O Level Description DDR3_DQ15 1.5V Data DDR3_LDM0 1.5V Data input mask DDR3_UDM0 1.5V Data input mask DDR3_LDQS0_P 1.5V Data Clock DDR3_LDQS0_N 1.5V Data Clock DDR3_UDQS0_P 1.5V Data Clock DDR3_UDQS0_N 1.5V Data Clock...

  • Page 24: Board-To-Board Connector

    3 Core Board Circuit 3.7 Board-to-board Connector 3.7 Board-to-board Connector 3.7.1 Introduction The core board has two 80Pin board-to-board connector with 0.5mm pitch for communication with the DK_VIDEO_GW5AT-LV60UG225_V1.0 carrier board. 3.7.2 Pin Distribution Table 3-6 Pin Distribution for J1 Board-to-Board Connector FPGA Signal Name BANK...
  • Page 25 3 Core Board Circuit 3.7 Board-to-board Connector FPGA Signal Name BANK Description Pin No. Pin No. Level F13_IOR9B/CSI_B/MOSI/MI 3.3V GPIO 0/LVDS E9_IOT78B/LVDS/DQ0 1.2V GPIO F12_IOR9A/D00/DIN/MISO/ 3.3V GPIO MI1/LVDS F8_IOT78A/LVDS/DQ0 1.2V GPIO F11_IOR15A/D11/LVDS 3.3V GPIO E14_IOR5B/MODE0/LVDS 3.3V GPIO G11_IOR15B/D12/LVDS 3.3V GPIO E13_IOR5A/CCLK/LVDS 3.3V GPIO...
  • Page 26 3 Core Board Circuit 3.7 Board-to-board Connector FPGA Signal Name BANK Description Pin No. Pin No. Level T_4/LVDS H13_IOR47A/DONE 3.3V GPIO J14_IOR57B/GCLKC_6/LVD 3.3V GPIO S/DQ5 K15_IOR56A/RECONFIG_N 3.3V GPIO J13_IOR57A/GCLKT_6/LVD 3.3V GPIO S/DQ5 G14_IOR20B/D02/MI3/LVDS 3.3V GPIO /DQ4 K11_IOR59B/LVDS/DQ5 3.3V GPIO G13_IOR20A/D01/MI2/LVDS 3.3V GPIO /DQ4...
  • Page 27 3 Core Board Circuit 3.7 Board-to-board Connector FPGA Signal Name BANK Description Pin No. Pin No. Level LVDS/DQ5 L12_IOR68A/LVDS/DQ5 3.3V GPIO M15_IOR66B/D06/SSPI_CL 3.3V GPIO K/PLL/LVDS/DQ5 N15_IOR70B/D09/CLKHOLD 3.3V GPIO _N/SSI3/LVDS/DQ5 L15_IOR66A/D05/SO/SSI1/P 3.3V GPIO LL/LVDS/DQ5 N14_IOR70A/D08/SSPI_WP 3.3V GPIO N/SSI2/LVDS/DQ5 VDD1V8 1.8V P15_IOR72B/CSO_B/MCS_ 3.3V GPIO N/PLL/LVDS/DQ5...

  • Page 28: Table 3-7 Pin Distribution For J2 Board-To-Board Connector

    3 Core Board Circuit 3.7 Board-to-board Connector Table 3-7 Pin Distribution for J2 Board-to-Board Connector FPGA Signal Name BANK Description Pin No. Pin No. Level TX data signal of Q0_TXP_3 SerDes Q0 RX data signal of Q0_RXP_3 SerDes Q0 TX data signal of Q0_TXN_3 SerDes Q0 RX data signal of...
  • Page 29 3 Core Board Circuit 3.7 Board-to-board Connector FPGA Signal Name BANK Description Pin No. Pin No. Level SerDes Q0 RX data signal of Q0_RXP_1 SerDes Q0 Reference clock of Q0_REFCLKN_0 SerDes Q0 RX data signal of Q0_RXN_1 SerDes Q0 TX data signal of Q0_TXN_0 SerDes Q0 RX data signal of...
  • Page 30 3 Core Board Circuit 3.7 Board-to-board Connector FPGA Signal Name BANK Description Pin No. Pin No. Level MIPI CPHY Data signal of DPHY0_D2N MIPI_M0 MIPI DPHY Data signal of CPHY0_D1B MIPI_M1 MIPI CPHY Data signal of CPHY0_D1C MIPI_M1 MIPI CPHY Data signal of DPHY0_CKP MIPI_M0...
  • Page 31 3 Core Board Circuit 3.7 Board-to-board Connector FPGA Signal Name BANK Description Pin No. Pin No. Level K5/IOL50A/GCLK 1.8V GPIO T_16/LVDS F5/IOL41A/LVDS 1.8V GPIO J5/IOL50B/GCLK 1.8V GPIO C_16/LVDS G5/IOL41B/LVDS 1.8V GPIO K4/IOL45A/GCLK 1.8V GPIO T_18/LVDS K3/IOL45B/GCLK 1.8V GPIO C_18/LVDS VDD5V 5.5V Power VDD5V...

  • Page 32: Backplane Circuit

    4 Backplane Circuit 4.1 Power Supply Backplane Circuit 4.1 Power Supply 4.1.1 Introduction The user can provide 5V power to the carrier board through the USB to Type-C interface (J9) or XH2.54-2P pin header (JP1). When using the XH2.54-2P pin header to provide 5V power supply, the 5V power from the USB to Type-C interface must be disconnected.

  • Page 33: Power System Distribution

    4 Backplane Circuit 4.2 Clock 4.1.2 Power System Distribution Figure 4-1 Power Supply System Distribution Diagram USB Type-C WLED Driver (Input) Connector 3.3V XH2.54-2P [XC6206P332MR] DP-TX 3.3V (Input) 2.8V [XC6206P282MR] 2.8V HDMI MIPI DPHY Hard 3.3V LVDS USB to UART 135MHz 3.3V MIPI Soft...

  • Page 34: Pin Distribution

    4 Backplane Circuit 4.3 UART Interface Figure 4-2 Clock Connection Diagram 4.2.2 Pin Distribution Table 4-1 Clock Pin Distribution Signal Name FPGA Pin No. BANK I/O Level Description Q0_REFCLKP_0 135 MHz differential clock Q0_REFCLKN_0 135 MHz differential clock 4.3 UART Interface 4.3.1 Introduction The UART interface led from the development board uses USB to Type-C connector, which is implemented via USB conversion chips.

  • Page 35: Dp Interface

    4 Backplane Circuit 4.4 DP Interface 4.4 DP Interface 4.4.1 Introduction The carrier board provides 1-channel DP-TX interface and 1-channel DP-RX interface. The connection diagram of the DP interfaces is as follows. Figure 4-4 Connection Diagram of DP-TX Interface Figure 4-5 Connection Diagram of DP-RX Interface 4.4.2 Pin Distribution Table 4-3 Pin Distribution of DP-TX Interface FPGA...
  • Page 36 4 Backplane Circuit 4.4 DP Interface FPGA Signal Name BANK I/O Level Description Pin No. Pin No. DPTXP_1 DP Data Transmit DPTXN_1 DP Data Transmit DPTXP_2 DP Data Transmit DPTXN_2 DP Data Transmit DPTXP_3 DP Data Transmit DPTXN_3 DP Data Transmit DPTX_AUXP 3.3V Auxiliary channel...

  • Page 37: Hdmi Interface

    4 Backplane Circuit 4.5 HDMI Interface Table 4-4 Pin Distribution of DP-RX Interface FPGA Signal Name BANK I/O Level Description Pin No. Pin No. DPRXN_3 DP Data Receive DPRXP_3 DP Data Receive DPRXN_2 DP Data Receive DPRXP_2 DP Data Receive DPRXN_1 DP Data Receive DPRXP_1...

  • Page 38: Pin Distribution

    4 Backplane Circuit 4.6 LVDS Interface Figure 4-6 Connection Diagram of HDMI Interface 4.5.2 Pin Distribution Table 4-5 HDMI Interface Pin Distribution Signal Name FPGA Pin No. BANK I/O Level Description HDMI_CLK+ 3.3V HDMI differential clock HDMI_CLK- 3.3V HDMI differential clock HDMI_D0+ 3.3V HDMI transmit data...

  • Page 39: Pin Distribution

    4 Backplane Circuit 4.6 LVDS Interface Figure 4-7 Connection Diagram of LVDS Interface 4.6.2 Pin Distribution Table 4-6 LVDS Interface Pin Distribution FPGA Signal Name BANK I/O Level Description Pin No. Pin No. Floating Floating Floating Floating LVDS_DAT0_N 3.3V LVDS signal LVDS_DAT0_P 3.3V LVDS signal...
  • Page 40 4 Backplane Circuit 4.6 LVDS Interface FPGA Signal Name BANK I/O Level Description Pin No. Pin No. LVDS_DATC_N 3.3V LVDS signal LVDS_DATC_P 3.3V LVDS signal LVDS_DAT3_N 3.3V LVDS signal LVDS_DAT3_P 3.3V LVDS signal Floating Floating Serial data signal CAM_SDA 1.8V of touchscreen Serial clock CAM_SCL...

  • Page 41: Mipi Interface

    4 Backplane Circuit 4.7 MIPI Interface 4.7 MIPI Interface 4.7.1 Introduction The carrier board provides 1-channel MIPI DPHY hard core interface, 1-channel MIPI DPHY hard core interface, 1-channel MIPI DPHY soft core interface, and 1-channel MIPI DPHY DSI interface. MIPI CPHY hard core (3*trios data), I2C, and reset signals are routed to 20P FPC connectors with 0.5mm pitch.

  • Page 42: Figure 4-9 Connection Diagram Of Mipi Dphy Hard Core Interface

    4 Backplane Circuit 4.7 MIPI Interface Figure 4-9 Connection Diagram of MIPI DPHY Hard Core Interface Figure 4-10 Connection Diagram of MIPI DPHY Soft Core Interface Figure 4-11 Connection Diagram of MIPI DPHY DSI Interface MIPI_TX0_P/N MIPI_TX1_P/N MIPI_TX2_P/N MIPI_TX3_P/N Connector MIPI DSI MIPI_TX_CLKP/N DSI_RESET_1V8...

  • Page 43: Pin Distribution

    4 Backplane Circuit 4.7 MIPI Interface 4.7.2 Pin Distribution Table 4-7 Pin Distribution of MIPI CPHY Hard Core Interface FPGA Signal Name BANK Description Pin No. Pin No. Level CPHY0_D2C MIPI_M1 MIPI CPHY data signal CPHY0_D2B MIPI_M1 MIPI CPHY data signal CPHY0_D2A MIPI_M1 MIPI CPHY data signal...
  • Page 44 4 Backplane Circuit 4.7 MIPI Interface FPGA Signal Name BANK Description Pin No. Pin No. Level MIPI DPHY data DPHY0_D3P MIPI_M0 signal MIPI DPHY data DPHY0_D3N MIPI_M0 signal MIPI DPHY data DPHY0_D2P MIPI_M0 signal MIPI DPHY data DPHY0_D2N MIPI_M0 signal MIPI DPHY clock DPHY0_CKP MIPI_M0...

  • Page 45: Table 4-9 Pin Distribution Of Mipi Dphy Soft Core Interface

    4 Backplane Circuit 4.7 MIPI Interface Table 4-9 Pin Distribution of MIPI DPHY Soft Core Interface FPGA Signal Name BANK Description Pin No. Pin No. Level VDD3V3 3.3V Power VDD3V3 3.3V Power Floating Floating Floating Floating Floating Floating Receive clock signal MIPI_RX_CLKP 1.2V of MIPI DPHY...

  • Page 46: Table 4-10 Pin Distribution Of Mipi Dphy Dsi Interface

    4 Backplane Circuit 4.7 MIPI Interface Table 4-10 Pin Distribution of MIPI DPHY DSI Interface FPGA Signal Name BANK Description Pin No. Pin No. Level LEDK Backlight cathode LEDA Backlight anode Floating Floating DSI_RESET_ 1.8V Reset signal VDD1V8 1.8V Power VDD2V8 2.8V Power...
  • Page 47 4 Backplane Circuit 4.7 MIPI Interface FPGA Signal Name BANK Description Pin No. Pin No. Level MIPI DSI 1.2V Transmit data signal of MIPI_TX0_N MIPI DSI DBUG1281-1.0E 39(41)

  • Page 48: Demo

    5 Demo Demo The demo includes basic demos and image demos. The basic demo is used to validate the board's basic functions such as HDMI, DDR3, LVDS, DSI, and DP. The image demo is used to conduct HDMI and LVDS screen display tests for various cameras based on DDR3, MIPI C-PHY hard core, and MIPI D-PHY soft core.

  • Page 49: Table 5-2 Image Demointroduction

    5 Demo 4.7 MIPI Interface Project Name Design Description 08-3_G60_DDR3_DSI_ 1080*1920@60 DDR3 image cache and MIPI DSI LCD screen display test Display_10801920 Table 5-2 Image Demo Introduction Project Name Design Description SC130GS black-and-white exposure 1-lane 01-1_SC130GS_DDR3_ HDMI screen display project based on DPHY HDMI_720P60 soft core and DDR3 SC130GS black-and-white exposure 1-lane...

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