GOWIN DK-START-GW2A18 User Manual
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GOWIN DK-START-GW2A18 User Manual

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DK-START-GW2A18
User Guide
DBUG354-1.0E,08/28/2018

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Summary of Contents for GOWIN DK-START-GW2A18

  • Page 1 DK-START-GW2A18 User Guide DBUG354-1.0E,08/28/2018...
  • Page 2 Copyright©2018 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer ®...
  • Page 3 Revision History Date Version Description 08/28/2018 1.0E Initial version published.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Supported Products ......................1 1.3 Related Documents ......................1 1.4 Abbreviations and Terminology ................... 1 1.5 Support and Feedback ....................... 2 2 Development Board Description ..............3 2.1 Overview ..........................
  • Page 5 3.10.1 Introduction ........................27 3.10.2 Pins Distribution ......................27 3.11 Key ..........................27 3.11.1 Introduction ........................27 3.11.2 Pins Distribution ......................28 3.12 Switch ..........................28 3.12.1 Introduction ........................28 3.12.2 Pins Distribution ......................29 4 Gowin YunYuan Software ................30 DBUG354-1.0E...
  • Page 6 List of Figures List of Figures Figure 2-1 PCB Components ......................5 Figure 2-2System Architecture ......................6 Figure 3-1 GW2A I/O Bank Distribution ..................... 10 Figure 3-2 View of GW2A-18 PG256 Pins Distribution (Top View) ............ 11 Figure 3-3 Connection Diagram for FPGA Downloading and Configuration ........13 Figure 3-4 Power System Distribution ....................
  • Page 7 List of Tables List of Tables Table 1-1 Abbreviations and Terminology ..................2 Table 3-1GW2A-LV18PG256 FPGA Resources List ................. 9 Table 3-2 FPGA I/O Bank Voltage and Functions ................11 Table 3-3 FPGA Download and Pins Distribution ................13 Table 3-4 Clock and Reset Pins Distribution ..................16 Table 3-5 DDR3 Pins Distribution ......................

  • Page 8: About This Guide

    3. An introduction to the hardware circuit functions, circuits, and pins distribution; 4. An introduction to the use of the Gowin YunYuan software. 1.2 Supported Products The information presented in this guide applies to the following Gowin FPGA products: GW2A-LV18PG256.

  • Page 9: Support And Feedback

    Low-Voltage Differential Signaling S-SRAM Shadow SRAM 1.5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 10: Development Board Description

    2.1Overview Development Board Description 2.1 Overview Figure 2-1 DK-START-GW2A18 DK-START-GW2A18 applies to high speed data storage, high-speed communication test, FPGA functions evaluation, the verification of hardware reliability, software learning and debugging, etc. The development board uses the GW2A-LV18PG256 FPGA device, which is the first generation products of Gowin Arora ®...

  • Page 11: A Development Board Suite

    55nm process to make the GW2A series of FPGA products ideal for high-speed and low-cost applications. DK-START-GW2A18 includes a DDR3 chip with 2Gbit storage space,16 bits data bus width, and the highest data speed of 1600MT/s. Its two Gigabit Ethernet interfaces support 10M,100M,1000M Ethernet communication.

  • Page 12: Pcb Components

    2Development Board Description 2.3PCB Components 2.3 PCB Components Figure 2-1 PCB Components 以太网 接口芯片*2 DDR3 备用电源 1.2V电源 2.5V电源 1.0V电源 1.5V电源 3.3V电源 电源插座 电源开关 以太网 20PIN 接口*2 GPIO 插针 30PIN GPIO 插针 MODE BANK7 电压选择 配置 FLASH LED*4 SD卡座 USB MINI B LVDS TX 复位...

  • Page 13: System Architecture

    2Development Board Description 2.4System Architecture 2.4 System Architecture Figure 2-2System Architecture 配置 DDR3 LVDS LVDS (2Gbit) FLASH 以太网 20PIN GPIO 接口1 Header 30PIN GPIO 以太网 Header 接口2 JTAG SD卡 晶振 按键 开关 2.5 Features The key features of DK-START-GW2A is as follows: 1.
  • Page 14 2Development Board Description 2.5Features The blue POWER light is on after power on  The development board generates 3.3V, 2.5V, 1.5V, 1.2V, 1.0V,  and 0.75V (required by DDR3) 4. Clock system 50MHz crystal oscillator Input  External signals input ...
  • Page 15 2Development Board Description 2.5Features Four blue LEDs  DBUG354-1.0E...

  • Page 16: Development Board Circuit

    3Development Board Circuit 3.1FPGA Module Development Board Circuit 3.1 FPGA Module 3.1.1 Introduction The resources of GW2A-LV18PG256 FPGA are set out in Table 3-1. Table 3-1GW2A-LV18PG256 FPGA Resources List Device GW2A-LV18PG256 LUT4 20,736 Flip-Flop (FF) 15,552 Shadow SRAM 41,472 S-SRAM (bits) Block SRAM 828K B-SRAM(bits)

  • Page 17: I/O Distribution

    3Development Board Circuit 3.1FPGA Module 3.1.2 I/O Distribution GW2A series FPGA products includes eight I/O Bank. The I/O Bank Distribution is as shown in Figure 3-1. Figure 3-1 GW2A I/O Bank Distribution The view of GW2A-18 PG256 pins distribution is as shown in Figure 3-2. DBUG354-1.0E...

  • Page 18: Figure 3-2 View Of Gw2A-18 Pg256 Pins Distribution (Top View)

    3Development Board Circuit 3.1FPGA Module Figure 3-2 View of GW2A-18 PG256 Pins Distribution (Top View) The board I/O Bank and functions are as listed in Table 3-2. Table 3-2 FPGA I/O Bank Voltage and Functions I/O BANK No. Supply voltage Functions LVDS_RX Interface 30PIN GPIO Interface...

  • Page 19: Download Module

    3Development Board Circuit 3.2Download Module I/O BANK No. Supply voltage Functions DONE RECONFIG_N READY FASTRD_N DDR3 BANK4 1.5V BANK5 1.5V DDR3 DDR3 BANK6 1.5V Switches 3.3V, 2.5V, 1.2V BANK7 20PIN GPIO Interface (Adjustable) Note！ For the V2.0 development board, the BANK0 voltage and BANK1 voltage can be set as 3.3V or 2.5V using J13.

  • Page 20: Pins Distribution

    3Development Board Circuit 3.3Power Supply Figure 3-3 Connection Diagram for FPGA Downloading and Configuration JTAG_TCK USB_D+ JTAG_TDO USB 转 USB_D- JTAG_TDI JTAG芯片 JTAG_TMS P10 R10 M9 L10 FLASH_SPI_MISO FLASH_SPI_MOSI 配置 FLASH_SPI_CS_N FLASH FLASH_SPI_CLK 3.2.2 Pins Distribution Table 3-3 FPGA Download and Pins Distribution Signal Name FPGA Pin No.
  • Page 21 3Development Board Circuit 3.3Power Supply is 2A. When the redundant power is used to replace the main power, you need to take off the main power's magnetic beads to avoid the power conflicts. DBUG354-1.0E...

  • Page 22: Power System Distribution

    3Development Board Circuit 3.3Power Supply 3.3.2 Power System Distribution Figure 3-4 Power System Distribution 5V 2A 电源 20PIN GPIO 适配器 插针 30PIN GPIO 插针 NCP3170 VCCO2 & VCCO3 & 开关电源 VCCO7 & VCCX 3.3V 3A (FPGA) 配置FLASH (W25Q64) 以太网接口芯片1 （B50610KML） USB转JTAG （FT2232）...

  • Page 23: Clock, Reset

    3Development Board Circuit 3.4Clock, Reset Note！ For the V2.0 development board, the BANK0 voltage and BANK1 voltage can be set as 3.3V or 2.5V using J13. 3.4 Clock, Reset 3.4.1 Introduction The development board offers a 50MHz oscillator, connecting to the global clock pins.

  • Page 24: Introduction

    3Development Board Circuit 3.5DDR3 3.5.1 Introduction The development board includes a DDR3 chip with 2Gbit storage space,16 bits data bus width, and the highest data speed of 1600MT/s. Figure 3-6 Connection Diagram of FPGA and DDR3 DDR3_A[13..0] DDR3_BA[2..0] DDR3_DQ[15..0] DDR3_UDM DDR3_UDQSn DDR3_UDQSp DDR3_LDM...
  • Page 25 3Development Board Circuit 3.5DDR3 Signal Name FPGA Pin No. BANK Description Address DDR3_A13 1.5V Bank address DDR3_BA0 1.5V Bank address DDR3_BA1 1.5V Bank address DDR3_BA2 1.5V Column address DDR3_CASn 1.5V strobe Clock Enable DDR3_CK_EN 1.5V Differential clock DDR3_CKn 1.5V Differential clock DDR3_CKp 1.5V Chip select...

  • Page 26: Ethernet Interface

    3Development Board Circuit 3.6Ethernet interface Signal Name FPGA Pin No. BANK Description Data strobe DDR3_UDQSn K6 1.5V Data strobe DDR3_UDQSp J5 1.5V Write enable DDR3_WEn 1.5V 3.6 Ethernet interface 3.6.1 Introduction The development board has two Ethernet circuits and supports gigabit mode, which can be used to test hardware environment in the LED display applications, and Ethernet data transmission.

  • Page 27: Lvds Interfaces

    3Development Board Circuit 3.7LVDS interfaces Signal Name FPGA Pin No. BANK Description PHY1_TXD2 3.3V PHY1 sending data channel 2 PHY1_TXD3 3.3V PHY1 sending data channel 3 PHY1_TX_EN 3.3V PHY1 sending data enable PHY1_RXC 3.3V PHY1 Clock receive PHY1_RXD0 3.3V PHY1 receive data channel 0 PHY1_RXD1 3.3V PHY1 receive data channel 1...

  • Page 28: Figure 3-8 Lvds Tx Interface

    3Development Board Circuit 3.7LVDS interfaces Figure 3-8 LVDS TX Interface Figure 3-9 LVDS RX Interface LVDS_A1_P LVDS_A1_N LVDS_A1_N LVDS_A1_P LVDS_A2_P LVDS_A2_N LVDS_A2_P LVDS_A2_N LVDS_A3_P LVDS_A3_N LVDS_A3_P LVDS_A3_N LVDS_A4_P LVDS_A4_N LVDS_A4_P LVDS_A4_N LVDS_A5_P LVDS_A5_N LVDS_A5_P LVDS_A5_N DBUG354-1.0E...

  • Page 29: Pins Distribution

    3Development Board Circuit 3.8SD Card 3.7.2 Pins Distribution Table 3-7 LVDS TX Interface Pins Distribution Pins Number Signal Name FPGA Pin No. BANK Description 2.5V Differential Channel 1+ LVDS_B1_P 2.5V Differential Channel 1- LVDS_B1_N 2.5V Differential Channel 2+ LVDS_B2_P 2.5V Differential Channel 2- LVDS_B2_N 2.5V...

  • Page 30: Figure 3-10 Connection Diagram Of Sd Card

    3Development Board Circuit 3.8SD Card contacts. It offers the detection of the card insertion. The connection diagram is shown as follows. Figure 3-10 Connection Diagram of SD Card SD_D0 SD_D1 SD_D2 SD_CD/D3 SD卡座 SD_CMD SD_CLK SD_SWITCH DBUG354-1.0E...

  • Page 31: Pins Distribution

    3Development Board Circuit 3.9GPIO 3.8.2 Pins Distribution Table 4-3 SD Card Pins Distribution Signal Name FPGA Pin No. BANK Description SD_D0 3.3V Data bits 0 SD_D1 3.3V Data bits 1 SD_D2 3.3V Data bits 2 SD_CD/D3 3.3V Card detection/Data bits 3 SD_CMD 3.3V Commands/Response...

  • Page 32: Pins Distribution

    3Development Board Circuit 3.9GPIO Figure 3-12 30pin Interface 3.3V H_GPIO_01 H_GPIO_01 H_GPIO_02 H_GPIO_03 H_GPIO_04 H_GPIO_05 H_GPIO_06 H_GPIO_07 H_GPIO_08 H_GPIO_09 H_GPIO_10 H_GPIO_11 H_GPIO_12 H_GPIO_13 H_GPIO_14 H_GPIO_15 H_GPIO_16 H_GPIO_17 H_GPIO_18 H_GPIO_19 H_GPIO_20 H_GPIO_21 H_GPIO_22 H_GPIO_23 H_GPIO_24 5.0V 3.9.2 Pins Distribution Table 3-9 20pin Interface Pins Distribution Pins Number Signal Name FPGA Pin No.

  • Page 33: Led

    3Development Board Circuit 3.10LED Pins Number Signal Name FPGA Pin No. BANK Description 3.3V / 2.5V / 1.2V General I/O H_A_IO13 3.3V / 2.5V / 1.2V General I/O H_A_IO14 3.3V / 2.5V / 1.2V General I/O H_A_IO15 3.3V / 2.5V / 1.2V General I/O H_A_IO16 Table 3-10 30pin Interface Pins Distribution...

  • Page 34: Introduction

    3Development Board Circuit 3.11Key 3.10.1 Introduction Four blue LEDs are incorporated into the development board and are used to display the required status. If the output signal of the related pins is logic low, LED is on; If logic is high, LED is off. The connection diagram is shown in Figure 3-13.

  • Page 35: Pins Distribution

    3Development Board Circuit 3.12Switch Figure 3-14 GPIO Circuit 3.11.2 Pins Distribution Table 3-12 Key Pins Distribution Signal Name FPGA Pin No. BANK Description KEY1 1.5V KEY1 KEY2 1.5V KEY2 KEY3 1.5V KEY3 KEY4 1.5V KEY4 3.12 Switch 3.12.1 Introduction Four slide switches are incorporated into the development board. These are used to control input during testing.

  • Page 36: Pins Distribution

    3Development Board Circuit 3.12Switch Figure 3-15 GPIO Circuit 3.12.2 Pins Distribution Table 3-13 Pins Distribution of the Switch Module Signal Name FPGA Pin No. BANK Description 1.5V Slide Switch1 1.5V Slide Switch2 1.5V Slide Switch3 1.5V Slide Switch4 DBUG354-1.0E...

  • Page 37: Gowin Yunyuan Software

    4Gowin YunYuan Software Gowin YunYuan Software Please refer to Gowin Software User Guide for details. DBUG354-1.0E...

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