TASKING CYPRESS CYT2BL Hardware User Manual page 15

winIDEA configuration
By default, P18 port pins (P18_3 – P18_7) or P22 port pins (P22_0 – P22_4) are set as GPIO pins.
To configure these pins as trace pins in winIDEA, open Hardware | CPU Options | Analyzer and add
a script
CYT2Bx_TraceInit.cpp
and depending on the user target board configuration allocate:
·
TRACE CLOCK Port to PORT 18 (or PORT 22)
·
TRACE DATAn PORT to PORT 18 (or PORT 22)
in the SoC Initialization section. Via the Parameters options
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