Analog Devices EVAL-AD4857 User Manual page 6

User Guide
EVALUATION BOARD HARDWARE
Table 1. Jumper Details with the Factory Default Settings (Continued)
Link Default Position
JVIO Not inserted
JVIO_LDO Not inserted
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Function
The JVIO link selects the V pin supply source. If not inserted, the V
IO
Alternatively, the V pin can be supplied from either the on-board LDO regulators or an external supply.
IO
In Position A, the V pin is provided by the on-board LT1761 LDO regulator with an output voltage dependent on the
IO
JVIO_LDO link. The R66 resistor (shown in
In Position B, the V pin is provided though the VIO_EXT connector. The R66 resistor is unsoldered.
IO
Note the field programmable gate array (FPGA) image provided works at a 2.5 V digital level; therefore, use caution when
changing the default position of the JVIO link jumper.
The JVIO_LDO link selects the LT1761 LDO regulator output voltage when the JVIO link is in Position B.
Inserted, the LT1761 output voltage is 3.3 V.
Not inserted, the LT1761 output voltage is 1.8 V.
pin is taken from the ZedBoard (default).
IO
Figure 7) is unsoldered.
EVAL-AD4857
Rev. A | 6 of 11