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GD32E513 Series
GigaDevice Semiconductor GD32E513 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32E513 Series. We have
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GigaDevice Semiconductor GD32E513 Series manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32E513 Series User Manual (1334 pages)
Arm Cortex-M33 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 11 MB
Table of Contents
Table of Contents
2
List of Figures
21
List of Tables
32
System and Memory Architecture
37
Arm ® Cortex ® -M33 Processor
37
Figure 1-1. the Structure of the Cortex ® -M33 Processor
37
System Architecture
38
Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix
38
Figure 1-2. High Density Devices System Architecture
40
Memory Map
41
Figure 1-3. Connectivity Line Devices System Architecture
41
Table 1-2. Memory Map of Gd32E51X Devices
42
On-Chip SRAM Memory
45
On-Chip Flash Memory Overview
45
Boot Configuration
46
Device Electronic Signature
46
Table 1-3. Boot Modes
46
Memory Density Information
47
Unique Device ID (96 Bits)
47
System Configuration Registers
48
Flash Memory Controller (FMC)
49
Overview
49
Characteristics
49
Function Overview
49
Flash Memory Architecture
49
Table 2-1. Gd32E51X_Hd and Gd32E51X_Cl Base Address and Size for Flash Memory
49
Error Checking and Correcting (ECC)
50
Read Operations
51
Table 2-2. the Relation between WSCNT and AHB Clock Frequency
51
Unlock the FMC_CTL Register
52
Page Erase
53
Mass Erase
54
Figure 2-1. Process of Page Erase Operation
54
Main Flash Programming
55
Figure 2-2. Process of Mass Erase Operation
55
OTP Programming
57
Option Bytes Erase
57
Figure 2-3. Process of Word Program Operation
57
Option Bytes Programming
58
Option Bytes Description
58
Table 2-3. Option Bytes
59
Page Erase / Program Protection
60
Security Protection
60
Table 2-4. OB_WP Bit for Pages Protected
60
Register Definition
62
Wait State Register (FMC_WS)
62
Unlock Key Register (FMC_KEY)
63
Option Byte Unlock Key Register (FMC_OBKEY)
63
Status Register (FMC_STAT)
64
Control Register (FMC_CTL)
64
Address Register (FMC_ADDR)
66
ECC Control and Status Register (FMC_ECCCS)
66
Option Byte Status Register (FMC_OBSTAT)
68
Erase/Program Protection Register (FMC_WP)
68
Product ID Register (FMC_PID)
69
Backup Registers (BKP)
70
Overview
70
Characteristics
70
Function Overview
70
RTC Clock Calibration
70
Tamper Detection
70
Register Definition
72
Backup Data Register X (Bkp_Datax) (X= 0
72
RTC Signal Output Control Register (BKP_OCTL)
72
Tamper Pin Control Register (BKP_TPCTL)
73
Tamper Control and Status Register (BKP_TPCS)
74
Power Management Unit (PMU)
75
Overview
75
Characteristics
75
Function Overview
75
Backup Domain
76
Figure 4-1. Power Supply Overview
76
VDD / V Dda
77
Figure 4-2. Waveform of the BOR
77
Figure 4-3. Waveform of the por / PDR
78
Power Domain
79
Figure 4-4. Waveform of the LVD Threshold
79
Power Saving Modes
80
Table 4-1. Power Saving Mode Summary
83
Register Definition
85
Control Register 0 (PMU_CTL0)
85
Control and Status Register 0 (PMU_CS0)
87
Control Register 1 (PMU_CTL1)
89
Control and Status Register 1 (PMU_CS1)
90
Reset and Clock Unit (RCU)
91
High Density Reset and Clock Control Unit (RCU)
91
Reset Control Unit (RCTL)
91
Overview
91
Function Overview
91
Clock Control Unit (CCTL)
92
Overview
92
Figure 5-1. the System Reset Circuit
92
Figure 5-2. Clock Tree
93
Characteristics
94
Function Overview
94
Figure 5-3. HXTAL Clock Source
95
Figure 5-4. HXTAL Clock Source in Bypass Mode
95
Table 5-1. Clock Output 0 Source Select
98
Table 5-2. 1.1V Domain Voltage Selected in Deep-Sleep Mode
98
Register Definition
99
Control Register (RCU_CTL)
99
Clock Configuration Register 0 (RCU_CFG0)
100
Clock Interrupt Register (RCU_INT)
104
APB2 Reset Register (RCU_APB2RST)
106
APB1 Reset Register (RCU_APB1RST)
109
AHB Enable Register (RCU_AHBEN)
113
APB2 Enable Register (RCU_APB2EN)
114
APB1 Enable Register (RCU_APB1EN)
117
Backup Domain Control Register (RCU_BDCTL)
120
Reset Source/Clock Register (RCU_RSTSCK)
122
AHB Reset Register (RCU_AHBRST)
123
Clock Configuration Register 1 (RCU_CFG1)
124
Deep-Sleep Mode Voltage Register (RCU_DSV)
125
Additional Clock Control Register (RCU_ADDCTL)
125
Additional Clock Interrupt Register (RCU_ADDINT)
126
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
127
Clock Configuration Register 2 (RCU_CFG2)
128
APB1 Additional Reset Register (RCU_ADDAPB1RST)
128
APB1 Additional Enable Register (RCU_ADDAPB1EN)
129
Connectivity Line Devices: Reset and Clock Control Unit (RCU)
130
Reset Control Unit (RCTL)
130
Overview
130
Function Overview
130
Clock Control Unit (CCTL)
131
Overview
131
Figure 5-5. the System Reset Circuit
131
Figure 5-6. Clock Tree
132
Characteristics
133
Function Overview
134
Figure 5-7. HXTAL Clock Source
134
Figure 5-8. HXTAL Clock Source in Bypass Mode
134
Table 5-3. Clock Output 0 Source Select
137
Table 5-4. 1.1V Domain Voltage Selected in Deep-Sleep Mode
138
Register Definition
139
Control Register (RCU_CTL)
139
Clock Configuration Register 0 (RCU_CFG0)
141
Clock Interrupt Register (RCU_INT)
145
APB2 Reset Register (RCU_APB2RST)
148
APB1 Reset Register (RCU_APB1RST)
151
AHB Enable Register (RCU_AHBEN)
154
APB2 Enable Register (RCU_APB2EN)
156
APB1 Enable Register (RCU_APB1EN)
159
Backup Domain Control Register (RCU_BDCTL)
162
Reset Source/Clock Register (RCU_RSTSCK)
163
AHB Reset Register (RCU_AHBRST)
165
Clock Configuration Register 1 (RCU_CFG1)
166
Deep-Sleep Mode Voltage Register (RCU_DSV)
169
Additional Clock Control Register (RCU_ADDCTL)
170
Additional Clock Configuration Register (RCU_ADDCFG)
171
Additional Clock Interrupt Register (RCU_ADDINT)
172
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
173
Clock Configuration Register 2 (RCU_CFG2)
174
APB1 Additional Reset Register (RCU_ADDAPB1RST)
175
APB1 Additional Enable Register (RCU_ADDAPB1EN)
176
Clock Trim Controller (CTC)
177
Overview
177
Characteristics
177
Function Overview
177
REF Sync Pulse Generator
178
CTC Trim Counter
178
Figure 6-1. CTC Overview
178
Frequency Evaluation and Automatically Trim Process
179
Figure 6-2. CTC Trim Counter
179
Software Program Guide
180
Register Definition
182
Control Register 0 (CTC_CTL0)
182
Control Register 1 (CTC_CTL1)
183
Status Register (CTC_STAT)
184
Interrupt Clear Register (CTC_INTC)
186
Interrupt/Event Controller (EXTI)
188
Overview
188
Characteristics
188
Interrupts Function Overview
188
Table 7-1. NVIC Exception Types in Cortex ® -M33
189
Table 7-2. Interrupt Vector Table
189
External Interrupt and Event (EXTI) Block Diagram
193
External Interrupt and Event Function Overview
193
Figure 7-1. Block Diagram of EXTI
193
Hardware Trigger
194
Software Trigger
194
Table 7-3. EXTI Source
194
EXTI Register
196
Interrupt Enable Register (EXTI_INTEN)
196
Event Enable Register (EXTI_EVEN)
196
Rising Edge Trigger Enable Register (EXTI_RTEN)
197
Falling Edge Trigger Enable Register (EXTI_FTEN)
197
Software Interrupt Event Register (EXTI_SWIEV)
197
Pending Register (EXTI_PD)
198
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
199
Overview
199
Characteristics
199
Function Overview
199
GPIO Pin Configuration
200
Figure 8-1. Basic Structure of a General-Pupose I/O
200
Table 8-1. GPIO Configuration Table
200
External Interrupt/Event Lines
201
Alternate Functions (AF)
201
Input Configuration
201
Output Configuration
202
Analog Configuration
202
Figure 8-2. Basic Structure of Input Configuration
202
Figure 8-3. Basic Structure of Output Configuration
202
Alternate Function (AF) Configuration
203
IO Pin Function Selection
203
Figure 8-4. Basic Structure of Analog Configuration
203
Figure 8-5. Basic Structure of Alternate Function Configuration
203
GPIO Locking Function
204
GPIO I/O Compensation Cell
204
Remapping Function I/O and Debug Configuration
204
Introduction
204
Main Features
205
JTAG/SWD Alternate Function Remapping
205
Table 8-2. Debug Interface Signals
205
Table 8-3. Debug Port Mapping and Pin Availability
205
ADC AF Remapping
206
TIMER AF Remapping
206
Table 8-4. ADC0/1 External Trigger Routine Conversion AF Remapping Function
206
Table 8-5. Timerx Alternate Function Remapping
206
Table 8-6. TIMER4 Alternate Function Remapping
207
USART AF Remapping
208
I2C0 AF Remapping
208
Table 8-7. USART0/1/2 Alternate Function Remapping
208
SPI0/SPI2/I2S AF Remapping
209
CAN0/1 AF Remapping
209
Table 8-8. I2C0 Alternate Function Remapping
209
Table 8-9. SPI0/SPI2/I2S Alternate Function Remapping
209
Table 8-10. CAN0/1 Alternate Function Remapping
209
Ethernet AF Remapping
210
CTC AF Remapping
210
CLK Pins AF Remapping
210
Table 8-11. ENET Alternate Function Remapping
210
Table 8-12. CTC Alternate Function Remapping
210
Table 8-13. OSC32 Pins Configuration
211
Table 8-14. OSC Pins Configuration
211
Register Definition
212
Port Control Register 0 (Gpiox_Ctl0, X=A
212
Port Control Register 1 (Gpiox_Ctl1, X=A
214
Port Input Status Register (Gpiox_Istat, X=A
215
Port Output Control Register (Gpiox_Octl, X=A
216
Port Bit Operate Register (Gpiox_Bop, X=A
216
Port Bit Clear Register (Gpiox_Bc, X=A
217
Port Configuration Lock Register (Gpiox_Lock, X=A
217
Port Bit Speed Register (Gpiox_ SPD, X=A
218
Event Control Register (AFIO_EC)
219
AFIO Port Configuration Register 0 (AFIO_PCF0)
219
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
226
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
227
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
228
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
229
AFIO Port Configuration Register 1 (AFIO_PCF1)
231
IO Compensation Control Register (AFIO_CPSCTL)
232
AFIO Port Configuration Register a (AFIO_PCFA)
233
AFIO Port Configuration Register B (AFIO_PCFB)
235
AFIO Port Configuration Register C (AFIO_PCFC)
238
AFIO Port Configuration Register D (AFIO_PCFD)
240
AFIO Port Configuration Register E (AFIO_PCFE)
241
AFIO Port Configuration Register G (AFIO_PCFG)
242
Cyclic Redundancy Checks Management Unit (CRC)
245
Overview
245
Characteristics
245
Function Overview
246
Figure 9-1. Block Diagram of CRC Management Unit
246
Register Definition
248
Data Register (CRC_DATA)
248
Free Data Register (CRC_FDATA)
248
Control Register (CRC_CTL)
249
Initialization Data Register (CRC_IDATA)
249
Polynomial Register (CRC_POLY)
250
Trigonometric Math Unit (TMU)
251
Overview
251
Characteristics
251
Function Overview
251
TMU Block Diagram
251
Table 10-1. 9 Different Operation Modes
251
Data Format
252
Figure 10-1. Block Diagram of Trigonometric Math Unit
252
Table 10-2. IEEE 32-Bit Single Precision Floating-Point Format
252
Mode 0 Description
253
Mode 1 Description
253
Table 10-3. Convert Per-Unit Values to Radians in Mode 0
253
Table 10-4. Convert Radians Values to Per-Unit Values in Mode 1
253
Mode 2 Description
254
Mode 3 Description
254
Mode 4 Description
255
Mode 5 Description
255
Mode 6 Description
255
Table 10-5. the Range of Input Value and R0 Value in Mode 5
255
Mode 7 Description
257
Figure 10-2. Calculation of R1 (Quadrant) and R0 (Ratio) Based on y and X Values
257
Table 10-6. the Condition of UDRF and OVRF Flag in Mode 6
257
Table 10-7. the Condition of UDRF and OVRF Flag in Mode 7
257
Mode 8 Description
258
Software Guideline
258
Figure 10-3. TMU Program Guidline
259
TMU Register
260
Input Data0 Register (TMU_IDATA0)
260
Input Data1 Register (TMU_IDATA1)
260
Control Register (TMU_CTL)
261
Data0 Register (TMU_DATA0)
262
Data1 Register (TMU_DATA1)
262
Status Register (TMU_STAT)
262
Direct Memory Access Controller (DMA)
264
Overview
264
Characteristics
264
Block Diagram
265
Function Overview
265
DMA Operation
265
Figure 11-1. Block Diagram of DMA
265
Table 11-1. DMA Transfer Operation
266
Peripheral Handshake
267
Arbitration
267
Figure 11-2. Handshake Mechanism
267
Address Generation
268
Circular Mode
268
Memory to Memory Mode
268
Channel Configuration
268
Interrupt
269
DMA Request Mapping
269
Figure 11-3. DMA Interrupt Logic
269
Table 11-2. Interrupt Events
269
Figure 11-4. DMA0 Request Mapping
270
Table 11-3. DMA0 Requests for each Channel
270
Figure 11-5. DMA1 Request Mapping
273
Table 11-4. DMA1 Requests for each Channel
273
Register Definition
274
Interrupt Flag Register (DMA_INTF)
274
Interrupt Flag Clear Register (DMA_INTC)
275
Channel X Control Register (Dma_Chxctl)
275
Channel X Counter Register (Dma_Chxcnt)
277
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
278
Channel X Memory Base Address Register (Dma_Chxmaddr)
278
Debug (DBG)
280
Introduction
280
JTAG/SW Function Description
280
Switch JTAG or SW Interface
280
Pin Assignment
280
JTAG Daisy Chained Structure
281
Debug Reset
281
JEDEC-106 ID Code
281
Debug Hold Function Description
281
Debug Support for Power Saving Mode
281
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
282
DBG Registers
283
ID Code Register (DBG_ID)
283
Control Register (DBG_CTL)
283
Analog-To-Digital Converter (ADC)
287
Introduction
287
Characteristics
287
Pins and Internal Signals
288
Figure 13-1. ADC Module Block Diagram (for ADC0 and ADC1)
288
Table 13-1. ADC Internal Input Signals
288
Table 13-2. ADC Input Pins Definition
288
Functional Overview
289
Foreground Calibration Function
290
Figure 13-2. ADC Module Block Diagram (for ADC2)
290
ADC Clock
291
ADCON Enable
291
Single-Ended and Differential Input Channels
291
Routine Sequence
292
Operation Modes
292
Figure 13-3. Single Operation Mode
292
Figure 13-4. Continuous Operation Mode
293
Figure 13-5. Scan Operation Mode, Continuous Operation Mode Disable
294
Figure 13-6. Scan Operation Mode, Continuous Operation Mode Enable
294
Figure 13-7. Discontinuous Operation Mode
294
Conversion Result Threshold Monitor
295
Data Storage Mode
295
Sample Time Configuration
296
External Trigger Configuration
296
Figure 13-8. 12-Bit Data Storage Mode
296
Figure 13-9. 6-Bit Data Storage Mode
296
Table 13-3. External Trigger Source for ADC0 and ADC1
296
DMA Request
297
ADC Internal Channels
297
Table 13-4. External Trigger Source for ADC2
297
Programmable Resolution (DRES)
298
On-Chip Hardware Oversampling
298
Table 13-5. T CONV Timings Depending on Resolution
298
Figure 13-10. 20-Bit to 16-Bit Result Truncation
299
Figure 13-11. Numerical Example with 5-Bits Shift and Rounding
299
Table 13-6. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)
299
ADC Sync Mode
300
Table 13-7. ADC Sync Mode Table
300
Free Mode
301
Routine Parallel Mode
301
Figure 13-12. ADC Sync Block Diagram
301
Routine Follow-Up Fast Mode
302
Routine Follow-Up Slow Mode
302
Figure 13-13. Routine Parallel Mode on 10 Channels
302
Figure 13-14. Routine Follow-Up Fast Mode on Routine Sequence (the CTN Bit of the Adcs Are Set)
302
ADC Interrupts
303
Figure 13-15. Routine Follow-Up Slow Mode on Routine Sequence Channel
303
ADC Registers
304
Status Register (ADC_STAT)
304
Control Register 0 (ADC_CTL0)
305
Control Register 1 (ADC_CTL1)
307
Sample Time Register 0 (ADC_SAMPT0)
309
Sample Time Register 1 (ADC_SAMPT1)
310
Watchdog High Threshold Register 0 (ADC_WDHT0)
311
Watchdog Low Threshold Register 0 (ADC_WDLT0)
311
Routine Sequence Register 0 (ADC_RSQ0)
311
Routine Sequence Register 1 (ADC_RSQ1)
312
Routine Sequence Register 2 (ADC_RSQ2)
313
Routine Data Register (ADC_RDATA)
313
Oversample Control Register (ADC_OVSAMPCTL)
314
Watchdog 1 Channel Selection Register (ADC_WD1SR)
315
Watchdog 2 Channel Selection Register (ADC_WD2SR)
316
Watchdog Threshold Register 1 (ADC_WDT1)
316
Watchdog Threshold Register 2 (ADC_WDT2)
317
Differential Mode Control Register (ADC_DIFCTL)
318
Digital-To-Analog Converter (DAC)
319
Overview
319
Characteristics
319
Figure 14-1. DAC Block Diagram
319
Table 14-1. DAC I/O Description
320
Table 14-2. DAC Triggers and Outputs Summary
320
Function Overview
321
DAC Enable
321
DAC Output Buffer
321
DAC Data Configuration
321
DAC Trigger
321
Table 14-3. Triggers of DAC
321
DAC Conversion
322
DAC Noise Wave
322
DAC Output Voltage
323
DMA Request
323
Figure 14-2. DAC LFSR Algorithm
323
Figure 14-3. DAC Triangle Noise Wave
323
DAC Concurrent Conversion
324
DAC Output FIFO
324
Register Definition
324
Dacx Control Register 0 (DAC_CTL0)
325
Dacx Software Trigger Register (DAC_SWT)
328
Dacx_Out0 12-Bit Right-Aligned Data Holding Register (DAC_OUT0_R12DH)
329
Dacx_Out0 12-Bit Left-Aligned Data Holding Register (DAC_OUT0_L12DH)
329
Dacx_Out0 8-Bit Right-Aligned Data Holding Register (DAC_OUT0_R8DH)
330
Dacx_Out1 12-Bit Right-Aligned Data Holding Register (DAC_OUT1_R12DH)
330
Dacx_Out1 12-Bit Left-Aligned Data Holding Register (DAC_OUT1_L12DH)
331
Dacx_Out1 8-Bit Right-Aligned Data Holding Register (DAC_OUT1_R8DH)
331
Dacx Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
332
Dacx Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
332
Dacx Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
333
Dacx_Out0 Data Output Register (DAC_OUT0_DO)
333
Dacx_Out1 Data Output Register (DAC_OUT1_DO)
334
Dacx Status Register 0 (DAC_STAT0)
334
Dacx Control Register 1 (DAC_CTL1)
335
Dacx Status Register 1 (DAC_STAT1)
336
Comparator (CMP)
338
Overview
338
Characteristics
338
Function Overview
338
CMP Clock
339
CMP I / O Configuration
339
Figure 15-1. CMP Block Diagram
339
CMP Register Write Protection
340
Table 15-1. CMP Inputs and Outputs Summary
340
CMP Output Blanking
341
Figure 15-2. the CMP Outputs Signal Blanking
341
Register Definition
342
CMP1 Control / Status Register (CMP1_CS)
342
CMP3 Control / Status Register (CMP3_CS)
344
CMP5 Control / Status Register (CMP5_CS)
345
Watchdog Timer (WDGT)
348
Free Watchdog Timer (FWDGT)
348
Overview
348
Characteristics
348
Function Overview
348
Figure 16-1. Free Watchdog Block Diagram
349
Table 16-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
349
Register Definition
351
Window Watchdog Timer (WWDGT)
354
Overview
354
Characteristics
354
Function Overview
354
Figure 16-2. Window Watchdog Timer Block Diagram
354
Figure 16-3. Window Watchdog Timing Diagram
355
Table 16-2. Min/Max Timeout Value at 100 Mhz (F PCLK1 )
356
Register Definition
357
Real-Time Clock (RTC)
359
Overview
359
Characteristics
359
Function Overview
359
RTC Reset
360
RTC Reading
360
RTC Configuration
360
Figure 17-1. Block Diagram of RTC
360
RTC Flag Assertion
361
Figure 17-2. RTC Second and Alarm Waveform Example (RTC_PSC = 3, RTC_ALRM = 2)
361
Figure 17-3. RTC Second and Overflow Waveform Example (RTC_PSC= 3)
362
RTC Register
363
RTC Interrupt Enable Register (RTC_INTEN)
363
RTC Control Register (RTC_CTL)
363
RTC Prescaler High Register (RTC_PSCH)
364
RTC Prescaler Low Register (RTC_PSCL)
365
RTC Divider High Register (RTC_DIVH)
365
RTC Divider Low Register (RTC_DIVL)
365
RTC Counter High Register (RTC_CNTH)
366
RTC Counter Low Register (RTC_CNTL)
366
RTC Alarm High Register (RTC_ALRMH)
367
RTC Alarm Low Register (RTC_ALRML)
367
Timer (Timerx)
368
Table 18-1. Timers (Timerx) Are Divided into Seven Sorts
368
Advanced Timer (Timerx, X=0, 7)
369
Overview
369
Characteristics
369
Block Diagram
371
Function Overview
371
Figure 18-1. Advanced Timer Block Diagram
371
Figure 18-2. Timing Chart of Internal Clock Divided by 1
372
Figure 18-3. Timing Chart of PSC Value Change from 0 to 2
373
Figure 18-4. Timing Chart of up Counting Mode, PSC=0/2
373
Figure 18-5. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
375
Figure 18-6. Timing Chart of down Counting Mode, PSC=0/2
376
Figure 18-7. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
377
Figure 18-8. Timing Chart of Center-Aligned Counting Mode
378
Figure 18-9. Repetition Timechart for Center-Aligned Counter
379
Figure 18-10. Repetition Timechart for Up-Counter
379
Figure 18-11. Repetition Timechart for Down-Counter
380
Figure 18-12. Channel Input Capture Principle
381
Figure 18-13. Channel Output Compare Principle (with Complementary Output, X=0,1,2)
382
Figure 18-15. Output-Compare in Three Modes
383
Figure 18-16. Timing Chart of EAPWM
385
Figure 18-17. Timing Chart of CAPWM
385
Table 18-2. Complementary Outputs Controlled by Parameters
387
Figure 18-18. Complementary Output with Dead-Time Insertion
388
Figure 18-19. Output Behavior of the Channel in Response to a Break (the Break High Active)
389
Figure 18-20. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
390
Table 18-3. Counting Direction in Different Quadrature Decoder Mode
390
Figure 18-21. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
391
Figure 18-22. Hall Sensor Is Used to BLDC Motor
391
Figure 18-23. Hall Sensor Timing between Two Timers
392
Figure 18-24. Restart Mode
393
Table 18-4. Examples of Slave Mode
393
Figure 18-25. Pause Mode
394
Figure 18-26. Event Mode
394
Figure 18-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
395
Figure 18-28. Timer0 Master/Slave Mode Example
395
Figure 18-29. Trigger TIMER0 and TIMER2 by the CI0 Signal of TIMER2
397
Timerx Registers(X=0, 7)
399
General Level0 Timer (Timerx, X=1, 2, 3, 4)
427
Overview
427
Characteristics
427
Block Diagram
427
Figure 18-30. General Level 0 Timer Block Diagram
427
Function Overview
428
Figure 18-31. Timing Chart of Internal Clock Divided by 1
429
Figure 18-32. Timing Chart of PSC Value Change from 0 to 2
430
Figure 18-33. Timing Chart of up Counting Mode, PSC=0/2
430
Figure 18-34. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
432
Figure 18-35. Timing Chart of down Counting Mode,Psc=0/2
433
Figure 18-36. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
434
Figure 18-37. Timing Chart of Center-Aligned Counting Mode
435
Figure 18-38. Channel Input Capture Principle
436
Figure 18-39. Channel Output Compare Principle (X=0,1,2,3)
437
Figure 18-40. Output-Compare in Three Modes
438
Figure 18-41. Timing Chart of EAPWM
439
Figure 18-42. Timing Chart of CAPWM
439
Table 18-5. Examples of Slave Mode
441
Figure 18-43. Restart Mode
442
Figure 18-44. Pause Mode
442
Figure 18-45. Event Mode
443
Timerx Registers(X=1, 2, 3, 4)
444
General Level1 Timer (Timerx, X=8, 11)
470
Overview
470
Characteristics
470
Block Diagram
470
Figure 18-46. General Level1 Timer Block Diagram
470
Function Overview
471
Figure 18-47. Timing Chart of Internal Clock Divided by 1
472
Figure 18-48. Timing Chart of PSC Value Change from 0 to 2
473
Figure 18-49. Timing Chart of up Counting Mode, PSC=0/2
473
Figure 18-50. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
475
Figure 18-51. Channel Input Capture Principle
476
Figure 18-52. Channel Output Compare Principle (X=0,1)
477
Figure 18-53. Output-Compare under Three Modes
478
Figure 18-54. PWM Mode Timechart
479
Figure 18-55. Restart Mode
480
Table 18-6. Examples of Slave Mode
480
Figure 18-56. Pause Mode
481
Figure 18-57. Event Mode
481
Figure 18-58. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
482
Timerx Registers(X=8, 11)
483
General Level2 Timer (Timerx, X=9, 10, 12, 13)
496
Overview
496
Characteristics
496
Block Diagram
496
Figure 18-59. General Level2 Timer Block Diagram
496
Function Overview
497
Figure 18-60. Timing Chart of Internal Clock Divided by 1
498
Figure 18-61. Timing Chart of PSC Value Change from 0 to 2
498
Figure 18-62. Timing Chart of up Counting Mode, PSC=0/2
499
Figure 18-63. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
500
Figure 18-64. Channel Input Capture Principle
501
Figure 18-65. Channel Output Compare Principle
502
Figure 18-66. Output-Compare under Three Modes
503
Timerx Registers(X=9, 10, 12, 13)
505
General Level3 Timer (Timerx, X=14)
516
Overview
516
Characteristics
516
Block Diagram
516
Function Overview
517
Figure 18-67. General Level3 Timer Block Diagram
517
Figure 18-68. Timing Chart of Internal Clock Divided by 1
518
Figure 18-69. Timing Chart of PSC Value Change from 0 to 2
519
Figure 18-70. Timing Chart of up Counting Mode, PSC=0/2
519
Figure 18-71. Timing Chart of up Counting, Change Timerx_Car Ongoing
521
Figure 18-72. Repetition Counter Timing Chart of up Counting Mode
522
Figure 18-73. Channel Input Capture Principle
523
Figure 18-74. Channel Output Compare Principle (with Complementary Output, X=0)
524
Figure 18-75. Channel Output Compare Principle (CH1_O)
524
Figure 18-76. Output-Compare in Three Modes
525
Figure 18-77. PWM Mode Timechart
527
Table 18-7. Complementary Outputs Controlled by Parameters
528
Figure 18-78. Complementary Output with Dead-Time Insertion
529
Figure 18-79. Output Behavior in Response to a Break(the Break High Active)
530
Figure 18-80. Restart Mode
531
Table 18-8. Slave Mode Example Table
531
Figure 18-81. Pause Mode
532
Figure 18-82. Event Mode
532
Figure 18-83. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
533
Timerx Registers(X=14)
535
General Level4 Timer (Timerx, X=15, 16)
555
Overview
555
Characteristics
555
Block Diagram
555
Function Overview
556
Figure 18-84. General Level4 Timer Block Diagram
556
Figure 18-85. Timing Chart of Internal Clock Divided by 1
557
Figure 18-86. Timing Chart of PSC Value Change from 0 to 2
558
Figure 18-87. Timing Chart of up Counting Mode, PSC=0/2
558
Figure 18-88. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
560
Figure 18-89. Repetition Counter Timing Chart of up Counting Mode
561
Figure 18-90. Channel Input Capture Principle
562
Figure 18-91. Channel Output Compare Principle (with Complementary Output, X=0)
563
Figure 18-92. Output-Compare under Three Modes
565
Figure 18-93. PWM Mode Timechart
566
Table 18-9. Complementary Outputs Controlled by Parameters
567
Figure 18-94. Complementary Output with Dead-Time Insertion
568
Figure 18-95. Output Behavior in Response to a Break(the Break High Active)
569
Figure 18-96. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
570
Timerx Registers(X=15, 16)
572
Basic Timer (Timerx, X=5, 6)
588
Overview
588
Characteristics
588
Block Diagram
588
Function Overview
588
Figure 18-97. Basic Timer Block Diagram
588
Figure 18-98. Timing Chart of Internal Clock Divided by 1
589
Figure 18-99. Timing Chart of PSC Value Change from 0 to 2
590
Figure 18-100. Timing Chart of up Counting Mode, PSC=0/2
591
Figure 18-101. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
592
Timerx Registers(X=5, 6)
593
Super High-Resolution Timer (SHRTIMER)
598
Overview
598
Characteristics
598
Block Diagram
598
Figure 19-1. SHRTIMER Block Diagram
598
Function Overview
599
Master_Timer Unit
599
Figure 19-2. Master_Timer Diagram
599
Table 19-1. the Limitations of Auto-Reload and Compare y (Y=0..3) Register
600
Figure 19-3. Counter Clock When Divided by 32
601
Figure 19-4. Counter Behavior in Single Pulse Mode
602
Figure 19-5. Counter Behavior in Continuous Mode
602
Figure 19-6. Repetition Counter Behavior in Continuous Mode
603
Figure 19-7. Repetition Counter Behavior in Single Pulse Mode with CNTRSTM = 0
603
Figure 19-8. Repetition Counter Behavior in Single Pulse Mode with CNTRSTM = 1
604
Figure 19-9 Reset Event Resynchronization When Prescaling Ratio Is 128
604
Table 19-3. Master_Timer Shadow Registers and Update Event
606
Slave_Timerx(X=0
607
Figure 19-10. Slave_Timerx Diagram
607
Table 19-4. the Limitations of Counter and Capture y(Y=0,1) Value Registers
608
Figure 19-11. Capture 0 Triggered by EXEV0 and EXEV1
611
Figure 19-12.Compare 1 Behavior with Stxcar=0X8, Stxcmp1V=0X02
612
Figure 19-13. Compare Delayed Mode Chart
612
Figure 19-14. Compare 1 Delayed Mode 0
613
Figure 19-15. Compare 1 Delayed Mode 1
614
Figure 19-16. Compare Delayed Mode with SHWEN = 0
615
Figure 19-17. Channel Output Diagram
615
Figure 19-18. O0PRE Wave: Set on CMP0, Reset on CMP1
616
Table 19-5. Slave_Timer Interconnection Event
617
Figure 19-19. Arbitration Mechanism During each T
618
Figure 19-20. Arbitration Mechanism Example
619
Figure 19-23. Super High-Resolution Oxpre Wave
620
Figure 19-24. Oxpre Wave with CNTCKDIV[3:0] = 4'B0110
621
Figure 19-25. C0OPRE Wave in Regular Mode
621
Figure 19-26. C0OPRE and C1OPRE Complementary Wave with Dead-Time
623
Figure 19-27. Complementary Wave with Pulse Width Less than Dead-Time
623
Figure 19-28. Structure Chart in Balanced Mode
624
Figure 19-29. C0OPRE and C1OPRE Wave in Balanced Mode
625
Table 19-6. Crossbar and IDLE Control Stage Work Together
626
Table 19-7. Request to Enter in IDLE and Exit IDLE State
627
Figure 19-30. ISO0 = 0 and CHOP = 0 in Delayed IDLE
628
Figure 19-31. ISO0 = 1 and CHOP = 0 in Delayed IDLE
628
Figure 19-32. ISO0 = 0 and CHOP = 1 in Delayed IDLE
629
Figure 19-33. ISO0 = 1 and CHOP = 1 in Delayed IDLE
629
Figure 19-34. Balanced IDEL with ISO0 = 0 and ISO1 = 0
630
Table 19-8. Output During IDEL State Controlled by Bunch Mode
631
Table 19-9. Output Stage Status Programming (X=0
631
Figure 19-35. Stxchy_O Wave with Chyp=0 or Chyp=1
632
Figure 19-36. Carrier-Signal Structure Diagram
633
Figure 19-37. SHRTIMER Output with Carrier-Signal Mode Enabled
634
Table 19-10. Slave_Timerx Shadow Registers and Update Event
635
Table 19-11. Stxupiny(Y=0..2) and Chip Internal Signal
635
Figure 19-38. Blanking Mode and Windowing Mode
636
Table 19-12. Filtering Signals Mapping in Blanking Mode
636
Table 19-13. Filtering Signals Mapping in Windowing Mode
637
DLL Calibrate
638
Bunch Mode
638
Figure 19-39. Bunch Mode Timing Chart
639
Table 19-14. Chip Internal Signal in Bunch Mode
639
Figure 19-40. Regular Entry for Bunch Mode
640
Figure 19-41. Delayed Entry for Bunch Mode
642
Synchronization Input/Output
643
Figure 19-42. Emulate Bunch Mode Example
643
External Event
644
Figure 19-43. Extern Event y(Y=0..4) Processed Diagram
645
Figure 19-44. Extern Event y(Y=5..9) Processed Diagram
645
Fault Input
646
Figure 19-45. Fault Input Diagram
646
Table 19-15. External Events Mapping
646
Table 19-16. Fault Channel Mapping
647
Trigger to ADC
648
Trigger to DAC
649
Figure 19-46. Trigger to ADC Selection Overview
649
Interrupt
650
Figure 19-47. Trigger to DAC Selection Overview
650
Table 19-17. Interrupt Mapping
650
DMA Request
651
Table 19-18. DMA Request Mapping
651
DMA Mode
652
Debug Mode
653
Register Definition
653
Figure 19-48. DMA Mode Operation Flowchart
653
Master_Timer Registers
654
Slave_Timerx Registers(X=0
666
Common Registers
727
Universal Synchronous/Asynchronous Receiver /Transmitter (USART)
771
Universal Synchronous/Asynchronous Receiver /Transmitter (Usartx, X=0
771
Characteristics
771
Function Overview
772
Table 20-1. Description of USART Important Pins
772
Figure 20-1. USART Module Block Diagram
773
Figure 20-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
773
Table 20-2. Configuration of Stop Bits
773
Figure 20-3. USART Transmit Procedure
775
Figure 20-4. Receiving a Frame Bit by Oversampling Method
776
Figure 20-5. Configuration Step When Using DMA for USART Transmission
778
Figure 20-6. Configuration Steps When Using DMA for USART Reception
779
Figure 20-7. Hardware Flow Control between Two Usarts
779
Figure 20-8. Hardware Flow Control
780
Figure 20-9. Break Frame Occurs During Idle State
781
Figure 20-10. Break Frame Occurs During a Frame
782
Figure 20-11. Example of USART in Synchronous Mode
782
Figure 20-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
783
Figure 20-13. Irda SIR ENDEC Module
783
Figure 20-14. Irda Data Modulation
784
Figure 20-15. ISO7816-3 Frame Format
785
Table 20-3. USART Interrupt Requests
787
Figure 20-16. USART Interrupt Mapping Diagram
788
Register Definition
789
Universal Synchronous/Asynchronous Receiver /Transmitter (Usartx, X=5)
803
Overview
803
Characteristics
803
Function Overview
804
Table 20-4. Description of USART Important Pins
804
Figure 20-17. USART Module Block Diagram
805
Figure 20-18. USART Character Frame (8 Bits Data and 1 Stop Bit)
805
Table 20-5. Configuration of Stop Bits
805
Figure 20-19. USART Transmit Procedure
807
Figure 20-20. Oversampling Method of a Receive Frame Bit (OSB=0)
809
Figure 20-21. Configuration Step When Using DMA for USART Transmission
810
Figure 20-22. Configuration Step When Using DMA for USART Reception
811
Figure 20-23. Hardware Flow Control between Two Usarts
811
Figure 20-24. Hardware Flow Control
812
Figure 20-25. Break Frame Occurs During Idle State
814
Figure 20-26. Break Frame Occurs During a Frame
814
Figure 20-27. Example of USART in Synchronous Mode
815
Figure 20-28. 8-Bit Format USART Synchronous Waveform (CLEN=1)
815
Figure 20-29. Irda SIR ENDEC Module
816
Figure 20-30. Irda Data Modulation
816
Figure 20-31. ISO7816-3 Frame Format
817
Figure 20-32. USART Receive FIFO Structure
820
Table 20-6. USART Interrupt Requests
821
Figure 20-33. USART Interrupt Mapping Diagram
822
Register Definition
823
Inter-Integrated Circuit Interface (I2C)
841
Inter-Integrated Circuit Interface (I2Cx, X=0, 1)
841
Overview
841
Characteristics
841
Function Overview
841
Figure 21-1. I2C Module Block Diagram
841
Table 21-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
842
Figure 21-2. Data Validation
843
Figure 21-3. START and STOP Signal
843
Figure 21-4. Clock Synchronization
844
Figure 21-5. SDA Line Arbitration
844
Figure 21-6. I2C Communication Flow with 7-Bit Address
845
Figure 21-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
845
Figure 21-8. I2C Communication Flow with 10-Bit Address (Master Receive)
845
Figure 21-9. Programming Model for Slave Transmitting (10-Bit Address Mode)
847
Figure 21-10. Programming Model for Slave Receiving (10-Bit Address Mode)
847
Figure 21-11. Programming Model for Master Transmitting (10-Bit Address Mode)
848
Figure 21-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)
851
Figure 21-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)
852
Table 21-2. Event Status Flags
856
Table 21-3. Error Flags
856
Register Definition
858
Inter-Integrated Circuit Interface (I2Cx, X=2)
872
Overview
872
Characteristics
872
Function Overview
872
Figure 21-14. I2C Module Block Diagram
872
Table 21-4. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
873
Figure 21-15. Data Validation
874
Figure 21-16. START and STOP Signal
875
Figure 21-17. I2C Communication Flow with 10-Bit Address (Master Transmit)
875
Figure 21-18. I2C Communication Flow with 7-Bit Address (Master Transmit)
876
Figure 21-19. I2C Communication Flow with 7-Bit Address (Master Receive)
876
Figure 21-20. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=0)
876
Figure 21-21. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=1)
876
Figure 21-22. Data Hold Time
877
Figure 21-23. Data Setup Time
878
Table 21-5. Data Setup Time and Data Hold Time
879
Figure 21-24. Data Transmission
880
Figure 21-25. Data Reception
880
Table 21-6. Communication Modes to be Shut down
880
Figure 21-26. I2C Initialization in Slave Mode
883
Figure 21-27. Programming Model for Slave Transmitting When SS=0
884
Figure 21-28. Programming Model for Slave Transmitting When SS=1
885
Figure 21-29. Programming Model for Slave Receiving
886
Figure 21-30. I2C Initialization in Master Mode
887
Figure 21-31. Programming Model for Master Transmitting (N<=255)
888
Figure 21-32. Programming Model for Master Transmitting (N>255)
889
Figure 21-33. Programming Model for Master Receiving (N<=255)
890
Figure 21-34. Programming Model for Master Receiving (N>255)
891
Figure 21-35. Smbus Master Transmitter and Slave Receiver Communication Flow
894
Figure 21-36. Smbus Master Receiver and Slave Transmitter Communication Flow
895
Table 21-7. I2C Error Flags
896
Table 21-8. I2C Interrupt Events
896
Register Definition
898
Serial Peripheral Interface/Inter-IC Sound (SPI/I2S)
912
Figure 22-1. Block Diagram of SPI
913
Table 22-1. SPI Signal Description
913
Table 22-2. Quad-SPI Signal Description
914
Figure 22-2. SPI Timing Diagram in Normal Mode
915
Figure 22-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
915
Table 22-3. NSS Function in Slave Mode
916
Table 22-4. NSS Function in Master Mode
916
Table 22-5. SPI Operation Modes
917
Figure 22-4. a Typical Full-Duplex Connection
918
Figure 22-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
918
Figure 22-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
919
Figure 22-7. a Typical Bidirectional Connection
919
Figure 22-8. Timing Diagram of TI Master Mode with Discontinuous Transfer
921
Figure 22-9. Timing Diagram of TI Master Mode with Continuous Transfer
921
Figure 22-10. Timing Diagram of TI Slave Mode
921
Figure 22-11. Timing Diagram of NSS Pulse with Continuous Transmit
922
Figure 22-12. Timing Diagram of Write Operation in Quad-SPI Mode
923
Figure 22-13. Timing Diagram of Read Operation in Quad-SPI Mode
924
Figure 22-14. Block Diagram of I2S
927
Table 22-6. SPI Interrupt Requests
927
Figure 22-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
928
Figure 22-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
929
Figure 22-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
929
Figure 22-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
929
Figure 22-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
929
Figure 22-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
929
Figure 22-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
930
Figure 22-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
930
Figure 22-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
930
Figure 22-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
931
Figure 22-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
931
Figure 22-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
931
Figure 22-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
931
Figure 22-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
931
Figure 22-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
931
Figure 22-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
932
Figure 22-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
932
Figure 22-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
932
Figure 22-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
933
Figure 22-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
933
Figure 22-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
933
Figure 22-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
933
Figure 22-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
933
Figure 22-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
934
Figure 22-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
934
Figure22-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
934
Figure 22-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
934
Figure 22-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
934
Figure 22-43. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
935
Figure22-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
935
Figure 22-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
935
Figure 22-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
935
Figure 22-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
935
Figure 22-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
936
Figure 22-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
936
Figure 22-51. Block Diagram of I2S Clock Generator
936
Table 22-7. I2S Bitrate Calculation Formulas
937
Table 22-8. Audio Sampling Frequency Calculation Formulas
937
Table 22-9. Direction of I2S Interface Signals for each Operation Mode
937
Figure 22-52. I2S Initialization Sequence
939
Figure 22-53. I2S Master Reception Disabling Sequence
941
Table 22-10. I2S Interrupt
943
Table 23-1. SQPI Controller Mode Definition
956
Figure 23-1. SQPI_PL Example
958
Figure 23-2. SQPI_SC Example
958
Figure 23-3. SQPI_RDID Example (SQPI_IDLEN=00)
959
Figure 23-4. SQPI_CLK Example
959
Figure 23-5. SQPI SSS Mode Timing (SPI)
960
Figure 23-6. SQPI SSQ Mode Timing
961
Figure 23-7. SQPI SQQ Mode Timing (SQPI)
961
Figure 23-8. SQPI QQQ Mode Timing (QPI)
961
Figure 23-9. SQPI SSD Mode Timing
962
Figure 23-10. SQPI SDD Mode Timing
962
Figure 24-1. SDIO "No Response" and "No Data" Operations
967
Figure 24-2. SDIO Multiple Blocks Read Operation
968
Figure 24-3. SDIO Multiple Blocks Write Operation
968
Figure 24-4. SDIO Sequential Read Operation
968
Figure 24-5. SDIO Sequential Write Operation
968
Figure 24-6. SDIO Block Diagram
969
Table 24-1. SDIO I/O Definitions
970
Figure 24-7. Command Token Format
976
Table 24-2. Command Format
976
Table 24-3. Card Command Classes (Cccs)
977
Table 24-4. Basic Commands (Class 0)
979
Table 24-5. Block-Oriented Read Commands (Class 2)
980
Table 24-6. Stream Read Commands (Class 1) and Stream Write Commands (Class 3)
981
Table 24-7. Block-Oriented Write Commands (Class 4)
981
Table 24-8. Erase Commands (Class 5)
982
Table 24-9. Block Oriented Write Protection Commands (Class 6)
983
Table 24-10. Lock Card (Class 7)
983
Table 24-11. Application-Specific Commands (Class 8)
984
Table 24-12. I/O Mode Commands (Class 9)
985
Table 24-13. Switch Function Commands (Class 10)
986
Figure 24-8. Response Token Format
987
Table 24-14. Response R1
987
Table 24-15. Response R2
988
Table 24-16. Response R3
988
Table 24-17. Response R4 for MMC
988
Table 24-18. Response R4 for SD I/O
988
Table 24-19. Response R5 for MMC
989
Table 24-20. Response R5 for SD I/O
989
Table 24-21. Response R6
989
Figure 24-9. 1-Bit Data Bus Width
990
Figure 24-10. 4-Bit Data Bus Width
990
Table 24-22. Response R7
990
Figure 24-11. 8-Bit Data Bus Width
991
Table 24-23. Card Status
992
Table 24-24. SD Status
994
Table 24-25. Performance Move Field
996
Table 24-26. AU_SIZE Field
996
Table 24-27. Maximum au Size
996
Table 24-28. Erase Size Field
997
Table 24-29. Erase Timeout Field
997
Table 24-30. Erase Offset Field
998
Table 24-31. Lock Card Data Structure
1006
Figure 24-12. Read Wait Control by Stopping SDIO_CLK
1008
Figure 24-13. Read Wait Operation Using SDIO_DAT[2]
1009
Figure 24-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle
1009
Figure 24-15. Read Interrupt Cycle Timing
1010
Figure 24-16. Write Interrupt Cycle Timing
1011
Figure 24-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
1011
Figure 24-18. Multiple Block 4-Bit Write Interrupt Cycle Timing
1011
Figure 24-19. the Operation for Command Completion Disable Signal
1012
Table 24-32. Sdio_Respx Register at Different Response Type
1017
Figure 25-1. the EXMC Block Diagram
1028
Figure 25-2. EXMC Memory Banks
1029
Figure 25-3. Four Regions of Bank0 Address Mapping
1030
Figure 25-4. NAND/PC Card Address Mapping
1031
Figure 25-5. Diagram of Bank1 Common Space
1031
Table 25-1. nor Flash Interface Signals Description
1032
Table 25-2. PSRAM Non-Muxed Signal Description
1033
Table 25-3. EXMC Bank 0 Supports All Transactions
1033
Table 25-4. nor / PSRAM Controller Timing Parameters
1034
Table 25-5. Exmc_Timing Models
1035
Figure 25-6. Mode 1 Read Access
1036
Figure 25-7. Mode 1 Write Access
1036
Table 25-6. Mode 1 Related Registers Configuration
1036
Figure 25-8. Mode a Read Access
1037
Figure 25-9. Mode a Write Access
1038
Table 25-7. Mode a Related Registers Configuration
1038
Figure 25-10. Mode 2/B Read Access
1039
Figure 25-11. Mode 2 Write Access
1040
Figure 25-12. Mode B Write Access
1040
Table 25-8. Mode 2/B Related Registers Configuration
1040
Figure 25-13. Mode C Read Access
1041
Figure 25-14. Mode C Write Access
1042
Table 25-9. Mode C Related Registers Configuration
1042
Figure 25-15. Mode D Read Access
1043
Figure 25-16. Mode D Write Access
1044
Table 25-10. Mode D Related Registers Configuration
1044
Figure 25-17. Multiplex Mode Read Access
1045
Figure 25-18. Multiplex Mode Write Access
1045
Table 25-11. Multiplex Mode Related Registers Configuration
1046
Figure 25-19. Read Access Timing Diagram under Async-Wait Signal Assertion
1047
Figure 25-20. Write Access Timing Diagram under Async-Wait Signal Assertion
1047
Figure 25-21. Read Timing of Synchronous Multiplexed Burst Mode
1049
Table 25-12. Timing Configurations of Synchronous Multiplexed Read Mode
1049
Figure 25-22. Write Timing of Synchronous Multiplexed Burst Mode
1050
Table 25-13. Timing Configurations of Synchronous Multiplexed Write Mode
1051
Table 25-14. 8-Bit or 16-Bit NAND Interface Signal
1051
Table 25-15. 16-Bit PC Card Interface Signal
1052
Table 25-16. Bank1/2/3 of EXMC Support the Memory and Access Mode
1052
Figure 25-23. Access Timing of Common Memory Space of PC Card Controller
1053
Table 25-17. NAND Flash or PC Card Programmable Parameters
1053
Figure 25-24. Access to None "NCE Don't Care" NAND Flash
1054
Figure 26-1. CAN Module Block Diagram
1069
Figure 26-2. Transmission Register
1072
Figure 26-3. State of Transmit Mailbox
1072
Figure 26-4. Reception Register
1074
Figure 26-5. 32-Bit Filter
1075
Figure 26-6. 16-Bit Filter
1075
Figure 26-7. 32-Bit Mask Mode Filter
1076
Figure 26-8. 16-Bit Mask Mode Filter
1076
Figure 26-9. 32-Bit List Mode Filter
1076
Figure 26-10. 16-Bit List Mode Filter
1076
Table 26-1. 32-Bit Filter Number
1076
Table 26-2. Filtering Index
1077
Figure 26-11. the Bit Time
1080
Figure 26-12. Transmitter Delay Measurement
1082
Table 26-3. CAN Event / Interrupt Flags
1084
Figure 27-1. ENET Module Block Diagram
1110
Figure 27-2. MAC / Tagged MAC Frame Format
1111
Table 27-1. Ethernet Signals (MII Default)
1112
Table 27-2. Ethernet Signals (MII Remap)
1112
Table 27-3. Ethernet Signals (RMII Default)
1113
Table 27-4. Ethernet Signals (RMII Remap)
1113
Figure 27-3. Station Management Interface Signals
1114
Table 27-5. Clock Range
1115
Figure 27-4. Media Independent Interface Signals
1116
Table 27-6. Rx Interface Signal Encoding
1117
Figure 27-5. Reduced Media-Independent Interface Signals
1118
Table 27-7. Destination Address Filtering Table
1123
Table 27-8. Source Address Filtering Table
1123
Figure 27-6. Descriptor Ring and Chain Structure
1130
Figure 27-7. Transmit Descriptor in Normal Mode
1136
Figure 27-8. Transmit Descriptor in Enhanced Mode
1141
Figure 27-9. Receive Descriptor in Normal Mode
1145
Table 27-9. Error Status Decoding in Receive Descriptor0, Only Used for Normal Descriptor (DFM=0)
1148
Figure 27-10. Receive Descriptor in Enhanced Mode
1151
Figure 27-11. Wakeup Frame Filter Register
1157
Figure 27-12. System Time Update Using the Fine Correction Method
1159
Figure 27-13. MAC Interrupt Scheme
1164
Figure 27-14. Ethernet Interrupt Scheme
1165
Figure 27-15. Wakeup Frame Filter Register
1175
Table 27-10. Supported Time Stamp Snapshot with PTP Register Configuration
1194
Figure 28-1. USBD Block Diagram
1216
Table 28-1. USBD Signal Description
1217
Figure 28-2. an Example with Buffer Descriptor Table Usage (USBD_BADDR = 0)
1219
Table 28-2. Double-Buffering Buffer Flag Definition
1220
Table 28-3. Double Buffer Usage
1220
Table 28-4. Reception Status Encoding
1232
Table 28-5. Endpoint Type Encoding
1232
Table 28-6. Endpoint Kind Meaning
1232
Table 28-7. Transmission Status Encoding
1233
Figure 29-1. USBHS Block Diagram
1237
Table 29-1. USBHS Signal Description
1237
Table 29-2. USBHS Supported Speeds
1238
Figure 29-2. Connection Using Internal Embedded PHY with Host or Device Mode
1239
Figure 29-3. Connection Using Internal Embedded PHY with OTG Mode
1240
Figure 29-4. Connection Using External ULPI PHY
1240
Figure 29-5. State Transition Diagram of Host Port
1241
Figure 29-6. Host Mode FIFO Space in SRAM
1247
Figure 29-7. Host Mode FIFO Access Register Map
1247
Figure 29-8. Device Mode FIFO Space in SRAM
1248
Figure 29-9. Device Mode FIFO Access Register Map
1249
Table 29-3. USBHS Global Interrupt
1256
Table 30-1. List of Abbreviations Used in Register
1331
Table 30-2. List of Terms
1331
Table 31-1. Revision History
1333
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