Related Manuals for GigaDevice Semiconductor GD32W51 Series
Summary of Contents for GigaDevice Semiconductor GD32W51 Series
- Page 1 GigaDevice Semiconductor Inc. GD32W51x ® ® Cortex -M33 32-bit MCU User Manual Revision 1.0 ( Nov 2021 )
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Page 2: Table Of Contents
GD32W51x User Manual Table of Contents Table of Contents......................... 2 List of Figures ........................24 List of Tables ........................32 1. System and me mory architecture ................37 1.1. Arm Cortex-M33 processor..................37 1.2. System architecture ....................38 1.3. TrustZone overview ....................40 ®... - Page 3 GD32W51x User Manual 2.4.8. TrustZone security protection ...................77 2.4.9. Security protection ....................78 2.4.10. Write protection......................82 2.4.11. Flash privileged and unprivileged mode ..............82 2.4.12. FLASH interrupts ....................82 2.5. Register definition....................84 2.5.1. Unlock key register (FMC_KEY) ................84 2.5.2. Option byte unlock key register (FMC_OBKEY) ............84 2.5.3.
- Page 4 GD32W51x User Manual Register definition....................108 3.5. 3.5.1. Control and status register (EFUSE_CS) ..............108 3.5.2. Address register (EFUSE_ADDR)................109 3.5.3. Control register (EFUSE_CTL) ................110 3.5.4. Trustzone control register(EFUSE_TZCTL) .............. 111 3.5.5. Flash protection control register (EFUSE_FP_CTL) ........... 112 3.5.6.
- Page 5 GD32W51x User Manual Function overview....................132 5.3. 5.3.1. Battery backup domain ..................132 5.3.2. VDD / VDDA power domain ................... 133 5.3.3. 1.2V power domain ....................135 5.3.4. Power saving modes .................... 136 5.3.5. Security description ....................141 5.4. Register definition....................143 5.4.1.
- Page 6 GD32W51x User Manual 6.5.17. AHB3 sleep mode enable register (RCU_AHB3SPEN)..........190 6.5.18. APB1 sleep mode enable register (RCU_APB1SPEN) ..........190 6.5.19. APB2 sleep mode enable register (RCU_APB2SPEN) ..........192 6.5.20. Backup domain control register (RCU_BDCTL)............194 6.5.21. Reset source/clock register (RCU_RSTSCK)............195 6.5.22.
- Page 7 GD32W51x User Manual 8.2. Characteristics ....................... 230 8.3. Function overview....................230 8.3.1. GPIO pin configuration ..................232 8.3.2. External interrupt/event lines .................. 233 8.3.3. Alternate functions (AF)..................233 8.3.4. Additional functions ....................233 8.3.5. Input configuration....................233 8.3.6. Output configuration ..................... 233 8.3.7.
- Page 8 GD32W51x User Manual 9.4.4. TZSPC secure access mode configuration register 2 (TZPCU_TZSPC_SAM_CFG2) ..263 9.4.5. TZSPC privilege access mode configuration register 0 (TZPCU_TZSPC_PAM_CFG0) ... 264 9.4.6. TZSPC privilege access mode configuration register 1 (TZPCU_TZSPC_PAM_CFG1) ... 266 9.4.7. TZSPC privilege access mode configuration register 2 (TZPCU_TZSPC_PAM_CFG2) ... 269 9.4.8.
- Page 9 GD32W51x User Manual 10.2. Characteristics ....................306 10.3. Function overview ....................307 10.4. Register definition ....................308 10.4.1. Data register (CRC_DATA) ..................308 10.4.2. Free data register (CRC_FDATA) ................308 10.4.3. Control register (CRC_CTL)................... 309 True random number generator (TRNG) ............310 11.1.
- Page 10 GD32W51x User Manual 12.6.3. Interrupt flag clear register 0 (DMA_INTC0).............. 339 12.6.4. Interrupt flag clear register 1 (DMA_INTC1).............. 339 12.6.5. Channel x control register (DMA_CHxCTL) .............. 340 12.6.6. Channel x counter register (DMA_CHxCNT)............. 344 12.6.7. Channel x peripheral base address register (DMA_CHxPADDR) ......... 344 12.6.8.
- Page 11 GD32W51x User Manual 14.4.9. External trigger ....................367 14.4.10. DMA request ....................... 369 14.4.11. Overflow detection ....................369 14.4.12. Temperature sensor, internal reference voltage VREFINT and external battery voltage VBAT 14.4.13. On-chip hardware oversampling ................370 14.4.14. ADC interrupts ..................... 372 14.5.
- Page 12 GD32W51x User Manual 16.3.3. Shadow registers introduction ................400 16.3.4. Configurable and field maskable alarm ..............400 16.3.5. Configurable periodic auto-wakeup counter .............. 401 16.3.6. RTC initialization and configuration ................. 401 16.3.7. Calendar reading ....................403 16.3.8. Resetting the RTC....................404 16.3.9.
- Page 13 GD32W51x User Manual 16.4.24. Secure masked interrupt status register (RTC_SMI_STAT) ......... 442 16.4.25. Status flag clear register (RTC_STATC) ..............443 16.4.26. Backup registers (RTC_BKPx) (x=0..19) ..............444 Timer (TIMERx) ....................... 446 17.1. Advanced timer (TIMERx, x=0) ................447 17.1.1. Overview ......................447 17.1.2.
- Page 14 GD32W51x User Manual 18.3.9. Synchronous mode ....................600 18.3.10. IrDA SIR ENDEC mode..................601 18.3.11. Half-duplex communication mode ................602 18.3.12. Smartcard (ISO7816-3) mode ................602 18.3.13. Auto baudrate detection ..................604 18.3.14. ModBus communication ..................605 18.3.15. Receive FIFO ...................... 605 18.3.16.
- Page 15 GD32W51x User Manual 19.4. Register definition ....................655 19.4.1. Control register 0 (I2C_CTL0) ................655 19.4.2. Control register 1 (I2C_CTL1) ................657 19.4.3. Slave address register 0 (I2C_SADDR0) ..............659 19.4.4. Slave address register 1 (I2C_SADDR1) ..............660 19.4.5. Timing register (I2C_TIMING) ................661 19.4.6.
- Page 16 GD32W51x User Manual 20.10.2. Error flags ......................698 20.11. Register definition ....................700 20.11.1. Control register 0 (SPI_CTL0) ................700 20.11.2. Control register 1 (SPI_CTL1) ................702 20.11.3. Status register (SPI_STAT) ..................703 20.11.4. Data register (SPI_DATA) ..................704 20.11.5. CRC polynomial register (SPI_CRCPOLY) ............... 705 20.11.6.
- Page 17 GD32W51x User Manual Operating modes ....................726 22.4. 22.4.1. Indirect mode ...................... 726 22.4.2. Status polling mode ....................727 22.4.3. Memory map mode ....................727 22.4.4. FMC mode ......................728 QSPI configuration ..................... 729 22.5. 22.5.1. Flash configuration ....................729 22.5.2.
- Page 18 GD32W51x User Manual 22.11.28.Complete bytes counter register (QSPI_BYTE_CNT)..........756 22.11.29.Privilege configuration register (QSPI_PRIVCFG) ............. 756 Secure digital input/output interface (SDIO) ............. 758 23.1. Introduction......................758 23.2. Main features ...................... 758 23.3. SDIO bus topology....................758 23.4. SDIO functional description ................761 23.4.1.
- Page 19 GD32W51x User Manual 23.8.12. Interrupt clear register (SDIO_INTC) ............... 816 23.8.13. Interrupt enable register (SDIO_INTEN) ..............818 23.8.14. FIFO counter register (SDIO_FIFOCNT) ..............819 23.8.15. FIFO data register (SDIO_FIFO)................820 Universal serial bus full-speed interface (USBFS) ........... 821 24.1. Overview ......................821 Characteristics ....................
- Page 20 GD32W51x User Manual 25.7.4. Interrupt enable register (DCI_INTEN) ..............902 25.7.5. Interrupt flag register (DCI_INTF)................903 25.7.6. Interrupt flag clear register (DCI_INTC)..............904 25.7.7. Synchronization codes register (DCI_SC) ..............904 25.7.8. Synchronization codes unmask register (DCI_SCUMSK) ........... 905 25.7.9. Cropping window start position register (DCI_CWSPOS)..........905 25.7.10.
- Page 21 GD32W51x User Manual Cryptographic acceleration processor............... 927 27.4. 27.4.1. DES/TDES cryptographic acceleration processor ............928 27.4.2. AES cryptographic acceleration processor ............... 932 Operating modes ....................939 27.5. 27.6. CAU DMA interface ..................... 940 27.7. CAU interrupts ....................940 27.8. CAU suspended mode ..................941 Register definition ....................
- Page 22 GD32W51x User Manual 28.7.4. HAU data output register (HAU_DO0..7) ..............964 28.7.5. HAU interrupt enable register (HAU_INTEN) ............966 28.7.6. HAU status and flag register (HAU_STAT) ............... 966 28.7.7. Context switch register x (HAU_CTXSx) (x = 0...53) ..........967 Public Ke y Cryptographic Acceleration Unit (PKCAU) ........968 29.1.
- Page 23 GD32W51x User Manual 30.4.2. HPDF filter y registers (y=0, 1) ................1022 Infrared ray port (IFRP) ..................1038 31.1. Overview ......................1038 31.2. Characteristics ....................1038 31.3. Function overview .................... 1038 Wi-Fi ........................1040 32.1. Overview ......................1040 32.2. Characteristics ....................1040 32.2.1.
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Page 24: List Of Figures
GD32W51x User Manual List of Figures ® -M33 processor ..............38 Figure 1-1. The structure of the Cortex Figure 1-2. GD32W51x system architecture ..................... 40 Figure 1-3. Example of memory map security attribution vs SAU configuration regions ... 41 Figure 2-1. FMC bus in GD32W51x ....................... 67 Figure 2-2. - Page 25 GD32W51x User Manual Figure 14-7. Auto-insertion, CTN = 1 ......................365 Figure 14-8. Triggered insertion ........................366 Figure 14-9. Data alignment of 12-bit resolution ..................367 Figure 14-10. 20-bit to 16-bit re sult truncation ..................371 Figure 14-11. A numerical example with 5-bit shifting and rounding ..........371 Figure 15-1.
- Page 26 GD32W51x User Manual Figure 17-34. General Level 0 timer block diagram................506 Figure 17-35. Normal mode, internal clock divided by 1..............507 Figure 17-36. Counter timing diagram with prescaler division change from 1 to 2 ....508 Figure 17-37. Timing chart of up counting mode, PSC=0/1 .............509 Figure 17-38.
- Page 27 GD32W51x User Manual Figure 18-8. Hardware flow control ......................598 Figure 18-9. Break frame occurs during idle state ................599 Figure 18-10. Break frame occurs during a frame ................600 Figure 18-11. Example of USART in synchronous mode ..............600 Figure 18-12. 8-bit format USART synchronous waveform (CLEN=1) ........601 Figure 18-13.
- Page 28 GD32W51x User Manual Figure 20-10. Timing diagram of TI slave mode..................679 Figure 20-11. Timing diagram of quad write operation in Quad-SPI mode.......680 Figure 20-12. Timing diagram of quad read operation in Quad-SPI mode........681 Figure 20-13. Block diagram of I2S......................684 Figure 20-14. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ..686 Figure 20-15.
- Page 29 GD32W51x User Manual Figure 20-44. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ..........................692 Figure 20-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ..........................692 Figure 20-46. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ..........................692 Figure 20-47.
- Page 30 GD32W51x User Manual Figure 23-19. The operation for command completion disable signal ........806 Figure 24-1. USBFS block diagram......................822 Figure 24-2. Connection with host or device mode ................823 Figure 24-3. Connection with OTG mode....................824 Figure 24-4. State transition diagram of host port................824 Figure 24-5.
- Page 31 GD32W51x User Manual Figure 29-13. Mutual mapping between Montgomery domain and natural domain....978 Figure 29-14. Montgomery multiplication ....................979 Figure 29-15. Modular exponentiation of normal mode ..............979 Figure 29-16. Modular exponentiation of fast mode ................980 Figure 29-17. Modular inversion ........................980 Figure 29-18. RSA CRT exponentiation ....................981 Figure 29-19.
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Page 32: List Of Tables
GD32W51x User Manual List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix ......39 Table 1-2. Default system security state ....................41 Table 1-3. Securable peripherals by TZSPC ..................... 42 Table 1-4. TrustZone-aware peripherals..................... 43 Table 1-5. Memory map based on IDAU mapping of GD32W51x devices ........44 Table 1-6. - Page 33 GD32W51x User Manual Table 7-2. Interrupt vector table ........................217 Table 7-3. EXTI source .............................221 Table 7-4. Register protection overview ....................223 Table 8-1. GPIO configuration table ......................231 Table 8-2. GPIO secure state .........................236 Table 8-3. GPIOx_CTL reset value ......................237 Table 8-4. GPIOx_ OSPD reset value ......................241 Table 8-5.
- Page 34 GD32W51x User Manual Table 18-1. Description of USART important pins ................591 Table 18-2. Configuration of stop bits .......................592 Table 18-3. USART interrupt requests.......................606 Table 19-1. Definition of I2C-bus terminology (refer to the I2C specification of Phili ps semiconductors)............................629 Table 19-2. Data setup time and data hold time ..................635 Table 19-3.
- Page 35 GD32W51x User Manual Table 23-20. Response R5 for SD I/O ......................782 Table 23-21. Response R6 ..........................783 Table 23-22. Response R7 ..........................783 Table 23-23. Card status ..........................785 Table 23-24. SD status ............................788 Table 23-25. Performance move field ......................790 Table 23-26. AU_SIZE field..........................790 Table 23-27.
- Page 36 GD32W51x User Manual Table 30-6. Relationship between the maximum output resolution and IOR, SFOR, SFO of the integrator............................1010 Table 30-7. Features of threshold monitor working mode ............1011 Table 30-8. Maximum output rate ......................1014 Table 30-9. HPDF interrupt event ......................1015 Table 33-1.
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Page 37: System And Memory Architecture
GD32W51x User Manual System and memory architecture The devices of GD32W51x series are highly integrated 2.4GHz Wi-Fi System-on-Chip (SoC) ® ® 32-bit general-purpose microcontrollers based on the Arm Cortex -M33 processor with ® ® Trustzone. The Arm Cortex -M33 processor includes two AHB buses known as Code and ®... -
Page 38: System Architecture
GD32W51x User Manual ® Figure 1-1. The structure of the Cortex -M33 processor Cortex-M33 processor Cortex-M33 core Nested Interrupts Vectored Floating Point Interrupt Unit(FPU) Controller (NVIC) DSP Extension Data Breakpoint Memory Watchpoint Unit Protection And Trace (BPU) Unit(MPU) (DWT) Serial-Wire Or JTAG Instrumentation Trace Port... -
Page 39: Table 1-1. The Interconnection Relationship Of The Ahb Interconnect Matrix
GD32W51x User Manual Table 1-1. The interconnection relationship of the AHB interconnect matrix S-CBUS F-CBUS SBUS DMA0M DMA1M Wi-Fi DMA0P DMA1P SRAM0 AHB1 AHB2 AHB3 SRAM1 SRAM2 SRAM3 APB1 APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, including S-CBUS, F-CBUS, SBUS, DMA0M, DMA0P DMA1M, DMA1P and Wi-Fi. -
Page 40: Trustzone ® Overview
GD32W51x User Manual These are interconnected using a multilayer AHB bus architecture as shown in Figure 1-2. GD32W51x system architecture. Figure 1-2. GD32W51x system architecture POR/ PDR SW/JTAG TPIU Flash Flash Memory EFUSE Memory Slave Controller Master Icache Arm Cortex-M33 Cbus Slave : 180MHz... -
Page 41: Figure 1-3. Example Of Memory Map Security Attribution Vs Sau Configuration Regions
GD32W51x User Manual secure callable (NSC), the IDAU memory map partition is not configurable and fixed by hardware implementation (refer toTable 1-5. Memory map based on IDAU mapping of GD32W51x devices). However the SAU can change security attribution of the memory by software. -
Page 42: Peripheral Classification
GD32W51x User Manual All SRAMs are secure after reset. TZBMPC (TrustZone block-based SRAMs memory protection controller) is secure. External memories QSPI_FLASH and SQPI_PSRA M banks are secure after reset. Securable peripherals are non-secure after reset. TrustZone-aw are peripherals are non-secure after reset (except GPIOA, GPIOB and GPIOC). -
Page 43: Memory Map
GD32W51x User Manual TIMER2 TIMER3 TIMER4 TIMER5 WWDGT FWDGT SPI1/I2S1 USART0 USART1 I2C0 I2C1 I2S1_add TIMER0 SPI0 USART2 APB2 TIMER15 TIMER16 Wi-Fi_RF SDIO HPDF Table 1-4. TrustZone-aware peripherals Peripheral DMA0 DMA1 AHB1 GPIOA GPIOB GPIOC TZSPC AHB3 QSPI_FLASH APB1 EXTI APB2 SYSCFG Memory map... -
Page 44: Table 1-5. Memory Map Based On Idau Mapping Of Gd32W51X Devices
GD32W51x User Manual registers and I/O ports are organized within the same linear 4-Gbyte address space which is ® the maximum address range of the Cortex -M33 since the bus address width is 32-bit. ® Additionally, a pre-defined memory map is provided by the Cortex -M33 processor to reduce the software complexity of repeated implementation of different device vendors. - Page 45 GD32W51x User Manual Pre-defined Secure Non-Secure Peripherals boundary address Regions boundary address 0x4003 0000 - 0x4003 2FFF Wi-Fi 0x5003 0000 - 0x5003 2FFF 0x4002 BC00 - 0x4002 FFFF Reserv ed 0x5002 BC00 - 0x5002 FFFF 0x4002 B000 - 0x4002 BBFF Reserv ed 0x5002 B000 - 0x5002 BBFF 0x4002 A000 - 0x4002 AFFF...
- Page 46 GD32W51x User Manual Pre-defined Secure Non-Secure Peripherals boundary address Regions boundary address 0x4001 4400 - 0x4001 47FF Reserv ed 0x5001 4400 - 0x5001 47FF 0x4001 4000 - 0x4001 43FF Reserv ed 0x5001 4000 - 0x5001 43FF 0x4001 3C00 - 0x4001 3FFF EXTI 0x5001 3C00 - 0x5001 3FFF 0x4001 3800 - 0x4001 3BFF...
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Page 47: On-Chip Sram Memory
GD32W51x User Manual Pre-defined Secure Non-Secure Peripherals boundary address Regions boundary address 0x4000 0400 - 0x4000 07FF TIMER2 0x5000 0400 - 0x5000 07FF 0x4000 0000 - 0x4000 03FF TIMER1 0x5000 0000 - 0x5000 03FF Reserv ed 0x3007 0000 - 0x3FFF FFFF 0x2007 0000 - 0x2FFF FFFF SRAM3 (192KB) 0x3004 0000 - 0x2006 FFFF... -
Page 48: Sram1 Security Protection
GD32W51x User Manual mechanism, which means by writing ‘1’ on a bit it will setup the write protection for that page of SRAM and it can be removed/cleared by a system reset only. SRAM1 security protection 1.4.3. The SRAM1 is protected with the security protection (SPC). SRAM1 Erase 1.4.4. -
Page 49: Table 1-8. Boot Address Modes When Trustzone Is Disabled (Tzen=0)
GD32W51x User Manual BOOT1 PA14 SWBOOT1 EFBOOT1 BOOT1 Refer to Table 1-8. Boot address modes when TrustZone is disabled (TZEN=0) Table 1-9. Boot modes when TrustZone is enabled (TZEN=1) for boot address when TrustZone is disabled and enabled respectively. When the EFBOOTLK bit in the EFUSE_CTL register is set, the boot memory address selected according to boot1 and boot0. - Page 50 GD32W51x User Manual GSSAC Boot MD == EFBOOTL K BOOT0 BOOT1 EFSB Boot area address 8’hc SPI Flash w hen cfg_qspi 0x0C000 is 0 QSPI Flash w hen cfg_qspi is 1 0X0FF84 secure boot 0x0FF80 GSSA 0x0FF80 GSSA Note: (1) When the GSSACMD bitfield is 0x0C, it means 1, otherwise it means 0. The BOOTx (x=0/1) value (either coming from the pin or the EFBOOTx bit) is latched upon reset release.
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Page 51: System Configuration Controller (Syscfg)
GD32W51x User Manual System configuration controller (SYSCFG) 1.6. SYSCFG main features 1.6.1. Setting SRMA1 write protection and software erase Configuring FPU interrupts Configuring TrustZone security register access SYSCFG TrustZone security and privilege 1.6.2. When the TrustZone security is activated, the SYSCFG is able to secure registers from being modified by non-secure accesses. -
Page 52: Syscfg Registers
GD32W51x User Manual SYSCFG registers 1.6.3. SYSCFG secure access base address: 0x5001 3800 SYSCFG son-secure access base address: 0x4001 3800 Configuration register 0 (SYSCFG_CFG0) Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 and BOOT1 pins) This register has to be accessed by word (32-bit) Reserved... - Page 53 GD32W51x User Manual 15:12 EXTI3_SS[3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin 0010: PC3 pin Other configurations are reserved. 11:8 EXTI2_SS[3:0] EXTI 2 sources selection 0000: PA2 pin 0001: PB2 pin 0010: PC2 pin Other configurations are reserved. EXTI1_SS[3:0] EXTI 1 sources selection 0000: PA1 pin...
- Page 54 GD32W51x User Manual 11:8 EXTI6_SS[3:0] EXTI 6 sources selection 0000: PA6 pin 0001: PB6 pin 0010: PC6 pin Other configurations are reserved. EXTI5_SS[3:0] EXTI 5 sources selection 0000: PA5 pin 0001: PB5 pin 0010: PC5 pin Other configurations are reserved. EXTI4_SS[3:0] EXTI 4 sources selection 0000: PA4 pin...
- Page 55 GD32W51x User Manual 0001: PB9 pin Other configurations are reserved. EXTI8_SS[3:0] EXTI 8 sources selection 0000: PA8 pin 0001: PB8 pin 0010: PC8 pin Other configurations are reserved. EXTI sources selection register 3 (SYSCFG_EXTISS3) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved EXTI15_SS [3:0]...
- Page 56 GD32W51x User Manual I/O compensation control register (SYSCFG_CPSCTL) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CPS_RDY Reserved CPS_EN Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. CPS_RDY Compensation cell ready flag 0: I/O compensation cell not ready 1: I/O compensation cell ready...
- Page 57 GD32W51x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. FPUSE FPU security 0: SYSCFG_FPU INTEN register can be w ritten by secure and non-secure access 1: SYSCFG_FPU INTEN register can be w ritten by secure access only. SRAM1SE SRAM1 security 0: SYSCFG_SKEY, SYSCFG_SCS and SYSCFG_SWPx registers can be w ritten...
- Page 58 GD32W51x User Manual 31:6 Reserved Must be kept at reset value. IXIE Inexact interrupt enable bit 0: Inexact interrupt disable. 1: Inexact interrupt enable. IDIE Input denormal interrupt enable bit 0: Input denormal interrupt disable. 1: Input denormal interrupt enable. OVFIE Overflow interrupt enable bit 0: Overflow interrupt disable.
- Page 59 GD32W51x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. LOCKNSMPU Non-secure MPU registers lock This bit is set by softw are and cleared only by a system reset. When is set, it disables w rite access to non-secure MPU_CTRL_NS, MPU_RNR_NS MPU_RBA R_NS registers.
- Page 60 GD32W51x User Manual 1: SAU registers w rite is disabled SMPULK Secure MPU registers lock. This bit is set by softw are and cleared only by a system reset. When is set, it disables w rite access to secure MPU_CTRL, MPU_RNR and MPU_ RBA R registers.
- Page 61 GD32W51x User Manual LVDEN and LVDT[2:0] in the PMU_CTL0 register. 0: LVD interrupt disconnected from TIMER0/15/16 Break input. LVDEN and LVDT[2:0] bits can be programmed by the application 1: LVD interrupt connected to TIMER0/15/16 Break input, LVDEN and LVDT[2:0] bits are read only Reserved Must be kept at reset value.
- Page 62 GD32W51x User Manual cleared at the end of the SRAM1 erase operation Note: This bit is w rite-protected: setting this bit is possible only after the correct key sequence is w ritten in the SYSCFG_SKEY register. SYSCFG SRAM 1 key register (SYSCFG_SKEY) Address offset: 0x5C Reset value: 0x0000 0000 When the system is secure (TZEN =1), this register can be protected against non-secure...
- Page 63 GD32W51x User Manual This register can be read and written by privileged and unprivileged access. This register has to be accessed by word(32-bit) P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP P15WP P14WP P13WP P12WP...
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Page 64: Device Electronic Signature
GD32W51x User Manual SYSCFG GSSA command register (SYSCFG_GSSACMD) Address offset: 0x6C Reset value: 0x0000 0000, reset by power reset only, system reset has no affected. When the system is secure (TZEN =1), this register can be read and written only when the APB access is secure. -
Page 65: Unique Device Id (96 Bits)
GD32W51x User Manual 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes. Example: 0x0008 indicates 8 Kbytes. 15:0 FLASH_DENSITY Flash memory density [15:0] The value indicates the Flash memory density of the device in Kbytes. Example: 0x0020 indicates 32 Kbytes. - Page 66 GD32W51x User Manual Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID...
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Page 67: Flash Memory Controller (Fmc)
GD32W51x User Manual Flash memory controller (FMC) 2.1. Overview For GD32W51x, the flash memory architecture is divided into FMC mode and QSPI mode. For FMC mode, there is on-chip (SIP, system in package) flash. For QSPI mode, there is EX T flash. -
Page 68: Function Overview
GD32W51x User Manual ICACHE CBUS FMC mode:0x08000000/ BUSMATRIX 0x0C000000-SIP QSPI XIP interface（SBUS） QSPI REG FMC REG QSPI mode:0x08000000/ 0x90000000 interface interface 0x0C000000-EXT QSPI Register Register RTDEC Control Control Flash interface ADDR ADDR DATA DATA EXT Flash SIP Flash 2.4. Function overview Flash memory architecture 2.4.1. -
Page 69: Read Operations
GD32W51x User Manual Block Nam e Address range size(bytes) 0x081F F000 - 0x081F FFFF Page 511 0x0C1F F000 - 0x0C1F FFFF normal 0x0BF4 0000 - 0x0BF4 5FFF 24KB secure boot 0x0FF8 4000 - 0x0FF8 7FFF 16KB Bootloader secure region2 0x0FF4 E000 - 0x0FF7 FFFF 200KB GSSA 0x0FF8 0000 - 0x0FF8 3FFF... -
Page 70: Unlock The Fmc_Ctl/Fmc_Secctl Register
GD32W51x User Manual In QSPI mode, fetch data use EXT Flash. Start address is 0x08000000 (non-secure) / 0x0C000000 (secure). Size is 32MB. It can support RTDEC function. NO- RTDEC function In FMC mode, for SIP Flash, up to four areas can be configured without RTDEC function by FMC_NODECx (x=0,1,2,3), even if AESEN bit in EFUSE_USER_CTL register is set. -
Page 71: Page Erase
GD32W51x User Manual Note: (1) As long as the wrong key is written to FMC_CTL/FMC_SECCTL, a bus error will be generated, regardless of whether FMC_PRIV bit in FMC_PRIVCFG is set or not. (2) Write wrong key to OBKEY does not generate a bus error. Page erase 2.4.4. -
Page 72: Mass Erase
GD32W51x User Manual Figure 2-2. Process of page erase operation Start Unlock the Is the LK/SECLK FMC_CTL/FMC_SEC bit is 0 Is the BUSY/SECBUSY bit is 0 Set the PER/SECPER bit, Write FMC_ADDR/FMC_SE CADD Send the command to FMC by set START/SECSTART Is the BUSY/SECBUSY... -
Page 73: Figure 2-3. Process Of Mass Erase Operation
GD32W51x User Manual BUSY/SECBUSY bit in the FMC_STAT/FMC_SECSTAT register. Read and verify the Flash memory using a DBUS access if required. When the operation is executed successfully, the ENDF/SECENDF bit in the FMC_STAT/FMC_SECSTAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL/FMC_SECCTL register is set. -
Page 74: Main Flash Programming
GD32W51x User Manual Main flash programming 2.4.6. The FMC provides a 32-bit word programming function by DBUS which is used to modify the main Flash memory contents. Operate secure Flash or non-secure Flash using secure or non-secure registers. The following steps show the register access sequence of the programming operation. ... -
Page 75: Option Bytes
GD32W51x User Manual Figure 2-4. Process of word program operation Start Unlock the Is the LK/SECLK FMC_CTL/FMC_SECC bit is 0 Is the BUSY/ SECBUSY bit is 0 Set the PG/SECPG bit Perform word write Is the BUSY/ SECBUSY bit is 0 Finish Note: 1. - Page 76 GD32W51x User Manual Nam e Register m ap [7:0]：SPC[7:0] Option byte user register [15:0]：USER[15:0] (FM C_OBUSER) Secure mark configuration register 0 [25:16]：SECM0_EPAGE[9:0] (FM C_SECM CFG0) [15:0]：SECM0_SPA GE[9:0] Secure dedicated mark protection 31：DMP0EN register 0 (FM C_DM P0) [25:16]：DMP0_EPAGE[9:0] Option byte write protection area [25:16]：WRP0_EPA GE[9:0] register 0 (FM C_OBWRP0) [15:0]：WRP0_SPAGE[9:0]...
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Page 77: Trustzone Security Protection
GD32W51x User Manual eturns to unprotected, and Trustzone is disabled. (from protection level 1 to no protec tion or from protection level 0.5 to no protection). Otherwise, the OBERR bit is set. 2. SECMCFGx_SPAGE[6:0] (x=0,1), SECMCFGx_EPAGE[6:0] (x=0,1), DMPx_EPAGE[6: 0] (x=0,1), DMPxEN (x=0,1) bits It can only be modified when DMPx_ACCFG (x=0,1) bit is cleared. -
Page 78: Security Protection
GD32W51x User Manual area. When DMPx_ACCFG (x=0,1) bit is set, the code in the DMP area can only be executed once and does not support read and write operations of data and read operation of instructions until the next system reset. The DMPx_ACCFG (x=0,1) bit can only be cleared by a system reset. -
Page 79: Table 2-4. Flash Secure Operation Under Different Protection Levels When Trustzone Is Active (Tzen=1)
GD32W51x User Manual Protection level 1 If there are option bytes, when TZEN = 0 and SPC[7:0] bits in FMC_OBR is set to to any value except 0xAA, after the system is reset, the Flash memory will be in protection level 1 state. -
Page 80: Table 2-5. Flash Non-Secure Operation Under Different Protection Levels When Trustzone Is Active (Tzen=1)
GD32W51x User Manual Access type Fetch Read Write Page erase Non-secure w rite invalid, SECWPERR flag SPC 1 page or secure Bus error page Table 2-5. Flash non-secure operation under different protection levels when TrustZone is active (TZEN=1) Access type Fetch Read Write... -
Page 81: Table 2-7. Flash Mass Erase Operation Under Different Protection Levels When Trustzone Is
GD32W51x User Manual Table 2-7. Flash mass erase operation under different protection levels when TrustZone is active (TZEN=1) SPC 0.5, SPC 1 SPC 1 Secure Flash Mix non-secure Access type DMP area Non-secure Non-secure page page and (DMPxEN=1 and page or secure page Others Secure page... -
Page 82: Write Protection
GD32W51x User Manual When the SPC[7:0] is programmed to the value 0x55 to move from level 1 to level 0.5, a partial mass erase of Flash main memory is performed. Only non-secure mark areas are erased. The backup registers and all SRAMs are also erased. Note: Only when there are option bytes, security protection level can be modified. -
Page 83: Table 2-9. Flash Interrupt Requests (Secure)
GD32W51x User Manual Table 2-9. Flash interrupt requests (secure) Interrupt Flag Description Clear m ethod enable bit SECENDF end of operation SECENDIE SECWPERR erase/program on protected pages Write 1 to corresponding bit an invalid secure DMP area is in FMC_SECSTAT register SECERRIE SECERR defined... -
Page 84: Register Definition
GD32W51x User Manual 2.5. Register definition FMC secure base address: 0x5002 2000 FMC non-secure base address: 0x4002 2000 Unlock key register (FMC_KEY) 2.5.1. Address offset: 0x04 Reset value: 0x0000 0000 This register is non-secure. Protected against non-provileged access when FMC_PRIV = 1. This register has to be accessed by word (32-bit). -
Page 85: Status Register (Fmc_Stat)
GD32W51x User Manual Status register (FMC_STAT) 2.5.3. Address offset: 0x0C Reset value: 0x0000 0000 This register is non-secure. Protected against non-provileged access when FMC_PRIV=1. This register has to be accessed by word (32-bit). Reserved Reserved ENDF WPERR OBERR Reserved BUSY rc_w1 rc_w1 rc_w1... - Page 86 GD32W51x User Manual FMC_SECCTL are reset. Otherwise, the write access is stalled till BUSY bit in FMC_CTL and SECBUSY bit in FMC_SECCTL are reset. This register has to be accessed by word (32-bit). Reserved OBRLD OBSTART Reserved ENDIE Reserved ERRIE OBWEN Reserved START Reserved...
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Page 87: Address Register (Fmc_Addr)
GD32W51x User Manual register. This bit can be set by softw are. START Send erase command to FMC This bit is set by softw are to send erase command to FMC. This bit is cleared by hardw are w hen the BUSY bit is cleared. Reserved Must be kept at reset value. -
Page 88: Option Byte Status Register (Fmc_Obstat)
GD32W51x User Manual Option byte status register (FMC_OBSTAT) 2.5.6. Address offset: 0x1C Reset value: 0x0XXX XXXX. This register is non-secure. Protected against non-provileged access when FMC_PRIV = 1. This register has to be accessed by word (32-bit). Reserved TZEN_ST Reserved FMCOB NQSPI SPC_P5... -
Page 89: Secure Status Register (Fmc_Secstat)
GD32W51x User Manual This register is secure. It can be read and written only by secure access. A non-secure read/write access is RAZ/WI. This register can be protected against non-privileged access when FMC_PRIV = 1. This register has to be accessed by word (32-bit). SECKEY[31:16] SECKEY[15:0] Bits... -
Page 90: Secure Control Register (Fmc_Secctl)
GD32W51x User Manual The softw are can clear it by w riting 1. SECERR Secure error flag (If there are no option bytes) If an invalid secure DMP area is defined (DMPx_EPAGE> SECMx_EPAGE), this bit is set and the FMC_DMPx (x=0,1) modification is discarded. The softw are can clear it by w riting 1. -
Page 91: Secure Address Register (Fmc_Secaddr)
GD32W51x User Manual 1: error interrupt enable Reserved Must be kept at reset value. SECLK FMC_SECCTL lock bit This bit is cleared by hardw are w hen right sequence w ritten to FMC_SECK EY register. This bit can be set by softw are. SECSTART Send erase command to FMC bit This bit is set by softw are to send erase command to FMC. -
Page 92: Option Byte Register (Fmc_Obr)
GD32W51x User Manual Bits Fields Descriptions 31:0 SECADDR[31:0] Flash erase/program command address bits These bits are configured by softw are. ADDR bits are the address of Flash erase/program command. Option byte register (FMC_OBR) 2.5.11. Address offset: 0x40 Reset value: 0xXXXX XXXX (Register bits 0 to 31 are loaded with values from Flash memory when OBRLD is set or system reset. -
Page 93: Option Byte User Register (Fmc_Obuser)
GD32W51x User Manual EFUSE_FP_CTL register. Option byte user register (FMC_OBUSER) 2.5.12. Address offset: 0x44 Reset value: 0xXXXX XXXX (Register bits 0 to 31 are loaded with values from Flash memory when OBRLD is set or system reset.) This register can only be written if OBWEN bit is set. This register is non-secure. It can be read and written by both secure and non-secure access. -
Page 94: Secure Dedicated Mark Protection Register 0 (Fmc_Dmp0)
GD32W51x User Manual Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:16 SECM0_EPAGE[9:0] End page of secure mark area 0. If DMP0_A CCFG is 1, this bits cannot be modified. If SECM0_EPAGE < DMP0_EPAGE, SECERR bit w ill be set and discard this w rite. 15:10 Reserved Must be kept at reset value. -
Page 95: Secure Mark Configuration Register 1 (Fmc_Secmcfg1)
GD32W51x User Manual when OBRLD is set or system reset.) This register can only be written if OBWEN bit is set. This register is non-secure. It can be read and written by both secure and non-secure access. This register can be protected against non-privileged access when FMC_PRIV=1. -
Page 96: Secure Dedicated Mark Protection Register 1 (Fmc_Dmp1)
GD32W51x User Manual 25:16 SECM1_EPAGE[9:0] End page of secure mark area 1. If DMP1_A CCFG is 1, this bits cannot be modified. If SECM1_EPAGE < DMP1_EPAGE, SECERR bit w ill be set and discard this w rite. 15:10 Reserved Must be kept at reset value. SECM1_SPAGE[9:0] Start page of secure mark area 1. -
Page 97: Secure Mark Configuration Register 2(Fmc_Secmcfg2)
GD32W51x User Manual This register has to be accessed by word (32-bit). Reserved WRP1_EPAGE[9:0] Reserved WRP1_SPAGE[9:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:16 WRP1_EPAGE[9:0] End page of w rite protection area 1 15:10 Reserved Must be kept at reset value. WRP1_SPAGE[9:0] Start page of w rite protection area 1 Secure mark configuration register 2(FMC_SECMCFG2) -
Page 98: Secure Mark Configuration Register 3 (Fmc_Secmcfg3)
GD32W51x User Manual Secure mark configuration register 3 (FMC_SECMCFG3) 2.5.20. Address offset: 0x64 Reset value: 0x0000 03FF. This register can not be written if OBWEN bit is set. This register is secure. It can be read and written only by secure access. A non-secure read/write access is RAZ/WI. -
Page 99: Offset Region Register (Fmc_Ofrg)
GD32W51x User Manual Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:16 NODECx_EPAGE[9: End page of NODEC region x (x=0,1,2,3). 15:10 Reserved Must be kept at reset value. NODECx_SPAGE[9: Start page of NODEC region x (x=0,1,2,3). Offset region register (FMC_OFRG) 2.5.22. -
Page 100: Secure Dedicated Mark Protection Control Register (Fmc_Dmpctl)
GD32W51x User Manual This register has to be accessed by word (32-bit). Reserved Reserved OF_VALUE[12:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:0 OF_VALUE[12:0] Offset value control register (FMC_DMPCTL) Secure dedicated mark protection 2.5.24. Address offset: 0x8C Reset value: 0x0000 0000 This register can only be written if OBWEN bit is set. -
Page 101: Privilege Configuration Register (Fmc_Privcfg)
GD32W51x User Manual modification are denied. Privilege configuration register (FMC_PRIVCFG) 2.5.25. Address offset: 0x90 Reset value: 0x0000 0000. This register can be read by both privileged and unprivileged access. When the system is secure (TZEN =1), this register can be read by secure and non-secure access. -
Page 102: Electronic Fuse (Efuse)
GD32W51x User Manual PID[15:0] Bits Field Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by softw are. These bits are unchanged constant after pow er on. These bits are one time program w hen the chip produced. Electronic fuse (EFUSE) 3.1. -
Page 103: Function Overview
GD32W51x User Manual Figure 3-1. Block diagram of efuse controller EFUSE Registers Read EFUSE Controller Master Write EFUSE Macro (2K Bits) AFIO 3.4. Function overview EFUSE architecture 3.4.1. The EFUSE consists of up to 2048 bits storage cells organized into 256 bytes. EFUSE uses 8-bit address encoding. - Page 104 GD32W51x User Manual Table 3-2. system parameters Width Start Program - Param eter Read-protected Description Note address protected Control bytes of relevant Can w rite Read out after parameters required for MCU multiple system reset User startup. Efuse control 8'd0 times, but and keep define...
- Page 105 GD32W51x User Manual Width Start Program - Param eter Read-protected Description Note address protected passw ord ROM after used for initial attestation define system reset, service bus readable For more details, refer to Debug password register (EFUSE_DP) Initial Attestation Key, w hich used for initial attestation service(When the efuse Write once...
- Page 106 GD32W51x User Manual Width Start Program - Param eter Read-protected Description Note address protected Calibrati after system reset, system bus readable trim 8'd 155 reset w hen rom_rd_en valid Read out after 8'd 196 Write once system reset, Custo Thermal after 1Bx2 bus readable...
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Page 107: Read Operation
GD32W51x User Manual Read operation 3.4.3. The value of the EFUSE can only be accessed through the corresponding register. After system reset, the EFUSE value take effect and reloaded to corresponding register. When read the ROTPK or its hash/Debug Password/IAK/GSSA/User data or RF data related bytes in the EFUSE, you need to follow the following steps: The following steps show the register access sequence of the EFUSE reading operation. -
Page 108: Register Definition
GD32W51x User Manual 3.5. Register definition EFUSE secure access base address: 0x5002 2800 EFUSE non-Secure access base address: 0x4002 2800 Control and status register (EFUSE_CS) 3.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved OVBERIC RDIC... -
Page 109: Address Register (Efuse_Addr)
GD32W51x User Manual 1: Enable the program operation completed interrupt Reserved Must be kept at reset value. OVBERIF Overstep boundary error flag 0: No overstep boundary error occurred 1: Overstep boundary error has occurred RDIF Read operation complete flag 0: Read EFUSE operation not completed 1: Read EFUSE operation completed PGIF Program operation completed flag... -
Page 110: Control Register (Efuse_Ctl)
GD32W51x User Manual 31:15 Reserved Must be kept at reset value. 14:8 EFSIZE[6:0] Read or w rite EFUSE data size EFADDR[7:0] Read or w rite EFUSE data start address Note: This register cannot be modified when the EFSTR bit is 1. Control register (EFUSE_CTL) 3.5.3. -
Page 111: Trustzone Control Register(Efuse_Tzctl)
GD32W51x User Manual This bit needs to w ork w ith the bits[5:1] and GSSACDM in SYSCFG_GSSA CMDR register to decide how to startup 0: Startup from Flash 1: Startup from Secure boot Trustzone control register(EFUSE_TZCTL) 3.5.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved... -
Page 112: Flash Protection Control Register (Efuse_Fp_Ctl)
GD32W51x User Manual 1: Can not debug TZEN Trust zone enable bit 0: Disable trust zone function 1: Enable trust zone function Flash protection control register (EFUSE_FP_CTL) 3.5.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved FP[7:0]... -
Page 113: Mcu Initialization Data Register (Efuse_Mcu_Init_Data)
GD32W51x User Manual 31:6 Reserved Must be kept at reset value. UDLK EFUSE_USER_DA TA register lock bit 0: Unlock EFUSE_USER_DA TA register 1: Lock EFUSE_USER_DATA register AESEN Lock EFUSE_A ES_KEY register and enable AES decrypt function 0: Disable AES decrypt and AES key can be w ritten 1: Enable AES decrypt and AES key can’t be w ritten MCUINITLK EFUSE_MCU_INIT_DA TA register... -
Page 114: Firmware Aes Key Register (Efuse_Aes_Key)
GD32W51x User Manual Bits Fields Descriptions 31:0 INITDA TA[31:0] Efuse mcu_init value. Firmware AES key register (EFUSE_AES_KEY) 3.5.8. Address offset: 0x24+X*4(X=0,1,2,3) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) AESKEY[31:16] AESKEY[15:0] Bits Fields Descriptions 31:0 AESKEY[31:0] EFUSE AES key value. -
Page 115: Iak Key Or Gssa Register (Efuse_Iak_Gssa)
GD32W51x User Manual DP[31:16] DP[15:0] Bits Fields Descriptions 31:0 DP[31:0] EFUSE Debug passw ord value. IAK key or GSSA register (EFUSE_IAK_GSSA) 3.5.11. Address offset: 0x5C+X*4(X=0,1,2,3,…,15) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) IAKGSSA[31:16] IAKGSSA[15:0] Bits Fields Descriptions... -
Page 116: Huk Key Register (Efuse_Huk_Key)
GD32W51x User Manual HUK key register (EFUSE_HUK_KEY) 3.5.13. Address offset: 0xAC+X*4(X=0,1,2,3) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) HKEY[31:16] HKEY[15:0] Bits Fields Descriptions 31:0 HKEY[31:0] EFUSE HUK value. RF data register (EFUSE_RF_DATA) 3.5.14. Address offset: 0xBC+X*4(X=0,1,2,3,…,11) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) RFDATA[31:16]... -
Page 117: Efuse Pre-Trustzone Enable Register (Efuse_Pre_Tzen)
GD32W51x User Manual USERDATA[15:0] Bits Fields Descriptions 31:0 USERDA TA[31:0] EFUSE USER_DA TA value. EFUSE Pre-TrustZone enable register (EFUSE_PRE_TZEN) 3.5.16. Address offset: 0x118 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved STZEN Bits Fields Descriptions 31:1... -
Page 118: Trustzone Boot Address Register (Efuse_Ntz_Boot_Addr)
GD32W51x User Manual No-TrustZone boot address register (EFUSE_NTZ_BOOT_ADDR) 3.5.18. Address offset: 0x124 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) NTZBOOTADDR[31:16] NTZBOOTADDR[15:0] Bits Fields Descriptions 31:0 NTZBOOTADDR[31: Boot from the address w hen TrustZone is disabled. -
Page 119: Instruction Cache (Icache)
GD32W51x User Manual Instruction cache (ICACHE) 4.1. Introduction The instruction cache (ICACHE) is based on C-AHB code bus of Cortex-M33 processor. It is necessary to improve performance in fetching instruction and data from both internal and external memories. 4.2. Characteristics •... -
Page 120: Icache Initialization
GD32W51x User Manual Figure 4-1. ICACHE block diagram Cortex-M33 C-AHB Execution port Execution port interface Configuration CACHE interface pLRU memory Region0 config Region1 config Cache control Region2 config logic Region3 config CACHE Configuration Hit monitor data REMAP Slave port Miss monitor memory control status... -
Page 121: Icache Tag Memory
GD32W51x User Manual Paired master feature insure that the processor have a backup method to fetch from different memory. It is feasible to separate the traffic to internal flash and the traffic to internal SRAM (if it is remapped), so as to decrease the processor stalls when ICACHE is not on hit. -
Page 122: Figure 4-2. Icache Remapping Address
GD32W51x User Manual which consist of MSBs (RADDR[31:RS] field of ICACHE_CFGx) and LSBs (AHB_ADDR_in[RS-1:0]). Figure 4-2. ICACHE remapping address Region x 000:BADDR[28:RS] address RADDR[31:RS] RS-1 RS-1 AHB_ADDR_in AHB_ADDR_out When programming BADDR and RADDR field in ICACHE_CFGx, it is notable that if programmed value is larger than expected (MSBs), the unnecessary extra LSBs are bypassed. -
Page 123: Cacheable And Uncacheable Access
GD32W51x User Manual Cacheable and uncacheable access 4.3.5. ICACHE support memory region remapping feature, so as to make external memory regions cacheable. ICACHE is able to access up to four external memory regions in cacheable way. There is an alias of external memory region address in the code region (address range [0x0000 0000:0x07FF FFFF] or [0x1000 0000:0x1FFF FFFF] ), so ICACHE can manage and C-AHB bus is able to route external memory region (physical address range [0x9000 0000:0x97FF FFFF]) through their code alias address. -
Page 124: Icache Performance Monitoring
GD32W51x User Manual However, according to hit-under-miss feature, if address is not present in TAG memory which belongs to the current refill burst, also means cache hit. Even if cache line is refilling, only if the data is available at its master interface, ICACHE is able to fetch the requested data quickly, so as to avid a miss. -
Page 125: Table 4-5. Icache Interrupt
GD32W51x User Manual in ICACHE_STAT. meanwhile, if the corresponding interrupt enable bit is s et, end interrupt is triggered, and then cache is available again. Table 4-5. ICACHE interrupt ICACHE error Interrupt event Functional error Operation end Event flag Interrupt enable bit ERRIE ENDIE Interrupt clear bit... -
Page 126: Register Definition
GD32W51x User Manual 4.4. Register definition ICACHE secure access base address: 0x5008 0000 ICACHE non-secure access base address: 0x4008 0000 Control register (ICACHE_CTL) 4.4.1. Address offset: 0x00 Reset value: 0x0000 0004 This register has to be accessed by word (32-bit) Reserved MMRST HMRST... -
Page 127: Status Register (Icache_Stat)
GD32W51x User Manual 1: invalidate entire cache Enable 0: cache disabled 1: cache enabled Status register (ICACHE_STAT) 4.4.2. Address offset: 0x04 Reset value: 0x0000 0001 This register has to be accessed by word (32-bit) Reserved Reserved BUSY Bits Fields Descriptions 31:3 Reserved Must be kept at reset value... -
Page 128: Flag Clear Register (Icache_Fc)
GD32W51x User Manual Bits Fields Descriptions 31:3 Reserved Must be kept at reset value ERRIE cache error interrupt enable 0: disable error interrupt 1: enable error interrupt ENDIE cache operation end interrupt enable 0: disable operation end interrupt 1: enable operation end interrupt Reserved Must be kept at reset value Flag clear register (ICACHE_FC) -
Page 129: Miss Monitor Counter Register (Icache_Mmc)
GD32W51x User Manual HMC [15:0] Bits Fields Descriptions 31:0 HMC [31:0] Cache hit monitor counter. Miss monitor counter register (ICACHE_MMC) 4.4.6. Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved MMC [15:0] Bits Fields Descriptions... - Page 130 GD32W51x User Manual MSEL Region x AHB cache master selection 0: select master0 by default 1: select master1 Reserved Must be kept at reset value 26:16 RADDR Region x remapped address, this field replaces the alias address defined by BADDR field. Region x enable 0: disabled 1: enabled...
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Page 131: Power Management Unit (Pmu)
GD32W51x User Manual Power management unit (PMU) 5.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32W51x series. According to the Power management unit (PMU), provides five types of power saving modes, including Sleep, Deep-sleep, Standby, SRAM_sleep and Wi-Fi_sleep mode. -
Page 132: Function Overview
GD32W51x User Manual 5.3. Function overview provides details on the internal configuration of the PMU Figure 4-3. Power supply overview and the relevant power domains. Figure 4-3. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUPR BKP PAD WKUPx PA15 PA12... -
Page 133: Vdd / Vdda Power Domain
GD32W51x User Manual The clock source of the Real Time Clock (RTC) circuit can be derived from the Internal 32KHz RC oscillator (IRC32K) or the Low Speed Crystal oscillator (LXTAL), or HXTAL clock divided by 2 to 31. When V is shut down, only LXTAL is valid for RTC. -
Page 134: Figure 4-5. Waveform Of The Lvd Threshold
GD32W51x User Manual Figure 4-4. Waveform of the POR / PDR 40mV hyst RSTTEMPO Power Reset (Active Low) The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register (PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the PMU_CS0 register, indicates if V is higher or lower than the LVD threshold. -
Page 135: 1.2V Power Domain
GD32W51x User Manual than the specified threshold (2.4V). The VLVD is enabled by setting the VLVDEN bit in PMU_CTL0 register, and VLVDF bit, which in the PMU_CS0 register, indicates if V higher or lower than the specified threshold (2.4V). This event is internally connected to the EXTI line 18 and can generate an interrupt if it is enabled through the EXTI registers. -
Page 136: Power Saving Modes
GD32W51x User Manual Power saving modes 5.3.4. After a system reset or a power reset, the GD32W51x MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS bits in PMU_CTL0 register. - Page 137 GD32W51x User Manual LDLP, LDOLP bits in the PMU_CTL0 register. The low-driver mode provides lower drive capability, and the low-power mode take lower power. Normal-driver & Normal-power: The Deep-sleep mode is not in low-driver mode by configure LDEN to 00 in the PMU_CTL0 register, and not in low-power mode depending on the LDOLP bit reset in the PMU_CTL0 register.
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Page 138: Table 4-6 Typical Work Mode
GD32W51x User Manual SRAMxPWAKE (x = 1/2/3) bit in PMU_CTL1 register is set, the SRAMx (x = 1/2/3) will be powered on. SRAM1 / SRAM2 / SRAM3 can be configured power on or power off when in run / sleep / deep_sleep mode. -
Page 139: Figure 4-6. Rf Sequence
GD32W51x User Manual Figure 4-6. RF sequence WIFI RF ON HXTALPU HXTALREADY BGPU PLLDIGPU LDOCLKPU LDOANAPU RFPLLPU HXTALPU, HXTALREADY and PLLDIGPU are bits of RCU_CTL register; BGPU, LDOCLKPU, LDOANAPU and RFPLLPU are bits of RCU_CFG1 register. When PLLDIGPU is 1, PLLDIGOSEL[1:0] bits in RCU_PLLCFG register should not change, and no rising edge should appear on PLLDIGEN bit of RCU_CTL register. -
Page 140: Table 4-8. Power Saving Mode Summary
GD32W51x User Manual Nam e Tim e Discription Pow er up interval The reserved time of simulated closing output clock of HXTAL If HXTAL is selected to output clock, when HXTALREADY and HXTALEN in RCU_CTL register are 1, the output clock will be stable within a HXTAL period. Table 4-8. -
Page 141: Security Description
GD32W51x User Manual Security description 5.3.5. PMU secure protection PMU register bits can be configured secured by PMU_SECCFG register against non-secure access when the TZEN bit in the EFUSE_TZCTL register is 1. LDOVS[1:0] bits can be secured when the system clock selection is secure in RCU. The features can be secured is shown as following: ... - Page 142 GD32W51x User Manual registers is supported or not. When PRIV bit is reset, both privileged and unprivileged accesses to PMU registers are supported. When PRIV bit is set, only privileged access to PMU registers is supported, unprivileged access to a privileged register is RAZ / WI.
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Page 143: Register Definition
GD32W51x User Manual 5.4. Register definition PMU secure access base address: 0x5000 7000 PMU non-secure access base address: 0x4000 7000 Control register 0 (PMU_CTL0) 5.4.1. Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) A non-secure read / write access on secured bits is RAZ / WI. When TZEN = 0, there is no access restriction. - Page 144 GD32W51x User Manual LDLP Low -driver mode w hen use low pow er LDO. 0: normal driver w hen use low pow er LDO 1: Low -driver mode enabled w hen LDEN is 11 and use low pow er LDO VLVDEN low voltage detect enable 0 : No detect...
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Page 145: Control And Status Register 0 (Pmu_Cs0)
GD32W51x User Manual Control and status register 0 (PMU_CS0) 5.4.2. Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) When PRIV in PMU_PRICFG register is 1, only privileged access is supported. This register can be accessed by half-word (16-bit) or word (32-bit). Reserved LDRF[1:0] Reserved... - Page 146 GD32W51x User Manual If WUPEN2 is set before entering the pow er saving mode, a rising edge on the WKUP pin2 w akes up the system from the pow er saving mode. As the WKUP pin2 is active high, the WKUP pin2 is internally configured to input pull dow n mode. And set this bit w ill trigger a w akup event w hen the input is aready high.
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Page 147: Control Register 1 (Pmu_Ctl1)
GD32W51x User Manual This bit is cleared only by a POR / PDR or by setting the WURST bit in the PMU_CTL0 register. Control register 1 (PMU_CTL1) 5.4.3. Address offset: 0x08 Reset value: 0x0000 0002 (reset by wakeup from Standby mode) This register can be accessed by half-word (16-bit) or word (32-bit). -
Page 148: Control And Status Register 1 (Pmu_Cs1)
GD32W51x User Manual w akeup Wi-Fi (Note that the IRC16M clock should be at w ork) Reserved Must be kept at reset value. Control and status register 1 (PMU_CS1) 5.4.4. Address offset: 0x0C Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) When PRIV in PMU_PRICFG register is 1, only privileged access is supported. -
Page 149: Secure Configuration Register (Pmu_Seccfg)
GD32W51x User Manual Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved RFFC RFFS RFSWEN Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Softw are set or clear (must >... -
Page 150: Privilege Configuration Register (Pmu_Pricfg)
GD32W51x User Manual RFSEC RF security When set, the bits of PMU_RFCTL register is secure. A non-secure read / w rite access on secured bits is RAZ / WI. 15:12 Reserved Must be kept at reset value. Wi-Fi_sleep and SRAM_sleep mode security LPSSEC When set, the bits of PMU_CTL1 register is secure. - Page 151 GD32W51x User Manual Reserved Reserved PRIV Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. PRIV Set and reset by softw are. This bit can be read by both privileged and unprivileged access. When set, it can only be cleared by a privileged access. 0: All PMU registers can be read and w ritten w ith privileged or unprivileged access.
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Page 152: Reset And Clock Unit (Rcu)
GD32W51x User Manual Reset and clock unit (RCU) Reset control unit (RCTL) 6.1. Overview 6.1.1. GD32W51x Reset Control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the Backup domain. -
Page 153: Clock Control Unit (Cctl)
GD32W51x User Manual Figure 6-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the Backup domain control register or Backup domain power on reset (V or V power on, if both supplies have previously been powered off). -
Page 154: Figure 6-2. Clock Tree
GD32W51x User Manual Figure 6-2. Clock tree CK_HXTAL /2 to /32 CK_RTC 32.768 KHz LXTAL OSC (to RTC) RTCSRC[1:0] CK_FWDGT 32 KHz IRC32K (to FWDGT) CK_SYS CK_OUT1 CKOUT1DIV CK_PLLI2S ÷ 1,2,3,4,5 CK_HXTAL CK_PLLDIG CKOUT1SEL[1:0] HCLK (to AHB bus,Cortex- AHB enable M33,SRAM,DMA,peripherals) CK_IRC16M CK_CST... -
Page 155: Characteristics
GD32W51x User Manual The frequency of AHB, APB2 and the APB1 domains can be configured by each prescaler. The maximum frequency of the AHB and the APB2/APB1 domains is 180MHz/90MHz/45 MHz. The Cortex-M33 System Timer (SysTick) external clock is clocked with the AHB clock (HCLK) divided by 8. -
Page 156: Function Overview
GD32W51x User Manual PLLDIG clock source can be HXTAL PLLI2S clock source can be HXTAL HXTAL clock monitor Function overview 6.2.3. High speed crystal oscillator (HXTAL) The high speed external crystal oscillator (HXTAL), which has a frequency from 20 to 52 MHz, produces a highly accurate clock source for use as the system clock. - Page 157 GD32W51x User Manual internal 16M RC oscillator is stable. The start-up time of the IRC16M oscillator is shorter than the HXTAL crystal oscillator. An interrupt can be generated if the related interrupt enable bit, IRC16MSTBIE, in the Clock Interrupt Register, RCU_INT, is set when the IRC16M becomes stable.
- Page 158 GD32W51x User Manual generated if the related interrupt enable bit, LXTALSTBIE, in the Interrupt Register RCU_INT is set when the LXTAL becomes stable. Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the Backup Domain Control Register (RCU_BDCTL). The CK_LXTAL is equal to the external clock which drives the OSC32IN pin.
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Page 159: Rcu Security Protection
GD32W51x User Manual CK_OUT1 is seleced by CKOUT1SEL, in the Clock Configuration Register 0 (RCU_CFG0). Table 6-1. Clock output 0 source select Clock Source 0 Selection bits Clock Source CK_IRC16M CK_LXTAL CK_HXTAL CK_PLLP Table 6-2. Clock output 1 source select Clock Source 1 Selection bits Clock Source CK_SYS... -
Page 160: Table 6-4. Rcu Secure Protection Configuration Summary
GD32W51x User Manual By configuring the RCU_SECP_CFG register, you can prohibit non-secure access to read or modify the configuration and status of HXTAL, CKMEN, IRC16M, IRC32K, LXTAL, PLL, PLLDIG, PLLI2S, AHB pre-scaler related registers, as well as the selection of the system clock source, CKOUT clock output and reset flag RMVF can also be configured through the RCU_SECP_CFG register. -
Page 161: Rcu Privilege Protection
GD32W51x User Manual Configuration bit in Corresponding Secured bit RCU_SECPCFG register PLLDIGSTBIC, PLLDIGSTBIE, RCU_INT PLLDIGSTBIF RMVFSECP=1 RCU_RSTSCK RSTFC BKPSECP=1 RCU_BDCTL BKPRST RCU_PLLCFG2 PLLI2SN[6:0], PLLI2SPSC[2:0], PLLI2SDIV[5:0] RCU_CTL PLLI2SSTB, PLLI2SEN PLLI2SSECP=1 RCU_ADDCTL PLLFI2SDIV PLLI2SSTBIC, PLLI2SSTBIE, RCU_INT PLLI2SSTBIF When a certain bit register in RCU_SECPCFG is set, some RCU registers will have security attributes, and the access to the secure and non-secure bits in the register will follow the rules Table 6-5. - Page 162 GD32W51x User Manual Access Read Write m ode Priviledg access Unprivileg access Priviledg access Unprivileg access SECP_STA T,RCUP RIP in RCU_CTL)
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Page 163: Register Definition
GD32W51x User Manual 6.5. Register definition RCU secure access base address: 0x5002 3800 RCU non-secure access base address: 0x4002 3800 Control register (RCU_CTL) 6.5.1. Address offset: 0x00 Reset value: 0x0004 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HXTALR HXTALE HXTALE... - Page 164 GD32W51x User Manual 0: High speed crystal oscillator Pow er dow n 1: High speed crystal oscillator Pow er up PLLI2SSTB PLLI2S clock stabilization flag Set by hardw are to indicate if the PLLI2S output clock is stable and ready for use. 0: PLLI2S is not stable 1: PLLI2S is stable PLLI2SEN...
- Page 165 GD32W51x User Manual 0: Disable the High speed 20 ~ 52 MHz crystal oscillator (HXTAL) clock monitor 1: Enable the High speed 20 ~ 52 MHz crystal oscillator (HXTAL) clock monitor When the hardw are detects that the HXTAL clock is stuck at a low or high state, the internal hardw are w ill sw itch the system clock to be the internal high speed IRC16M RC clock.
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Page 166: Pll Register (Rcu_Pll)
GD32W51x User Manual nonsecure w rite is ignored. A secure unprivileged w rite access on RCUPRIV bit is ignored. IRC16MSTB IRC16M Internal 16MHz RC Oscillator stabilization flag Set by hardw are to indicate if the IRC16M oscillator is stable and ready for use. 0: IRC16M oscillator is not stable 1: IRC16M oscillator is stable IRC16MEN... -
Page 167: Clock Configuration Register 0 (Rcu_Cfg0)
GD32W51x User Manual PLLSEL PLL clock source selection Set and reset by softw are to control the PLL clock source. 0: IRC16M clock selected as source clock of PLL 1: HXTAL clock selected as source clock of PLL 14:6 PLLN[8:0] The PLL VCO clock multiplication factor Set and reset by softw are (only use w ord/half -word w rite) w hen the PLL is disable. - Page 168 GD32W51x User Manual APB2PSC[2:0] APB1PSC[2:0] Reserved AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions 31:30 CKOUT1SEL[1:0] CKOUT1 clock source selection Set and reset by softw are. 00: System clock selected 01: CK_PLLI2S clock selected (SPI1EN or HPDFEN must be 1, to generate CK_ PLLI2S) 10: High Speed crystal oscillator clock (HXTAL) selected 11: CK_PLLDIG clock selected...
- Page 169 GD32W51x User Manual … 11111: CK_HXTAL / 32 15:13 APB2PSC[2:0] APB2 prescaler selection Set and reset by softw are to control the APB2 clock division ratio. 0xx: Reserved 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected 12:10 APB1PSC[2:0]...
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Page 170: Clock Interrupt Register (Rcu_Int)
GD32W51x User Manual 01: select CK_HXTAL as the CK_SYS source 10: select CK_PLLP as the CK_SYS source 11: select CK_PLLDIG as the CK_SYS source Clock interrupt register (RCU_INT) 6.5.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) PLLDIGS PLLI2SS PLLSTBI... - Page 171 GD32W51x User Manual 1: Reset HXTALSTBIF flag IRC16MSTBIC IRC16M stabilization interrupt clear Write 1 by softw are to reset the IRC16MSTBIF flag. 0: Not reset IRC16MSTBIF flag 1: Reset IRC16MSTBIF flag LXTALSTBIC LXTAL stabilization interrupt clear Write 1 by softw are to reset the LXTALSTBIF flag. 0: Not reset LXTALSTBIF flag 1: Reset LXTALSTBIF flag IRC32KSTBIC...
- Page 172 GD32W51x User Manual IRC32KSTBIE IRC32K Stabilization interrupt enable IRC32K stabilization interrupt enable/disable control 0: Disable the IRC32K stabilization interrupt 1: Enable the IRC32K stabilization interrupt CKMIF HXTAL Clock Stuck Interrupt Flag Set by hardw are w hen the HXTAL clock is stuck. Reset w hen setting the CKMIC bit by softw are.
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Page 173: Ahb1 Reset Register (Rcu_Ahb1Rst)
GD32W51x User Manual 0: No LXTAL stabilization interrupt generated 1: LXTAL stabilization interrupt generated IRC32KSTBIF IRC32K stabilization interrupt flag Set by hardw are w hen the Internal 32kHz RC oscillator clock is stable and the IRC32KSTBIE bit is set. Reset w hen setting the IRC32KSTBIC bit by softw are. 0: No IRC32K stabilization clock ready interrupt generated 1: IRC32K stabilization interrupt generated AHB1 reset register (RCU_AHB1RST) -
Page 174: Ahb2 Reset Register (Rcu_Ahb2Rst)
GD32W51x User Manual WIFIRST Wi-Fi reset This bit is set and reset by softw are. 0: No reset 1: Reset the Wi-Fi CRCRST CRC reset This bit is set and reset by softw are. 0: No reset 1: Reset the CRC 11:9 Reserved Must be kept at reset value... -
Page 175: Ahb3 Reset Register (Rcu_Ahb3Rst)
GD32W51x User Manual TRNGRS PKCAUR Reserved HAURST CAURST Reserved DCIRST Bits Fields Descriptions 31:7 Reserved Must be kept at reset value TRNGRST TRNG reset This bit is set and reset by softw are. 0: No reset 1: Reset the TRNG HAURST HAU reset This bit is set and reset by softw are. -
Page 176: Apb1 Reset Register (Rcu_Apb1Rst)
GD32W51x User Manual Reserved QSPIRST SQPIRST Bits Fields Descriptions 31:2 Reserved Must be kept at reset value QSPIRST QSPI reset This bit is set and reset by softw are. 0: No reset 1: Reset the QSPI SQPIRST SQPI reset This bit is set and reset by softw are. 0: No reset 1: Reset the SQPI APB1 reset register (RCU_APB1RST) - Page 177 GD32W51x User Manual I2C0RST I2C0 reset This bit is set and reset by softw are. 0: No reset 1: Reset the I2C0 20:19 Reserved Must be kept at reset value USART0RST USART0 reset This bit is set and reset by softw are. 0: No reset 1: Reset the USART0 USART1RST...
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Page 178: Apb2 Reset Register (Rcu_Apb2Rst)
GD32W51x User Manual 0: No reset 1: Reset the TIMER2 TIMER1RST TIMER1 reset This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER1 APB2 reset register (RCU_APB2RST) 6.5.9. Address offset: 0x24 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HPDFRS TIMER16... -
Page 179: Ahb1 Enable Register (Rcu_Ahb1En)
GD32W51x User Manual 16:15 Reserved Must be kept at reset value. SYSCFGRST SYSCFG reset This bit is set and reset by softw are. 0: No reset 1: Reset the SYSCFG Reserved Must be kept at reset value. SPI0RST SPI0 reset This bit is set and reset by softw are. - Page 180 GD32W51x User Manual USBFSE SRAM3E SRAM2E SRAM1E SRAM0E Reserved Reserved DMA1EN DMA0EN Reserved WIFIRUN TZGPCE Reserved WIFIEN CRCEN Reserved TSIEN Reserved PCEN PBEN PAEN Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. USBFSEN USBFS clock enable This bit is set and reset by softw are. 0: Disabled USBFS clock 1: Enabled USBFS clock 28:23...
- Page 181 GD32W51x User Manual 1: Enabled SRAM0 clock Reserved Must be kept at reset value WIFIRUNEN WIFIRUNEN clock enable, This bit is set and reset by softw are. If WIFIEN is 0, this bit don’t w ork. 0: Disabled WIFIRUNEN clock 1: Enabled WIFIRUNEN clock WIFIEN Wi-Fi Module clock enable...
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Page 182: Ahb2 Enable Register (Rcu_Ahb2En)
GD32W51x User Manual AHB2 enable register (RCU_AHB2EN) 6.5.11. Address offset: 0x34 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved PKCAUE Reserved TRNGEN HAUEN CAUEN Reserved DCIEN Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRNGEN TRNG clock enable This bit is set and reset by softw are. -
Page 183: Ahb3 Enable Register (Rcu_Ahb3En)
GD32W51x User Manual AHB3 enable register (RCU_AHB3EN) 6.5.12. Address offset: 0x38 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved Reserved QSPIEN SQPIEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. QSPIEN QSPI clock enable This bit is set and reset by softw are. - Page 184 GD32W51x User Manual This bit is set and reset by softw are. 0: Disabled PMU clock 1: Enabled PMU clock 27:23 Reserved Must be kept at reset value. I2C1EN I2C1 clock enable This bit is set and reset by softw are. 0: Disabled I2C1 clock 1: Enabled I2C1 clock I2C0EN...
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Page 185: Apb2 Enable Register (Rcu_Apb2En)
GD32W51x User Manual This bit is set and reset by softw are. 0: Disabled TIMER4 clock 1: Enabled TIMER4 clock TIMER3EN TIMER3 clock enable This bit is set and reset by softw are. 0: Disabled TIMER3 clock 1: Enabled TIMER3 clock TIMER2EN TIMER2 clock enable This bit is set and reset by softw are. - Page 186 GD32W51x User Manual 29:19 Reserved Must be kept at reset value. TIMER16EN TIMER16 clock enable This bit is set and reset by softw are. 0: Disabled TIMER16 clock 1: Enabled TIMER16 clock TIMER15EN TIMER15 clock enable This bit is set and reset by softw are. 0: Disabled TIMER15 clock 1: Enabled TIMER15 clock 16:15...
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Page 187: Ahb1 Sleep Mode Enable Register (Rcu_Ahb1Spen)
GD32W51x User Manual 1: Enabled TIMER0 clock AHB1 sleep mode enable register (RCU_AHB1SPEN) 6.5.15. Address offset: 0x50 Reset value: 0x206F F187 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) USBFSS DMA1SP DMA0SP SRAM3S SRAM2S SRAM1S SRAM0S Reserved Reserved Reserved FMCSPE WIFIRUN... - Page 188 GD32W51x User Manual 1: Enabled SRAM2 clock w hen sleep mode SRAM1SPEN SRAM1 clock enable w hen sleep mode This bit is set and reset by softw are. 0: Disabled SRAM1 clock w hen sleep mode 1: Enabled SRAM1 clock w hen sleep mode SRAM0SPEN SRAM0 clock enable w hen sleep mode This bit is set and reset by softw are.
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Page 189: Ahb2 Sleep Mode Enable Register (Rcu_Ahb2Spen)
GD32W51x User Manual 1: Enabled GPIO port C clock w hen sleep mode PBSPEN GPIO port B clock enable w hen sleep mode This bit is set and reset by softw are. 0: Disabled GPIO port B clock w hen sleep mode 1: Enabled GPIO port B clock w hen sleep mode PASPEN GPIO port A clock enable w hen sleep mode... -
Page 190: Ahb3 Sleep Mode Enable Register (Rcu_Ahb3Spen)
GD32W51x User Manual 0: Disabled PKCAU clock w hen sleep mode 1: Enabled PKCAU clock w hen sleep mode Reserved Must be kept at reset value. DCISPEN DCI clock enable w hen sleep mode This bit is set and reset by softw are. 0: Disabled DCI clock w hen sleep mode 1: Enabled DCI clock w hen sleep mode AHB3 sleep mode enable register (RCU_AHB3SPEN) - Page 191 GD32W51x User Manual PMUSPE I2C1SPE I2C0SPE USART0 USART1 Reserved Reserved Reserved Reserved SPEN SPEN SPI1SPE WWDGT TIMER5S TIMER4S TIMER3S TIMER2S TIMER1S Reserved Reserved Reserved SPEN Bits Fields Descriptions 31:29 Reserved Must be kept at reset value PMUSPEN PMU clock enable w hen sleep mode This bit is set and reset by softw are.
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Page 192: Apb2 Sleep Mode Enable Register (Rcu_Apb2Spen)
GD32W51x User Manual WWDGTSPEN WWDGT clock enable w hen sleep mode This bit is set and reset by softw are. 0: Disabled WWDGT clock w hen sleep mode 1: Enabled WWDGT clock w hen sleep mode 10:5 Reserved Must be kept at reset value. TIMER5SPEN TIMER5 clock enable w hen sleep mode This bit is set and reset by softw are. - Page 193 GD32W51x User Manual Bits Fields Descriptions RFSPEN RF clock enable w hen sleep mode This bit is set and reset by softw are. 0: Disabled RF clock w hen sleep mode 1: Enabled RF clock w hen sleep mod HPDFSPEN HPDF clock enable w hen sleep mode This bit is set and reset by softw are.
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Page 194: Backup Domain Control Register (Rcu_Bdctl)
GD32W51x User Manual Reserved Must be kept at reset value. USART2SPEN USART2 clock enable w hen sleep mode This bit is set and reset by softw are. 0: Disabled USART2 clock w hen sleep mode 1: Enabled USART2 clock w hen sleep mode Reserved Must be kept at reset value. -
Page 195: Reset Source/Clock Register (Rcu_Rstsck)
GD32W51x User Manual RTCSRC[1:0] RTC clock entry selection Set and reset by softw are to control the RTC clock source. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. 00: No clock selected 01: CK_LXTAL selected as RTC source clock 10: CK_IRC32K selected as RTC source clock 11: (CK_HXTAL / RTCDIV) selected as RTC source clock, please refer to RTCDIV... - Page 196 GD32W51x User Manual IRC32K IRC32KE Reserved Bits Fields Descriptions LPRSTF Low -pow er reset flag Set by hardw are w hen Deep-sleep /standby reset generated. Reset by w riting 1 to the RSTFC bit. 0: No Low -pow er management reset generated 1: Low -pow er management reset generated WWDGTRSTF Window w atchdog timer reset flag...
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Page 197: Pll Clock Spread Spectrum Control Register (Rcu_Pllssctl)
GD32W51x User Manual 1: Option byte loader reset generated RSTFC Reset flag clear This bit is set by softw are to clear all reset flags. 0: Not clear reset flags 1: Clear reset flags 23:2 Reserved Must be kept at reset value. IRC32KSTB IRC32K stabilization flag Set by hardw are to indicate if the IRC32K output clock is stable and ready for use. -
Page 198: Pll Clock Configuration Register (Rcu_Pllcfg)
GD32W51x User Manual SS_TYPE PLL spread spectrum modulation type select 0: Center spread selected 1: Dow n spread selected 29:28 Reserved Must be kept at reset value. 27:13 MODSTEP[14:0] These bits configure PLL spread spectrum modulation profile amplitude and frequency. The follow ing criteria must be met: MODSTEP*MODCNT≤2 12:0 MODCNT[12:0] These bits configure PLL spread spectrum modulation profile amplitude and... -
Page 199: Clock Configuration Register 1 (Rcu_Cfg1)
GD32W51x User Manual 23:19 Reserved Must be kept at reset value. 18:16 PLLI2SPSC[2:0] The PLLI2S VCO source clock pre-scale. Set and reset by softw are when the PLLI2S is disable. These bits used to generate the clock of PLLI2SVCO source clock CK_PLLI2SV COSRC. 000: CK_PLLI2SSRC / 1 001: CK_PLLI2SSRC / 2 ………... - Page 200 GD32W51x User Manual TIMERSE LDO_AN LDO_CLK LDOCLK LDOANA USART0SEL[1:0] USART2SEL[1:0] I2C0SEL[1:0] Reserved Reserved BGPU RFPLLPU A_LQB _LQB RFPLLLO RFPLLCA Reserved BGVBIT[2:0] IRC16MDIV[8:0] Bits Fields Descriptions 31:30 USART0SEL[1:0] USART0 Clock Source Selection Set and reset by softw are to control the USART0 clock source. 00: CK_APB1 selected as USART0 source clock 01: CK_SYS selected as USART0 source clock 10: CK_LXTAL selected as USART0 source clock...
- Page 201 GD32W51x User Manual 23:22 Reserved Must be kept at reset value LDO_ANA_LQB Trust zone security by RF 0: Analog LDO high current bias mode 1: Analog LDO low current bias mode LDO_CLK_LQB Trust zone security by RF 0: Clock LDO high current bias mode 1:Clock LDO low current bias mode BGPU BandGap pow er on enable, Trust zone security by RF...
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Page 202: Additional Clock Control Register (Rcu_Addctl)
GD32W51x User Manual Additional clock control register (RCU_ADDCTL) 6.5.25. Address offset: 0x90 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) SDIOSEL[ SDIOSEL Reserved PLLFI2SDIV[5:0] Reserved SDIODIV[5:0] HPDFAUDIOSEL[1:0 HPDFSE USBFSS I2SSEL[1:0] Reserved USBFSDIV[4:0] Bits Fields Descriptions 31:30 Reserved... -
Page 203: Secure Protection Configuration Register (Rcu_Secp_Cfg)
GD32W51x User Manual Set and reset by softw are to control the HPDF AUDIO clock source. 00: PLLI2S output clock selected as HPDF AUDIO source clock 01: External I2S_CKIN PIN selected as HPDF AUDIO source clock 10: PLL division selected as HPDF AUDIO source clock 11: IRC16M selected as HPDF AUDIO source clock 13:12 I2SSEL[1:0]... - Page 204 GD32W51x User Manual BKPSEC RMVRST PLLI2SS PLLDIGS PRESCS SYSCLK LXTALSE IRC32KS HXTALS IRC16MS Reserved PLLSECP FSECP SECP Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. BKPSECP BKP security protection Set and reset by softw are. 0: Non secure 1: Secure RMVRSTFSECP Remove reset flag security protection...
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Page 205: Secure Protection Status Register (Rcu_Secp_Stat)
GD32W51x User Manual IRC32KSECP IRC32K clock configuration and status bits security protection Set and reset by softw are. 0: Non secure 1: Secure HXTALSECP HXTAL clock configuration and status bits security protection Set and reset by softw are. 0: Non secure 1: Secure IRC16MSECP IRC16M clock configuration and status bits security protection... -
Page 206: Ahb1 Secure Protection Status Register (Rcu_Ahb1Secp_Stat)
GD32W51x User Manual PLLI2SSECPF PLLI2S configuration and status bits security protection flag Set and reset by softw are. 0: Non secure 1: Secure PLLDIGSECPF PLLDIG configuration and status bits security protection flag Set and reset by softw are. 0: Non secure 1: Secure PLLSECPF Main PLL configuration and status bits security protection flag... - Page 207 GD32W51x User Manual Reset value: 0x0000 8007 (TZEN = 0) Reset value: 0x000f 8007 (TZEN = 1) When TZEN = 1, this register provides AHB1 peripheral clock security status. Privileged and unprivileged, secure and non-secure accesses are all allowed access. When the peripheral is configured to be secure, the corresponding peripheral clock is also secure.
- Page 208 GD32W51x User Manual 0: Non secure SRAM2 1: Secure SRAM2 SRAM1SECF SRAM1 security protection flag This flag is set by hardw are w hen it is secure. 0: Non secure SRAM1 1: Secure SRAM1 SRAM0SECF SRAM0 security protection flag This flag is set by hardw are w hen it is secure. 0: Non secure SRAM0 1: Secure SRAM0 FMCSECF...
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Page 209: Ahb2 Secure Protection Status Register (Rcu_Ahb2Secp_Stat)
GD32W51x User Manual AHB2 secure protection status register (RCU_AHB2SECP_STAT) 6.5.29. Address offset: 0xCC Reset value: 0x0000 0000 When TZEN = 1, this register provides AHB2 peripheral clock security status. Privileged and unprivileged, secure and non-secure accesses are all allowed access. When the peripheral is configured to be secure, the corresponding peripheral clock is also secure. -
Page 210: Ahb3 Secure Protection Status Register (Rcu_Ahb3Secp_Stat)
GD32W51x User Manual 1: Secure DCI AHB3 secure protection status register (RCU_AHB3SECP_STAT) 6.5.30. Address offset: 0xD0 Reset value: 0x0000 0000 (QSPI is not security aware) Reset value: 0x0000 0002 (QSPI is security aware) When TZEN = 1, this register provides AHB3 peripheral clock security status. Privileged and unprivileged, secure and non-secure accesses are all allowed access. - Page 211 GD32W51x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) PMUSEC I2C1SEC I2C0SEC USART0 USART1 Reserved Reserved Reserved Reserved SECPF SECPF SPI1SEC WWDGT TIMER5S TIMER4S TIMER3S TIMER2S TIMER1S Reserved Reserved Reserved SECPF ECPF ECPF ECPF ECPF ECPF Bits Fields Descriptions...
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Page 212: Apb2 Secure Protection Status Register (Rcu_Apb2Secp_Stat)
GD32W51x User Manual 1: Secure SPI1 13:12 Reserved Must be kept at reset value WWDGTSECPF WWDGT security protection flag This flag is set by hardw are w hen it is secure. 0: Non secure WWDGT 1: Secure WWDGT 10:5 Reserved Must be kept at reset value TIMER5SECPF TIMER5 security protection flag... - Page 213 GD32W51x User Manual RFSECP HPDFSE TIMER16 TIMER15 Reserved Reserved SECPF SECPF SYSCFG SPI0SEC SDIOSEC ADC0SE USART2 TIMER0S Reserved Reserved Reserved Reserved Reserved SECPF SECPF ECPF Bits Fields Descriptions RFSECPF RF security protection flag This flag is set by hardw are w hen it is secure 0: Non secure RF 1: Secure RF HPDFSECPF...
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Page 214: Voltage Key Register (Rcu_Vkey)
GD32W51x User Manual 0: Non secure SDIO 1: Secure SDIO 10:9 Reserved Must be kept at reset value ADC0SECPF ADC0 security protection flag This flag is set by hardw are w hen it is secure. 0: Non secure ADC0 1: Secure ADC0 Reserved Must be kept at reset value USART2SECPF... - Page 215 GD32W51x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved Reserved DSLPVS[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DSLPVS[1:0] Deep-sleep mode voltage select These bits are set and reset by softw are. 00 : The core voltage is 1.1V in Deep-sleep mode 01 : The core voltage is 1.0V in Deep-sleep mode 10 : The core voltage is 0.9V in Deep-sleep mode...
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Page 216: Interrupt/Event Controller (Exti)
GD32W51x User Manual Interrupt/event controller (EXTI) 7.1. Overview Cortex-M33 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. You can read the Technical Reference Manual of Cortex-M33 for more details about NVIC. -
Page 217: Table 7-1. Nvic Exception Types In Cortex-M33
GD32W51x User Manual Table 7-1. NVIC exception types in Cortex-M33 Vector Exception Type Priority (a) Vector Address Description Num ber 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non m askable interrupt Secure HardFault w hen AIRCR.BFHFNMINS is 1 HardFault 0x0000_000C Secure HardFault w hen AIRCR.BFHFNMINS is 0 All class of fault Mem Manage... - Page 218 GD32W51x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Num ber Num ber IRQ 3 RTC Wakeup event interrupt 0x0000_004C IRQ 4 FMC global interrupt 0x0000_0050 IRQ 5 RCU global interrupt 0x0000_0054 IRQ 6 EXTI Line0 interrupt 0x0000_0058 IRQ 7 EXTI Line1 interrupt 0x0000_005C IRQ 8...
- Page 219 GD32W51x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Num ber Num ber IRQ 42 VLVDF interrupt 0x0000_00E8 IRQ 43 Reserved 0x0000_00EC IRQ 44 TIMER15 global interrupt 0x0000_00F0 IRQ 45 TIMER16 global interrupt 0x0000_00F4 IRQ 46 Reserved 0x0000_00F8 IRQ 47 Reserved 0x0000_00FC IRQ 48...
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Page 220: External Interrupt And Event (Exti) Block Diagram
GD32W51x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Num ber Num ber RQ90 HPDF global interrupt1 0x0000_01A8 Wi-Fi11N global interrupt0 IRQ91 0x0000_01AC Wi-Fi11N global interrupt1 IRQ92 0x0000_01B0 Wi-Fi11N global interrupt2 IRQ93 0x0000_01B4 IRQ94 EFUSE global interrupt 0x0000_01B8 IRQ95 QSPI global interrupt 0x0000_01BC IRQ96... -
Page 221: Table 7-3. Exti Source
GD32W51x User Manual event to the processer. The EXTI has three trigger types: rising edge, falling edge and both edges. Each edge detector in the EXTI can be configured and masked independently. The EXTI trigger source includes external lines from GPIO pins and lines from internal modules (including LVD, RTC, USART, USBFS, I2C and Wi-Fi). -
Page 222: Exti Event Protection
GD32W51x User Manual EXTI Line Source Num ber PA1 / PB1 / PC1 PA2 / PB2 / PC2 PA3 / PB3 / PC3 PA4 / PB4 / PC4 PA5 / PB5 / PC5 PA6 / PB6 / PC6 PA7 / PB7 / PC7 PA8 / PB8 / PC8 PA9 / PB9 PA10 / PB10... -
Page 223: Exti Security Protection
GD32W51x User Manual Table 7-4. Register protection overview (1)(2) Register nam e Access type Protection EXTI_INTEN EXTI_EVEN EXTI_RTEN Security and privilege can be bit w ise enabled in EXTI_FTEN EXTI_SECCFG and EXTI_PRIV CFG. EXTI_SWIEV EXTI_PD Alw ays secure, and privilege can be bit w ise enabled in EXTI_SECCFG EXTI_PRIV CFG. -
Page 224: Register Definition
GD32W51x User Manual 7.9. Register definition EXTI secure access base address: 0x5001 3C00 EXTI non-secure access base address: 0x4001 3C00 Interrupt enable register (EXTI_INTEN) 7.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved INTEN28 INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9... -
Page 225: Rising Edge Trigger Enable Register (Exti_Rten)
GD32W51x User Manual EVEN15 EVEN14 EVEN13 EVEN12 EVEN11 EVEN10 EVEN9 EVEN8 EVEN7 EVEN6 EVEN5 EVEN4 EVEN3 EVEN2 EVEN1 EVEN0 Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28: 0 EVENx Event enable bit x(x=0..28 ) When EXTI_SECCFG SECx is disabled, EVENx can be accessed w ith non- secure and secure access. -
Page 226: Falling Edge Trigger Enable Register (Exti_Ften)
GD32W51x User Manual privilege access.Unprivileged w rite to this bit x is discarded, unprivileged read returns 0. 0: Rising edge of Linex is invalid 1: Rising edge of Linex is valid as an interrupt/event request Falling edge trigger enable register (EXTI_FTEN) 7.9.4. -
Page 227: Pending Register (Exti_Pd)
GD32W51x User Manual SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28: 0 SWIEVx Interrupt/Event softw are trigger (x=0..28) When EXTI_SECCFG SECx is disabled, SWIEVx can be accessed w ith non- secure and secure access. -
Page 228: Security Configuration Register (Exti_Seccfg)
GD32W51x User Manual When EXTI_PRIVCFG PRIVx is enabled, PDx can only be accessed w ith privilege access.Unprivileged w rite to this bit x is discarded, unprivileged read returns 0. 0: EXTI Linex is not triggered 1: EXTI Linex is triggered. This bit is cleared to 0 by w riting 1 to it. Security configuration register (EXTI_SECCFG) 7.9.7. -
Page 229: Lock Register (Exti_Lock)
GD32W51x User Manual PRIV15 PRIV14 PRIV13 PRIV12 PRIV11 PRIV10 PRIV9 PRIV8 PRIV7 PRIV6 PRIV5 PRIV4 PRIV3 PRIV2 PRIV1 PRIV0 Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:0 PRIVx Privilege enable on event input x (w here x = 0 to 28) When EXTI_SECCFG.SECx is disabled, PRIVx can be accessed w ith secure and nonsecure access. -
Page 230: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32W51x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 8.1. There are up to 43 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC8, and PC14 ~ PC15 for the device to implement logic input/output functions. Each GPIO port has related control and configuration registers to satisfy the requirements of specific applications. -
Page 231: Figure 8-1. Basic Structure Of A Standard I/O Port Bit
GD32W51x User Manual as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up/pull-down registers (GPIOx_PUD). Table 8-1. GPIO configuration table PAD TYPE CTLy PUDy Floating GPIO pull-up INPUT pull-dow n Floating push-pull pull-up GPIO pull-dow n OUTPUT Floating open-drain pull-up... -
Page 232: Gpio Pin Configuration
GD32W51x User Manual Figure 8-1. Basic structure of a standard I/O port bit Write Bit Operate Registers Output Output driver Control Read/Write Register Output Control Alternate Function Output protection Analog ( Input / Output ) I/O pin Alternate Function Input Input Read Status... -
Page 233: External Interrupt/Event Lines
GD32W51x User Manual External interrupt/event lines 8.3.2. All ports have external interrupt capability. To use external interrupt lines, the port must be configured as input mode. Alternate functions (AF) 8.3.3. When the port is configured as AFIO (set CTLy bits to “0b10”, which is in GPIOx_CTL registers), the port is used as peripheral alternate functions. -
Page 234: Analog Configuration
GD32W51x User Manual The schmitt trigger input is enabled The weak pull-up and pull-down resistors could be chosen The output buffer is enabled Open Drain Mode: The pad output low level when a “0” in the output control register; while the pad leaves Hi-Z when a “1”... -
Page 235: Alternate Function (Af) Configuration
GD32W51x User Manual Figure 8-4. Analog configuration Alternate function (AF) configuration 8.3.8. To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software. When be configured as alternate function: The output buffer is enabled in open-drain or push-pull configuration. ... -
Page 236: Gpio Single Cycle Toggle Function
GD32W51x User Manual GPIOx_AFSELz (z=0, 1). It allows the I/O configuration to be frozen by the 32-bit locking register (GPIOx_LOCK). When the special LOCK sequence has occurred on LKK bit in GPIOx_LOCK register and the LKy bit is set in GPIOx_LOCK register, the corresponding port is locked and the corresponding port configuration cannot be modified until the next reset. -
Page 237: Register Definition
GD32W51x User Manual Register definition 8.5. GPIOA secure access base address: 0x5002 0000 GPIOA non-secure base address: 0x4002 0000 GPIOB secure access base address: 0x5002 0400 GPIOB non-secure base address: 0x4002 0400 GPIOC secure access base address: 0x5002 0800 GPIOC non-secure base address: 0x4002 0800 Port control register (GPIOx_CTL, x=A..C) 8.5.1. - Page 238 GD32W51x User Manual refer to CTL0[1:0]description 27:26 CTL13[1:0] Pin 13 configuration bits These bits are set and cleared by softw are. refer to CTL0[1:0]description 25:24 CTL12[1:0] Pin 12 configuration bits These bits are set and cleared by softw are. refer to CTL0[1:0]description 23:22 CTL11[1:0] Pin 11 configuration bits...
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Page 239: Port Output Mode Register (Gpiox_Omode, X=A
GD32W51x User Manual CTL1[1:0] Pin 1 configuration bits These bits are set and cleared by softw are. refer to CTL0[1:0]description CTL0[1:0] Pin 0 configuration bits These bits are set and cleared by softw are. 00: GPIO Input mode (reset value) 01: GPIO output mode 10: Alternate function mode. - Page 240 GD32W51x User Manual refer to OM0 description OM10 Pin 10 output mode bit These bits are set and cleared by softw are. refer to OM0 description Pin 9 output mode bit These bits are set and cleared by softw are. refer to OM0 description Pin 8 output mode bit These bits are set and cleared by softw are.
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Page 241: Port Output Speed Register (Gpiox_Ospd, X=A
GD32W51x User Manual Port output speed register (GPIOx_OSPD, x=A..C) 8.5.3. Address offset: 0x08 Reset value: The reset value is determined by the FW AES Key bit0 and bit1 in the EFUSE. When the bit0 is 1, the PA4/PA5/PA6/PA7/PB3/PB4 is configured as one set of QSPI port automatically by the hardware, and when the bit1 is 1, the PA9/PA10/PA11/PA12/PC4/PC5 is configured as the other set of QSPI port automatically by the hardware as well. - Page 242 GD32W51x User Manual 21:20 OSPD10[1:0] Pin 10 output max speed bits These bits are set and cleared by softw are. refer to OSPD0[1:0]description 19:18 OSPD9[1:0] Pin 9 output max speed bits These bits are set and cleared by softw are. refer to OSPD0[1:0]description 17:16 OSPD8[1:0]...
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Page 243: Port Pull-Up/Pull-Down Register (Gpiox_Pud, X=A
GD32W51x User Manual Port pull-up/pull-down register (GPIOx_PUD, x=A..C) 8.5.4. Address offset: 0x0C Reset value: The reset value is determined by the FW AES Key bit0 and bit1 in the EFUSE. When the bit0 is 1, the PA4/PA5/PA6/PA7/PB3/PB4 is configured as one set of QSPI port automatically by the hardware, and when the bit1 is 1, the PA9/PA10/PA11/PA12/PC4/PC5 is configured as the other set of QSPI port automatically by the hardware as well. - Page 244 GD32W51x User Manual 21:20 PUD10[1:0] Pin 10 pull-up or pull-dow n bits These bits are set and cleared by softw are. refer to PUD0[1:0]description 19:18 PUD9[1:0] Pin 9 pull-up or pull-dow n bits These bits are set and cleared by softw are. refer to PUD0[1:0]description 17:16 PUD8[1:0]...
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Page 245: Port Input Status Register (Gpiox_Istat, X=A
GD32W51x User Manual Port input status register (GPIOx_ISTAT, x=A..C) 8.5.5. Address offset: 0x10 Reset value: 0x0000 XXXX This register has to be accessed by word(32-bit) Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3... -
Page 246: Port Bit Operate Register (Gpiox_Bop , X=A
GD32W51x User Manual Port bit operate register (GPIOx_BOP, x=A..C) 8.5.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)/half-word(16-bit)/byte(8-bit) CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4... -
Page 247: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
GD32W51x User Manual Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can alw ays be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked. 1: GPIO_LOCK register is locked until an MCU reset. LOCK key configuration sequence Write 1→Write 0→Write 1→... -
Page 248: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
GD32W51x User Manual 27:24 SEL6[3:0] Pin 6 alternate function selected These bits are set and cleared by softw are. refer to SEL0 [3:0]description 23:20 SEL5[3:0] Pin 5 alternate function selected These bits are set and cleared by softw are. refer to SEL0 [3:0]description 19:16 SEL4[3:0] Pin 4 alternate function selected... - Page 249 GD32W51x User Manual 0x0000 0000 0x0000 0000 0x0000 0000 0x0004 4440 0x0000 0000 0x0000 0000 0x0004 4440 0x0000 0000 0x0000 0000 This register has to be accessed by word(32-bit)/half-word(16-bit)/byte(8-bit) SEL15[3:0] SEL14[3:0] SEL13[3:0] SEL12[3:0] SEL11[3:0] SEL10[3:0] SEL9[3:0] SEL8[3:0] Bits Fields Descriptions 31:28 SEL15[3:0] Pin 15 alternate function selected...
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Page 250: Bit Clear Register (Gpiox_Bc, X=A
GD32W51x User Manual … 1111: AF15 selected Bit clear register (GPIOx_BC, x=A..C) 8.5.11. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)/half-word(16-bit)/byte(8-bit) Reserved CR15 CR14 CR13 CR12 CR11 CR10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. -
Page 251: Gpio Secure Configuration Register (Gpiox_Scfg) (X=A
GD32W51x User Manual 1: Toggle the corresponding OCTLy bit GPIO secure configuration register (GPIOx_SCFG) (x=A…C) 8.5.13. Address offset: 0x30 Reset value: 0x0000 FFFF If TZEN = 0 the register is RAZ/WI, if TZEN = 1, secure code can use this register to configure GPIO pin secure state, non-secure code can read, but write will ignore. -
Page 252: Trustzone Protection Controller Union (Tzpcu)
GD32W51x User Manual TrustZone protection controller union (TZPCU) Overview 9.1. This section describes the TrustZone® protection controller union. Three different sub-blocks, TrustZone® security privilege controller (TZSPC), TrustZone® block-based memory protection controller (TZBMPC) and TrustZone® illegal access controller (TZIAC), are used to configure system security or privileg in a product with programmable-security and privileged attributes. -
Page 253: Table 9-1. Trustzone® Peripherals
GD32W51x User Manual SW/JTAG TPIU Flash Flash Memory Memory AHB3 illegal interrupt Controller Slave Master Icache ARM Cortex-M33 Cbus Processor Master QSPI TZMMPCX SysDecode3 SQPI Slave NVIC Master NSMx_LEN securable peripheral AHB1 sec/priv NSMx_SADD TZIAC illegal interrupt DMA0 securable Master SysDecode2 DMA1 Slave... -
Page 254: Illegal Access Definition
GD32W51x User Manual According to security mode TrustZone-aware AHB masters can drive HNONSEC signal, secure transactions are signaled with HNONSEC = 0 on AHB bus, non-secure transactions are signaled with HNONSEC = 1 on AHB bus. Peripherals connected directly to AHB or APB bus and implementing a specific TrustZone® behavior (such as TZSPC, whether non- privilege access is supported for secure configuration registers is defined by privilege configuration registers). -
Page 255: Trustzone® Security Privilege Controller (Tzspc)
GD32W51x User Manual NOTE: If during a burst, any of the beats of the burst tries to transfer to/from an illegal address, the module masks the rest of the burst, and forwards IDLE transfers on the master port. TrustZone® security privilege controller (TZSPC) 9.3.3. -
Page 256: Trustzone® Block Based Memory Protection Controller (Tzbmpc)
GD32W51x User Manual TZMMPC1 (extern memory 1) Non secure mark 2 (0~1) SQPI_PSRA M The TZSPC is a TrustZone-aware peripheral, meaning that secure and non-secure registers co-exist within the peripheral. An exception exists for the TZPCU_TZSPC_SAM_CFG and TZPCU_TZSPC_PAM_CFG: any read access, secure or not, are supported. A dedicated interrupt signal is asserted whenever a security violation is detected. -
Page 257: Spc/Gssa Debug
GD32W51x User Manual TZPCU_TZIAC_INTENx can be used to enable an illegal access event, if an illegal access event happened, the flag bit in TZPCU_TZIAC_STATx register will be set, TZPCU_TZIAC_STATCx registers can use to clear an illegal access event flag bit. SPC/GSSA debug 9.3.6. -
Page 258: Tzspc Register Definition
GD32W51x User Manual TZSPC Register definition 9.4. TZSPC secure access base address: 0x500A 0000 TZSPC non-secure access base address: 0x400A 0000 TZSPC control register (TZPCU_TZSPC_CTL) 9.4.1. Address offset: 0x00 Reset value: 0x0000 0000 Secure write access only. Read accesses are not limited. This register has to be accessed by word (32-bit). - Page 259 GD32W51x User Manual Read accesses are not limited. This register has to be accessed by word (32-bit). TIMER0S USBFSS SPI0SAM Reserved Reserved USART2 USART1 FWDGTS WWDGT TIMER5S TIMER4S TIMER3S TIMER2S TIMER1S I2C1SAM I2C0SAM Reserved Reserved SPI1SAM Reserved Bits Fields Descriptions SPI0SAM SPI0 secure access mode configuration bit This bit is set and cleared by softw are.
- Page 260 GD32W51x User Manual 1: Configure USART2 secure access mode to secure USART1SAM USART1 secure access mode configuration bit This bit is set and cleared by softw are. 0: Configure USART1 secure access mode to non-secure 1: Configure USART1 secure access mode to secure Reserved Must be kept at reset value SPI1SAM...
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Page 261: Tzspc Secure Access Mode Configuration Register 1 (Tzpcu_Tzspc_Sam_Cfg1)
GD32W51x User Manual 1: Configure TIMER1 secure access mode to secure TZSPC secure access mode configuration register 9.4.3. (TZPCU_TZSPC_SAM_CFG1) Address offset: 0x014 Reset value: 0x0000 0000 Secure write access only. If a given bit in TZPCU_TZSPC_PAM_CFGx register is not set, the relative bit in TZPCU_TZSPC_SAM_CFGx register can be written by non privilege secure code. - Page 262 GD32W51x User Manual This bit is set and cleared by softw are. 0: Configure HAU secure access mode to non-secure 1: Configure HAU secure access mode to secure CAUSAM CAU secure access mode configuration bit This bit is set and cleared by softw are. 0: Configure CAU secure access mode to non-secure 1: Configure CAU secure access mode to secure ADCSAM...
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Page 263: Tzspc Secure Access Mode Configuration Register 2 (Tzpcu_Tzspc_Sam_Cfg2)
GD32W51x User Manual This bit is set and cleared by softw are. 0: Configure USART0 secure access mode to non-secure 1: Configure USART0 secure access mode to secure Reserved Must be kept at reset value TZSPC secure access mode configuration register 9.4.4. -
Page 264: Tzspc Privilege Access Mode Configuration Register 0 (Tzpcu_Tzspc_Pam_Cfg0)
GD32W51x User Manual 0: Configure I2S1_ADD secure access mode to non-secure 1: Configure I2S1_ADD secure access mode to secure WIFI_RFSA M Wi-Fi RF secure access mode configuration bit This bit is set and cleared by softw are. 0: Configure WIFI_RF secure access mode to non-secure 1: Configure WIFI_RF secure access mode to secure QSPI_FLASHREGSA QSPI flash register secure access mode configuration bit... - Page 265 GD32W51x User Manual USART2 USART1 FWDGTP WWDGT TIMER5P TIMER4P TIMER3P TIMER2P TIMER1P I2C1PAM I2C0PAM Reserved Reserved SPI1PAM Reserved Bits Fields Descriptions SPI0PA M SPI0 privilege access mode configuration bit This bit is set and cleared by softw are. 0: Configure SPI0 privilege access mode to non-privilege 1: Configure SPI0 privilege access mode to privilege TIMER0PA M TIMER0 privilege access mode configuration bit...
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Page 266: Tzspc Privilege Access Mode Configuration Register 1 (Tzpcu_Tzspc_Pam_Cfg1)
GD32W51x User Manual SPI1PA M SPI1 privilege access mode configuration bit This bit is set and cleared by softw are. 0: Configure SPI1 privilege access mode to non-privilege 1: Configure SPI1 privilege access mode to privilege FWDGTPA M FWDGT privilege access mode configuration bit This bit is set and cleared by softw are. - Page 267 GD32W51x User Manual Privilege write access only. If a given bit in TZPCU_TZSPC_SAM_CFGx register is not set, the relative bit in TZPCU_TZSPC_PAM_CFGx register can be written by non-secure privilege code. If a given register set, relative TZPCU_TZSPC_SAM_CFGx TZPCU_TZSPC_PAM_CFGx register can be written only by secure privilege code. Read accesses are not limited.
- Page 268 GD32W51x User Manual ADCPAM ADC privilege access mode configuration bit This bit is set and cleared by softw are. 0: Configure ADC privilege access mode to non-privilege 1: Configure ADC privilege access mode to privilege ICACHEPA M ICACHE register privilege access mode configuration bit This bit is set and cleared by softw are.
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Page 269: Tzspc Privilege Access Mode Configuration Register 2 (Tzpcu_Tzspc_Pam_Cfg2)
GD32W51x User Manual TZSPC privilege access mode configuration register 9.4.7. (TZPCU_TZSPC_PAM_CFG2) Address offset: 0x028 Reset value: 0x0000 0000 Privilege write access only If a given bit in TZPCU_TZSPC_SAM_CFGx register is not set, the relative bit in TZPCU_TZSPC_PAM_CFGx register can be written by non-secure privilege code. If a given register set, relative... -
Page 270: (Tzpcu_Tzspc_Tzmmpcx_Nsm0)
GD32W51x User Manual 1: Configure Wi-Fi RF privilege access mode to privilege QSPI_FLASHREGPA QSPI flash register privilege access mode configuration bit This bit is set and cleared by softw are. 0: Configure QSPI flash register privilege access mode to non-privilege 1: Configure QSPI flash register privilege access mode to privilege SQPI_PSRA MREGP SQPI PSRAM register privilege access mode configuration bit... -
Page 271: (Tzpcu_Tzspc_Tzmmpcx_Nsm1)
GD32W51x User Manual This register has to be accessed by word (32-bit). Reserved NSM0_LEN[14:0] Reserved NSM0_SADD[13:0] Bits Fields Descriptions Reserved Must be kept at reset value 30:16 NSM0_LEN[14:0] Length of the non-secure area (multiple of 8 Kbytes) of TZBMPC0 will set to 0x4000 –... -
Page 272: (Tzpcu_Tzspc_Tzmmpcx_Nsm2)
GD32W51x User Manual Reserved NSM1_LEN[14:0] Reserved NSM1_SADD[13:0] Bits Fields Descriptions Reserved Must be kept at reset value 30:16 NSM1_LEN[14:0] Length of the non-secure area (multiple of 8 Kbytes) of TZBMPC1 0x4000 – will set to Note: If NSM1_LEN + NSM1_SADD is over 16384, the value NSM1_SADD. -
Page 273: (Tzpcu_Tzspc_Tzmmpcx_Nsm3)
GD32W51x User Manual Reserved NSM2_SADD[13:0] Bits Fields Descriptions Reserved Must be kept at reset value 30:16 NSM2_LEN[14:0] Length of the non-secure area (multiple of 8 Kbytes) of TZBMPC2 0x4000 – will set to Note: If NSM0_LEN + NSM2_SADD is over 16384, the value NSM2_SADD. -
Page 274: Tzspc Debug Configuration Register (Tzpcu_Tzspc_Dbg_Cfg)
GD32W51x User Manual Reserved NSM3_SADD[13:0] Bits Fields Descriptions Reserved Must be kept at reset value 30:16 NSM3_LEN[14:0] Length of the non-secure area (multiple of 8 Kbytes) of TZBMPC3 0x4000 – will set to Note: If NSM3_LEN + NSM3_SADD is over 16384, the value NSM3_SADD. -
Page 275: Tzbmpc0 Registers Definition
GD32W51x User Manual SPIDEN Secure invasive debug enable bit This bit is set and cleared by softw are. 0: Disabled secure invasive debug 1: Enabled secure invasive debug NIDEN Non-invasive debug enable bit This bit is set and cleared by softw are. 0: Disabled non-invasive debug 1: Enabled non-invasive debug IDEN... -
Page 276: Tzbmpc0 Vector Register Y (Tzpcu_Tzbmpc0_Vecy)
GD32W51x User Manual This bit is set and cleared by softw are. 0: Configure TZBMPC source clock to non-secure if there do not exists secure area in TZBMPC, if exits secure area, then TZBMPC source clock is secure 1: Configure TZBMPC source clock still to secure if there do not exists secure area in TZBMPC 29:1 Reserved... -
Page 277: Tzbmpc1 Registers Definition
GD32W51x User Manual Reset value: 0x0000 0000 Secure access only. This register has to be accessed by word (32-bit). Software can only write once to this bit and can also read it at any time. Only a reset can return the bit to its reset value Reserved Reserved LKUB7... -
Page 278: Tzbmpc1 Vector Register Y (Tzpcu_Tzbmpc1_Vecy)
GD32W51x User Manual Reserved Bits Fields Descriptions SRWACFG Secure read/w rite access non-secure SRAM configuration bit. This bit is set and cleared by softw are. illegal 0: Configure secure read/w rite access non-secure SRAM is legal 1: Configure secure read/w rite access non-secure SRAM is SECSTATCFG Security state configuration bit. -
Page 279: Tzbmpc1 Lock Register 0 (Tzpcu_Tzbmpc1_Lock0)
GD32W51x User Manual 31:0 B (x + 32 * y) Secure access mode for the union-block y configuration bits x, x=0..31. These bits are set and cleared by softw are 0: block of union-block y is non-secure. 1: block of union-block y is secure. TZBMPC1 lock register 0 (TZPCU_TZBMPC1_LOCK0) 9.6.3. -
Page 280: Tzbmpc2 Vector Register Y (Tzpcu_Tzbmpc2_Vecy)
GD32W51x User Manual This register has to be accessed by word (32-bit). SRWACF SECSTAT Reserved Reserved Bits Fields Descriptions SRWACFG Secure read/w rite access non-secure SRAM configuration bit. This bit is set and cleared by softw are. illegal 0: Configure secure read/w rite access non-secure SRAM is legal 1: Configure secure read/w rite access non-secure SRAM is SECSTATCFG... -
Page 281: Tzbmpc2 Lock Register 0 (Tzpcu_Tzbmpc2_Lock0)
GD32W51x User Manual B(15+32* B(14+32* B(13+32* B(12+32* B(11+32* B(10+32* B(9+32*y) B(8+32*y) B(7+32*y) B(6+32*y) B(5+32*y) B(4+32*y) B(3+32*y) B(2+32*y) B(1+32*y) B(0+32*y) Bits Fields Descriptions 31:0 B (x + 32 * y) Secure access mode for the union-block y configuration bits x, x=0..31. These bits are set and cleared by softw are 0: block of union-block y is non-secure. -
Page 282: Tzbmpc3 Control Register (Tzpcu_Tzbmpc3_Ctl)
GD32W51x User Manual TZBMPC3 non-secure access base address: 0x400B 0400 TZBMPC3 control register (TZPCU_TZBMPC3_CTL) 9.8.1. Address offset: 0x000 Reset value: 0x0000 0000 Secure access only. This register has to be accessed by word (32-bit). SRWACF SECSTAT Reserved Reserved Bits Fields Descriptions SRWACFG Secure read/w rite access non-secure SRAM configuration bit. -
Page 283: Tzbmpc3 Lock Register 0 (Tzpcu_Tzbmpc3_Lock0)
GD32W51x User Manual Secure access only. This register has to be accessed by word (32-bit). B(31+32* B(30+32* B(29+32* B(28+32* B(27+32* B(26+32* B(25+32* B(24+32* B(23+32* B(22+32* B(21+32* B(20+32* B(19+32* B(18+32* B(17+32* B(16+32* B(15+32* B(14+32* B(13+32* B(12+32* B(11+32* B(10+32* B(9+32*y) B(8+32*y) B(7+32*y) B(6+32*y) B(5+32*y) B(4+32*y) B(3+32*y) B(2+32*y) B(1+32*y) B(0+32*y) Bits Fields Descriptions... -
Page 284: Tziac Register Definition
GD32W51x User Manual 0x0000 0001: security configuration locked only for union-blocks 0 ..0x0000 0FFF: security configuration locked for all union-blocks of SRAM3 TZIAC Register definition 9.9. TZIAC secure access base address: 0x500A 0400 TZIAC non-secure access base address: 0x400A 0400 TZIAC interrupt enable register 0 (TZPCU_TZIAC_INTEN0) 9.9.1. - Page 285 GD32W51x User Manual 1: Enable USBFS illegal access interrupt 25:16 Reserved Must be kept at reset value. I2C1IE I2C1 illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable I2C1 illegal access interrupt 1: Enable I2C1 illegal access interrupt I2C0IE I2C0 illegal access interrupt enable bit This bit is set and cleared by softw are.
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Page 286: Tziac Interrupt Enable Register 1 (Tzpcu_Tziac_Inten1)
GD32W51x User Manual TIMER4IE TIMER4 illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable TIMER4 illegal access interrupt 1: Enable TIMER4 illegal access interrupt TIMER3IE TIMER3 illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable TIMER3 illegal access interrupt 1: Enable TIMER3 illegal access interrupt TIMER2IE... - Page 287 GD32W51x User Manual 1: Enable EXTI illegal access interrupt FMCIE FMC illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable FMC illegal access interrupt 1: Enable FMC illegal access interrupt FLASHIE FLASH illegal access interrupt enable bit This bit is set and cleared by softw are.
- Page 288 GD32W51x User Manual 1: Enable SDIO illegal access interrupt PKCAUIE PKCAU illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable PKCAU illegal access interrupt 1: Enable PKCAU illegal access interrupt TRNGIE TRNG illegal access interrupt enable bit This bit is set and cleared by softw are.
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Page 289: Tziac Interrupt Enable Register 2 (Tzpcu_Tziac_Inten2)
GD32W51x User Manual TIMER16IE TIMER16 illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable TIMER16 illegal access interrupt 1: Enable TIMER16 illegal access interrupt TIMER15IE TIMER15 illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable TIMER15 illegal access interrupt 1: Enable TIMER15 illegal access interrupt Reserved... - Page 290 GD32W51x User Manual This bit is set and cleared by softw are. 0: Disable DCI illegal access interrupt 1: Eisable DCI illegal access interrupt I2S1_ADDIE I2S1_ADD illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable I2S1_ADD illegal access interrupt 1: Eisable I2S1_ADD illegal access interrupt WIFI_RFIE...
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Page 291: Tziac Status Register 0 (Tzpcu_Tziac_Stat0)
GD32W51x User Manual 1: Eisable SRAM3 illegal access interrupt TZBMPC2_REGIE TZBMPC2 REG illegal access interrupt enable bit This bit is set and cleared by softw are. 0: Disable TZBMPC2 REG illegal access interrupt 1: Eisable TZBMPC2 REG illegal access interrupt SRAM2IE SRAM2 illegal access interrupt enable bit This bit is set and cleared by softw are. - Page 292 GD32W51x User Manual Secure access only. This register has to be accessed by word (32-bit). TIMER0I USBFSIA SPI0IAF Reserved Reserved USART2I USART1I FWDGTI WWDGTI TIMER5I TIMER4I TIMER3I TIMER2I TIMER1I I2C1IAF I2C0IAF Reserved Reserved SPI1IAF Reserved Bits Fields Descriptions SPI0IAF SPI0 illegal access event flag bit 0: no SPI0 illegal access event 1: SPI0 illegal access event pending TIMER0IA F...
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Page 293: Tziac Status Register 1 (Tzpcu_Tziac_Stat1)
GD32W51x User Manual 1: USART1 illegal access event pending Reserved Must be kept at reset value SPI1IAF SPI1 illegal access event flag bit 0: no SPI1 illegal access event 1: SPI1 illegal access event pending FWDGTIA F FWDGT illegal access event flag bit 0: no FWDGT illegal access event 1: FWDGT illegal access event pending WWDGTIAF... - Page 294 GD32W51x User Manual PKCAUIA ICACHEI TIMER16I TIMER15I USART0I TRNGIAF HAUIAF CAUIAF ADCIAF TSIIAF CRCIAF HPDFIAF Reserved Reserved Reserved Bits Fields Descriptions 31:29 Reserved Must be kept at reset value EXTIIA F EXTI illegal access event flag bit 0: no EXTI illegal access event 1: EXTI illegal access event pending FMCIAF FMC illegal access event flag bit...
- Page 295 GD32W51x User Manual 0: no SDIO illegal access event 1: SDIO illegal access event pending PKCAUIAF PKCAU illegal access event flag bit 0: no PKCAU illegal access event 1: PKCAU illegal access event pending TRNGIAF TRNG illegal access event flag bit 0: no TRNG illegal access event 1: TRNG illegal access event pending HAUIAF...
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Page 296: Tziac Status Register 2 (Tzpcu_Tziac_Stat2)
GD32W51x User Manual USART0IAF USART0 illegal access event flag bit 0: no USART0 illegal access event 1: USART0 illegal access event pending Reserved Must be kept at reset value TZIAC status register 2 (TZPCU_TZIAC_STAT2) 9.9.6. Address offset: 0x018 Reset value: 0x0000 0000 Secure access only. - Page 297 GD32W51x User Manual SQPI_PSRA MREGIA SQSPI PSRAMREG illegal access event flag bit 0: no SQSPI PSRAMREG illegal access event 1: SQSPI PSRAMREG illegal access event pending QSPI_FLASHIAF QSPI FLASH illegal access event flag bit 0: no QSPI FLASH illegal access event 1: QSPI FLASH illegal access event pending SQPI_PSRA MIA F SQPI PSRAM illegal access event flag bit...
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Page 298: Tziac Flag Clear Register 0 (Tzpcu_Tziac_Statc0)
GD32W51x User Manual Reserved Must be kept at reset value TZIACIAF TZIAC illegal access event flag bit 0: no TZIAC illegal access event 1: TZIAC illegal access event pending TZSPCIAF TZSPC illegal access event flag bit 0: no TZSPC illegal access event 1: TZSPC illegal access event pending TZIAC flag clear register 0 (TZPCU_TZIAC_STATC0) 9.9.7. - Page 299 GD32W51x User Manual I2C1IAFC I2C1 illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear I2C1 illegal access flag I2C0IAFC I2C0 illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear I2C0 illegal access flag 13:12...
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Page 300: Tziac Flag Clear Register 1 (Tzpcu_Tziac_Statc1)
GD32W51x User Manual 1: Clear TIMER4 illegal access flag TIMER3IA FC TIMER3 illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear TIMER3 illegal access flag TIMER2IA FC TIMER2 illegal access flag clear bit This bit is set by softw are. - Page 301 GD32W51x User Manual 1: Clear FMC illegal access flag FLASHIAFC FLASH illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear FLASH illegal access flag RCUIAFC RCU illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear RCU illegal access flag Reserved...
- Page 302 GD32W51x User Manual 1: Clear PKCAU illegal access flag TRNGIAFC TRNG illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear TRNG illegal access flag HAUIAFC HAU illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear HAU illegal access flag CAUIAFC...
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Page 303: Tziac Flag Clear Register 2 (Tzpcu_Tziac_Statc2)
GD32W51x User Manual TIMER15IAFC TIMER15 illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear TIMER15 illegal access flag Reserved Must be kept at reset value USART0IAFC USART0 illegal access flag clear bit This bit is set by softw are. - Page 304 GD32W51x User Manual 1: Clear I2S1_ADD illegal access flag WIFI_RFIAFC Wi-Fi RF illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear Wi-Fi RF illegal access flag QSPI_FLASHREGIA QSPI FLASHREG illegal access flag clear bit This bit is set by softw are.
- Page 305 GD32W51x User Manual SRAM2IAFC SRAM2 illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear SRAM2 illegal access f lag TZBMPC1_REGIA FC TZBMPC1 REG illegal access flag clear bit This bit is set by softw are. 0: No action 1: Clear TZBMPC1 REG illegal access flag SRAM1IAFC...
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Page 306: Crc Calculation Unit (Crc)
GD32W51x User Manual CRC calculation unit (CRC) Overview 10.1. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 32 bit CRC code with fixed polynomial. Characteristics 10.2. -
Page 307: Function Overview
GD32W51x User Manual Function overview 10.3. CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA. -
Page 308: Register Definition
GD32W51x User Manual Register definition 10.4. CRC secure access base address: 0x5002 3000 CRC non-secure access base address: 0x4002 3000 Data register (CRC_DATA) 10.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits... -
Page 309: Control Register (Crc_Ctl)
GD32W51x User Manual Softw are w rites and reads. These bits are unrelated w ith CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register w ill take no effect to the byte. Control register (CRC_CTL) 10.4.3. -
Page 310: True Random Number Generator (Trng)
GD32W51x User Manual True random number generator (TRNG) Overview 11.1. The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. Characteristics 11.2. About 40 periods of TRNG_CLK are needed between two consecutive random numbers ... -
Page 311: Operation Flow
GD32W51x User Manual TRNG_CLK (refer to chapter), so that the quality of the Reset and clock unit (RCU) generated random number depends on TRNG_CLK exclusively, no matter what HCLK frequency was set or not. The 32-bit value of LFSR will transfer into TRNG_DATA register after a sufficient number of seeds have been sent to the LFSR. -
Page 312: Register Definition
GD32W51x User Manual Register definition 11.4. TRNG secure base address: 0x5C06 0800 TRNG non-secure base address: 0x4C06 0800 Control register (TRNG_CTL) 11.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TRNGEN Reserved Bits... -
Page 313: Data Register (Trng_Data)
GD32W51x User Manual rc_w0 rc_w0 Bits Fields Descriptions Must be kept at reset value. 31:7 Reserved SEIF Seed error interrupt flag This bit w ill be set if more than 64 consecutive same bit or more than 32 consecutive 01(or 10) changing are detected. 0: No fault detected 1: Seed error has been detected. - Page 314 GD32W51x User Manual TRNDATA[15:0] Bits Fields Descriptions 31:0 TRNDATA[31:0] 32-bit random data...
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Page 315: Direct Memory Access Controller (Dma)
GD32W51x User Manual Direct memory access controller (DMA) 12.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data. -
Page 316: Block Diagram
GD32W51x User Manual Both DMA and peripheral can be configured as flow controller: – DMA: Programmable length of data to be transferred, max to 65535. – Peripheral: The last request signal given to DMA from peripheral determines the end of transfer. ... -
Page 317: Function Overview
GD32W51x User Manual 12.4. Function overview The DMA controller transfers data from one address to another without CPU intervention. It supports multiple data sizes, burst types, address generation algorithm, priority levels and several transfer modes to allow for flexible application by configuring the c orresponding bits in DMA registers. -
Page 318: Secure & Priviledge
GD32W51x User Manual interfaces are implemented in each DMA respectively for memory and peripheral. Memory to peripheral: read data from memory through AHB master interface for memory, and write data to peripheral through AHB master interface for peripheral. Peripheral to memory: read data from peripheral through AHB master interface for ... -
Page 319: Peripheral Handshake
GD32W51x User Manual cleared), the illegal access pulse is generated on a non-secure write access to the DMA_CHxSCTL register which attempts to write 1 into any of the secure configuration bits SECM, DSEC, SSEC. When the software is switching from a secure state to a non-secure state (after the secure transfer is completed), the secure software must disable the channel by a 32-bit write at the DMA_CHxCTL address before switching. -
Page 320: Table 12-2. Peripheral Requests To Dma0
GD32W51x User Manual Figure 12-3. Handshake mechanism Peripheral is ready to transmit Peripheral releases the or receive data, and assert the request signal when it receives Peripheral launches request signal to DMA the acknowledge signal the next request Peripheral Peripheral Peripheral request request request... -
Page 321: Data Process
GD32W51x User Manual TIMER4_UP TIMER4_T TIMER4_T TIMER5_ USART2_ ● ● ● I2C1_RX I2C1_RX I2C1_TX Table 12-3. Peripheral requests to DMA1 Channel Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 TIMER0_C TIMER0_C ● ●... - Page 322 GD32W51x User Manual Transfer width, burst and counter Transfer width PWIDTH and MWIDTH in the DMA_CHxCTL register indicate the data width of a peripheral and memory transfer seperately. The DMA supports 8-bit, 16-bit and 32-bit transfer width. In multi-data mode, if PWIDTH is not equal to MWIDTH, the DMA can automatically packs/unpacks data to achieve an integrated and correct data transfer operation.
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Page 323: Table 12-4. Cnt Configuration
GD32W51x User Manual If the circular mode is disabled by clearing the CMEN bit in the DMA_CHxCTL register, the rules to configure the CNT bits in the DMA_CHxCNT register based on the transfer width are listed in the Table 12-4. CNT configuration. The number of data bytes must be an integer multiple of the memory transfer width to guarantee an integrated single memory transfer. -
Page 324: Table 12-5. Fifo Counter Critical Value Configuration Rules
GD32W51x User Manual Note: when the switch-buffer mode is enabled by setting the SBMEN bit in the DMA_CHxCTL register, the circular mode is enabled automatically by hardware, and the above rules must also be respected. FIFO A four-word depth 32-bit FIFO is implemented as a data buffer for each DMA channel. Data reading from the source address is stored in the FIFO temporarily and transmitted to the destination through the destination port. - Page 325 GD32W51x User Manual 1 single 2 single 3 single 4 single single transaction transactions transactions transactions 32-bit INCR4 ERROR ERROR ERROR 1 burst transactions INCR8 ERROR ERROR ERROR ERROR INCR16 ERROR ERROR ERROR ERROR Note: When transfer mode peripheral-to-memory, PBURST_beats×PWIDTH_bytes = 16, the FIFO counter critical value must not be equal to ‘10’.
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Page 326: Figure 12-4. Data Packing/Unpacking When Pwidth = '00
GD32W51x User Manual Figure 12-4. Data packing/unpacking when PWIDTH = ‘00’ PAIF = 0, MWIDTH = 8-bit read 0xB0[7:0] @0x0 read 0xB8[7:0] @0x8 write 0xB0[7:0] @0x0 write 0xB8[7:0] @0x8 word 4 read 0xB1[7:0] @0x1 read 0xB9[7:0] @0x9 write 0xB1[7:0] @0x1 write 0xB9[7:0] @0x9 read 0xB2[7:0] @0x2 read 0xB10[7:0] @0xA write 0xB2[7:0] @0x2 write 0xB10[7:0] @0xA word 3... -
Page 327: Address Generation
GD32W51x User Manual Figure 12-6. Data packing/unpacking when PWIDTH = ‘10’ PAIF = 1, MWIDTH = 8-bit write 0xB0[7:0] @0x0 write 0xB8[7:0] @0x8 word 4 write 0xB1[7:0] @0x1 write 0xB9[7:0] @0x9 read 0xB3B2B1B0[31:0] @0x0 write 0xB2[7:0] @0x2 write 0xB10[7:0] @0xA word 3 read 0xB7B6B5B4[31:0] @0x4 write 0xB3[7:0] @0x3 write 0xB11[7:0] @0xB... -
Page 328: Switch-Buffer Mode
GD32W51x User Manual DMA_CHxCTL register is cleared. Switch-buffer mode 12.4.6. Similar to circular mode, switch-buffer mode is also implemented to handle continues peripheral requests. The SBMEN bit in the DMA_CHxCTL register is used to enable/disable the switch-buffer mode. When the switch-buffer mode is enabled, the circular mode is automatically enabled immediately after the channel is enabled. -
Page 329: Transfer Operation
GD32W51x User Manual the transfer flow. DMA as transfer flow controller: The CNT bits in the DMA_CHxCNT register determine the number of data items to be transferred. The CNT bits must be configured before the channel is enabled. Peripheral as transfer flow controller: The CNT bits configured in the DMA_CHxCNT register before the channel is enabled have no meaning and these bits are force to ‘0xFFFF’... -
Page 330: Transfer Finish
GD32W51x User Manual data in the FIFO for a peripheral transfer, DMA starts a peripheral transfers to fetch the FIFO data and write to the peripheral. Memory-to-memory mode: Only the multi-data mode is supported. When the channel is enabled, DMA starts several peripheral transfers to fill up the FIFO. During the transmission, the peripheral transfer is initiated once when there is enough space for it in the FIFO. -
Page 331: Channel Configuration
GD32W51x User Manual the FIFO is not enough for a burst memory transfer, these data items are transferred in single transaction. If the remaining byte number is less than the memory transfer width, these data items are still written in memory transfer width with MSBs filled with zero. The software can read the CNT bits to calculate the number of valid data items in the memory. -
Page 332: Interrupts
GD32W51x User Manual step can be skipped. Configure the memory and peripheral burst types, the target memory buffer, switch- buffer mode, priority of the channel, memory and peripheral transfer width, memory and peripheral address generation algorithm, circular mode, the transfer flow controller in the DMA_CHxCTL register. -
Page 333: Flag
GD32W51x User Manual access error interrupt, single-data mode exception interrupt, and FIFO error and exception interrupt. A DMA channel interrupt may be produced when any interrupt event occurs on the channel. Each interrupt event has a dedicated flag bit in the DMA_INTF0 or DMA_INTF1 register, a dedicated clear bit in the DMA_INTC0 and DMA_INTC1 register, and a dedicated enable bit in the DMA_CHxCTL and CHxFCTL register, as described in the Table 12-6. -
Page 334: Exception
GD32W51x User Manual When the channel is disabled because of register access error before the end of the transfer, the current memory and peripheral is completed and the contents of the FIFO are entirely written into the memory in peripheral-to-memory or memory-to-memory mode. -
Page 335: Error
GD32W51x User Manual Error 12.5.3. FIFO error and transfer access error (including the register access error and bus error) can be detected during the DMA transmission, and the transmission can be stopped when one of the errors occurs. FIFO error For a good DMA operation, when the multi-data mode is enabled, the right and wrong configurations of the FIFO counter critical value corresponding with the memory transfer width 错误!未找到引用源。. -
Page 336: Figure 12-8. System Connection Of Dma0 And Dma1
GD32W51x User Manual and exception interrupt is set, an interrupt is generated. Figure 12-8. System connection of DMA0 and DMA1 Bus matrix Bus matrix FMC_I FMC_I FMC_D FMC_D SRAM0 SRAM0 AHB1 AHB1 QSPI QSPI DMA0 DMA1 memory port memory port AHB2 AHB2 SRAM1... -
Page 337: Register Definition
GD32W51x User Manual 12.6. Register definition DMA0 secure access base address: 0x5002 6000 DMA0 non-Secure access base address: 0x4002 6000 DMA1 secure access base address: 0x5002 6400 DMA1 non-Secure access base address: 0x4002 6400 Interrupt flag register 0 (DMA_INTF0) 12.6.1. Address offset: 0x00 Reset value: 0x0000 0000 Reserved... -
Page 338: Interrupt Flag Register 1 (Dma_Intf1)
GD32W51x User Manual Hardw are set and softw are cleared by configuring DMA_INTC0 register. 0: FIFO error or exception has not occurred on channel x 1: FIFO error or exception has occurred on channel x Interrupt flag register 1 (DMA_INTF1) 12.6.2. -
Page 339: Interrupt Flag Clear Register 0 (Dma_Intc0)
GD32W51x User Manual Interrupt flag clear register 0 (DMA_INTC0) 12.6.3. Address offset: 0x08 Reset value: 0x0000 0000 Reserved FTFIFC3 HTFIFC3 TAEIFC3 SDEIFC3 Reserved FEEIFC3 FTFIFC2 HTFIFC2 TAEIFC2 SDEIFC2 Reserved FEEIFC2 Reserved FTFIFC1 HTFIFC1 TAEIFC1 SDEIFC1 Reserved FEEIFC1 FTFIFC0 HTFIFC0 TAEIFC0 SDEIFC0 Reserved FEEIFC0 Bits Fields Descriptions... -
Page 340: Channel X Control Register (Dma_Chxctl)
GD32W51x User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. Clear bit for full transfer finish flag of channel x (x=4…7) 27/21/11/5 FTFIFCx 0: No effect 1: Clear full transfer finish flag Clear bit for half transfer finish flag of channel x (x=4…7) 26/20/10/4 HTFIFCx 0: No effect... - Page 341 GD32W51x User Manual 001: Enable peripheral 1 010: Enable peripheral 2 011: Enable peripheral 3 100: Enable peripheral 4 101: Enable peripheral 5 110: Enable peripheral 6 111: Enable peripheral 7 These bits can NOT be w ritten w hen CHEN is ‘1’. 24:23 MBURST[1:0] Transfer burst type of memory...
- Page 342 GD32W51x User Manual 00: Low 01: Medium 10: High 11: Ultra high These bits can NOT be w ritten w hen CHEN is ‘1’. PAIF Peripheral address increment fixed Softw are set and clear. 0: The peripheral address increment is determined by PWIDTH 1: The peripheral address increment is fixed to 4 This bit can NOT be w ritten w hen CHEN is ‘1’.
- Page 343 GD32W51x User Manual Softw are set and clear. 0: Disable circular mode. 1: Enable circular mode This bit can NOT be w ritten w hen CHEN is ‘1’. This bit is automatically locked as ‘0’ by hardw are immediately after enable CHEN if TFCS is configured to ‘1’.
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Page 344: Channel X Counter Register (Dma_Chxcnt)
GD32W51x User Manual When this bit is asserted, the DMA transfer is started. This bit is automaticly cleared w hen one of the follow ing situations occurs: When the transfer of channel is fully finished. When a w rong FIFO configuration or a transfer access error is detec ted. After a softw are clear operation, this bit is still read as 1 to indicate that there are memory or peripheral transfers still active until hardw are has terminated all activity, at w hich point this bit is read as 0. -
Page 345: Channel X Memory 0 Base Address Register (Dma_Chxm0Addr)
GD32W51x User Manual PADDR[31:16] PADDR[15:0] Bits Fields Descriptions 31:0 PADDR[31:0] Peripheral base address These bits can NOT be w ritten w hen CHEN in the DMA_CHxCTL register is ‘1’. When PWIDTH is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half w ord address. -
Page 346: Channel X Memory 1 Base Address Register (Dma_Chxm1Addr)
GD32W51x User Manual Channel x memory 1 base address register (DMA_CHxM1ADDR) 12.6.9. x = 0...7, where x is a channel number Address offset: 0x20 + 0x18 × x Reset value: 0x0000 0000 M1ADDR[31:16] M1ADDR[15:0] Bits Fields Descriptions 31:0 M1ADDR[31:0] Memory 1 base address When MBS in the DMA_CHxCTL register is read as to ‘1’, these bits specific the memory base address accessed by DMA during the transmission. -
Page 347: Security Status Register (Dma_Sstat)
GD32W51x User Manual Softw are set and clear. 0: Disable FIFO error and exception interrupt 1: Enable FIFO error and exception interrupt Reserved Must be kept at reset value. FCNT[2:0] FIFO counter Hardw are set and clear. 000: No data 001: One w ord 010: Tw o w ords 011: Three w ords... -
Page 348: Security Status Clear Register (Dma_Ssc)
GD32W51x User Manual mode of each channel (PRIV bit of the DMA_CHxSCTL register). A privileged software can read the full interrupt status. An unprivileged software is restricted to read the status of unprivileged channel(s), other privileged bit fields returning zero. Every status / flag bit is set by hardware, independently of the privileged and the secure mode of the channel. -
Page 349: Channel X Security Control Register (Dma_Chxsctl)
GD32W51x User Manual Writing 0 into any flag clear bit has no effect. Reserved Reserved CIAIF7 CIAIF6 CIAIF5 CIAIF4 CIAIF3 CIAIF2 CIAIF1 CIAIF0 Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. Stream x clear illegal access interrupt flag (x = 0…7) CIAIFx Writing 1 to this bit clears the corresponding IAIFx flag in the DMA_SSTAT register... - Page 350 GD32W51x User Manual 1: enabled It must not be w ritten w hen the channel is enabled (CHEN = 1). It is read-only w hen the channel is enabled (CHEN = 1). DSEC Security of the DMA transfer to the destination This bit can only be read, set or cleared by a secure softw are.
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Page 351: Debug (Dbg)
GD32W51x User Manual Debug (DBG) 13.1. Overview The GD32W51x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSightTM module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM Cortex-M33. -
Page 352: Jtag Daisy Chained Structure
GD32W51x User Manual PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST : JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JT AG function without NJTRST pin, then the PB4 can be used to other GPIO functions. (NJTRST tied to 1 by hardware). -
Page 353: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Rtc
GD32W51x User Manual When SLP_HOLD bit in DBG control register 0 (DBG_CTL0) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode. Debug support for TIMER, I2C, WWDGT, FWDGT and RTC 13.3.2. -
Page 354: Dbg Registers
GD32W51x User Manual 13.4. DBG registers DEBUG base address: 0xE0044000 ID code register (DBG_ID) 13.4.1. Address offset: 0x00 Reset value: 0x0000 0000; Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by softw are, These bits are unchanged constant Control register 0 (DBG_CTL0) 13.4.2. -
Page 355: Control Register 1 (Dbg_Ctl1)
GD32W51x User Manual 11: Trace pin used in synchronous mode and the data length is 4 TRACE_IOEN Trace pin allocation enable This bit is set and reset by softw are 0: Trace pin allocation disable 1: Trace pin allocation enable Reserved Must be kept at reset value STB_HOLD... - Page 356 GD32W51x User Manual 0: no effect 1: hold the I2C1 SMBUS timeout for debug w hen core halted I2C0_HOLD I2C0 hold bit This bit is set and reset by softw are 0: no effect 1: hold the I2C0 SMBUS timeout for debug w hen core halted 20:13 Reserved Must be kept at reset value...
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Page 357: Control Register 2 (Dbg_Ctl2)
GD32W51x User Manual 0: no effect 1: hold the TIMER1 counter for debugging w hen the core is halted. Control register 2 (DBG_CTL2) 13.4.4. Address offset: 0x0C Reset value: 0x0000 0000; power reset only This register has to be accessed by word(32-bit) TIMER16_ TIMER15_ Reserved... -
Page 358: Analog To Digital Converter (Adc)
GD32W51x User Manual Analog to digital converter (ADC) Overview 14.1. The 12-bit ADC is an analog-to-digital converter using the successive approximation method. The ADC includes 9 external channels, 2 internal channels and the battery voltage (V channel that can convert analog signals. Analog watchdog allows the application to detect whether the input voltage exceeds the user's set of high and low threshold. -
Page 359: Pins And Internal Signals
GD32W51x User Manual Oversampling ratio adjustable from 2x to 256x Programmable data shift up to 8-bits ADC supply requirements: 2.5V to 3.6V, and typical power supply voltage is 3.3V. ADC input range: 0 ≤ V ≤ Pins and internal signals 14.3. -
Page 360: Function Overview
GD32W51x User Manual Function overview 14.4. Figure 14-1. ADC module block diagram Trig select Trig select DMA request Regular Inserted channels channels EOIC Interrupt Interrupt RVOF Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Injected data registers （16 bits x 4） Over ADC_IN8 sampler... -
Page 361: Conversion Modes
GD32W51x User Manual In the regular group, a sequence of up to 9 conversions can be organized in a specific sequence. The ADC_RSQ0~ADC_RSQ2 registers specify the selected channels of the regular group. The RL[3:0] bits in the ADC_RSQ0 register specify the total conversion sequence length. -
Page 362: Figure 14-3. Continuous Conversion Mode
GD32W51x User Manual Configure ISQ3 with the analog channel number; Configure ADC_SAMPTx register; Configure the ETMIC and ETSIC bits in the ADC_CTL1 register if it is needed; Set the SWICST bit, or generate an external trigger for the inserted group; Wait for the EOC/ EOIC flags to be set;... -
Page 363: Figure 14-4. Scan Conversion Mode, Continuous Disable
GD32W51x User Manual specified in the ADC_RSQ0~ADC_RSQ2 registers or ADC_ISQ register. When the ADCON is 1, the ADC samples and converts specified channels one by one in the regular or inserted group till the end of the regular or inserted group, once the corresponding software trigger or external trigger is active. -
Page 364: Figure 14-5. Scan Conversion Mode, Continuous Enable
GD32W51x User Manual Figure 14-5. Scan conversion mode, continuous enable · · · CH11 CH11 Regular trigger One circle of regular group, RL=5 Discontinuous mode For regular channel group, the discontinuous conversion mode will be enabled when the DISRC bit in the ADC_CTL0 register is set. In this mode, the ADC performs a short sequence of n conversions (n<=8) which is a part of the sequence of conversions selected in the ADC_RSQ0~ADC_RSQ2 registers. -
Page 365: Inserted Channel Management
GD32W51x User Manual Configure DISNUM [2:0] bits in the ADC_CTL0 register; Configure ADC_RSQx and ADC_SAMPTx registers; Configure the ETMRC and ETSRC bits in the ADC_CTL1 register if it is needed; Prepare the DMA module to transfer data from the ADC_RDATA; Set the SWRCST bit, or generate an external trigger for the regular group;... -
Page 366: Analog Watchdog
GD32W51x User Manual conversion. Figure 14-8. Triggered insertion Analog watchdog 14.4.6. The analog watchdog is enabled when the RWDEN and IWDEN bits in the ADC_CTL0 register are set for regular and inserted channel groups respectively. When the analog voltage converted by the ADC is below the low threshold or above the high threshold, the WDE bit in ADC_STAT register will be set. -
Page 367: Programmable Sampling Time
GD32W51x User Manual Figure 14-9. Data alignment of 12-bit resolution Programmable sampling time 14.4.8. The number of ADC_CLK cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers. And each channel can specify different sampling times. -
Page 368: Table 14-4. External Trigger For Regular Channels Of Adc
GD32W51x User Manual Table 14-4. External trigger for regular channels of ADC ETSRC[3:0] Trigger source Trigger type 0000 TIMER0_CH0 0001 TIMER0_CH1 0010 TIMER0_CH2 0011 TIMER1_CH1 0100 TIMER1_CH2 0101 TIMER1_CH3 0110 TIMER1_TRGO 0111 TIMER2_CH0 Internal on-chip signal 1000 TIMER2_TRGO 1001 TIMER3_CH3 1010 TIMER4_CH0 1011... -
Page 369: Dma Request
GD32W51x User Manual DMA request 14.4.10. The DMA request is used to transfer data for conversion of more than one channel. The DMA request of regular channel is enabled by the DMA bit of ADC_CTL1 register. When this bit is set, the ADC generates a DMA request at the end of conversion of a regular channel. -
Page 370: On-Chip Hardware Oversampling
GD32W51x User Manual variations than absolute temperature. When it is used to detect accurate temperature, an external temperature sensor part should be used to calibrate the offset error. The internal reference voltage (V ) provides a stable (bandgap) voltage output for the REFINT ADC and comparators. -
Page 371: Figure 14-10. 20-Bit To 16-Bit Result Truncation
GD32W51x User Manual Figure 14-10. 20-bit to 16-bit result truncation Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated. Figure 14-11. A numerical example with 5-bit shifting and rounding shows a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. -
Page 372: Adc Interrupts
GD32W51x User Manual 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Oversa No-shift shift shift shift shift shift shift shift shift m pling OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= ratio data 0000 0001 0010 0011 0100 0101 0110 0111 1000... -
Page 373: Register Definition
GD32W51x User Manual Register definition 14.5. ADC secure access base address: 0x5001 2000 ADC non-secure access base address: 0x4001 2000 Status register (ADC_STAT) 14.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ROVF Reserved... -
Page 374: Control Register 0 (Adc_Ctl0)
GD32W51x User Manual Set by hardw are at the end of all inserted group channel conversion. Cleared by softw are writing 0 to it. End of group conversion flag 0: No end of group conversion 1: End of group conversion Set by hardw are at the end of a regular or inserted group channel conversion. - Page 375 GD32W51x User Manual 21:16 Reserved Must be kept at reset value. 15:13 DISNUM[2:0] Number of conversions in discontinuous mode The number of channels to be converted after a trigger w ill be DISNUM [2:0] +1 DISIC Discontinuous mode on inserted channels 0: Discontinuous mode on inserted channels disable 1: Discontinuous mode on inserted channels enable DISRC...
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Page 376: Control Register 1 (Adc_Ctl1)
GD32W51x User Manual 01011: ADC channel 11 Other values are reserved. Note: ADC analog inputs Channel 9, Channel 10 and Channel 11 are inter nally connected to the temperature sensor and V and V analog inputs. REFINT Control register 1 (ADC_CTL1) 14.5.3. - Page 377 GD32W51x User Manual 1100: TIMER4 CH2 1101: Reserved 1110: Reserved 1111: EXTI line 11 Reserved Must be kept at reset value. SWICST Softw are start on inserted channel. Setting 1 on this bit starts a conversion of a group of inserted channels. It is set by softw are and cleared by softw are or by hardw are after the conversion starts.
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Page 378: Sample Time Register 0 (Adc_Sampt0)
GD32W51x User Manual This bit configure the DMA disable mode for single ADC mode 0: The DMA engine is disabled after the end of transfer signal from DMA controller is detected. 1: When DMA=1, the DMA engine issues a request at end of each regular conversion. -
Page 379: Sample Time Register 1 (Adc_Sampt1)
GD32W51x User Manual 101: 111.5 cycles 110: 143.5 cycles 111: 479.5 cycles Sample time register 1 (ADC_SAMPT1) 14.5.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved SPT9[2:0] SPT8[2:0] SPT7[2:0] SPT6[2:0] SPT5[2:1] SPT5[0] SPT4[2:0] SPT3[2:0] SPT2[2:0]... -
Page 380: Inserted Channel Data Offset Register X (Adc_Ioffx) (X=0
GD32W51x User Manual Inserted channel data offset register x (ADC_IOFFx) (x=0..3) 14.5.6. Address offset: 0x14 + 0x04 * x (x=0..3) Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved IOFF [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. -
Page 381: Regular Sequence Register 0 (Adc_Rsq0)
GD32W51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved WDLT [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 WDLT[11:0] Analog w atchdog low threshold These bits define the low threshold for the analog w atchdog. Regular sequence register 0 (ADC_RSQ0) 14.5.9. -
Page 382: Regular Sequence Register 2 (Adc_Rsq2)
GD32W51x User Manual Reserved Reserved RSQ8[4:0] RSQ7[4:0] RSQ6[4:0] Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. 14:10 RSQ8[4:0] Refer to RSQ0[4:0] description RSQ7[4:0] Refer to RSQ0[4:0] description RSQ6[4:0] Refer to RSQ0[4:0] description Regular sequence register 2 (ADC_RSQ2) 14.5.11. -
Page 383: Inserted Sequence Register (Adc_Isq)
GD32W51x User Manual Inserted sequence register (ADC_ISQ) 14.5.12. Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved IL[1:0] ISQ3[4:1] ISQ3[0] ISQ2[4:0] ISQ1[4:0] ISQ0[4:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:20 IL[1:0] Inserted channel group length. -
Page 384: Regular Data Register (Adc_Rdata)
GD32W51x User Manual IDATAn [15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 IDATAn[15:0] Inserted number n conversion data These bits contain the number n conversion result, w hich is read only.. Regular data register (ADC_RDATA) 14.5.14. - Page 385 GD32W51x User Manual 31:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by softw are. 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio(OVSR[2:0]) Note: Softw are is allow ed to w rite this bit only w hen ADCON=0 (w hich ensures that no conversion is ongoing).
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Page 386: Commom Control Register (Adc_Cctl)
GD32W51x User Manual Commom control register (ADC_CCTL) 14.5.16. Address offset: 0x304 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). TSVREN VBATEN ADCCK[2:0] Reserved Reserved Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TSVREN Channel 9 (temperature sensor) and 10 (internal reference voltage) enable of ADC. -
Page 387: Watchdog Timer (Wdgt)
GD32W51x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy. -
Page 388: Figure 15-1. Free Watchdog Timer Block Diagram
GD32W51x User Manual Figure 15-1. Free watchdog timer block diagram The free watchdog timer is enabled by writing the value 0xCCCC to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value 0x000, there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at anytime. - Page 389 GD32W51x User Manual The FWDGT timeout can be more accurate by calibrating the IRC32K.
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Page 390: Register Definition
GD32W51x User Manual Register definition 15.1.4. FWDGT Secure access base address: 0x5000 3000 FWDGT Non-Secure access base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved CMD[15:0] Bits... - Page 391 GD32W51x User Manual before w riting these bits. During a w rite operation to this register, the PUD bit in the FWDGT_STAT register is set and the value read from this register is invalid. 000: 1/4 001: 1/8 010: 1/16 011: 1/32 100: 1/64 101: 1/128...
- Page 392 GD32W51x User Manual This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free w atchdog timer counter reload value update During a w rite operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
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Page 393: Window Watchdog Timer (Wwdgt)
GD32W51x User Manual 15.2. Window watchdog timer (WWDGT) Overview 15.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared). -
Page 394: Figure 15-2. Window Watchdog Timer Block Diagram
GD32W51x User Manual Figure 15-2. Window watchdog timer block diagram PCLK1/4096 Prescaler /1/2/4/8 7-Bit Down Counter CNT[6]=0 WDGTEN Reset CNT>WIN Reset Window WIN Write WWDGT_CTL The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. -
Page 395: Figure 15-3. Window Watchdog Timing Diagram
GD32W51x User Manual Figure 15-3. Window watchdog timing diagram Calculate the WWDGT timeout by using the formula below. ×4096 ×2 × ( CNT [ 5:0 ] +1 ) (ms) (13-1) WWDGT PCLK1 where: : WWDGT timeout WWDGT : APB1 clock period measured in ms PCLK1 The table below shows the minimum and maximum values of the t WWDGT... -
Page 396: Register Definition
GD32W51x User Manual Register definition 15.2.4. WWDGT Secure access base address: 0x5000 2C00 WWDG Non-Secure access base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved WDGTEN CNT[6:0]... - Page 397 GD32W51x User Manual EWIE Early w akeup interrupt enable. If the bit is set, an interrupt occurs w hen the counter reaches 0x40. It can be cleared by a hardw are reset or softw are clock reset (refer 错误 未找到引用源。 ).
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Page 398: Real Time Clock (Rtc)
GD32W51x User Manual Real time clock (RTC) 16.1. Overview The RTC provides a time which includes hour/minute/second/sub-second and a calendar includes year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time. Working in power saving mode and smart wakeup is software configurable. -
Page 399: Function Overview
GD32W51x User Manual 16.3. Function overview Block diagram 16.3.1. Figure 16-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre (Default 1 Hz) IRC32K 7-bit... -
Page 400: Clock Source And Prescalers
GD32W51x User Manual Clock source and prescalers 16.3.2. RTC unit has three independent clock sources: LXTAL, IRC32K and HXTAL with divided by 2~31(configured in RCU_CFG register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions. -
Page 401: Configurable Periodic Auto-Wakeup Counter
GD32W51x User Manual If a field is masked, the field is considered as matched in logic. If all the fields have been masked, the Alarm Flag will assert 3 RTC clock later after ALRMxEN is set. Configurable periodic auto-wakeup counter 16.3.5. - Page 402 GD32W51x User Manual The registers protected by INITPRIP are write-protected by the INIT KEY. The registers protected by CALDPRIV are write-protected by the CAL KEY. In case RTCPRIP or INITPRIP is set in the RTC_PPM_CTL, and/or DPROT or INITSECP is cleared in the RTC_SPM_CTL: the INIT KEY is unlocked and locked only if the write accesses into the RTC_ WPK register are done in the privilege and security mode defined by RTCPRIP, INITPRIP, DPROT, INITSECP configuration.
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Page 403: Calendar Reading
GD32W51x User Manual Set the Alarm registers needed(RTC_ALRMxTD/RTC_ALRMxSS) Enable Alarm function (by setting ALRMxEN in the RTC_CTL) Calendar reading 16.3.7. Reading calendar registers under BPSHAD=0 When BPSHAD=0, calendar value is read from shadow registers. For the existence of synchronization mechanism, a basic request has to meet: the APB1 bus clock frequency must be equal to or greater than 7 times the RTC clock frequency.APB1 bus clock frequency lower than RTC clock frequency is not allowed in any case whatever happens. -
Page 404: Resetting The Rtc
GD32W51x User Manual calendar counter directly. The benefit of this configuration is that software can get the real current time without any delay after wakeup from power saving mode (Deep-sleep /Standby Mode). Because of no RSYNF bit periodic assertion, the results of the different calendar registers (RTC_SS/RTC_TIME/RTC_DATE) might not be coherent with each other when clock ck_apre edge occurs between two reading calendar registers. -
Page 405: Rtc Reference Clock Detection
GD32W51x User Manual counter SSC[15:0] or by adding the SFS[14:0] value to the synchronous prescaler counter SSC[15:0] and at the same time set A1S bit can delay or advance the time when next second arrives. The maximal RTC_SS value depends on the FACTOR_S value in RTC_PSC. The higher FACTOR_S, the higher adjust precision. -
Page 406: Rtc Coarse Digital Calibration
GD32W51x User Manual Note: Software must configure the FACTOR_A=0x7F and FACTOR_S=0xFF before enabling reference detection function (REFEN=1) Reference detection function does not work in Standby Mode and must not be used with coarse digital function. RTC coarse digital calibration 16.3.11. There are two digital methods can be chose for calibration: coarse digital calibration and smooth digital calibration. - Page 407 GD32W51x User Manual This calibration is equally executed in a period time and the cycle number of the RTC clock in the period time will be added or subtracted. The resolution of the calibration is about 0.954PPM with the range from -487.1PPM to +488.5PPM. The calibration period time can be configured to the 220/219/218 RTC clock cycles which stands for 32/16/8 seconds if RTC input frequency is 32.768 KHz.
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Page 408: Time-Stamp Function
GD32W51x User Manual Verifying the RTC calibration Calibration 1Hz output is provided to assist software to measure and verify the RTC precision. Up to 2 RTC clock cycles measurement error may occur when measuring the RTC frequency over a limited measurement period. To eliminate this measurement error the measurement period should be the same as the calibration period. -
Page 409: Tamper Detection
GD32W51x User Manual Tamper detection 16.3.14. The RTC_TAMPx pin input can be used for tamper event detection under edge detection mode or level detection mode with configurable filtering setting. RTC backup registers (RTC_BKPx) The RTC backup registers are located in the VDD backup domain that remains powered-on by V even if V power is switched off. -
Page 410: Calibration Clock Output
GD32W51x User Manual Level detection mode with configurable filtering on tamper input detection When FLT bit is not reset to 0x0, the tamper detection is set to level detection mode and FLT bit determines the consecutive number of samples (2, 4 or 8) needed for valid level. When DISPU is set to 0x0(this is default), the internal pull-up resistance will pre-charge the tamper input pin before each sampling and thus larger capacitance is allowed to connect to the tamper input pin. -
Page 411: Table 16-1. Rtc Register Secure Access Rules
GD32W51x User Manual Table 16-1. RTC register secure access rules Read Write Access m ode Secure access Nonsecure access Secure access Nonsecure access Allow ed access RTC_SPM_CTL, RTC_PPM_CTL, Allow ed(except for Allow ed(except for RTCSECP = RTC_NSMI_STA T, the backup the backup Not allow ed RTC_TIME,... - Page 412 GD32W51x User Manual Configuration bit in Read in non-secure Write in secure m ode Read in secure m ode RTC_SPM_CTL m ode ALRM0FC in RTC_CTL; RTC_STATC; ALRM0FC in the ALRM0F in RTC_STA T; RTC_STATC;ALRM0F ALRM0SMF in in RTC_STAT; RTC_SMI_STAT; ALRM0SMF in ALRM0SECP in RTC_SMI_STAT.
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Page 413: Rtc Privilege Protection
GD32W51x User Manual Configuration bit in Read in non-secure Write in secure m ode Read in secure m ode RTC_SPM_CTL m ode Allow ed access RTC_TAMP register, Allow ed access except for the AOT bit; RTC_TAMP register, TPxFC in RTC_STATC, except for the AOT bit;... -
Page 414: Table 16-4. Rtc Privileged Protected Mode Configuration Summary
GD32W51x User Manual The summary of the RTC privileged protected bits in RCU_PPM_CTL register is show as Table 16-4. RTC privileged protected mode configuration summary. Table 16-4. RTC privileged protected mode configuration summary Configuration bit Read in non-privilege Write in privilege m ode Read in privilege m ode in RTC_PPM_CTL m ode Allow ed access... - Page 415 GD32W51x User Manual Configuration bit Read in non-privilege Write in privilege m ode Read in privilege m ode in RTC_PPM_CTL m ode RTC_STATC, ALRM1F in RTC_STATC, ALRM1F in RTC_STAT, RTC_STAT, ALRM1NSMF in ALRM1NSMF in RTC_NSMI_STA T ; RTC_NSMI_STA T ; ALRM1SMF in ALRM1SMF in RTC_SMI_STAT;...
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Page 416: Rtc Backup Registers Protection
GD32W51x User Manual Configuration bit Read in non-privilege Write in privilege m ode Read in privilege m ode in RTC_PPM_CTL m ode TAMPPRIP in RTC_ RTC_PPM_CTL. By default, after the backup domain is powered on and reset, except for the RTC_PPM_CTL register, all other RTC registers can be read and written in privilege and unprivilege modes. -
Page 417: Rtc Power Saving Mode Management
GD32W51x User Manual with non-secure access. RTC power saving mode management 16.3.20. Table 16-5. RTC power saving mode management Mode Active in Mode Exit Mode Sleep RTC Interrupts Deep- Yes: if clock source is LXTAL or RTC Alarm / Tamper Event / Timestamp Event / Sleep IRC32K Wake up... -
Page 418: Table 16-7. Rtc Secure Interrupts Control
GD32W51x User Manual RTCSECP=1) TPxIE and(TAMPSECP=1 Write 1 in Tamper x TPxF TPxFC RTCSECP=1) NOTE: (*)Only active when RTC clock source is LXTAL or IRC32K. Table 16-7. RTC secure interrupts control Exit deep- Clear interrupt Interrupt Event flag Control bit Exit sleep sleep and flag... -
Page 419: Register Definition
GD32W51x User Manual 16.4. Register definition RTC secure access base address: 0x5000 2800 RTC non-secure access base address: 0x4000 2800 Time register (RTC_TIME) 16.4.1. Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state This register can be write-protected to prevent non-secure access or non-privileged access This register has to be accessed by word (32-bit) -
Page 420: Control Register (Rtc_Ctl)
GD32W51x User Manual Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state This register can be write-protected to prevent non-secure access or non-privileged access This register has to be accessed by word (32-bit) Reserved YRT[3:0] YRU[3:0]... - Page 421 GD32W51x User Manual Bits Fields Descriptions RTC_OUT pin select OUT2EN 0: RTC_OUT output to PC15 1: RTC_OUT output to P A3 or P A8 30:24 Reserved Must be kept at reset value. COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0]...
- Page 422 GD32W51x User Manual WTIE Auto-w akeup timer interrupt enable 0: Disable auto-w akeup timer interrupt 1: Enable auto-w akeup timer interrupt ALRM1IE RTC alarm-1 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt ALRM0IE RTC alarm-0 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt TSEN Time-stamp function enable...
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Page 423: Initialization Control And Status Register (Rtc_Icsr)
GD32W51x User Manual Note: Can only be w ritten in initialization state and FACTOR_S must be 0x00FF TSEG Valid event edge of time-stamp 0: rising edge is valid event edge for time-stamp event 1: falling edge is valid event edge for time-stamp event WTCS[2:0] Auto-w akeup timer clock selection 0x0:RTC Clock divided by 16... -
Page 424: Prescaler Register (Rtc_Psc)
GD32W51x User Manual this state. 0: Calendar registers and prescaler register cannot be changed 1: Calendar registers and prescaler register can be changed RSYNF Register synchronization flag Set to 1 by hardw are every 2 RTCCLK w hich w ill copy current calendar time/date into shadow register. -
Page 425: Wakeup Timer Register (Rtc_Wut)
GD32W51x User Manual Reserved FACTOR_S[14:0] Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. 22:16 FACTOR_A[6:0] Asynchronous prescaler factor ck_apre frequency = RTCCLK frequency/(FACTOR_A+1) Reserved Must be kept at reset value. 14:0 FACTOR_S[14:0] Synchronous prescaler factor ck_spre frequency = ck_apre frequency/(FACTOR_S+1) Wakeup timer register (RTC_WUT) 16.4.6. -
Page 426: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32W51x User Manual This register can be write-protected to prevent non-secure access or non-privileged access This register has to be accessed by word (32-bit) Reserved Reserved COSD Reserved COSS[4:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. COSD Coarse Calibration direction 0: Increase calendar update frequency... -
Page 427: Alarm 1 Time And Date Register (Rtc_Alrm1Td)
GD32W51x User Manual MSKM MNT[2:0] MNU[3:0] MSKS SCT[2:0] SCU[3:0] Bits Fields Descriptions MSKD Alarm date mask bit 0: Not mask date/day field 1: Mask date/day field DOWS Day of the w eek selected 0: DAYU[3:0] indicates the date units 1: DAYU[3:0] indicates the w eek day and DAYT[1:0] has no means. 29:28 DAYT[1:0] Date tens in BCD code... - Page 428 GD32W51x User Manual This register can be write-protected to prevent non-secure access or non-privileged access This register has to be accessed by word (32-bit) MSKD DOWS DAYT[1:0] DAYU[3:0] MSKH HRT[1:0] HRU[3:0] MSKM MNT[2:0] MNU[3:0] MSKS SCT[2:0] SCU[3:0] Bits Fields Descriptions MSKD Alarm date mask bit 0: Not mask date/day field...
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Page 429: Write Protection Key Register (Rtc_Wpk)
GD32W51x User Manual Write protection key register (RTC_WPK) 16.4.10. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved WPK[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. WPK[7:0] Key for w rite protection Sub second register (RTC_SS) 16.4.11. -
Page 430: Time Of Time Stamp Register (Rtc_Tts)
GD32W51x User Manual This register can be write-protected to prevent non-secure access or non-privileged access This register has to be accessed by word (32-bit) Reserved Reserved SFS[14:0] Bits Fields Descriptions One second add 0: Not add 1 second 1: Add 1 second to the clock/calendar. This bit is jointly used w ith SFS field to add a fraction of a second to the clock. -
Page 431: Date Of Time Stamp Register (Rtc_Dts)
GD32W51x User Manual AM/PM mark 0:AM or 24-hour format 1:PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code Reserved Must be kept at reset value. 14:12 MNT[2:0] Minute tens in BCD code 11:8 MNU[3:0] Minute units in BCD code Reserved Must be kept at reset value. -
Page 432: Sub Second Of Time Stamp Register (Rtc_Ssts)
GD32W51x User Manual Sub second of time stamp register (RTC_SSTS) 16.4.15. Address offset: 0x38 Backup domain reset: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1. Reset TSF bit will also clear this register. This register can be write-protected to prevent non-secure access or non-privileged access This register has to be accessed by word (32-bit) Reserved... -
Page 433: Tamper Register (Rtc_Tamp)
GD32W51x User Manual 32.768KHz, the number of RTCCLK pulses added during 32s calibration w indow is (512 * FREQI) - CMSK CWND8 Frequency compensation w indow 8 second selected 0: No effect 1: Calibration w indow is 8 second Note: When CWND8=1, CMSK[1:0] are stuck at “00”. CWND16 Frequency compensation w indow 16 second selected 0: No effect... - Page 434 GD32W51x User Manual 1: Tamper 0 event does not erase the backup registers RTC_ALARM Output Type 0: Open-drain output type 1: Push-pull output type 17:16 Reserved Must be kept at reset value. DISPU RTC_TAMPx pull up disable bit 0: Enable inner pull-up before sampling for pre-charge RTC_TAMPx pin 1: Disable pre-charge duration 14:13 PRCH[1:0]...
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Page 435: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32W51x User Manual TP1EG Tamper 1 event trigger edge If tamper detection is in edge mode(FLT =0): 0: Rising edge triggers a tamper detection event 1: Falling edge triggers a tamper detection event If tamper detection is in level mode(FLT !=0): 0: Low level triggers a tamper detection event 1: High level triggers a tamper detection event TP1EN... -
Page 436: Alarm 1 Sub Second Register (Rtc_Alrm1Ss)
GD32W51x User Manual 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched. 0x1: SSC[0] is to be compared and all others are ignored 0x2: SSC[1:0] is to be compared and all others are ignored 0x3: SSC[2:0] is to be compared and all others are ignored... -
Page 437: Privilege Protection Mode Control Register (Rtc_Ppm_Ctl)
GD32W51x User Manual 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched. 0x1: SSC[0] is to be compared and all others are ignored 0x2: SSC[1:0] is to be compared and all others are ignored 0x3: SSC[2:0] is to be compared and all others are ignored... - Page 438 GD32W51x User Manual When set, backup registers zone B can be w ritten only w hen the APB access is in privileged mode, otherw ise both APB access is in privileged and non-privileged mode can w ritten backup domain registers. BKPRWPRIP Backup registers zone A privilege protection When set, backup registers zone A can be read and w ritten only w hen the APB...
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Page 439: Secure Protection Mode Control Register (Rtc_Spm_Ctl)
GD32W51x User Manual non-privileged mode can be w ritten the above configuration. ALRM0PRIP Alarm 0 privilege protection When set, Alarm 0 configuration and interrupt clear can be w ritten only w hen the APB access is in privileged mode, otherw ise w hether APB access is in privileged or non-privileged mode can be w ritten the above configuration. -
Page 440: Status Register (Rtc_Stat)
GD32W51x User Manual When set, all RTC registers can be w ritten only w hen the APB access is in secure ed mode, otherw ise w hether APB access is in secured or non- secured mode can be w ritten all RTC registers (except the registers protected by other secure protection bits). -
Page 441: Non-Secure Masked Interrupt Status Register (Rtc_Nsmi_Stat)
GD32W51x User Manual System reset: no effect This register can be protected globally or individually per bit can be configured to prevent non-secure access or non-privileged access.. This register has to be accessed by word (32-bit) Reserved TP1F TP0F Reserved TSOVRF ALRM1F ALRM0F Bits... -
Page 442: Secure Masked Interrupt Status Register (Rtc_Smi_Stat)
GD32W51x User Manual Backup domain reset: 0x0000 0000 System reset: no effect This register can be protected globally or individually per bit can be configured to prevent non-privileged access. This register has to be accessed by word (32-bit) TP0NSM Reserved TP1NSMF TSOVRN ALRM1N... -
Page 443: Status Flag Clear Register (Rtc_Statc)
GD32W51x User Manual This register can be protected globally or individually per bit can be configured to prevent non-secure access or non-privileged access. This register has to be accessed by word (32-bit) Reserved TP1SMF TP0SMF TSOVRS ALRM1S ALRM0S Reserved TSSMF WTSMF Bits Fields... -
Page 444: Backup Registers (Rtc_Bkpx) (X=0
GD32W51x User Manual This register has to be accessed by word (32-bit) Reserved TP1FC TP0FC TSOVRF ALRM1F ALRM0F Reserved TSFC WTFC Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. TP1FC TAMP1 detection flag clear Writing 1 in this bit clears the TP1F bit in the RTC_STAT register. TP0FC TAMP0 detection flag clear Writing 1 in this bit clears the TP0F bit in the RTC_STAT register. - Page 445 GD32W51x User Manual Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be w rote or read by softw are. The content remains valid even in pow er saving mode because they can pow ered-on by V . Tamper detection flag TPxF assertion w ill reset these registers.
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Page 446: Timer (Timerx)
GD32W51x User Manual Timer (TIMERx) Table 17-1. Timers (TIMERx) are divided into four sorts TIMER TIMER0 TIMER1/2/3/4 TIMER15/16 TIMER5 TYPE Advanced General-L0 General-L4 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 32-bit(TIMER1/2) Counter 16-bit 16-bit 16-bit 16-bit(TIMER3/4) UP,DOWN, UP,DOWN, Count m ode UP ONLY UP ONLY Center-aligned... -
Page 447: Advanced Timer (Timerx, X=0)
GD32W51x User Manual Advanced timer (TIMERx, x=0) 17.1. Overview 17.1.1. The advanced timer module (Timer0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. -
Page 448: Block Diagram
GD32W51x User Manual Block diagram 17.1.3. Figure 17-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 17-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2... -
Page 449: Figure 17-2. Normal Mode, Internal Clock Divided By 1
GD32W51x User Manual sources selected by the TRGS [2:0] in the TIMERx_SMCFG register, details as follows. When the slave mode selection bits SMC [2:0] are set to 0x4, 0x5 or 0x6, the internal clock TIMER_CK is the counter prescaler driving clock source. Figure 17-2. -
Page 450: Figure 17-3. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32W51x User Manual be changed on the go but is taken into account at the next update event. Figure 17-3. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB FC Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode... -
Page 451: Figure 17-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32W51x User Manual Figure 17-4. Timing chart of up counting mode, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 17-5. -
Page 452: Figure 17-6. Timing Chart Of Down Counting Mode, Psc=0/1
GD32W51x User Manual Down counting mode In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter restarts to count again from the counter-reload value. If the repetition counter is set, the update event will be generated after (TIMERx_CREP+1) times of underflow. -
Page 453: Figure 17-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32W51x User Manual Figure 17-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set... -
Page 454: Figure 17-8. Timing Chart Of Center-Aligned Counting Mode
GD32W51x User Manual prescaler register) are updated. Figure 17-8. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0 Figure 17-8. Timing chart of center-aligned counting mode TIMER_CK CNT_CLK (PSC_CLK) CNT_REG Underflow Overflow UPIF TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only... -
Page 455: Figure 17-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32W51x User Manual starting the counter. Figure 17-9. Repetition counter timing chart of center-aligned counting mode TIMER_CK CNT_CLK Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Figure 17-10. Repetition counter timing chart of up counting mode TIMER_CK CNT_CLK 61 62 63 00 01... -
Page 456: Figure 17-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32W51x User Manual Figure 17-11. Repetition counter timing chart of down counting mode TIMER_CK CNT_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Capture/compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs. -
Page 457: Figure 17-12. Input Capture Logic
GD32W51x User Manual Figure 17-12. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Prescaler Register Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2... -
Page 458: Figure 17-13. Output Compare Logic (With Complementary Output, X=0,1,2)
GD32W51x User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. -
Page 459: Figure 17-15. Output-Compare In Three Modes
GD32W51x User Manual (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;... - Page 460 GD32W51x User Manual Figure 17-15. Output-compare in three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
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Page 461: Figure 17-16. Timing Chart Of Eapwm
GD32W51x User Manual Figure 17-16. Timing chart of EAPWM Figure 17-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output reference signal Figure 17-13. - Page 462 GD32W51x User Manual the CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
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Page 463: Table 17-2. Complementary Outputs Controlled By Parameters
GD32W51x User Manual Table 17-2. Complementary outputs controlled by parameters Com plem entary Param eters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable: CHx_O = ISOx CHx_ON = ISOxN CHx_O = CHxP CHx_ON = CHxNP... -
Page 464: Figure 17-18. Complementary Output With Dead-Time Insertion
GD32W51x User Manual The dead time delay insertion ensures that no two complementary signals drive the active state at the same time. When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled Figure 17-18. Complementary output with because under PWM0 mode. -
Page 465: Figure 17-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32W51x User Manual TIMERx_CTL1 register as soon as POEN is 0. If IOS is 0 then the timer releases the enable output else the enable output remains high. The complementary outputs are first put in reset state, and then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead-time. -
Page 466: Figure 17-20. Example Of Counter Operation In Encoder Interface Mode
GD32W51x User Manual Table 17-3. Counting direction versus encoder signals CI0FE0 CI1FE1 Counting m ode Level Rising Falling Rising Falling CI0 only CI1FE1=High Dow n counting CI1FE1=Low Dow n CI1 only CI0FE0=High Dow n counting CI0FE0=Low Dow n CI1FE1=High Dow n CI0 and CI1 CI1FE1=Low Dow n... -
Page 467: Figure 17-22. Hall Sensor I S Used To Bldc Motor
GD32W51x User Manual Figure 17-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in（Advanced/General L0 TIMER） should accept three Rotor Position signals from Motor. Each of the 3 sensors provides a pulse that applied to an input capture pin, can then be analyzed and both speed and position can be deduced. -
Page 468: Figure 17-23. Hall Sensor Timing Between Two Timers
GD32W51x User Manual Figure 17-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Slave controller The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register. -
Page 469: Figure 17-24. Restart Mode
GD32W51x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 101: CI0FE0 If ETIFP is selected as prescaler can be 110: CI1FE1 the trigger source, used. 111: ETIFP configure the ETP for For the ETIFP, filter polarity selection and can be used by inversion. -
Page 470: Figure 17-26. Event Mode
GD32W51x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Event m ode ETPSC = 1, ETI is The counter w ill start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2. to count w hen a rising of ETI does not ETIFP is selected. -
Page 471: Figure 17-27. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32W51x User Manual Figure 17-27. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 Timers interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode. -
Page 472: Figure 17-29. Trigger Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32W51x User Manual Figure 17-28. Timer0 TIMER2 is configured as a prescaler for TIMER0. Refer to master/slave mode example for connections. Steps are shown as follows: Configure TIMER2 in master mode and select its update event (UPE) as trigger output (MMC=3’b010 in the TIMER2_CTL1 register). -
Page 473: Figure 17-30. Trigger Mode Of Timer0 Controlled By Update Signal Of Timer2
GD32W51x User Manual Configure TIMER2 in master mode to send its update event (UPE) as trigger output (MMC=3’b010 in the TIMER2_CTL1 register). Configure the TIMER2 period (TIMER2_CARL registers). Select TIMER2 as TIMER0 input trigger source (TRGS=3’b010 in the TIMERx_SMCFG register). Configure TIMER0 in event mode (SMC=3’b110 in TIMERx_SMCFG register). -
Page 474: Figure 17-31. Pause Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32W51x User Manual Figure 17-31. Pause mode of TIMER0 controlled by enable signal of TIMER2 In this example, O0CPRE can also be used as trigger source instead of enable signal output. Steps are shown as follows: Configure TIMER2 in master mode and O0CPRE as trigger output (MMS=3’b100 in the TIMER2_CTL1 register). -
Page 475: Figure 17-33. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32W51x User Manual Configure TIMER2 in master/slave mode by writing MSM=1 (TIMER2_SMCFG register). Select TIMER2 as TIMER0 input trigger source (TRGS=3’b010 in the TIMERx_SMCFG register). Configure TIMER0 in event mode (SMC=3’b110 in the TIMER0_SMCFG register). When the CI0 signal of TIMER2 generates a rising edge, two timer counters start counting synchronously with the internal clock and both TRGIF flags are set. - Page 476 GD32W51x User Manual If one more DMA request event occurs, TIMERx will repeat the process above. Timer debug mode When the Cortex™-M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register is set to 1, the TIMERx counter stops.
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Page 477: Timerx Registers(X=0)
GD32W51x User Manual TIMERx registers(x=0) 17.1.5. TIMER0 secure access base address: 0x5001 0000 TIMER0 non-secure access base address: 0x4001 0000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0]... - Page 478 GD32W51x User Manual can be set. 11: Center-aligned and counting up/dow n assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 TIMERx_CHCTL0 register). Both w hen the counter is counting up and counting dow n, compare interrupt flag of channels can be set. After the counter is enabled, cannot be sw itched from 0x00 to non 0x00.
- Page 479 GD32W51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit...
- Page 480 GD32W51x User Manual generated by the slave mode controller, a TRGO pulse occurs. And in the latter case, the signal on TRGO is delayed compared to the actual reset. 001: Enable. This mode is useful to start several timers at the same time or to control a w indow in w hich a slave timer is enabled.
- Page 481 GD32W51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge.
- Page 482 GD32W51x User Manual 0011: f , N=8. SAMP CK_TIMER 0100: f /2, N=6. SAMP 0101: f /2, N=8. SAMP 0110: f /4, N=6. SAMP 0111: f /4, N=8. SAMP 1000: f /8, N=6. SAMP 1001: f /8, N=8. SAMP 1010: f /16, N=5.
- Page 483 GD32W51x User Manual updated on the rising edge of the selected trigger input. 101: Pause mode. The trigger input enables the counter clock w hen it is high and disables the counter w hen it is low . 110: Event mode. A rising edge of the trigger input enables the counter. The counter cannot be disabled by the slave mode controller.
- Page 484 GD32W51x User Manual 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE...
- Page 485 GD32W51x User Manual Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description...
- Page 486 GD32W51x User Manual Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardw are and cleared by softw are. When channel 0 is in input mode, this flag is set w hen a capture event occurs.
- Page 487 GD32W51x User Manual 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by softw are and cleared by hardw are automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
- Page 488 GD32W51x User Manual CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output com pare m ode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0]...
- Page 489 GD32W51x User Manual 011: Toggle on match. O0CPRE toggles w hen the counter matches the output compare register TIMERx_CH0CV. 100: Force low . O0CPRE is forced low level. 101: Force high. O0CPRE is forced high level. 110: PWM mode0. When counting up, O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV else inactive.
- Page 490 GD32W51x User Manual only if an internal trigger input is selected through TRGS bits in TIMERx_S MCF G register. Input capture m ode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0]...
- Page 491 GD32W51x User Manual Same as Output compare mode Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0]...
- Page 492 GD32W51x User Manual ETIF input. 0: Channel 2 output compare clear disable 1: Channel 2 output compare clear enable CH2COMCTL[2:0] Channel 2 compare output control This bit-field controls the behavior of the output reference signal O2CPRE w hich drives CH2_O and CH2_ON. O2CPRE is active high, w hile CH2_O and CH2_ON active level depends on CH2P and CH2NP bits.
- Page 493 GD32W51x User Manual compare match, and CH2_O is set to the compare level independently from the result of the comparison. 0: Channel 2 output quickly compare disable. The minimum delay from an edge on the trigger input to activate CH2_O output is 5 clock cycles. 1: Channel 2 output quickly compare enable.
- Page 494 GD32W51x User Manual 1011: f /16, N=6 SAMP 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset w hen CH2EN bit in TIMERx_CHCTL2 register is clear.
- Page 495 GD32W51x User Manual Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description CH1NEN Channel 1 complementary output enable Refer to CH0NEN description CH1P Channel 1 capture/compare function polarity...
- Page 496 GD32W51x User Manual [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CIxFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode. And CIxFE0 w ill be not inverted. This bit cannot be modified w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
- Page 497 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed w ill be loaded to the corresponding shadow register at every update event.
- Page 498 GD32W51x User Manual CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting dow n to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed w hen these shadow registers are enabled.
- Page 499 GD32W51x User Manual 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
- Page 500 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
- Page 501 GD32W51x User Manual This bit specifies the polarity of the BRKIN input signal. 0: BRKIN input active low 1; BRKIN input active high BRKEN Break enable This bit can be set to enable the BRKIN and CCS clock failure event inputs. 0: Break inputs disabled 1;...
- Page 502 GD32W51x User Manual This bit-field controls the value of the dead-time, w hich is inserted before the output transitions. The relationship betw een DTCFG value and the duration of dead-time is as follow : DTCFG [7:5] =3’b0xx: DTvalue =DTCFG [7:0]x t DTCFG [7:5] =3’b 10x: DTvalue = (64+DTCFG [5:0])xt DTCFG [7:5] =3’b 110: DTvalue = (32+DTCFG [4:0])xt DTCFG [7:5] =3’b 111: DTvalue = (32+DTCFG [4:0])xt...
- Page 503 GD32W51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or w rite operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) w ill be accessed.
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Page 505: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32W51x User Manual General level0 timer (TIMERx, x=1, 2, 3, 4) 17.2. Overview 17.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications. -
Page 506: Function Overview
GD32W51x User Manual Figure 17-34. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Trigger processor Input logic PSC_CLK Trigger Selector&Counter Polarity selection TIMER_CK Quadrate Decoder DMA REQ/ ACK... -
Page 507: Figure 17-35. Normal Mode, Internal Clock Divided By 1
GD32W51x User Manual Figure 17-35. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111( external clock mode 0 ). External input pin source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1. -
Page 508: Figure 17-36. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32W51x User Manual Figure 17-36. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB FC Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. -
Page 509: Figure 17-37. Timing Chart Of Up Counting Mode, Psc=0/1
GD32W51x User Manual Figure 17-37. Timing chart of up counting mode, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 17-38. -
Page 510: Figure 17-39. Timing Chart Of Down Counting Mode,Psc=0/1
GD32W51x User Manual Down counting mode In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter restarts to count again from the counter-reload value. If the repetition counter is set, the update event was generated after the number (TIMERx_CREP+1) of underflow. -
Page 511: Figure 17-40. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32W51x User Manual Figure 17-40. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set... -
Page 512: Figure 17-41. Timing Chart Of Center-Aligned Counting Mode
GD32W51x User Manual When an update event occurs, all the registers (repetition counter, auto reload register, prescaler register) are updated. Figure 17-41. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0 Figure 17-41. Timing chart of center-aligned counting mode TIMER_CK CNT_CLK (PSC_CLK) -
Page 513: Figure 17-42. Input Capture Logic
GD32W51x User Manual at the same time the CHxIF bit is set and the channel interrupt is generated if enabled by CHxIE = 1. Figure 17-42. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling... -
Page 514: Figure 17-43. Output Compare Logic (X=0,1,2,3)
GD32W51x User Manual and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly. The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. -
Page 515: Figure 17-44. Output-Compare In Three Modes
GD32W51x User Manual Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. -
Page 516: Figure 17-46. Timing Chart Of Capwm
GD32W51x User Manual The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by Figure 17-46. Timing chart of CAPWM 2*TIMERx_CHxCV. shows the CAPWM output and interrupts waveform. If TIMERx_CHxCV is greater than TIMERx_CAR, the output will be always active under PWM mode0 (CHxCOMCTL==3’b110). -
Page 517: Table 17-5. Counting Direction Versus Encoder Signals
GD32W51x User Manual Channel output reference signal (x=0,1,2,3), when the TIMERx is used As is shown in Figure 17-43. Output compare logic in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function. -
Page 518: Figure 17-47. Example Of Counter Operation In Encoder Interface Mode
GD32W51x User Manual counting CI0FE0=Low Dow n CI1FE1=High Dow n CI0 and CI1 CI1FE1=Low Dow n counting CI0FE0=High Dow n CI0FE0=Low Dow n "-" means "no counting"; "X" means impossible. Note: Figure 17-47. Example of counter operation in encoder interface mode Figure 17-48. -
Page 519: Figure 17-49. Restart Mode
GD32W51x User Manual Table 17-6. Examples of slave mode Mode Selection Source Selection Polarity Selection Filter and Prescaler For the ITIx, no filter If CI0FE0 or CI1FE1 is and prescaler can be TRGS[2:0] selected as the trigger used. 000: ITI0 source, configure the For the CIx, filter can 001: ITI1... -
Page 520: Figure 17-50. Pause Mode
GD32W51x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 17-50. Pause m ode TIMER_CK CNT_REG CI0FE0 TRGIF Event m ode ETPSC = 1, ETI is The counter w ill start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2. -
Page 521: Figure 17-52. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32W51x User Manual In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0/1 register. - Page 522 GD32W51x User Manual Timer debug mode When the Cortex™-M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
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Page 523: Timerx Registers(X=1, 2, 3, 4)
GD32W51x User Manual TIMERx registers(x=1, 2, 3, 4) 17.2.5. TIMER1 secure access base address: 0x5000 0000 TIMER1 non-secure access base address: 0x4000 0000 TIMER2 secure access base address: 0x5000 0400 TIMER2 non-secure access base address: 0x4000 0400 TIMER3 secure access base address: 0x5000 0800 TIMER3 non-secure access base address: 0x4000 0800 TIMER4 secure access base address: 0x5000 0C00 TIMER4 non-secure access base address: 0x4000 0C00... - Page 524 GD32W51x User Manual TIMERx_CHCTL0 register). Only w hen the counter is counting dow n, compar e interrupt flag of channels can be set. 10: Center-aligned and counting up assert mode. The counter counts under center - aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCT L0 register).
- Page 525 GD32W51x User Manual The CEN bit must be set by softw are w hen timer w orks in external clock, pause mode and encoder mode. While in event mode, the hardw are can set the CEN bit automatically. Control register 1 (TIMERx_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
- Page 526 GD32W51x User Manual is used as TRGO 110: Compare. In this mode the master mode controller selects the O2CPRE signal is used as TRGO 111: Compare. In this mode the master mode controller selects the O3CPRE signal is used as TRGO DMAS DMA request source selection 0: DMA request of channel x is sent w hen channel x event occurs.
- Page 527 GD32W51x User Manual TIMER_CK frequency. When the external trigger signal is a fast clock, the prescaler can be enabled to reduce ETI frequency. 00: Prescaler disable 01: ETI frequency w ill be divided by 2 10: ETI frequency w ill be divided by 4 11: ETI frequency w ill be divided by 8 11:8 ETFC[3:0]...
- Page 528 GD32W51x User Manual 111: External trigger input filter output(ETIFP) These bits must not be changed w hen slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) w hen CEN bit is set high.
- Page 529 GD32W51x User Manual 0: disabled 1: enabled CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled...
- Page 530 GD32W51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions...
- Page 531 GD32W51x User Manual Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardw are and cleared by softw are. When channel 0 is in input mode, this flag is set w hen a capture event occurs. When channel 0 is in output mode, this flag is set w hen a compare event occurs.
- Page 532 GD32W51x User Manual Channel 1’s capture or compare event generation CH1G Refer to CH0G description Channel 0’s capture or compare event generation CH0G This bit is set by softw are in order to generate a capture or compare event in channel 0, it is automatically cleared by hardw are.
- Page 533 GD32W51x User Manual Refer to CH0COMSEN description CH1COMFEN Channel 1 output compare fast enable Refer to CH0COMSEN description CH1MS[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is w ritable only w hen the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset).
- Page 534 GD32W51x User Manual CH0COMSEN Channel 0 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0CV register, w hich updates at each update event, w ill be enabled. 0: Channel 0 output compare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used w ithout validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set).
- Page 535 GD32W51x User Manual signal and the length of the digital filter applied to CI0. 0000: Filter disabled, f , N=1 SAMP 0001: f , N=2 SAMP CK_TIMER 0010: f , N=4 SAMP CK_TIMER 0011: f , N=8 SAMP CK_TIMER 0100: f /2, N=6 SAMP 0101: f...
- Page 536 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable...
- Page 537 GD32W51x User Manual 110: PWM mode0. When counting up, O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV else inactive. When counting dow n, O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV else active. 111: PWM mode1.
- Page 538 GD32W51x User Manual Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control An event counter is used in the digital filter, in w hich a transition on the output occurs after N input events.
- Page 539 GD32W51x User Manual Reserved CH3NP Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH3NP Channel 3 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value CH3P...
- Page 540 GD32W51x User Manual When channel 0 is configured in output mode, this bit spec ifies the output signal polarity. 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] w ill select the active trigger or capture polarity for CI0FE0 or CI1FE0.
- Page 541 GD32W51x User Manual This register has to be accessed by word (32-bit). Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter.
- Page 542 GD32W51x User Manual CARL[15:0] Bits Fields Descriptions 31:0 CARL[31:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Counter auto reload register (TIMERx_CAR) (x=3,4) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits...
- Page 543 GD32W51x User Manual 31:0 CH0VAL[31:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
- Page 544 GD32W51x User Manual 31:0 CH1VAL[31:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
- Page 545 GD32W51x User Manual 31:0 CH2VAL[31:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
- Page 546 GD32W51x User Manual 31:0 CH3VAL[31:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
- Page 547 GD32W51x User Manual 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed is defined the number of DMA w ill access(R/W) the register of TIMERx_DMA TB Reserved Must be kept at reset value. DMATA [4:0] DMA transfer access start address This filed define the first address for the DMA access the TIMERx_DMA TB.
- Page 548 GD32W51x User Manual Reserved Reserved CI3_RMP[1:0] Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value CI3_RMP[1:0] Channel 3 input remap 00: Channel 3 input is connected to GPIO(TIMER4_CH3) 01: Channel 3 input is connected to IRC32K 10: Channel 3 input is connected to LXTAL 11: Channel 3 input is connected to RTC w akeup Reserved Must be kept at reset value...
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Page 549: General Level4 Timer (Timerx, X=15,16)
GD32W51x User Manual General level4 timer (TIMERx, x=15,16) 17.3. Overview 17.3.1. The general level4 timer module (TIMER15, TIMER16) is a one-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level4 timer has a 16-bit counter that can be used as an unsigned counter. -
Page 550: Function Overview
GD32W51x User Manual configuration of the general level4 timer. Figure 17-53. General level4 timer block diagram Input Logic Synchronizer&Filter CH0_IN Edge selector Prescaler &Edge Detector TIMERx_CHxCV CK_TIMER Counter PSC_CLK Counter Control TIMER_CK DMA REQ/ACK TIMERx_CH0 TIMERx_UP DMA controller req en/direct req set Register /Interrupt APB BUS Output Logic... -
Page 551: Figure 17-54. Normal Mode, Internal Clock Divided By 1
GD32W51x User Manual Figure 17-54. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Prescaler The prescaler can divide the timer clock (TIMER_CK) to a counter clock (PSC_CLK) by any factor between 1 and 65536. -
Page 552: Figure 17-56. Up-Counter Timechart, Psc=0/1
GD32W51x User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts from 0. If the repetition counter is set, the update events will be generated after (TIMERx_CREP+1) times of overflow. -
Page 553: Figure 17-57. Up-Counter Timechart, Change Timerx_Car On The Go
GD32W51x User Manual Figure 17-57. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set... -
Page 554: Figure 17-58. Repetition Timechart For Up-Counter
GD32W51x User Manual Figure 17-58. Repetition timechart for up-counter TIMER_CK CNT_CLK 61 62 63 00 01 62 63 00 01 62 63 00 01 62 63 00 01 CNT_REG 62 63 00 01 62 63 00 01 Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF... -
Page 555: Figure 17-59. Input Capture Logic
GD32W51x User Manual Figure 17-59. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock Prescaler Register Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2... -
Page 556: Figure 17-60. Output Compare Logic (With Complementary Output, X=0)
GD32W51x User Manual TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. Output compare mode Figure 17-60. Output compare logic (with complementary output, x=0) Figure 17-60. Output compare logic (with complementary output, x=0) show the logic circuit of output compare mode. -
Page 557: Figure 17-61. Output-Compare Under Three Modes
GD32W51x User Manual * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP/CHxNP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE/CHxDEN Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV About the CHxVAL;... - Page 558 GD32W51x User Manual And if TIMERx_CHxCV is equal to zero, the output will be always inactive under PWM mode0 (CHxCOMCTL==3’b110). Figure 17-62. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF Channel output reference signal Figure 17-60. Output compare logic (with complementary output, As is shown in x=0).When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
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Page 559: Table 17-7. Complementary Outputs Controlled By Parameters
GD32W51x User Manual CHxEN and CHxNEN bits in the TIMERx_CHCTL2 register and the POEN, ROS, IOS, ISOx and ISOxN bits in the TIMERx_CCHP and TIMERx_CTL1 registers. The outputs polarity is determined by CHxP and CHxNP bits in the TIMERx_CHCTL2 register. Table 17-7. -
Page 560: Figure 17-63. Complementary Output With Dead-Time Insertion
GD32W51x User Manual Dead time insertion The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 1. The detail about the delay time, refer to the register TIMERx_CCHP. The dead time delay insertion ensures that no two complementary signals drive the active state at the same time. -
Page 561: Figure 17-64. Output Behavior In Response To A Break(The Break High Active)
GD32W51x User Manual and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0. -
Page 562: Figure 17-65. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32W51x User Manual a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software. If the CEN bit is cleared to 0 using software, the counter will be stopped and its value held. - Page 563 GD32W51x User Manual Timer debug mode When the Cortex™-M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1, the TIMERx counter stops.
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Page 564: Timerx Registers(X=15, 16)
GD32W51x User Manual TIMERx registers(x=15, 16) 17.3.5. TIMER15 secure access base address: 0x5001 8000 TIMER15 non-secure access base address: 0x4001 8000 TIMER16 secure access base address: 0x5001 8400 TIMER16 non-secure access base address: 0x4001 8400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved... - Page 565 GD32W51x User Manual The counter generates an overflow or underflow event The slave mode controller generates an update event. 1: Only counter overflow /underflow generates an update interrupt or DMA request. UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: update event enable.
- Page 566 GD32W51x User Manual 1: When POEN bit is reset, CH0_O is set high The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only w hen PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value DMAS...
- Page 567 GD32W51x User Manual 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH0IE Channel 0 capture/compare interrupt enable...
- Page 568 GD32W51x User Manual 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRKIF Break interrupt flag This flag is set by hardw are w hen the break input goes active, and cleared by softw are if the break input is not active.
- Page 569 GD32W51x User Manual 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by softw are and cleared by hardw are automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
- Page 570 GD32W51x User Manual CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output com pare m ode: Bits Fields Descriptions 31:7 Reserved Must be kept at reset value CH0COMCTL[2:0] Channel 0 compare output control This bit-field controls the behavior of the output reference signal O0CPRE w hich drives CH0_O and CH0_ON.
- Page 571 GD32W51x User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output w ill be accelerated if the channel is configured in PWM0 or PWM1 mode.
- Page 572 GD32W51x User Manual 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, capture is done on each channel input edge 01: Capture is done every 2 channel input edges 10: Capture is done every 4channel input edges...
- Page 573 GD32W51x User Manual 1: Channel 0 complementary output enabled CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
- Page 574 GD32W51x User Manual the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock.
- Page 575 GD32W51x User Manual Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate.
- Page 576 GD32W51x User Manual Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable This bit s set by softw are or automatically by hardw are depending on the OAEN bit.
- Page 577 GD32W51x User Manual When POEN bit is set, this bit specifies the output state for the channels w hich has a complementary output and has been configured in output mode. 0: When POEN bit is set, the channel output signals (CHx_O/CHx_ON) disabled.
- Page 578 GD32W51x User Manual DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed is defined the number of DMA w ill access(R/W) the register of...
- Page 579 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or w rite operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) w ill be accessed. The transfer Timer is calculated by hardw are, and ranges from 0 to DMATC.
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Page 580: Basic Timer (Timerx, X=5)
GD32W51x User Manual Basic timer (TIMERx, x=5) 17.4. Overview 17.4.1. The basic timer module (Timer5) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request. Characteristics 17.4.2. ... -
Page 581: Figure 17-67. Normal Mode, Internal Clock Divided By 1
GD32W51x User Manual Figure 17-67. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Prescaler The prescaler can divide the timer clock (TIMER_CK) to the counter clock (PSC_CLK by any factor between 1 and 65536. -
Page 582: Figure 17-69. Timing Chart Of Up Counting Mode, Psc=0/1
GD32W51x User Manual Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter restarts to count once again from 0.The update event is generated at each counter overflow. -
Page 583: Figure 17-70. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32W51x User Manual Figure 17-70. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear... -
Page 584: Timerx Registers(X=5)
GD32W51x User Manual TIMERx registers(x=5) 17.4.5. TIMER5 secure access base address: 0x5000 1000 TIMER5 non-secure access base address: 0x4000 1000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE... - Page 585 GD32W51x User Manual The counter generates an overflow or underflow event The slave mode controller generates an update event. 1: update event disable. The buffered registers keep their value, w hile the counter and the prescaler are reinitialized if the UG bit is set or if the slave mode controller generates a hardw are reset event.
- Page 586 GD32W51x User Manual Reserved Must be kept at reset value. Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value.
- Page 587 GD32W51x User Manual This bit is set by hardw are on an update event and cleared by softw are. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
- Page 588 GD32W51x User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock.
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Page 589: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32W51x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 18.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK, CK_SYS, LXTAL, IRC16M) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver. - Page 590 GD32W51x User Manual Parity control – Transmits parity bit – Checks parity of received data byte LIN Break generation and detection IrDA Support Synchronous mode and transmitter clock output for synchronous transmission ISO 7816-3 compliant smartcard interface –...
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Page 591: Function Overview
GD32W51x User Manual 18.3. Function overview The interface is externally connected to another device by the main pins listed in Table 18-1. Description of USART important pins. Table 18-1. Description of USART important pins Type Description Input Receive Data Output I/O (single- Transmit Data. -
Page 592: Baud Rate Generation
GD32W51x User Manual Figure 18-2. USART character frame (8 bits data and 1 stop bit) transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register. Table 18-2. Configuration of stop bits STB[1:0] stop bit length (bit) usage description... -
Page 593: Usart Transmitter
GD32W51x User Manual If USART_BAUD=0x21D, then INTDIV=33 (0x21), FRADIV=13 (0xD). USARTDIV=33+13/16=33.81. Get the value of USART_BAUD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). 16*0.37=5.92, the nearest integer is 6, so FRADIV=6 (0x6). USART_BAUD=0x1E6. Note: If the roundness of FRADIV is 16 (overflow), the carry must be added to the integer part. -
Page 594: Usart Receiver
GD32W51x User Manual Figure 18-3. USART transmit procedure Write data0 to Write data2 to Write data1 to USART_TDATA by USART_TDATA by USART_TDATA by DMA or software DMA or software DMA or software set by set by set by hardware hardware hardware data0 data1... -
Page 595: Use Dma For Data Buffer Access
GD32W51x User Manual oversampling 16 mode, the 7th, 8th, and 9th samples are used. If two or more samples of a frame bit is 0, the frame bit is confirmed as a 0, else 1. If the value of the three samples of any bit are not the same, whatever it is a start bit, data bit, parity bit or stop bit, a noisy error (NERR) status will be generated for the frame. -
Page 596: Figure 18-5. Configuration Step When Using Dma For Usart Transmission
GD32W51x User Manual Configuration step when using DMA for USART transmission. Figure 18-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number... -
Page 597: Hardware Flow Control
GD32W51x User Manual Figure 18-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc... -
Page 598: Multi-Processor Communication
GD32W51x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame c an be transmitted. -
Page 599: Lin Mode
GD32W51x User Manual The idle frame wake up method is selected by default. When an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode. When it is woken up by an idle frame, the IDLEF bit in USART_STAT will not be set. -
Page 600: Figure 18-10. Break Frame Occurs During A Frame
GD32W51x User Manual As shown in Figure 18-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame. Figure 18-10. Break frame occurs during a frame Synchronous mode 18.3.9. -
Page 601: Figure 18-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32W51x User Manual Figure 18-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 18.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode. -
Page 602: Figure 18-14. Irda Data Modulation
GD32W51x User Manual width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times of PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block. -
Page 603: Figure 18-15. Iso7816-3 Frame Format
GD32W51x User Manual smartcard, the TX pin must be configured as open drain mode, and drives a bidirectional line that is also driven by the smartcard. Figure 18-15. ISO7816-3 frame format Character (T=0) mode Compared to the timing in normal operation, the transmission time from transmit shift register to the TX pin is delayed by half baud clock, and the TC flag assertion time is delayed by a guard time that is configured by the GUAT[7:0] bits in USART_GP. - Page 604 GD32W51x User Manual When requesting a read from the smartcard, the RT[23:0] bits in USART_RT register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. A timeout interrupt will be generated, if no answer is received from the card before the expiration of this period.
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Page 605: Figure 18-16. Usart Receive Fifo Structure
GD32W51x User Manual ABDM bits in the USART_CTL1 register. These methods are: The USART will measure the duration of the start bit (falling edge to rising edge). In this case the receiving pattern should be any character starting with a bit at 1. The USART will measure the duration of the start and of the 1st data bit. -
Page 606: Table 18-3. Usart Interrupt Requests
GD32W51x User Manual If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out. The PERR/NERR/FERR/EBF/ABDE/ABDF flags should be cleared before reading a receive data out. -
Page 607: Figure 18-17. Usart Interrupt Mapping Diagram
GD32W51x User Manual Interrupt event Event flag Enable Control bit overrun error, framing error) in DMA reception Character match AMIE Receiver timeout error RTIE End of Block EBIE Wakeup from Deep-sleep WUIE mode All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time. - Page 608 GD32W51x User Manual 18.4. Register definition USART0 access secure base address: 0x5000 4800 USART0 access non-secure base address: 0x4000 4800 USART1 access secure base address: 0x5000 4400 USART1 access non-secure base address: 0x4000 4400 USART2 access secure base address: 0x5001 1000 USART2 access non-secure base address: 0x4001 1000 Control register 0 (USART_CTL0) 18.4.1.
- Page 609 GD32W51x User Manual OVSMOD bit. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). OVSMOD Oversample mode 0: Oversampling by 16 1: Oversampling by 8 This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be w ritten w hen the USART is enabled (UEN=1).
- Page 610 GD32W51x User Manual 1: Transmission complete interrupt is enabled RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 0: Read data register not empty interrupt and overrun error interrupt disabled 1: An interrupt w ill occur w henever the ORERR bit is set or the RBNE bit is set in USART_STAT.
- Page 611 GD32W51x User Manual used for w akeup w ith address mark detection. The received frame, the MSB of w hich is equal to 1, w ill be compared to these bits. When the ADDM bit is reset, only the ADDR[3:0] bits are used to compare. In normal reception, these bits are also used for character detection.
- Page 612 GD32W51x User Manual STRP Sw ap TX/RX pins 0: The TX and RX pins functions are not sw apped 1: The TX and RX pins functions are sw apped This bit field cannot be w ritten w hen the USART is enabled (UEN=1). LMEN LIN mode enable 0: LIN mode disabled...
- Page 613 GD32W51x User Manual This bit is reserved in USART1. LBLEN LIN break frame length 0: 10 bit break detection 1: 11 bit break detection This bit field cannot be w ritten w hen the USART is enabled (UEN=1). This bit is reserved in USART1. ADDM Address detection mode This bit is used to select betw een 4-bit address detection and full-bit address...
- Page 614 GD32W51x User Manual 11: WUF active on RBNE This bit field cannot be w ritten w hen the USART is enabled (UEN=1). This bit is reserved in USART1. 19:17 SCRTNUM[2:0] Smartcard auto-retry number In smartcard mode, these bits specify the number of retries in transmission and reception.
- Page 615 GD32W51x User Manual overw rites the previous content of the USART_RDATA register This bit field cannot be w ritten w hen the USART is enabled (UEN=1). One sample bit method 0: Three sample bit method 1: One sample bit method This bit field cannot be w ritten w hen the USART is enabled (UEN=1).
- Page 616 GD32W51x User Manual 0: Normal mode 1: Low -pow er mode This bit field cannot be w ritten w hen the USART is enabled (UEN=1). IREN IrDA mode enable 0: IrDA disabled 1: IrDA enabled This bit field cannot be w ritten w hen the USART is enabled (UEN=1). This bit is reserved in USART1.
- Page 617 GD32W51x User Manual This register is reserved in USART1 Reserved GUAT[7:0] PSC[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:8 GUAT[7:0] Guard time value in smartcard mode This bit field cannot be w ritten w hen the USART is enabled (UEN=1). PSC[7:0] Prescaler value for dividing the system clock In IrDA Low -pow er mode, the division factor is the prescaler value.
- Page 618 GD32W51x User Manual Bits Fields Descriptions 31:24 BL[7:0] Block Length These bits specify the block length in smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2- CRC) - 1. This value, w hich must be programmed only once per received block, can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field).
- Page 619 GD32W51x User Manual This bit is reserved in USART1. RXFCMD Receive data flush command Writing 1 to this bit clears the RBNE flag to discard the received data w ithout reading it. MMCMD Mute mode command Writing 1 to this bit makes the USART into mute mode and sets the RWU flag. SBKCMD Send break command Writing 1 to this bit sets the SBKF flag and makes the USART send a BREAK...
- Page 620 GD32W51x User Manual 0: No w akeup from Deep-sleep mode 1: Wakeup from Deep-sleep mode. An interrupt is generated if WUFIE=1 in the USART_CTL2 register and the MCU is in Deep-sleep mode. This bit is set by hardw are w hen a w akeup event, w hich is defined by the WUM bit field, is detected.
- Page 621 GD32W51x User Manual Set by hardw are if the baud rate out of range or character comparison failed Cleared by softw are, by w riting 1 to the ABDCMD bit in the USART_CMD register. This bit is reserved in USART1. Reserved Must be kept at reset value End of block flag...
- Page 622 GD32W51x User Manual 1: Data is transferred to the shift register. An interrupt w ill occur if the TBEIE bit is set in USART_CTL0 Set by hardw are w hen the content of the USART_TDATA register has been transferred into the transmit shift register or w riting 1 to TXFCMD bit of the USART_CMD register.
- Page 623 GD32W51x User Manual Cleared by w riting 1 to NEC bit in USART_INTC register. FERR Frame error flag 0: No framing error is detected 1: Frame error flag or break character is detected. In multibuffer communication, an interrupt w ill occur if the ERRIE bit is set in USART_CTL2. Set by hardw are w hen a de-synchronization, excessive noise or a break character is detected.
- Page 624 GD32W51x User Manual Writing 1 to this bit clears the EBF bit in the USART_STAT register. This bit is reserved in USART1. Receiver timeout clear Writing 1 to this bit clears the RTF flag in the USART_STA T register. This bit is reserved in USART1. Reserved Must be kept at reset value CTSC...
- Page 625 GD32W51x User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value RDATA[8:0] Receive Data value The received data character is contained in these bits. The value read in the MSB (bit 7 or bit 8 depending on the data length) w ill be the received parity bit, if receiving w ith the parity is enabled (PCEN bit set to 1 in the USART_CTL0 register).
- Page 626 GD32W51x User Manual Reserved EPERR Reserved rc_w0 Bits Fields Descriptions 31:9 Reserved Forced by hardw are to 0. EPERR Early parity error flag. This flag w ill be set as soon as the parity bit has been detected, w hich is before RBNE flag. This flag is cleared by w riting 0. 0: No parity error is detected 1: Parity error is detected.
- Page 627 GD32W51x User Manual 0: Receive FIFO full interrupt disable 1: Receive FIFO full interrupt enable RFEN Receive FIFO enable This bit can be set w hen UESM = 1. 0: Receive FIFO disable 1: Receive FIFO enable Reserved Must be kept at reset value ELNACK Early NACK w hen smartcard mode is selected.
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Page 628: Figure 19-1. I2C Module Block Diagram
GD32W51x User Manual Inter-integrated circuit interface (I2C) Overview 19.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus). -
Page 629: Table 19-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32W51x User Manual Figure 19-1. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Digital Register Noise Noise filter filter... -
Page 630: Figure 19-2. Data Validation
GD32W51x User Manual with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters Analog filter delay is maximum 260ns. Digital filter delay is DNF[3:0] x tI2CCLK The period of PCLK clock tPCLK match the conditions as follows: ... -
Page 631: Figure 19-3. Start And Stop Condition
GD32W51x User Manual Figure 19-3. START and STOP condition Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. It operates in slave mode by default. When it generates a START condition, the interface automatically switches from slave to master. -
Page 632: Figure 19-5. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32W51x User Manual Figure 19-5. I2C communication flow with 7-bit address (Master Transmit) Figure 19-6. I2C communication flow with 7-bit address (Master Receive) In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent. When HEAD10R=0, the complete 10 bit address read sequence must be excuted with START + header of 10-bit address in write direction + slave address byte 2 + RESTART + header of 10-bit address in read direction, as is shown in... -
Page 633: Figure 19-9. Data Hold Time
GD32W51x User Manual Noise filter 19.3.3. The noise filters must be configured before setting the I2CEN bit in I2C_CTL0 register if it is necessary. The analog noise filter is present on the SDA and SCL inputs by default. The analog filter requires the suppression of spikes with a pulse width up to 50ns in fast mode and fast mode plus. -
Page 634: Figure 19-10. Data Setup Time
GD32W51x User Manual Figure 19-10. Data setup time SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t = SDADELY * t where t = (PSC+1) * t SDADELY I2CCLK I2CCLK SDADELY... -
Page 635: Table 19-2. Data Setup Time And Data Hold Time
GD32W51x User Manual Table 19-2. Data setup time and data hold time Standard Fast m ode Fast m ode SMBus Sym bol Param eter m ode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of 1000... -
Page 636: Figure 19-11. Data Transmission
GD32W51x User Manual Figure 19-11. Data transmission SCL Stret ch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA Data Reception When receiving data, the SDA input fills the shift register. After the 8th SCL pulse, the complete data byte is received. If RBNE=0 (I2C_RDATA register is empty), the data in the shift register is moved into I2C_RDATA register. -
Page 637: Table 19-3. Communication Modes To Be Shut Down
GD32W51x User Manual Table 19-3. Communication modes to be shut down Working m ode Action Master mode NACK, STOP and RESTART generation Slave receiver mode ACK control SMBus mode PEC generation/checking The byte counter is always used in master mode. It is disabled in slave mode by default, but it can be enabled by software by setting the SBCTL (slave byte control) bit in the I2C_CTL0 register. - Page 638 GD32W51x User Manual I2C slave mode 19.3.7. Initialization When works in slave mode, at least one slave address should be enabled. Slave address 1 can be programmed in I2C_SADDR0 register and slave address 2 can be programmed in I2C_SADDR1 register. ADDRESSEN in I2C_SADDR0 register and ADDRESS2EN in I2C_SADDR1 register should be set when the corresponding address is used.
- Page 639 GD32W51x User Manual In slave transmitting mode, the data should be written in the I2C_TDATA register before the first SCL pulse corresponding to its transfer occurs. Or else the OUERR bit in the I2C_STAT register will be set, if the ERRIE bit is set, an interrupt will be generated. When the STPDET bit is set and the first data transmission starts, OUERR bit in the I2C_ST AT register will also be set.
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Page 640: Figure 19-13. I2C Initialization In Slave Mode
GD32W51x User Manual Figure 19-13. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0 Clear ADDRESS2EN in I2C_SADDR1 Configure ADDRESS[9:0], ADDFORMAT and ADDRESSEN in I2C_SADDR0, ADDRESS2[7:1], ADDMSK2[2:0] and ADDRESS2EN in I2C_SADDR1, ADDM[6:0] in I2C_CTL2... -
Page 641: Figure 19-14. Programming Model For Slave Transmitting When Ss=0
GD32W51x User Manual When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set. In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine. So the first data byte to be sent must be programmed in the I2C_TDATA register previously. -
Page 642: Figure 19-15. Programming Model For Slave Transmitting When Ss=1
GD32W51x User Manual Figure 19-15. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND... -
Page 643: Figure 19-16. Programming Model For Slave Receiving
GD32W51x User Manual Figure 19-16. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1) -
Page 644: Figure 19-17. I2C Initialization In Master Mode
GD32W51x User Manual (PSC+1) x t I2CCLK The t depends on the SCL falling slope, delay by input analog and digital noise filter and SYNC1 SCL synchronization with I2CCLK clock, which generally 2 to 3 I2CCLK periods. The t SYNC2 depends on the SCL rising slope, delay by input analog and digital noise filter and SCL synchronization with I2CCLK clock, which generally 2 to 3 I2CCLK periods. -
Page 645: Figure 19-18. Programming Model For Master Transmitting (N<=255)
GD32W51x User Manual transmission. If the TIE bit in I2C_CTL0 register is set, an interrupt will be generated. The bytes to be transferred is programmed in BYTENUM[7:0] in I2C_CTL0 register. If the bytes to be transferred is greater than 255, RELOAD bit in I2C_CTL0 register must be set to enable the reload mode. -
Page 646: Figure 19-19. Programming Model For Master Transmitting (N>255)
GD32W51x User Manual Figure 19-19. Programming model for master transmitting (N>255) Software Flow I2C Line State Hardware Action Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave... -
Page 647: Figure 19-20. Programming Model For Master Receiving (N<=255)
GD32W51x User Manual Figure 19-20. Programming model for master receiving (N<=255) Hardware I2C Line State Software Flow Action Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) ……（Data transmission）... -
Page 648: Figure 19-21. Programming Model For Master Receiving (N>255)
GD32W51x User Manual Figure 19-21. Programming model for master receiving (N>255) I2C Line State Hardware Software Flow Action Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) ……（Data transmission）... - Page 649 GD32W51x User Manual specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications. I2C devices that do not adhere to these protocols cannot be accessed by standard methods as defined in the SMBus and Advanced Configuration and Power Management Interface (abbreviated to ACPI) specifications.
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Page 650: Table 19-5. Smbus With Pec Configuration
GD32W51x User Manual In order to enable the t , the BUSTOA[11:0] must be programmed with the timer to check TIMEOUT the t parameter. To detect SCL low level timeout, the TOIDLE bit must be configured to TIMEOUT "0". Then set TOEN in the I2C_TIMEOUT register to enable the timer. If the low level time of SCL is greater than (BUSTOA + 1) x 2048 x t , the TIMEOUT flag is set in the I2C_ST AT I2CCLK... - Page 651 GD32W51x User Manual the same time. Only the device(s) which pulled SMBALERT# low will acknowledge the Alert Response Address. When SMBHAEN is 0, it is configured as a slave device, the SMBA pin is pulled low by setting the SMBALTEN bit in the I2C_CTL0 register. Meanwhile the Alert Response Address is enabled.
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Page 652: Figure 19-22. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32W51x User Manual BYTENUM=0x1 and PECTRANS bit is set at the same time, the contents of the I2C_PEC register are automatically transferred. If the automatic end mode is selected (AUTOEND=1), the SMBus master automatically sends the STOP condition after the PEC byte. If the automatic end mode is not selected (AUTOEND=0), the SMBus master can send a REST ART condition after the PEC. -
Page 653: Figure 19-23. Smbus Master Receiver And Slave Transmitter Communication Flow
GD32W51x User Manual master is greater than BYTENUM-1, the total number of TI interrupts will be BYTENUM-1, and the contents of the I2C_PEC register will be transmitted automatically. Note: After the RELOAD bit is set, the PECTRANS cannot be changed. Figure 19-23. -
Page 654: Table 19-6. I2C Error Flags
GD32W51x User Manual I2C error and interrupts 19.3.13. The I2C error flags are listed in Table 19-6. I2C error flags. Table 19-6. I2C error flags I2C Error Nam e Description BERR Bus error LOSTARB Arbitration lost OUERR Overrun/Underrun flag CRC value doesn’t match PECERR TIMEOUT Bus timeout in SMBus mode... - Page 655 GD32W51x User Manual Register definition 19.4. I2C0 secure access base address: 0x5000 5400 I2C0 non-secure access base address: 0x4000 5400 I2C1 secure access base address: 0x5000 5800 I2C1 non-secure access base address: 0x4000 5800 Control register 0 (I2C_CTL0) 19.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit) SMBALT...
- Page 656 GD32W51x User Manual 1: Host address is enabled, address 0b0001000x w ill be acknow ledged. GCEN Whether or not to response to a General Call (0x00) 0: Slave w on’t response to a General Call 1: Slave w ill response to a General Call WUEN Wakeup from Deep-sleep mode enable 0: Wakeup from Deep-sleep mode disable.
- Page 657 GD32W51x User Manual 1: Error interrupt enabled. When BERR, LOSTARB, OUERR, PECERR, TIMEO UT or SMBALT bit is set, an interrupt w ill be generated. TCIE Transfer complete interrupt enable 0: Transfer complete interrupt is disabled 1: Transfer complete interrupt is enabled STPDETIE Stop detection interrupt enable 0: Stop detection (STPDET) interrupt is disabled...
- Page 658 GD32W51x User Manual Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. PECTRA NS PEC Transfer Set by softw are. Cleared by hardw are in the follow ing cases: When PEC byte is transferred or ADDSEND bit is set or STOP condition is detected or I2CEN=0.
- Page 659 GD32W51x User Manual the arbitration is lost, or a timeout error occurred, or I2CEN=0, this bit can also be cleared by hardw are. It can be cleared by softw are by setting the ADDSENDC bit in I2C_STATC register. 0: START w ill not be sent 1: START w ill be sent HEAD10R 10-bit address header executes read direction only in master receive mode...
- Page 660 GD32W51x User Manual ADDRES ADDFOR ADDRES Reserved ADDRESS[9:8] ADDRESS[7:1] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ADDRESSEN I2C address enable 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address...
- Page 661 GD32W51x User Manual ADDRESS2EN Second I2C address enable 0: Second I2C address disable. 1: Second I2C address enable. 14:11 Reserved Must be kept at reset value. 10:8 ADDMSK2[2:0] ADDRESS2[7:1] mask Defines w hich bits of ADDRESS2[7:1] are compared w ith an incoming address byte, and w hich bits are masked (don’t care).
- Page 662 GD32W51x User Manual A delay t betw een SDA edge and SCL rising edge can be generated by SCLDELY configuring these bits. And during t , the SCL line is stretched low in master SCLDELY mode and in slave mode w hen SS = 0. = (SCLDELY +1) x t SCLDELY 19:16...
- Page 663 GD32W51x User Manual In master mode, the master cumulative clock low extend time t is detected. LOW:MEXT In slave mode, the slave cumulative clock low extend time t is detected. LOW:SEXT = (BUSTOB +1) x 2048 x t LOW:EXT I2CCLK Note: These bits can be modified only w hen EXTOEN =0.
- Page 664 GD32W51x User Manual Whether the I2C is a transmitter or a receiver in slave mode This bit is updated w hen the ADDSEND bit is set. 0: Receiver 1: Transmitter I2CBSY Busy flag This bit is set by hardw are w hen a START condition is detected and cleared by hardw are after a STOP condition.
- Page 665 GD32W51x User Manual BERR Bus error When an unexpected START or STOP condition on I2C bus is detected, a bus error occurs and this bit w ill be set. It is cleared by softw are by setting BERRC bit and cleared by hardw are w hen I2CEN=0.
- Page 666 GD32W51x User Manual Transmit interrupt This bit is set by hardw are w hen the I2C_TDATA register is empty and the I2C is ready to transmit data. It is cleared w hen the next data to be sent is w ritten in the I2C_TDATA register.When SS=1, this bit can be set by softw are, in order to generate a TI event (interrupt if TIE=1 or DMA request if DENT =1).
- Page 667 GD32W51x User Manual Softw are can clear the LOSTARB bit of I2C_STAT by w riting 1 to this bit BERRC Bus error flag clear. Softw are can clear the BERR bit of I2C_STAT by w riting 1 to this bit Reservced Must be kept at reset value.
- Page 668 GD32W51x User Manual Reserved RDATA[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. RDATA[7:0] Receive data value Transmit data register (I2C_TDATA) 19.4.11. Address offset: 0x28 Reset value: 0x0000 0000 This register can be accessed by word (32-bit) Reserved Reserved TDATA [7:0]...
- Page 669 GD32W51x User Manual 31:16 Reserved Must be kept at reset value. 15:9 ADDM[6:0] Defines w hich bits of ADDRESS[7:1] are compared w ith an incoming address byte, and w hich bits are ignored. Any bit set to 1 in ADDM[6:0] enables comparisons w ith the corresponding bit in ADDRESS[7:1].
- Page 670 GD32W51x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) Overview 20.1. The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
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Page 671: Figure 20-1. Block Diagram Of Spi
GD32W51x User Manual Transmission and reception using DMA. SPI block diagram 20.3. Figure 20-1. Block diagram of SPI SYSCLK MOSI TX Buffer MISO RX Buffer SPI signal description 20.4. Normal configuration (Not Quad-SPI Mode) 20.4.1. Table 20-1. SPI signal description Pin nam e Direction Description... -
Page 672: Table 20-2. Quad-Spi Signal Description
GD32W51x User Manual Pin nam e Direction Description Slave in hardw are NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration 20.4.2. SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0). -
Page 673: Figure 20-2. Spi Timing Diagram In Normal Mode
GD32W51x User Manual Figure 20-2. SPI timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI LF=1 FF16=0 MISO Figure 20-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample D[4] D[0] D[4]... -
Page 674: Table 20-3. Spi Operating Modes
GD32W51x User Manual NSS mode (SWNSSEN = 0) or from SWNSS bit in software NSS mode (SWNSSEN = 1), and SPI transmits/receives data only when NSS level is low. In software NSS mode, NSS pin is not used. Master mode In master mode (MSTMOD=1), if the application uses multi-master connection, NSS can be configured to hardware input mode (SWNSSEN=0, NSSDRV=0) or software mode (SWNSSEN=1). -
Page 675: Figure 20-4. A Typical Full-Duplex Connection
GD32W51x User Manual Mode Description Register configuration Data pin usage MSTMOD = 0 RO = 0 MOSI: Reception Slave full-duplex BDEN = 0 MISO: Transmission BDOEN: Don’t care MSTMOD = 0 Slave transmission w ith RO = 0 MOSI: Not used unidirectional connection BDEN = 0 MISO: Transmission... -
Page 676: Figure 20-6. A Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
GD32W51x User Manual Figure 20-6. A typical simplex connection (Master: Transmit only, Slave: Receive) Figure 20-7. A typical bidirectional connection SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step. - Page 677 GD32W51x User Manual SPI basic transmission and reception sequence Transmission sequence After the initialization sequence, the SPI is enabled and stays at idle state. In master mode, the transmission starts when the application writes a data into the transmit buffer. In slave mode the transmission starts when SCK clock signal at SCK pin begins to toggle and NSS level is low, so application should ensure that data is already written into transmit buffer before the transmission starts in slave mode.
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Page 678: Figure 20-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32W51x User Manual SPI TI mode SPI TI mode takes NSS as a special frame header flag signal and its operation sequence is similar to normal mode described above. The modes described above (MFD, MTU, MRU, MTB, MRB, SFD, STU, SRU, STB and SRB) are still supported in TI mode. While, in TI mode the CKPL and CKPH bits in SPI_CTL0 registers take no effect and the SCK sample edge is falling edge. -
Page 679: Figure 20-10. Timing Diagram Of Ti Slave Mode
GD32W51x User Manual Figure 20-10. Timing diagram of TI slave mode In slave TI mode, after the last rising edge of SCK in transfer, the slave begins to transmit the LSB bit of the last data byte, and after a half-bit time, the master begins to sample the line. To make sure that the master samples the right value, the slave should continue to drive this bit after the falling sample edge of SCK for a period of time before releasing the pin. -
Page 680: Figure 20-11. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32W51x User Manual checks TBE status at the end of a frame and stops when condition is not met. The operation flow for transmitting in quad mode is shown below: 1. Configure clock prescaler, clock polarity, phase, etc. in SPI_CTL0 and SPI_CTL1 based on application requirements. -
Page 681: Figure 20-12. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32W51x User Manual Write an arbitrary byte (for example, 0xFF) to SPI_DATA to receive the next byte. Figure 20-12. Timing diagram of quad read operation in Quad-SPI mode Software writes Hadware sets TBE SPI_DATA Software writes SPI_DATA Software reads SPI_DATA RBNE MOSI D1[4]... - Page 682 GD32W51x User Manual TRANS=0 to ensure the ongoing transfer completes. TI mode The disabling sequence of TI mode is the same as the sequences described above. NSS pulse mode The disabling sequence of NSSP mode is the same as the sequences described above. Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in...
- Page 683 GD32W51x User Manual will automatically process the CRC transmitting and checking. SPI interrupts 20.6. Status flags 20.6.1. Transmit buffer empty flag (TBE) This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register.
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Page 684: Figure 20-13. Block Diagram Of I2S
GD32W51x User Manual When the CRCEN bit is set, the CRC calculation result of the received data in the SPI_RCRC register is compared with the received CRC value after the last data, the CRCERR is set when they are different. Table 20-4. - Page 685 GD32W51x User Manual I2S signal description 20.8. There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
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Page 686: Figure 20-14. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32W51x User Manual Figure 20-14. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) Figure 20-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame. -
Page 687: Figure 20-19. I2S Phillips Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32W51x User Manual Figure 20-19. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame. In transmission mode, if a 24-bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits D[23:8]. -
Page 688: Figure 20-23. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32W51x User Manual Figure 20-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 20-24. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 20-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 20-26. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) 24-bit data... -
Page 689: Figure 20-29. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32W51x User Manual Figure 20-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) LSB justified standard For LSB justified standard, I2S_WS and I2S_SD are updated on the falling edge of I2S_CK. In the case that the channel length is equal to the data length, LSB justified standard and MSB justified standard are exactly the same. -
Page 690: Figure 20-33. Lsb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32W51x User Manual Figure 20-33. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame. The remaining 16 bits are forced by hardware to 0x0000 to extend the data to 32-bit format. -
Page 691: Figure 20-38. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32W51x User Manual (DTLEN=10, CHLEN=1, CKPL=1) Figure 20-38. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 20-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2 24-bit data 8-bit 0 Figure 20-40. -
Page 692: Figure 20-43. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32W51x User Manual (DTLEN=00, CHLEN=0, CKPL=0) Figure 20-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 20-44. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 frame 2 13 bits 32 bits Figure 20-45. -
Page 693: Figure 20-48. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32W51x User Manual Figure 20-48. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 20-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16-bit data 16-bit 0 I2S_SD I2S clock 20.9.2. -
Page 694: Table 20-6. Audio Sampling Frequency Calculation Formulas
GD32W51x User Manual So, in order to get the desired audio sampling frequency, the clock generator needs to be configured according to the formulas listed in Table 20-6. Audio sampling frequency calculation formulas. Table 20-6. Audio sampling frequency calculation formulas MCKOEN CHLEN Form ula... - Page 695 GD32W51x User Manual step 3, step 4 and step 5 should be done. Step 1: Configure the DIV[7:0] bits, the OF bit, and the MCKOEN bit in the SPI_I2SPSC register to define the I2S bitrate and determine whether I2S_MCK needs to be provided or not.
- Page 696 GD32W51x User Manual (RBNE is low). When a reception sequence finishes, the received data in the shift register is loaded into the receive buffer (RBNE goes high). The data should be read from the SPI_DATA register, when the RBNE flag is high. After a read operation to the SPI_DATA register, the RBNE flag goes low.
- Page 697 GD32W51x User Manual In order to disable I2S, it is mandatory to clear the I2SEN bit after the TBE flag is high and the TRANS flag is low. I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below.
- Page 698 GD32W51x User Manual I2S interrupts 20.10. Status flags 20.10.1. There are four status flags implemented in the SPI_STAT register, including TBE, RBNE, TRANS and I2SCH. The user can use them to fully monitor the state of the I2S bus. Transmit buffer empty flag (TBE) This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register.
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Page 699: Table 20-8. I2S Interrupt
GD32W51x User Manual Table 20-8. I2S interrupt Interrupt Interrupt flag Description Clear m ethod enable bit Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA register RBNEIE TXURERR Transmission underrun error Read SPI_STAT register Read SPI_DATA register and RXORERR Reception overrun error ERRIE... - Page 700 GD32W51x User Manual Register definition 20.11. SPI0 secure access base address: 0x5001 3000 SPI0 non-secure access base address: 0x4001 3000 SPI1/I2S1 secure access base address: 0x5000 3800 SPI1/I2S1 non-secure access base address: 0x4000 3800 I2S1_add secure access base address: 0x5000 3400 I2S1_add non-secure access base address: 0x4000 3400 Control register 0 (SPI_CTL0) 20.11.1.
- Page 701 GD32W51x User Manual When the transfer is managed by DMA, CRC value is transferred by hardw are. This bit should be cleared. In full-duplex or transmit-only mode, set this bit after the last data is w ritten to SPI_DA TA register.
- Page 702 GD32W51x User Manual CKPH Clock phase selection 0: Capture the first data at the first clock transition 1: Capture the first data at the second clock transition Control register 1 (SPI_CTL1) 20.11.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved TBEIE...
- Page 703 GD32W51x User Manual 0: Transmit buffer DMA is disabled. 1: Transmit buffer DMA is enabled, w hen the TBE bit in SPI_STAT is set, there w ill be a DMA request on corresponding DMA channel. DMAREN Receive buffer DMA enable 0: Receive buffer DMA is disabled.
- Page 704 GD32W51x User Manual 0: No configuration fault occurs. 1: Configuration fault occurred. (In master mode, the NSS pin is pulled low in NSS hardw are mode or SWNSS bit is low in NSS softw are mode.) This bit is set by hardw are and cleared by a read or w rite operation on the SPI_STA T register follow ed by a w rite access to the SPI_CTL0 register.
- Page 705 GD32W51x User Manual 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register The hardw are has tw o buffers, including transmit buffer and receive buffer. Write data to SPI_DATA w ill save the data to transmit buffer and read data from SPI_DA TA w ill get the data from receive buffer.
- Page 706 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardw are computes the CRC value of the received bytes and saves them in RCRC register. If the data frame format is set to 8- bit data, CRC calculation is based on CRC8 standard, and saves the value in RCRC[7:0], w hen the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in RCRC[15:0].
- Page 707 GD32W51x User Manual I2S control register (SPI_I2SCTL) 20.11.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PCMSMO Reserved I2SSEL I2SEN I2SOPMOD[1:0] Reserved I2SSTD[1:0] CKPL DTLEN[1:0] CHLEN Bits Fields Descriptions 31:12 Reserved Must be kept at reset value.
- Page 708 GD32W51x User Manual 10: LSB justified standard 11: PCM standard These bits should be configured w hen I2S is disabled. These bits are not used in SPI mode. CKPL Idle state clock polarity 0: The idle state of I2S_CK is low level 1: The idle state of I2S_CK is high level This bit should be configured w hen I2S is disabled.
- Page 709 GD32W51x User Manual This bit is not used in SPI mode. Odd factor for the prescaler 0: Real divider value is DIV * 2 1: Real divider value is DIV * 2 + 1 This bit should be configured w hen I2S is disabled. This bit is not used in SPI mode.
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Page 711: Table 21-1. Sqpi Controller Mode Definition
GD32W51x User Manual Serial/Quad Parallel Interface (SQPI) 21.1. Overview Serial/Quad Parallel Interface (SQPI) is a controller for external serial/dual/quad parallel interface memory peripheral. For example: SQPI-PSRAM and SQPI-FLASH. With this controller, users can use external SQPI interface memory as SRAM simply. 21.2. -
Page 712: Figure 21-1. Sqpi Polarity Example
GD32W51x User Manual SQPI_CSN Output Chip-Enable (active low ) Com m and Phase SQPI_D0 Output SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Address Phase SQPI_D0 Output SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Waitcycle Phase SQPI_D0 Inout SQPI_D1 Inout SQPI_D2 Inout SQPI_D3 Inout Data Phase SQPI_D0... -
Page 713: Figure 21-2. Sqpi Scmd Example
GD32W51x User Manual SQPI controller special command 21.3.3. SQPI controller special command (SCMD bit in SQPI_WCMD register) function can send only command phase with no address, waitcycle, and data phase. Special command function will be mandatory to SSS mode by hardware. If you set SCMD bit to 1, you must read this bit and wait it cleared before doing other memory access because this can ensure the operation has performed in the interface. -
Page 714: Figure 21-4. Sqpi_Clk Example
GD32W51x User Manual SQPI controller output clock configuration 21.3.5. SQPI clock period is configured by CLKDIV bits(SQPI_INIT register). The frequency formula of SQPI_CLK is: �� ℎ������ �� ��������_������ ������������ + 1 Note: CLKDIV cannot be 0. When CLKDIV field is even number, the output clock high level time has 1 HCLK period more than low level time. -
Page 715: Figure 21-5. Sqpi Sss Mode Timing (Spi)
GD32W51x User Manual Figure 21-5. SQPI SSS Mode Timing (SPI) SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Command Phase Address Phase Waitcycle Phase Data Phase Figure 21-6. SQPI SSQ Mode Timing SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Byte1 Command Phase Address Phase Waitcycle Phase Data Phase... -
Page 716: Figure 21-8. Sqpi Qqq Mode Timing (Qpi)
GD32W51x User Manual Figure 21-8. SQPI QQQ Mode Timing (QPI) SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Byte1 Command Phase Address Phase Waitcycle Phase Data Phase Figure 21-9. SQPI SSD Mode Timing SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Command Phase Address Phase Waitcycle Phase Data Phase... - Page 717 GD32W51x User Manual SQPI Initial Register (SQPI_INIT 21.4.1. Address offset: 0x00 Reset Value: 0x1801 0004 This register has to be accessed by word (32-bit). IDLEN[1:0] ADDRBIT[4:0] CLKDIV[5:0] CMDBIT[1:0] Reserved Bits Fields Descriptions Read data sample polarity. 0: Sample data at rising edge(default) 1: Sample data at falling edge.
- Page 718 GD32W51x User Manual This register has to be accessed by word (32-bit). RMODE[2:0] RWAITCYCLE[3:0] Reserved RCMD[15:0] Bits Fields Descriptions Send read ID command, command code comes from RCMD. 30:23 Reserved Must be kept at reset value. 22:20 RMODE[2:0] SQPI controller read command mode: 000: SSQ mode 001: SSS mode 010: SQQ mode...
- Page 719 GD32W51x User Manual code comes from WCMD. 30:23 Reserved Must be kept at reset value. 22:20 WMODE[2:0] SQPI controller w rite command mode: 000: SSQ mode 001: SSS mode 010: SQQ mode 011: QQQ mode 100: SSD mode 101: SDD mode 19:16 WWAITCYCLE[3:0] SQPI w rite command w aitcycle number after address phase...
- Page 720 GD32W51x User Manual IDH[31:16] IDH[15:0] Bits Fields Descriptions 31:0 IDH[31:0] ID High Data saved for SQPI read ID command This register only valid w hen IDLEN = 00.
- Page 721 GD32W51x User Manual Quad-SPI interface (QSPI) 22.1. Overview The QSPI is a specialized interface that communicate with Flash memories. This interface support single, dual or quad SPI FLASH. It can operate in any of the 4 following modes: indirect mode(address extend): all operations are performed depends on QSPI registers ...
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Page 722: Figure 22-1. Qspi Diagram
GD32W51x User Manual Table 22-1. QSPI signal description Pin nam e Direction Description (active low) chip select output clock output single mode:data output IO0/SO dual mode: data intput or output qual mode: data intput or output single mode:data input IO1/SI dual mode: data intput or output qual mode: data intput or output single mode:connect WP pin of flash,control “w rite... -
Page 723: Figure 22-2. Qspi Command Format
GD32W51x User Manual QSPI command format 22.3.2. The QSPI communicates with the Flash memory using commands in various formats. There are totally 5 phases which can be included or not: instruction, address, alternate byte, dummy and data. Any of these phases can be configured to be omitted or not, but at least one of the instructions, address, alternate byte, or data phase must be present, this must be guaranteed by software, hardware is not designed to provide any protection methods. -
Page 724: Table 22-2. Qspi Singnal Line Modes
GD32W51x User Manual (QSPI_TCFG register) defines the alternate bytes phase mode (no alternate bytes, 1-line, 2- lines, or 4-lines). Dummy phase In this phase, 0-31 cycles, as specified by DUMYC field (QSPI_TCFG register), are given without any data being transferred for external flash, in order to wait flash prepare data. DATAMOD field (QSPI_TCFG register) defines the dummy phase mode (1-line, 2-lines, or which is used in Data phase. - Page 725 GD32W51x User Manual Signal line m odes Single m ode Dual m ode Quad m ode IO0 (SO) Output Input:data read (high impedance) output: all other phases IO1 (SI) Input (high inpedance) Input ： data read (high impedance) Pins Output: all other phases. Output 0 (deactivate “w rite protect function”) Output 1 (deactivate “hold”...
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Page 726: Figure 22-3. Csn And Sck Behavior
GD32W51x User Manual Figure 22-3. CSN and SCK behavior When the FIFO stays empty in a write command, or full in a read command, SCK will be stalled and stays low until the FIFO can work again. At this moment if the CSN is high, SCK will rises back up one half of a SCK cycle after the rising edge of the CSN. - Page 727 GD32W51x User Manual FIFO and flag control A FIFO with a size of 8-bit by 16 is implemented to transfer data. In indirect write mode, 32- bit AHB write access add 4-bytes to FIFO, 16-bit add 2-bytes, and 8-bit add 1-byte. FIFO threshold is defined by FTL, in indirect read mode, when the amount of bytes in the FIFO is equal or above the defined threshold, FIFO threshold flag FT is set.
- Page 728 GD32W51x User Manual which is judge as an unaccessable transfer(such as a secure transfer trys to access a nonsecure area), and generate a hard-fault. If any of above condition happens, AHB will generate an error .The effect of the error depends on the AHB master.
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Page 729: Table 22-3. Flash Secure/Non-Secure And Privileged/Unprivileged Operation Under Fmc Mode When Trustzone Is Active (Tzen=1)
GD32W51x User Manual 22.5. QSPI configuration Flash configuration 22.5.1. The configuration in QSPI_DCFG register can be used to specify the characteristics of the external flash memory, so that the QSPI interface can work consistently. FMSZ field defines the size of the external memory, FMSZ + 1 is the number of address bits in the flash memory. - Page 730 GD32W51x User Manual FMC mode when TrustZone is active (TZEN=1) non-secure register secure register access type PRIV=1 PRIV=0 PRIV=1 PRIV=0 privileged accesses secure operation unprivileged all read data is all read data is 0, accesses 0, w rite invalid w rite invalid read/w rite privileged non-...
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Page 731: Table 22-4. Qspi Interrupt Requests
GD32W51x User Manual QSPI is disabled, will generate an AHB error. When an AHB master is accessing the memory mapped space while the memory mapped mode is not enabled, will generate an AHB error. When wrong access operation (such as seq trans attend to access the nonseq area )detected, support the error response to TZIAC, and if in memory map mode, will also return an AHB error. - Page 732 GD32W51x User Manual Register definition 22.11. QSPI secure access base address: 0x5002 5800 QSPI non-secure access base address: 0x4002 5800 Control register (QSPI_CTL) 22.11.1. Address offset: 0x00 Reset value: 0x0000 0010 This register can be accessed by word (32-bit). PSC[7:0] SPMOD Reserved FL[4:0]...
- Page 733 GD32W51x User Manual Reserved Must be kept at reset value 20:16 FL[4:0] FIFO level This field gives the number of valid bytes w hich are being held in the FIFO in indirect mode. In memory-mapped mode and in automatic status polling mode, FL is zero. FMC_MOD Busy in FMC mode This bit is set w hen a command is transferring in FMC mode.
- Page 734 GD32W51x User Manual This field can be modified only w hen BUSY = 0. TMOUTEN Timeout counter enable This bit is valid only in memory-mapped mode (FMOD = 11). Activating this bit causes the chip select (CSN) to be released if there is no access after a certain amount of time, and this time is defined by TMOUT[15:0].
- Page 735 GD32W51x User Manual 31:21 Reserved Must be kept at reset value 20:16 FMSZ[4:0] Flash memory size This field defines the size of external memory using the follow ing formula: [FMSZ+1] Number of bytes in Flash memory = 2 FMSZ+1 is effectively the number of address bits in the Flash memory. The Flash memory capacity can be up to 4GB in indirect mode, w hile it is limited to 256MB in memory mapped mode.
- Page 736 GD32W51x User Manual are initiated w hen FT is set. 0: DMA disabled 1: DMA enabled 15:12 Reserved Must be kept at reset value WSIE Wrong start sequence interrupt enable This bit enables the w rong start sequence interrupt. 0: Interrupt disable 1: Interrupt enabled TMOUTIE Timeout interrupt enable...
- Page 737 GD32W51x User Manual In automatic polling mode this bit is set every time the status register is read from the flash, and it is cleared once the QSPI_DA TA is read. Transfer complete flag This bit is set in indirect mode w hen the programmed number of data has been transmitted or in any mode w hen abort operation is completed.
- Page 738 GD32W51x User Manual Data length register (QSPI_DTLEN) 22.11.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). DTLEN[31:16] DTLEN[15:0] Bits Fields Descriptions 31:0 DTLEN[31:0] Data length Number of data to be retrieved (value+1) in indirect and status -polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status -polling mode.
- Page 739 GD32W51x User Manual Bits Fields Descriptions 31:29 Reserved must be kept at reset value SIOO Send instruction only once mode This bit has no effect w hen IMOD = 00. 0: Send instruction on every command sequence 1: Send instruction only for the first command sequence This field can be w ritten only w hen BUSY = 0.
- Page 740 GD32W51x User Manual 01: Alternate bytes on a single line 10: Alternate bytes on tw o lines 11: Alternate bytes on four lines This field can be w ritten only w hen BUSY = 0. 13:12 ADDRSZ[1:0] Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address...
- Page 741 GD32W51x User Manual Bits Fields Descriptions 31:0 ADDR[31:0] Address Address to be send to the external Flash memory This bits can only be w ritten w hen BUSY = 0 and memory -mapped mode is not configured. Alternate bytes register (QSPI_ALTE) 22.11.8.
- Page 742 GD32W51x User Manual has enough space. In indirect read mode, reading this register gives the data received from the Flash memory. If the FIFO does not have as many bytes as requested by the read command and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete.
- Page 743 GD32W51x User Manual 0: Interrupt disable 1: Interrupt enabled FTIE FIFO threshold interrupt enable This bit enables the fifo threshold interrupt. 0: Interrupt disable 1: Interrupt enabled TCIE Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disable 1: Interrupt enabled TERRIE Transfer error interrupt enable...
- Page 744 GD32W51x User Manual This register can be accessed by word (32-bit). Reserved Reserved TMOUTC Reserved TERRC Bits Fields Descriptions 31:6 Reserved Must be kept at reset value Clear w rong start sequence flag Writing 1 clears the WS flag in the QSPI_STAT register TMOUTC Clear timeout flag Writing 1 clears the TMOUT flag in the QSPI_STAT register...
- Page 745 GD32W51x User Manual end of memory, as defined by FMSZ. 0x0000_0000: 1 byte is to be transferred 0x0000_0001: 2 bytes are to be transferred 0x0000_0002: 3 bytes are to be transferred 0x0000_0003: 4 bytes are to be transferred 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred 0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined by FMSZ) are to be transferred.
- Page 746 GD32W51x User Manual This field can be w ritten only w hen BUSY = 0. 25:24 DATAMOD[1:0] Data mode This field defines the data phase’s mode of operation: 00: No data 01: Data on a single line 10: Data on tw o lines 11: Data on four lines This field also determines the dummy phase mode of operation.
- Page 747 GD32W51x User Manual This field can be w ritten only w hen BUSY = 0. IMOD[1:0] Instruction mode This field defines the instruction phase mode of operation: 00: No instruction 01: Instruction on a single line 10: Instruction on tw o lines 11: Instruction on four lines This field can be w ritten only w hen BUSY = 0.
- Page 748 GD32W51x User Manual Bits Fields Descriptions 31:0 ALTE[31:0] Alternate Bytes Optional data to be send to the flash memory. This field can be w ritten only w hen BUSY = 0 Secure Data register (QSPI_DATA_SEC) 22.11.16. Address offset: 0x120 Reset value: 0x0000 0000 This register can be accessed by word/half word/byte.(32-bits/16-bits/8-bits) DATA[31:16] DATA[15:0]...
- Page 749 GD32W51x User Manual MASK [15:0] Bits Fields Descriptions 31:0 MASK[31:0] Status mask Mask to be applied to the status bytes received from the flash memory. For bit n: 0: Bit n of the data received is masked and its value is not considered in the matching logic 1: Bit n of the data received is unmasked and its value is considered in the matching logic...
- Page 750 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 INTERVAL [15:0] Interval cycle Number of SCK cycles betw een tw o read commands in status polling mode. This field can be w ritten only w hen BUSY = 0. Timeout register (QSPI_TMOUT) 22.11.20.
- Page 751 GD32W51x User Manual FLUSH Used to flush all qspi interal fifo. Wait cnt for indirect wire mode register (QSPI_WTCNT) 22.11.22. Address offset: 0x38 Reset value: 0x0007 A120 This register can be accessed by word (32-bit). WTCNT [31:16] WTCNT [15:0] Bits Fields Descriptions 31:0...
- Page 752 GD32W51x User Manual When the system is secure (TZEN =1), this register provides write access security and can be written only when the access is secure. A non-secure write access is WI and generates an illegal access event. There are no read restrictions . When the system is not secure (TZEN=0), this register is RAZ/WI.
- Page 753 GD32W51x User Manual low one cycle longer than it stays high. This field can be modified only w hen BUSY = 0. CKMODEF This bit indicates the SCK level in FMC mode w hen QSPI is free 0: CLK must stay low w hile CSN is high (QSPI is free). 1: CLK must stay high w hile CSN is high (QSPI is free).
- Page 754 GD32W51x User Manual Reserved SIOOF Reserved DATAMODF[1:0] Reserved DUMYCF[4:0] ALTESZF[1:0] ALTEMODF[1:0] ADDRSZF[1:0] ADDRMODF[1:0] IMODF[1:0] INSTRUCTIONF[7:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value SIOOF Send instruction only once mode in FMC mode This bit has no effect w hen IMODE = 00. 0: Send instruction on every command sequence 1: Send instruction only for the first command sequence This field can be w ritten only w hen BUSY = 0.
- Page 755 GD32W51x User Manual This field can be w ritten only w hen BUSY = 0. 13:12 ADDRSZF[1:0] Address size in FMC mode This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be w ritten only w hen BUSY = 0. 11:10 ADDRMODF[1:0] Address mode in FMC mode...
- Page 756 GD32W51x User Manual Optional data to be send to the flash memory. This field can be w ritten only w hen BUSY = 0 Complete bytes counter register (QSPI_BYTE_CNT) 22.11.28. Address offset: 0x8C Reset value: 0x0000 0000 This register can be accessed by word (32-bit). BYTECNT [31:16] BYTECNT [15:0] Bits...
- Page 757 GD32W51x User Manual read and w ritten by privileged or unprivileged access. 1: FMC mode registers can be (QSPI_CTLF/QSPI_TCFGF/QSPI_ALTEF/QSPI_BY TE_CNT) read and w ritten by privileged access only. If the QSPI FMC mode is not secure, the PRIV bit can be w ritten by a secure or non- secure privileged access.
- Page 758 GD32W51x User Manual Secure digital input/output interface (SDIO) Introduction 23.1. The secure digital input/output interface (SDIO) defines the SD/SD I/O /MMC CE -ATA card host interface, which provides command/data transfer between the APB2 system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC), and CE-ATA devices. The supported SD memory card and SD I/O card system specifications are defined in the SD card Association website at www.sdcard.org.
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Page 759: Figure 23-1. Sdio "No Response" And "No Data" Operations
GD32W51x User Manual Response: a response is a token which is sent from the card to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines. -
Page 760: Figure 23-2. Sdio Multiple Blocks Read Operation
GD32W51x User Manual Figure 23-2. SDIO multiple blocks read operation Figure 23-3. SDIO multiple blocks write operation Command Response Command Response Host to Device Device to Host Host to Device Device to Host DATA BLOCK CRC DATA BLOCK CRC Host to Device Host to Device Block write operation Multiple block write operation... -
Page 761: Figure 23-6. Sdio Block Diagram
GD32W51x User Manual SDIO functional description 23.4. The following figure shows the SDIO structure. There have two main parts: The SDIO adapter block consists of control unit which manage clock, command unit which manage command transfer, data unit which manage data transfer. ... -
Page 762: Table 23-1. Sdio I/O Definitions
GD32W51x User Manual open-drain for initialization (only for MMC3.31 or previous), and push-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for initialization). SDIO_D[7:0]: These are bidirectional data channels. The D signals operate in push-pull mode. Only the card or the host is driving these signals at a time. By default, after power up or reset, only D0 is used for data transfer. - Page 763 GD32W51x User Manual Then receive response from the card if CMDRESP in SDIO_CMDCTL register is not 0b00/0b10. There are short response which have 48 bits or long response which have 136 bits. The response stores in SDIO_RESP0 - SDIO_RESP3 registers. The command unit also generates the command status flags defined in SDIO_STAT register.
- Page 764 GD32W51x User Manual CS_Waitcompl Wait for the Command Completion signal. → 1.CE-ATA Command Completion signal received CS_Idle → 2.CSM disabled CS_Idle → 3.Command CRC failed CS_Idle Data unit The data unit performs data transfers to and from cards. The data transfer uses SDIO_D[7:0] signals when 8-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b10), use SDIO_D[3:0] signals when 4-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b01), or SDIO_D[0] signal when 1-bit data width (BUSMODE bits in SDIO_CLKCTL register...
- Page 765 GD32W51x User Manual → 3.DSM disabled DS_Idle → 4.Timeout occurs DS_Idle Note: The command timeout programmed in the data timer register (SDIO_DATA TO). DS_WaitR Wait for the start bit of the receive data. → 1.Data receive ended DS_Idle → 2.DSM disabled DS_Idle →...
- Page 766 GD32W51x User Manual SDIO_FIFO register address. Configure DMA1 _Channel3 or DMA1 _Channel6 Peripheral4 control register (memory with increment transfer, peripheral with not increment transfer, peripheral and memory data size is word size). Program the incremental burst transfer to 4 on peripheral side in DMA1 _Channel 3 or DMA1 _Channel 6 Peripheral4. 5.
- Page 767 GD32W51x User Manual SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters. The EXT_CSD register carries both, card specific information and actual configuration parameters. For specific information, please refer to the relevant specifications. OCR register: The 32-bit operation conditions register (OCR) stores the V voltage profile of the card and the access mode indication (MMC).
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Page 768: Figure 23-7. Command Token Format
GD32W51x User Manual register shall be set in the factory by the SD Memory Card manufacturer. The host can use ACMD51 to get the content of this register. Commands 23.5.2. Commands types There are four kinds of commands defined to control the Card: ... -
Page 769: Table 23-3. Card Command Classes (Cccs)
GD32W51x User Manual CMD40 is mandatory for SDHC. The other classes are optional. The supported Card Command Classes (CCC) are coded as a parameter in the card specific data (CSD) register of each card, providing the host with information on how to access the card. For MMC cards, Class 0 is mandatory and shall be supported. - Page 770 GD32W51x User Manual CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61 ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51...
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Page 771: Table 23-4. Basic Commands (Class 0)
GD32W51x User Manual are only available for SD card. CMD60, CMD61 are only available for CE-ATA device. 2. All the ACMDs shall be preceded with APP_CMD command (CMD55). 3. CMD8 has different meaning for MMC and SD memory. Detailed command description The following tables describe in detail all bus commands. - Page 772 GD32W51x User Manual Cm d Response type argum ent Abbreviation Description index form at Command toggles a card betw een the stand-by and transfer states or betw een the programming and disconnects [31:16] RCA SELECT/DESELE CMD7 states. In both cases the card is [15:0] stuff bits CT_CARD selected by its ow n relative...
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Page 773: Table 23-5. Block-Oriented Read Commands (Class 2)
GD32W51x User Manual Table 23-5. Block-Oriented read commands (class 2) Cm d Response type argum ent Abbreviation Description index form at In the case of a Standard Capacity SD and MMC, this command sets the block length (in bytes) for all follow ing block commands (read, w rite, lock). -
Page 774: Table 23-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32W51x User Manual Table 23-6. Stream read commands (class 1) and stream write commands (class 3) Cm d Response type argum ent Abbreviation Description index form at Reads data stream from the card, starting at the given [31:0] data READ_DAT_UNTI CMD11 adtc address, until a... -
Page 775: Table 23-8. Erase Commands (Class 5)
GD32W51x User Manual Cm d Response type argum ent Abbreviation Description index form at Continuously w rites blocks of data until a STOP_TRA NSMISSION [31:0] data WRITE_MULTIPL CMD25 adtc follow s. address E _BLOCK Block length is specified the same as WRITE_BLOCK command. -
Page 776: Table 23-9. Block Oriented Write Protection Commands (Class 6)
GD32W51x User Manual Cm d Response type argum ent Abbreviation Description index form at versions of the MMC. 2. Data address is in byte units in a Standard Capacity SD Memory Card and in block (512 Byte) units in a High Capacity SD Memory Card. Table 23-9. -
Page 777: Table 23-11. Application-Specific Commands (Class 8)
GD32W51x User Manual Cm d Response type argum ent Abbreviation Description index form at Reserved bits in the argument and in Lock Card Data Structure shall be set to 0. Table 23-11. Application-specific commands (class 8) Cm d Response type argum ent Abbreviation Description... -
Page 778: Table 23-12. I/O Mode Commands (Class 9)
GD32W51x User Manual Cm d Response type argum ent Abbreviation Description index form at reserved bits. [31] WR [15:0] Data Unit R1(read)/ RW_MULTIPLE_ Read or w rite data block in CMD61 adtc Count R1b(w rite) BLOCK address range. Other bits are reserved bits Note: 1.ACMDx is Application-specific Commands for SD memory. -
Page 779: Table 23-13. Switch Function Commands (Class 10)
GD32W51x User Manual Cm d Response type argum ent Abbreviation Description index form at to read or w rite single I/O registers, as it requires only a single command/response pair. [31] R/W Flag [30:28] Function Number This command allow s the [27] Block Mode IO_RW_EXTEN reading or w riting of a large... -
Page 780: Figure 23-8. Response Token Format
GD32W51x User Manual bit of the bit string corresponding to the response code word. The code length depends on the response type. Responses types There are 7 types of responses show as follows. R1 / R1b : normal response command. R2 : CID, CSD register. -
Page 781: Table 23-14. Response R1
GD32W51x User Manual Table 23-14. Response R1 Bit position [45:40] [39:8] [7:1] Width ‘0’ ‘0’ ‘1’ Value command description start bit transmission bit card status CRC7 end bit index R1b is identical to R1 with an optional busy signal transmitted on the data line D0. The card may become busy after receiving these commands based on its state prior to the command reception. -
Page 782: Table 23-17. Response R4 For Mmc
GD32W51x User Manual Table 23-17. Response R4 for MMC Bit position [45:40] [39:8] Argument field [7:1] Width ‘0’ ‘0’ ‘100111’ ‘1’ Value read register start transmission status register description CMD39 address CRC7 [31:16] [15] contents [14:8] [7:0] For SD I/O only. Code length is 48 bits. The SDIO card receive the CMD5 will respond with a unique SD I/O response R4. -
Page 783: Figure 23-9. 1-Bit Data Bus Width
GD32W51x User Manual ‘0’ ‘0’ ‘11010X’ ‘0’ ‘1’ Value start transmission Response Read or description CMD52/53 Stuff Bits CRC7 Flags Write Data R6 (Published RCA response) Code length is 48 bit. The bits [45:40] indicate the index of the command to be responded to (CMD3). -
Page 784: Figure 23-10. 4-Bit Data Bus Width
GD32W51x User Manual Figure 23-9. 1-bit data bus width Start Byte Byte Byte Byte b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 4-bit data packet format Figure 23-10. 4-bit data bus width 8-bit data packet format Figure 23-11. -
Page 785: Table 23-23. Card Status
GD32W51x User Manual Card status The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card’s status information (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previous issued command. - Page 786 GD32W51x User Manual Bits Identifier Type Value Description Clear Condition ’0’= no error ERASE_PA RAM An invalid selection of w rite- ’1’= error blocks for erase occurred. ’0’= not protected WP_VIOLATION Set w hen the host attempts to ’1’= protected w rite to a protected block or to the temporary or permanent w rite protected...
- Page 787 GD32W51x User Manual Bits Identifier Type Value Description Clear Condition bits w as made. ’0’= not protected WP_ERASE_SKIP Set w hen only partial address ’1’= protected space w as erased due to existing w rite protected blocks or the temporary or permanent w rite protected card w as erased.
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Page 788: Table 23-24. Sd Status
GD32W51x User Manual Bits Identifier Type Value Description Clear Condition authentication process. Reserved for application specific commands. [1:0] Reserved for manufacturer test mode. Note: 18, 17, 7 bits are only for MMC. 14, 3 bits are only for SD memory. SD status register The SD Status contains status bits that are related to the SD Memory Card proprietary features and may be used for future application-specific usage. - Page 789 GD32W51x User Manual Bits Identifier Type Value Description Clear Condition card [439:4 PERFORMA NCE_M Performance of (See below ) move indicated by 1 [MB/s] step. [431:4 AU_SIZE Size of AU (See below ) [427:4 reserved [423:4 ERASE_SIZ E Number of AUs to (See below ) be erased at a time...
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Page 790: Table 23-25. Performance Move Field
GD32W51x User Manual 03h: Class 6 04h: Class 10 05h–FFh: Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm and the value can be set by 1 [MB/sec] step. If the card does not move using RUs, Pm should be considered as infinity. Setting to FFh means infinity. The minimum value of Pm is defined in Table 23-25. -
Page 791: Table 23-27. Maximum Au Size
GD32W51x User Manual than or equal to the maximum AU size. The card should set smaller AU size as possible. Table 23-27. Maximum AU size Card Capacity up to 64MB up to 256MB up to 512MB up to 32GB up to 2TB Maxim um AU 512 KB 1 MB... -
Page 792: Table 23-30. Erase Offset Field
GD32W51x User Manual meaningless if ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 23-30. Erase offset field ERASE_OFFSET Value Definition 0 [sec] 1 [sec] 2 [sec] 3 [sec] Programming sequence 23.6. Card identification 23.6.1. The host will be in card identification mode after reset and while it is looking for new cards on the bus. - Page 793 GD32W51x User Manual this command. If the card cannot perform data transfer in the specified range it must discard itself from further bus operations and go into Inactive State. Otherwise, the card shall respond sending back its V range. If the card can operate on the supplied voltage, the response echoes back the supply voltage and the check pattern that were set in the command argument.
- Page 794 GD32W51x User Manual No data commands 23.6.2. To send any non-data command, the software needs to program the SDIO_CMDCTL register and the SDIO_CMDAGMT register with appropriate parameters. Using these two registers, the host forms the command and sends it to the command bus. The host reflects the errors in the command response through the error bits of the SDIO_STAT register.
- Page 795 GD32W51x User Manual preceding ACMD23. The host will use this command to define how many number of write blocks are going to be send in the next write operation. Steps involved in a single-block or multiple-block write are: 1. Write the data size in bytes in the SDIO_DATALEN register. 2.
- Page 796 GD32W51x User Manual misalignment is not allowed, the card shall detect a block misalignment at the beginning of the first misaligned block, set the ADDRESS_ERROR error bit in the status register, abort transmission and wait in the Data State for a stop command. Steps involved in a single block or multiple block read are: 1.
- Page 797 GD32W51x User Manual frequency for the stream write operation is given by the following formula: WRITE_BL_LEN 8∗2 −100∗NSAC (23-2) max write frequence = min(TRAN_SPEED, TAAC∗R2W_FACTOR TRAN_SPEED: Max bus clock frequency. WRITE_BL_LEN: Max write data block length. NSAC: Data read access-time 2 in CLK cycles. TAAC: Data read access-time 1.
- Page 798 GD32W51x User Manual READ_BL_LEN: Max read data block length. NSAC: Data read access-time 2 in CLK cycles. TAAC: Data read access-time. R2W_FACTOR: Write speed factor. All the parameters are defined in CSD register. If the host attempts to use a higher frequency, the card may not be able to process the data and will stop programming, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop command.
- Page 799 GD32W51x User Manual Bus width selection 23.6.7. After the host has verified the functional pins on the bus it should change the bus width configuration. For MMC, using the SWITCH command (CMD6).The bus width configuration is changed by writing to the BUS_WIDTH byte in the Modes Segment of the EXT_CSD register (using the SWITCH command to do so).
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Page 800: Table 23-31. Lock Card Data Structure
GD32W51x User Manual bit PWD and 8-bit PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not erase them. Locked cards respond to (and execute) all commands in the basic command class (class 0), ACMD41, CMD16 and lock card command class (class 7). Thus, the host is allowed to reset, initialize, select, query for status, but not to access data on the card. - Page 801 GD32W51x User Manual (the old and the new one) are sent with the command. Send the Card Lock/Unlock command with the appropriate data block size on the data line including the 16-bit CRC. The data block shall indicate the mode (SET_PWD), the length (PWDS_LEN) and the password itself.
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Page 802: Figure 23-12. Read Wait Control By Stopping Sdio_Ck
GD32W51x User Manual If the PWD content is equal to the sent password, then the card will be unlocked and the card- locked status bit will be cleared in the status register. If the password is not correct, then the LOCK_UNLOCK_FAILED error bit will be set in the status register. -
Page 803: Figure 23-13. Read Wait Operation Using Sdio_D[2]
GD32W51x User Manual Figure 23-13. Read wait operation using SDIO_D[2] We can start the Read Wait interval before the data block is received: when the data unit is enabled (SDIO_DATACTL[0] bit set), the SD I/O specific operation is enabled (SDIO_DATACTL[11] bit set), Read Wait starts (SDIO_DATACTL[10] = 0 and SDIO_DATACTL[8] = 1) and data direction is from card to SD I/O (SDIO_DATACTL[1] = 1), the DSM directly moves from Idle to Read Wait. -
Page 804: Figure 23-15. Read Interrupt Cycle Timing
GD32W51x User Manual SDIO_CMDCTL[11] bit is set and indicates to the CSM that the current command is a suspend command. The CSM analyzes the response and when the response is received from the card (suspend accepted), it acknowledges the DSM that goes Idle after receiving the CRC token of the current block. -
Page 805: Figure 23-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
GD32W51x User Manual timing shows the operation for an interrupt during a 4-bit multi-block read and Figure 23-18. Multiple block 4-Bit write interrupt cycle timing shows the operation for an interrupt during a 4-bit multi-block write Figure 23-17. Multiple block 4-Bit read interrupt cycle timing Figure 23-18. -
Page 806: Figure 23-19. The Operation For Command Completion Disable Signal
GD32W51x User Manual Command completion disable signal The host may cancel the ability for the device to return a command completion signal by issuing the command completion signal disable. The host shall only issue the command completion signal disable when it has received an R1b response for an outstanding RW_MULTIPLE_BLOCK (CMD61) command. - Page 807 GD32W51x User Manual SDIO registers 23.8. SDIO secure access base address: 0x5001 2C00 SDIO non-secure access base address: 0x4001 2C00 Power control register (SDIO_PWRCTL) 23.8.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0]...
- Page 808 GD32W51x User Manual Bits Fields Descriptions DIV[8] MSB of Clock division This field defines the MSB division betw een the input clock (SDIOCLK) and the output clock, refer to bit 7:0 of SDIO_CLKCTL 30:15 Reserved Must be kept at reset value. HWCLKEN Hardw are Clock Control enable bit If this bit is set, hardw are controls the SDIO_CK on/off depending on the system...
- Page 809 GD32W51x User Manual Command argument register (SDIO_CMDAGMT) 23.8.3. Address offset: 0x08 Reset value: 0x0000 0000 This register defines 32 bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit) CMDAGMT[31:16] CMDAGMT[15:0] Bits...
- Page 810 GD32W51x User Manual 1: CE-ATA enable NINTEN No CE-ATA Interrupt (CE-ATA only) This bit defines if there is CE-ATA interrupt or not. This bit is only used w hen CE- ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card.
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Page 811: Table 23-32. Sdio_Respx Register At Different Response Type
GD32W51x User Manual Command index response register (SDIO_RSPCMDIDX) 23.8.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RSPCMDIDX[5:0] Last response command index Read-only bits field. - Page 812 GD32W51x User Manual Register Short response Long response SDIO_RESP1 reserved Card response [95:64] SDIO_RESP2 reserved Card response [63:32] SDIO_RESP3 reserved Card response [31:1],plus bit 0 Data timeout register (SDIO_DATATO) 23.8.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DATATO[31:16] DATATO[15:0] Bits...
- Page 813 GD32W51x User Manual 24:0 DATALEN[24:0] Data transfer length This register defined the number of bytes to be transferred. When the data transfer starts, the data counter loads this register and starts decrement. Note: If block data transfer selected, the content of this register must be a multiple of the block size (refer to SDIO_DA TACTL).
- Page 814 GD32W51x User Manual 0011: block size = 2 = 8 bytes 0100: block size = 2 = 16 bytes 0101: block size = 2 = 32 bytes 0110: block size = 2 = 64 bytes 0111: block size = 2 = 128 bytes 1000: block size = 2 = 256 bytes...
- Page 815 GD32W51x User Manual DATACNT[15:0] Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. 24:0 DATACNT[24:0] Data count value Read-only bits field. When these bits are read, the number of remaining data bytes to be transferred is returned. Status register (SDIO_STAT) 23.8.11.
- Page 816 GD32W51x User Manual When HW Flow control is enabled, RFF signals becomes activated 2 w ords before the FIFO is full. Transmit FIFO is full Receive FIFO is half full: at least 8 w ords can be read in the FIFO Transmit FIFO is half empty: at least 8 w ords can be w ritten into the FIFO RXRUN Data reception in progress...
- Page 817 GD32W51x User Manual DTBLKE CMDSEN CMDREC DTTMOU CMDTMO DTCRCE CCRCER Reserved STBITEC DTENDC RXOREC TXUREC Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. ATAENDC ATAEND flag clear bit Write 1 to this bit to clear the flag. SDIOINTC SDIOINT flag clear bit Write 1 to this bit to clear the flag.
- Page 818 GD32W51x User Manual Interrupt enable register (SDIO_INTEN) 23.8.13. Address offset: 0x3C Reset value: 0x0000 0000 This register enables the corresponding interrupt in the SDIO_STAT register. This register has to be accessed by word(32-bit) ATAENDI SDIOINTI RXDTVA TXDTVAL Reserved RFEIE TFEIE RFFIE TFFIE CMDRUN...
- Page 819 GD32W51x User Manual Write 1 to this bit to enable the interrupt. TXRUNIE Data transmission interrupt enable Write 1 to this bit to enable the interrupt. CMDRUNIE Command transmission interrupt enable Write 1 to this bit to enable the interrupt. DTBLKENDIE Data block end interrupt enable Write 1 to this bit to enable the interrupt.
- Page 820 GD32W51x User Manual FIFOCNT[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:0 FIFOCNT[23:0] FIFO counter. These bits define the remaining number w ords to be w ritten or read from the FIFO. It loads the data length register (SDIO_DATALEN[24:2] if SDIO_DATALEN is w ord- aligned or SDIO_DA TALEN[24:2]+1 if SDIO_DATALEN is not w ord-aligned) w hen DATAEN is set, and start count decrement w hen a w ord w rite to or read from the FIFO.
- Page 821 GD32W51x User Manual Universal serial bus full-speed interface (USBFS) 24.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution for portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol). USBFS contains a full-speed internal USB PHY and external PHY chip is not contained.
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Page 822: Figure 24-1. Usbfs Block Diagram
GD32W51x User Manual 24.3. Block diagram Figure 24-1. USBFS block diagram interrupts AHB Slave Device bus Host Port control Control Data FIFO Transcation Scheduler Control VBUS USB Clock 48MHz 24.4. Signal description Table 24-1. USBFS signal description I/O port Type Description VBUS Input... -
Page 823: Figure 24-2. Connection With Host Or Device Mode
GD32W51x User Manual Figure 24-2. Connection with host or device mode USBFS 5V Power Supply GPIO (needed in host mode) VBUS VBUS When USBFS works in host mode (FHM bit is set and FDM bit is cleared), the VBUS is 5V power detecting pin used for voltage detection defined in USB protocol. -
Page 824: Figure 24-3. Connection With Otg Mode
GD32W51x User Manual Figure 24-3. Connection with OTG mode USBFS 5V Power GPIO Supply VBus VBUS USB host function 24.5.2. USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state. - Page 825 GD32W51x User Manual Connection, Reset and Speed identification As a USB host, USBFS will trigger a connection flag for application after a connection is detected and will trigger a disconnection flag after a disconnection event. PRST bit is used for USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset.
- Page 826 GD32W51x User Manual USB 2.0 protocol divides these transfers into 2 kinds: non-periodic transfer (control and bulk) and periodic transfer (interrupt and isochronous). Based on this, USBFS includes two request queues: periodic request queue and non-periodic request queue, to perform efficient transaction schedule.
- Page 827 GD32W51x User Manual As required by USB 2.0 protocol, USBFS doesn’t support low-speed in device mode. Suspend and Wake-up A USB device will enter into suspend state when the USB bus stays at IDLE state and there is no change on data lines for 3ms. When USB device is in suspend state, most of its clock are closed to save power.
- Page 828 GD32W51x User Manual The Host Negotiation Protocol (HNP) allows the host function to be swit ched between two directly connected On-The-Go devices and eliminates the necessity of switching the cable connections for the change of control of communications between the devices. HNP will be initialized typically by the user or an application on the On-The-Go B-Device.
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Page 829: Figure 24-5. Host Mode Fifo Space In Sram
GD32W51x User Manual transmission packet. All IN channels shares the Rx FIFO for pack ets reception. All the periodic OUT channels share the periodic Tx FIFO to packets tramsmission. All the non- periodic OUT channels share the non-Periodic Tx FIFO for transmit packets. The size and start offset of these data FIFOs should be configured using these registers: USBFS_GRFLEN, USBFS_HNPTFLEN and USBFS_HPTFLEN. -
Page 830: Figure 24-7. Device Mode Fifo Space In Sram
GD32W51x User Manual (one for each IN endpoint). All the OUT endpoints share the Rx FIFO for receiving packets. The size and start offset of these data FIFOs should be configured using USB FS_GRFLEN and USBFS_DIEPxTFLEN (x=0…3) registers. Figure 24-7. Device mode FIFO space in SRAM describes the structure of these FIFOs in SRAM. -
Page 831: Figure 24-8. Device Mode Fifo Access Register Map
GD32W51x User Manual Figure 24-8. Device mode FIFO access register map Operation guide 24.5.6. This section describes the advised operation guide for USBFS. Host mode Global register initialization sequence 1. Program USBFS_GAHBCS register according to application’s demand, such as the TxFIFO’s empty threshold, etc. - Page 832 GD32W51x User Manual Channel initialization and enable sequence 1. Program USBFS_HCHxCTL registers with desired transfer type, direction, packet size, etc. Ensure that CEN and CDIS bits keep cleared during configuration. 2. Program USBFS_HCHxINTEN register. Set the desired interrupt enable bits. 3.
- Page 833 GD32W51x User Manual received data packet into the Rx FIFO and triggers ACK flag. Otherwise, the status flag (NAK) reports the transaction result. 7. If the IN transaction described in step 5 is successful and PCNT is larger than 1 in step2, return to step 3 and continues to receive the remaining packets.
- Page 834 GD32W51x User Manual 2. Program USBFS_GUSBCS register according to application’s demand, such as: the operation mode (host, device or OTG) and some parameters of OTG and USB protocols. 3. Program USBFS_GCCFG register according to application’s demand. 4. Program USBFS_GRFLEN, USBFS_HNPTFLEN_DIEP0TFLEN, USBFS_DIEPxTFLEN register to configure the data FIFOs according to application’s demand.
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Page 835: Table 24-2. Usbfs Global Interrupt
GD32W51x User Manual 1. Initialize USBFS global registers. 2. Initialize and enable the IN endpoint. 3. Write packets into the endpoint’s Tx FIFO. Each time a data packet is written into the FIFO, USBFS decreases the TLEN field in USBFS_DIEPxLEN register by the written packet’s size. - Page 836 GD32W51x User Manual Interrupt Flag Description Operation Mode PTXFEIF Periodic Tx FIFO empty interrupt flag Host Mode HCIF Host channels interrupt flag Host Mode HPIF Host port interrupt flag Host Mode ISOONCIF/PXNCIF Periodic transfer Not Complete Interrupt Host or device mode flag /Isochronous OUT transfer Not Complete Interrupt Flag ISOINCIF...
- Page 837 GD32W51x User Manual 24.7. Register definition USBFS secure base address: 0x5900 0000 USBFS non-secure base address: 0x4900 0000 Global control and status registers 24.7.1. Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
- Page 838 GD32W51x User Manual 1: Indicates the short debounce interval, w hen a soft connection is used in HNP protocol. Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes.
- Page 839 GD32W51x User Manual 1: Session request Note: Only accessible in device mode. SRPS SRP success This bit is set by the core w hen SRP succeeds, and this bit is cleared w hen SRPREQ bit is set. 0: SRP fails 1: SRP succeeds Note: Only accessible in device mode.
- Page 840 GD32W51x User Manual HNPEND HNP end Set by the core w hen a HNP ends. Read the HNPS in USBFS_GOTGCS register to get the result of HNP. Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core w hen a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP.
- Page 841 GD32W51x User Manual 1: TXFEIF w ill be triggered w hen the IN endpoint transmit FIFO is completely empty Host mode: 0: NPTXFEIF w ill be triggered w hen the non-periodic transmit FIFO is half empty 1: NPTXFEIF w ill be triggered w hen the non-periodic transmit FIFO is completely empty 6：1 Reserved...
- Page 842 GD32W51x User Manual pin. 0: Normal mode 1: Host mode The application must w ait at least 25 ms for the change taking effect after setting the force bit. Note: Accessible in both device and host modes. 28:14 Reserved Must be kept at reset value 13:10 UTT[3:0] USB turnaround time...
- Page 843 GD32W51x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value 10:6 TXFNUM[4:0] Tx FIFO number Indicates w hich Tx FIFO w ill be flushed w hen TXFF bit in the same register is set. Host Mode: 00000: Only non-periodic Tx FIFO is flushed 00001: Only periodic Tx FIFO is flushed 1XXXX: Both periodic and non-periodic Tx FIFOs are flushed...
- Page 844 GD32W51x User Manual Set by the application to reset AHB clock domain circuit. Hardw are automatically clears this bit after the reset process completes. After setting this bit, application should w ait until this bit is cleared before any other operation on USBFS.
- Page 845 GD32W51x User Manual Note: Accessible in both device and host modes. Reserved Must be kept at reset value PTXFEIF Periodic Tx FIFO empty interrupt flag This interrupt is triggered w hen the periodic transmit FIFO is either half or completely empty. The threshold is determined by the periodic Tx FIFO empty level bit (PTXFTH) in the USBFS_GAHBCS register.
- Page 846 GD32W51x User Manual Note: Only accessible in device mode. IEPIF IN endpoint interrupt flag Set by USBFS w hen one of the IN endpoints in device mode has raised an interrupt. Softw are should first read USBFS_DA EPINT register to get the device number, and then read the corresponding USBFS_DIEPx INTF register to get the flags of the endpoint that cause the interrupt.
- Page 847 GD32W51x User Manual flag after the w riting to SGINAK takes effect. Note: Only accessible in device mode. NPTXFEIF Non-Periodic Tx FIFO empty interrupt flag This interrupt is triggered w hen the non-periodic transmit FIFO is either half or completely empty. The threshold is determined by the non-periodic Tx FIFO empty level bit (TXFTH) in the USBFS_GAHBCS register.
- Page 848 GD32W51x User Manual This register has to be accessed by word (32-bit) Bits Fields Descriptions WKUPIE Wakeup interrupt enable 0: Disable w akeup interrupt 1: Enable w akeup interrupt Note: Accessible in both host and device modes. SESIE Session interrupt enable 0: Disable session interrupt 1: Enable session interrupt Note: Accessible in both host and device modes.
- Page 849 GD32W51x User Manual HPIE Host port interrupt enable 0: Disable host port interrupt 1: Enable host port interrupt Note: Only accessible in host mode. 23:22 Reserved Must be kept at reset value PXNCIE Periodic transfer not complete Interrupt enable 0: Disable periodic transfer not complete interrupt 1: Enable periodic transfer not complete interrupt Note: Only accessible in host mode.
- Page 850 GD32W51x User Manual 0: Disable USB reset interrupt 1: Enable USB reset interrupt Note: Only accessible in device mode. SPIE USB suspend interrupt enable 0: Disable USB suspend interrupt 1: Enable USB suspend interrupt Note: Only accessible in device mode. ESPIE Early suspend interrupt enable 0: Disable early suspend interrupt...
- Page 851 GD32W51x User Manual Note: Accessible in both device and host modes. Reserved Must be kept at reset value Global receive status read/receive status read and pop registers (USBFS_GRSTATR/USBFS_GRSTATP) Address offset for Read: 0x001C Address offset for Pop: 0x0020 Reset value: 0x0000 0000 A read to the receive status read register returns the entry of the top of the Rx FIFO.
- Page 852 GD32W51x User Manual 01: DATA2 11: MDATA 14:4 BCOUNT[10:0] Byte count The byte count of the received IN data packet. CNUM[3:0] Channel number The channel number to w hich the current received packet belongs. Device mode: Bits Fields Descriptions 31:21 Reserved Must be kept at reset value 20:17...
- Page 853 GD32W51x User Manual Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 RXFD[15:0] Rx FIFO depth In terms of 32-bit w ords.
- Page 854 GD32W51x User Manual Host Mode: Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host Non-periodic Tx FIFO depth In terms of 32-bit w ords. 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host Non-periodic Tx RAM start address The start address for non-periodic transmit FIFO RAM is in term of 32-bit w ords. Device Mode: Bits Fields...
- Page 855 GD32W51x User Manual 30:24 NPTXRQTOP[6:0] Top entry of the non-periodic Tx request queue Entry in the non-periodic transmit request queue. Bits 30:27: Channel number Bits 26:25: – 00: IN/OUT token – 01: Zero-length OUT packet – 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel.
- Page 856 GD32W51x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value VBUSIG VBUS ignored When this bit is set, USBFS doesn’t monitor the voltage on VBUS pin and alw ays consider VBUS voltage as valid both in host mode and in device mode, then free the VBUS pin for other usage.
- Page 857 GD32W51x User Manual Bits Fields Descriptions 31:0 CID[31:0] Core ID Softw are can w rite or read this field and uses this field as a unique ID for its application Host periodic transmit FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600 This register has to be accessed by word 32-bit) r/rw...
- Page 858 GD32W51x User Manual r/rw r/rw Bits Fields Descriptions 31:16 IEPTXFD[15:0] IN endpoint Tx FIFO depth In terms of 32-bit w ords. 1≤HPTXFD≤1024 15:0 IEPTXRSA R[15:0] IN endpoint FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32-bit w ords. Host control and status registers 24.7.2.
- Page 859 GD32W51x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CLKSEL[1:0] Clock select for usbclock. 01: 48MHz clock others: reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the frame interval for the current enumerating speed when USBFS controller is enumerating.
- Page 860 GD32W51x User Manual Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clocks . 15:0 FRNUM[15:0] Frame number This field reports the frame number of current frame and returns to 0 after it reaches 0x3FFF.
- Page 861 GD32W51x User Manual Entry in the periodic transmit request queue. Bits 30:27: Channel Number Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel. 23:16 PTXREQS[7:0] Periodic Tx request queue space The remaining space of the periodic transmit request queue.
- Page 862 GD32W51x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value HACHINT[7:0] Host all channel interrupts Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host all channels interrupt enable register (USBFS_HACHINTEN) Address offset: 0x0418 Reset value: 0x0000 0000 This register can be used by software to enable or disable a channel’s interrupt.
- Page 863 GD32W51x User Manual register is set by USBFS: PRST, PEDC and PCD. This register has to be accessed by word (32-bit) rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:19 Reserved Must be kept at reset value 18:17 PS[1:0] Port speed Report the enumerated speed of the device attached to this port. 01: Full speed 10: Low speed Others: Reserved...
- Page 864 GD32W51x User Manual Port suspend Application sets this bit to put port into suspend state. When this bit is set the port stops sending SOF tokens. This bit can only be cleared by the follow ing operations : PRST bit in this register is set by application PREM bit in this register is set A remote w akeup signal is detected A device disconnect is detected...
- Page 865 GD32W51x User Manual Bits Fields Descriptions Channel enable Set by the application and cleared by USBFS. 0: Channel disabled 1: Channel enabled Softw are should follow ing the operation guide to disable or enable a channel. CDIS Channel disable Softw are can set this bit to disable the channel from processing transactions . Softw are should follow the operation guide to disable or enable a channel.
- Page 866 GD32W51x User Manual EPDIR Endpoint direction The transfer direction of the endpoint that this channel w ants to communicate w ith. 0: OUT 1: IN 14:11 EPNUM[3:0] Endpoint number The number of the endpoint that this channel w ants to communicate w ith. 10:0 MPL[10:0] Maximum packet length...
- Page 867 GD32W51x User Manual a device sends a data packet and the packet length exceeds the endpoint’s maximum packet length. USBER USB Bus Error The USB error flag is set w hen the follow ing conditions occurs during receiving a packet: A received packet has a w rong CRC field A stuff error detected on USB bus Timeout w hen w aiting for a response packet...
- Page 868 GD32W51x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value DTERIE Data toggle error interrupt enable 0: Disable data toggle error interrupt 1: Enable data toggle error interrupt REQOVRIE Request queue overrun interrupt enable 0: Disable request queue overrun interrupt 1: Enable request queue overrun interrupt BBERIE Babble error interrupt enable...
- Page 869 GD32W51x User Manual CHIE Channel halted interrupt enable 0: Disable channel halted interrupt 1: Enable channel halted interrupt TFIE Transfer finished interrupt enable 0: Disable transfer finished interrupt 1: Enable transfer finished interrupt Host channel-x transfer length register (USBFS_HCHxLEN) (x = 0..7, where x = channel number) Address offset: 0x0510 + (channel_number ×...
- Page 870 GD32W51x User Manual Softw are should program this field before the channel is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet transmission. 18:0 TLEN[18:0] Transfer length The total data bytes number of a transfer. For OUT transfers, this field is the total data bytes of all the data packets desired to be transmitted in an OUT transfer.
- Page 871 GD32W51x User Manual 10: 90% of the frame time 11: 95% of the frame time 10:4 DAR[6:0] Device address This field defines the USB device’s address. USBFS uses this field to match w ith the incoming token’s device address field. Softw are should program this field after receiving a Set Address command from USB host.
- Page 872 GD32W51x User Manual Softw are should set this bit to notify USBFS that the registers are initialized after w aking up from pow er dow n state. CGONAK Clear global OUT NAK Softw are sets this bit to clear GONS bit in this register. SGONAK Set global OUT NAK Softw are sets this bit to set GONS bit in this register.
- Page 873 GD32W51x User Manual Device status register (USBFS_DSTAT) Address offset: 0x0808 Reset value: 0x0000 0000 This register contains status and information of the USBFS in device mode. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:22 Reserved Must be kept at reset value 21:8 FNRSOF[13:0]...
- Page 874 GD32W51x User Manual is able to trigger an endpoint interrupt in USBFS_DAEPINT register. The bits in this register are set and cleared by software. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:7 Reserved Must be kept at reset value IEPNEEN IN endpoint NAK effective interrupt enable bit 0: Disable IN endpoint NAK effective interrupt...
- Page 875 GD32W51x User Manual Reset value: 0x0000 0000 This register contains the interrupt enable bits for the flags in USBFS_DOEPxINTF register. If a bit in this register is set by software, the corresponding bit in USBFS_DOEPxINTF register is able to trigger an endpoint interrupt in USBFS_DAEPINT register. The bits in this register are set and cleared by software.
- Page 876 GD32W51x User Manual Device all endpoints interrupt register (USBFS_DAEPINT) Address offset: 0x0818 Reset value: 0x0000 0000 When an endpoint interrupt is triggered, USBFS sets corresponding bit in this register and software should read this register to know which endpoint is asserting an interrupt. This register has to be accessed by word (32-bit) Bits Fields...
- Page 877 GD32W51x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value 19:16 OEPIE[3:0] Out endpoint interrupt enable 0: Disable OUT endpoint-n interrupt 1: Enable OUT endpoint-n interrupt Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value...
- Page 878 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DVBUSDT[15:0] Device V discharge time There is a discharge process after V pulsing in SRP protocol. This field defines the discharge time of V The true discharge time is 1024 * DVBUSDT[1 5:0] BUS.
- Page 879 GD32W51x User Manual This register contains the enable bits for the Tx FIFO empty interrupts of IN endpoints. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:4 Reserved Must be kept at reset value IEPTXFEIE[3:0] IN endpoint Tx FIFO empty interrupt enable bits This field controls w hether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DA EPINT register.
- Page 880 GD32W51x User Manual Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Softw are should follow the operation guide to disable or enable an endpoint. Endpoint disable Softw are can set this bit to disable the endpoint. Softw are should follow ing the operation guide to disable or enable an endpoint.
- Page 881 GD32W51x User Manual MPL[1:0] Maximum packet length This field defines the maximum packet length for a control data packet. As described in USB 2.0 protocol, there are 4 kinds of length for control transfers: 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes Device IN endpoint-x control register (USBFS_DIEPxCTL) (x = 1..3, where x =...
- Page 882 GD32W51x User Manual SEVENFRM Set even frame (For isochronous IN endpoints) Softw are sets this bit to clear EOFRM bit in this register. SD0PID Set DATA0 PID (For interrupt/bulk IN endpoints) Softw are sets this bit to clear DPID bit in this register. SNAK Set NAK Softw are sets this bit to set NAKS bit in this register.
- Page 883 GD32W51x User Manual 0: Only sends data in even frames 1: Only sends data in odd frames DPID Endpoint data PID (For interrupt/bulk IN endpoints) There is a data PID toggle scheme in interrupt or bulk transfer. Set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers according to the data toggle scheme described in USB protocol.
- Page 884 GD32W51x User Manual 29:28 Reserved Must be kept at reset value SNAK Set NAK Softw are sets this bit to set NAKS bit in this register. CNAK Clear NAK Softw are sets this bit to clear NAKS bit in this register 25:22 Reserved Must be kept at reset value...
- Page 885 GD32W51x User Manual Device OUT endpoint-x control register (USBFS_DOEPxCTL) (x = 1..3, where x = endpoint_number) Address offset: 0x0B00 + (endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the operations of each logical OUT endpoint other than OUT endpoint 0.
- Page 886 GD32W51x User Manual Softw are sets this bit to set NAKS bit in this register. CNAK Clear NAK Softw are sets this bit to clear NAKS bit in this register. 25:22 Reserved Must be kept at reset value STALL STALL handshake Softw are can set this bit to make USBFS sends STALL handshake during an OUT transaction.
- Page 887 GD32W51x User Manual These is a data PID toggle scheme in interrupt or bulk transfer. Softw are should set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers follow ing the data toggle scheme described in USB protocol. 0: Data packet’s PID is DATA0 1: Data packet’s PID is DATA1 EPACT...
- Page 888 GD32W51x User Manual The setting of SNAK bit in USBFS_DIEPxCTL register takes effect. This bit can be cleared either by w riting 1 to it or by setting CNAK bit in USBFS_DIEPx CTL register. Reserved Must be kept at reset value EPTXFUD Endpoint Tx FIFO underrun This flag is triggered if the Tx FIFO has no packet data w hen an IN token is incoming...
- Page 889 GD32W51x User Manual BTBSTP Back-to-back SETUP packets (Only for control OUT endpoint) This flag is triggered w hen a control out endpoint has received more than 3 back- to-back setup packets. Reserved Must be kept at reset value EPRXFOV R Endpoint Rx FIFO overrun This flag is triggered if the OUT endpoint’s Rx FIFO has no enough space for a packet data w hen an OUT token is incoming.
- Page 890 GD32W51x User Manual The number of data packets desired to be transmitted in a transfer . Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet transmission.
- Page 891 GD32W51x User Manual 11: 3 packets 28:20 Reserved Must be kept at reset value PCNT Packet count The number of data packets desired to receive in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet reception on bus.
- Page 892 GD32W51x User Manual 10: 2 packets 11: 3 packets 28:19 PCNT[9:0] Packet count The number of data packets desired to be transmitted in a transfer . Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet...
- Page 893 GD32W51x User Manual This field defines the maximum number of back-to-back SETUP packets this endpoint can accept. Program this field before setup transfers. Each time a back-to-back setup packet is received, USBFS decrease this field by one. When this field reaches zero, the BTBSTP flag in USBFS_DOEPxINTF register w ill be triggered.
- Page 894 GD32W51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 IEPTFS[15:0] IN endpoint’s Tx FIFO space remaining IN endpoint’s Tx FIFO space remaining in 32-bit w ords: 0: FIFO is full 1: 1 w ord available …...
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Page 895: Figure 25-1. Dci Module Block Diagram
GD32W51x User Manual Digital camera interface (DCI) Overview 25.1. DCI is a parallel interface to capture video or picture from a camera. It supports various color space such as YUV/RGB, as well as compression format such as JPEG. Characteristics 25.2. ... -
Page 896: Figure 25-2. Hardware Synchronization Mode
GD32W51x User Manual signal (DCI_Hs or DCI_Vs). DCI uses embedded sync detection module to extract synchronization information from pixel data, and then recover horizontal and vertical synchronization signals. The window timing module performs image cutting function. This module calculates a pixel’s position using synchronization signals either from DCI interface or embedded sync detection module and then decides whether this pixel data needs to be received according to the configuration of DCI_CWSPOS and DCI_CWSZ registers. -
Page 897: Figure 25-3. Hardware Synchronization Mode: Jpeg Format Supporting
GD32W51x User Manual JPEG mode DCI supports JPEG video/picture compression format in hardware synchronization mode. In JPEG mode (JM bit in DCI_CTL is set), the DCI_Vs is used to indicate start of a new frame, and DCI_Hs is used as stream data valid signal. Figure 25-3. -
Page 898: Table 25-2. Memory View In Byte Padding Mode
GD32W51x User Manual The DCI capture frequency is defined by FR[1:0] bits in continuous mode. For example, if FR[1:0]=00, DCI captures each frame, and if FR[1:0]=01, DCI only captures every alternate frame. In continuous mode, software may clear the CAP bit any time when DCI is capturing data, but DCI doesn’t stop capture immediately. -
Page 899: Table 25-3. Memory View In Half-Word Padding Mode
GD32W51x User Manual D7[7:0] D6[7:0] D5[7:0] D4[7:0] Half-word padding mode Half-word padding is used if data width of DCI interface is configured into 10/12/14. In this mode each pixel data is extended into 16-bits length by filling zero at higher position, so the 32-bits width data buffer is able to hold two pixel data. - Page 900 GD32W51x User Manual Register definition 25.7. DCI secure access base address: 0x5C05 0000 DCI non-secure access base address: 0x4C05 0000 Control register (DCI_CTL) 25.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved DCIEN Reserved...
- Page 901 GD32W51x User Manual 1: High level during blanking period Clock Polarity Selection 0: Capture at falling edge 1: Capture at rising edge Embedded Synchronous Mode 0: Embedded synchronous mode is disabled 1: Embedded synchronous mode is enabled JPEG Mode 0: JPEG mode is disabled 1: JPEG mode is enabled WDEN Window Enable...
- Page 902 GD32W51x User Manual 0: Not in vertical blanking period 1: In vertical blanking period HS line status 0: Not in horizontal blanking period 1: In horizontal blanking period Status register1 (DCI_STAT1) 25.7.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ESEF...
- Page 903 GD32W51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ELIE VSIE ESEIE OVRIE EFIE Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. ELIE End of Line Interrupt Enable 0: End of line flag w on’t generate interrupt 1: End of line flag w ill generate interrupt VSIE...
- Page 904 GD32W51x User Manual Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. ELIF End of Line Interrupt Flag VSIF Vsync Interrupt Flag ESEIF Embedded Synchronous Error Interrupt Flag OVRIF FIFO Overrun Interrupt Flag EFIF End of Frame Interrupt Flag Interrupt flag clear register (DCI_INTC) 25.7.6.
- Page 905 GD32W51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) FE[7:0] LE[7:0] LS[7:0] FS[7:0] Bits Fields Descriptions 31:24 FE[7:0] Frame End Code in Embedded Synchronous Mode 23:16 LE[7:0] Line End Code in Embedded Synchronous Mode 15:8 LS[7:0] Line Start Code in Embedded Synchronous Mode...
- Page 906 GD32W51x User Manual This register has to be accessed by word (32-bit) Reserved WVSP[12:0] Reserved WHSP[13:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value. 28:16 WVSP[12:0] Window Vertical Start Position Zero means the first line 15:14 Reserved Must be kept at reset value 13:0 WHSP[13:0]...
- Page 907 GD32W51x User Manual DATA register (DCI_DATA) 25.7.11. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) DT3[[7:0] DT2[7:0] DT1[7:0] DT0[7:0] Bits Fields Descriptions 31:24 DT3[7:0] Pixel Data 3 23:16 DT2[7:0] Pixel Data 2 15:8 DT1[7:0] Pixel Data 1...
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Page 908: Figure 26-1. Block Diagram Of Tsi Module
GD32W51x User Manual Touch sensing interface (TSI) 26.1. Overview Touch Sensing Interface (TSI) provides a convenient solution for touch keys, sliders and capacitive proximity sensing applications. The controller builds on charge transfer method. Placing a finger near fringing electric fields adds capacitance to the system and TSI is able to measure this capacitance change using charge transfer method. -
Page 909: Figure 26-2. Block Diagram Of Sample Pin And Channel Pin
GD32W51x User Manual etc. Detecting the change of a system is the key problem and goal in these technologies. The TSI module is designed to use charge transfer method which detects the capacitive change of an electrode when touched by or a finger close to it. In order to detect the capacitive change, TSI performs a charge transfer sequence including several charging, transfer steps. -
Page 910: Table 26-1. Pin And Analog Switch State In A Charge-Transfer Sequence
GD32W51x User Manual Table 26-1. Pin and analog switch state in a charge-transfer sequence Step Nam e ASW_0 ASW_1 Pin0 Pin1 Discharge Close Close Input Floating Pull Dow n Buffer Time1 Open Open Input Floating Input Floating Charge Open Open Output High Input Floating Extend Charge... -
Page 911: Figure 26-3. Voltage Of A Sample Pin During Charge-Transfer Sequence
GD32W51x User Manual 6. Charge transfer ASW_0 and ASW_1 are closed and PIN0 is configured to input floating to transfer charge from C to C . The transfer time should be configured (see Register Section for detail) to ensure the full transfer after that the voltage of C and C will be equal. -
Page 912: Figure 26-4. Fsm Flow Of A Charge-Transfer Sequence
GD32W51x User Manual Figure 26-4. FSM flow of a charge-transfer sequence IDLE(discharge) Started Buffer Time1 Extend Charge Charge enabled Spread spectrum disabled Extend Charge Buffer Time2 Vx > Vth ！(Vx > Vth) or the cycle number or the cycle number reaches MCN Charge Transfer reaches MCN... -
Page 913: Table 26-2. Duration Time Of Extend Charge State In Each Cycle
GD32W51x User Manual cycles, V (the voltage of sample pin) reaches V (the threshold voltage). There is also a max cycle number defined by MCN in TSI_CTL0 register. When the cycle number reaches MCN, FSM returns to IDLE state and stops after Compare State, whether reaches V or not. -
Page 914: Table 26-3. Spread Spectrum Deviation Base On Hclk Period
GD32W51x User Manual Cycle Num ber Num ber of ECCLKs in Extend Charge state … … Table 26-3. Spread spectrum deviation base on HCLK period Spread spectrum deviation w ith different ECDIV value (ECDT=0x7F) HCLK Period ECDIV[2:0]=0x0 (Min) ECDIV[2:0]=0x1 ECDIV[2:0]=0x7(Max) 41.6ns (24MHz) 5333.3ns 10666.6ns... -
Page 915: Table 26-4. Tsi Errors And Flags
GD32W51x User Manual TSI operation flow 26.3.8. The normal operation flow of TSI is listed below: System initialization, such as system clock configuration, TSI related GPIO configuration, etc. Program TSI_CTL0, TSI_CHCFG, TSI_INTEN, TSI_SAMPCFG and GEx bits of TSI_GCTL register according to demand. Enable TSI by setting TSIEN bit in TSI_CTL0 register. - Page 916 GD32W51x User Manual 26.4. Registers definition TSI secure access base address: 0x5002 4000 TSI non-secure access base address: 0x4002 4000 Control register0 (TSI_CTL0) 26.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). CDT[3:0] CTDT[3:0] ECDT[6:0] ECEN...
- Page 917 GD32W51x User Manual …. 1111111: 128 × t ECCLK ECEN Extend Charge State Enable. 0: Extend Charge disabled 1: Extend Charge enabled ECDIV[0] Extend Charge clock(ECCLK) division factor. ECCLK in TSI is divided from HCLK and ECDIV defines the division factor. 0x0: f ECCLK HCLK...
- Page 918 GD32W51x User Manual 111: Reserved PINMOD Pin mode This bit defines a TSI pin’s mode w hen charge-transfer sequence is IDLE. 0: TSI pin w ill output low w hen IDLE 1: TSI pin w ill keep input mode w hen IDLE EGSEL Edge selection This bit defines the edge type in hardw are trigger mode.
- Page 919 GD32W51x User Manual 0: MNERR interrupt is disabled 1: MNERR interrupt is enabled CTCFIE Charge-transfer complete flag Interrupt Enable 0: CTCF interrupt is disabled 1: CTCF interrupt is enabled Interrupt flag clear register (TSI_INTC) 26.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by word(32-bit).
- Page 920 GD32W51x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value MNERR Max Cycle Number Error This bit is set by hardw are after charge-transfer sequence stops because it reaches the max cycle number defined by MCN[2:0]. This bit is cleared by w riting 1 to CMNERR bit in TSI_ICR register.
- Page 921 GD32W51x User Manual This register can be accessed by word(32-bit). Reserved Reserved G2P3 G2P2 G2P1 G2P0 G1P3 G1P2 G1P1 G1P0 G0P3 G0P2 G0P1 G0P0 Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 GxPy Analog sw itch state. This bit is set and cleared by softw are.
- Page 922 GD32W51x User Manual Reserved Reserved G2P3 G2P2 G2P1 G2P0 G1P3 G1P2 G1P1 G1P0 G0P3 G0P2 G0P1 G0P0 Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 GxPy Channel pin mode This bit is set and cleared by softw are. 0: Pin GxPy is not a channel pin 1: Pin GxPy is a channel pin Group control register(TSI_GCTL)
- Page 923 GD32W51x User Manual Group x cycle number registers(TSI_GxCYCN)(x = 0..2) 26.4.10. Address offset: 0x30 + 0x04 *(x + 1) Reset value: 0x0000 0000 This register can be accessed by word (32-bit). Reserved Reserved CYCN[13:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value 13:0 CYCN[13:0] Cycle number...
- Page 924 GD32W51x User Manual 0x3: f ECCLK HCLK 0x4: f ECCLK HCLK 0x5: f ECCLK HCLK 0x6: f ECCLK HCLK 0x7: f ECCLK HCLK Note: ECDIV[2:1] are located in TSI_CTL1 and ECDIV[0] is located in TSI_CTL0. 27:25 Reserved Must be kept at reset value CTCDIV[3] Charge Transfer clock(CTCLK) division factor.
- Page 925 GD32W51x User Manual Cryptographic Acceleration Unit (CAU) 27.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ...
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Page 926: Figure 27-1. Datam No Swapping And Half-Word Swapping
GD32W51x User Manual and OFB modes 8*32-bit input and output FIFO Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping Data can be transferred by DMA, CPU during interrupts, or without both of them 27.3. -
Page 927: Figure 27-2. Datam Byte Swapping And Bit Swapping
GD32W51x User Manual Figure 27-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping Initialization vectors 27.3.2. The initialization vectors are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes to XOR with data blocks. - Page 928 GD32W51x User Manual Figure 27-3. CAU diagram CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_CTL CAU_STAT0 DMAEN INTEN INTF STAT1 KEY0..3 IV0..1 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Config 8*32 8*32 Data swapping Data swapping Cryptographic acceleration core (DES/TDES/AES) DES/TDES cryptographic acceleration processor 27.4.1.
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Page 929: Figure 27-4. Des/Tdes Ecb Encryption
GD32W51x User Manual DES/TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1. The output is fed back directly to next DEA and then decrypted using KEY2. After that, the output is fed back directly to the last DEA and encrypted with KEY3. -
Page 930: Figure 27-5. Des/Tdes Ecb Decryption
GD32W51x User Manual Figure 27-5. DES/TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES/TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. -
Page 931: Figure 27-6. Des/Tdes Cbc Encryption
GD32W51x User Manual Figure 27-6. DES/TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES/TDES CBC decryption In DES/TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3. -
Page 932: Figure 27-7. Des/Tdes Cbc Decryption
GD32W51x User Manual Figure 27-7. DES/TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext AES cryptographic acceleration processor 27.4.2. The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce. -
Page 933: Figure 27-8. Aes Ecb Encryption
GD32W51x User Manual Figure 27-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the dec ryption. -
Page 934: Figure 27-10. Aes Cbc Encryption
GD32W51x User Manual AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the AEA and encrypted using the 128-, 192-, 256-bit key. -
Page 935: Figure 27-11. Aes Cbc Decryption
GD32W51x User Manual plaintext is also obtained after data swapping according to the data type. The procedure of AES CBC mode decryption is illustrated in Figure 27-11. AES CBC decryption. Figure 27-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) SWAP... - Page 936 GD32W51x User Manual Figure 27-13. AES CTR encryption/decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext CAU_DO Plaintext AES-GCM mode The AES Galois/counter mode (GCM) can be used to encrypt or authenticate message, then ciphertext and tag can be obtained. This algorithm is based on AES CTR mode to ensure confidentiality.
- Page 937 GD32W51x User Manual Repeat (h) until all AAD data are supplied, wait until BUSY bit is cleared. 3. GCM encryption/decryption phase This phase must be performed after GCM AAD phase. In this phase, the message is authenticated and encrypted/decrypted. Configure GCM_CCMPH[1:0] bits to ‘10’. (k) Configure the computation direction in CAUDIR.
- Page 938 GD32W51x User Manual 1. CCM prepare phase In this phase, B0 packet (the first packet) is programmed into the CAU_DI register. CAU_DO never contain data in this phase. (a) Clear the CAUEN bit to make sure CAU is disabled. (b) Configure the ALGM[3:0] bits to ‘1001’. (c) Configure GCM_CCMPH[1:0] bits to ‘00’.
- Page 939 GD32W51x User Manual (q) Wait until the ONE flag is set to 1, and then read CAU_DO 4 times. The output corresponds to the authentication tag. (r) Disable the CAU AES-CFB mode The Cipher Feedback (CFB) mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and the decryption process is similar to the encryption described before.
- Page 940 GD32W51x User Manual 2. Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen. 3. Configure the CAU_KEY0..3(H/L) registers according to the algorithm. 4. Configure the DATAM bit in the CAU_CTL register to select the data swapping type. 5.
- Page 941 GD32W51x User Manual Enable register CAU_INTEN. Value 1 of the register enable the interrupts. Input FIFO interrupt The input FIFO interrupt is asserted when the number of words in the input FIFO is less than four words, then ISTA is asserted. And if the input FIFO interrupt is enabled by IINTEN with a 1 value, the IINTF is also asserted.
- Page 942 GD32W51x User Manual When data transfer is done by CPU access to CAU_DI and CAU_DO: 1. When the data transfer is done by CPU access, then wait for the fourth read of the CAU_DO register and before the next CAU_DI write access so that the message is suspended at the end of a block processing.
- Page 943 GD32W51x User Manual 27.9. Register definition CAU secure access base address: 0x5C06 0000 CAU non-secure access base address: 0x4C06 0000 Control register (CAU_CTL) 27.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ALGM[3] Reserved GCM_CCMPH[1:0] CAUEN FFLUSH...
- Page 944 GD32W51x User Manual 01: 192-bit key length 10: 256-bit key length 11: never use DATAM[1:0] Data sw apping type mode configuration, must be configured w hen BUSY = 0 00: No sw apping 01: Half-w ord sw apping 10: Byte sw apping 11: Bit sw apping ALGM[2:0] Encryption/decryption algorithm mode bit 0 to bit 2...
- Page 945 GD32W51x User Manual Reset value: 0x0000 0003 This register has to be accessed by word (32-bit). Reserved Reserved BUSY Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing. This is because: - CAU is disabled by CAUEN = 0 or the processing has been completed. - No enough data or no enough space in the input/output FIFO to perform a data block 1: CAU is processing data or key derivation.
- Page 946 GD32W51x User Manual This register has to be accessed by word (32-bit). DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Data input Write these bits w ill w rite data to IN FIFO, read these bits w ill return IN FIFO value if CAUEN is 0, or it w ill return an undefined value Data output register (CAU_DO) 27.9.4.
- Page 947 GD32W51x User Manual Reserved DMAOEN DMAIEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DMAOEN DMA output enable 0: DMA for OUT FIFO data is disabled 1: DMA for OUT FIFO data is enabled DMAIEN DMA input enable 0: DMA for IN FIFO data is disabled 1: DMA for IN FIFO data is enabled Interrupt enable register (CAU_INTEN)
- Page 948 GD32W51x User Manual This register has to be accessed by word (32-bit). Reserved Reserved OSTA ISTA Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. OSTA OUT FIFO interrupt status 0: OUT FIFO interrupt status not pending 1: OUT FIFO interrupt status pending ISTA IN FIFO interrupt status 0: IN FIFO interrupt not pending...
- Page 949 GD32W51x User Manual Key registers (CAU_KEY0..3(H/L)) 27.9.9. Address offset: 0x20 to 0x3C Reset value: 0x0000 0000 This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0. In DES mode, only CAU_KEY1 is used. In TDES mode, CAU_KEY1, CAU_KEY2 and CAU_KEY3 are used.
- Page 950 GD32W51x User Manual CAU_KEY1H Address offset: 0x28 Reset value: 0x0000 0000 KEY1H[31:16] KEY1H[15:0] CAU_KEY1L Address offset: 0x2C Reset value: 0x0000 0000 KEY1L[31:16] KEY1L[15:0] CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0] CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 KEY2L[31:16] KEY2L[15:0]...
- Page 951 GD32W51x User Manual CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 KEY3H[31:16] KEY3H[15:0] CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000 KEY3L[31:16] KEY3L[15:0] Bits Fields Descriptions KEY0...3(H/L) The key for DES, TDES, AES 31:0 Initial vector registers (CAU_IV0..1(H/L)) 27.9.10. Address offset: 0x40 to 0x4C Reset value: 0x0000 0000 This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0.
- Page 952 GD32W51x User Manual IV0H[31:16] IV0H[15:0] CAU_IV0L Address offset: 0x44 Reset value: 0x0000 0000 IV0L[31:16] IV0L[15:0] CAU_IV1H Address offset: 0x48 Reset value: 0x0000 0000 IV1H[31:16] IV1H[15:0] CAU_IV1L Address offset: 0x4C Reset value: 0x0000 0000 IV1L[31:16] IV1L[15:0] Bits Fields Descriptions IV0...1(H/L) The initialization vector for DES, TDES, AES 31:0...
- Page 953 GD32W51x User Manual GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x 27.9.11. = 0..7) Address offset: 0x50 to 0x6C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CTXx[31:16] CTXx[15:0] Bits Fields Descriptions 31:0 CTXx[31:0] The internal status of the CAU core.
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Page 954: Figure 28-1. Datam No Swapping And Half-Word Swapping
GD32W51x User Manual Hash Acceleration Unit (HAU) 28.1. Overview The hash acceleration unit is used for information security. The secure hash algorithm (SHA- 1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash message authentication code (HMAC) algorithm are supported for various applications. The digest will be computed and the length is 160/224/256/128 bits for a message up to (2 - 1) bits computed by SHA-1, SHA-224, SHA-256 and MD5 algorithms respectively. -
Page 955: Figure 28-2. Datam Byte Swapping And Bit Swapping
GD32W51x User Manual types. Figure 28-1. DATAM No swapping and Half-word swapping word0 word0 WORD 0 (MSB) word1 word1 WORD 1 word2 word2 WORD 2 word3 word3 WORD 3 (LSB) No swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Half-word swapping Figure 28-2. -
Page 956: Figure 28-3. Hau Block Diagram
GD32W51x User Manual 28.4. HAU core The hash acceleration unit is used to compute condensed information of input messages with secure hash algorithms. The digest result has a length of 160/224/256/128 bits for a message up to (2 -1) bits computed by SHA-1, SHA-224, SHA256 and MD5 algorithms respectively. It can be used to generate or verify the signature of a message with a higher efficiency because of the much simpler of the information. - Page 957 GD32W51x User Manual set 1 to start the calculation of the digest of the last block. Data Padding Example: The input message is “HAU”, which ASCII hexadecimal c ode is: 484155 Then the VBL bits in the HAU_CFG register is set as decimal 24 because of the valid bit length.
- Page 958 GD32W51x User Manual The intermediate block computing can be started when HAU_DI is filled with another new word of the next block The last block computing can be started when CALEN bit in the HAU_CFG register is 1. Hash mode 28.4.3.
- Page 959 GD32W51x User Manual 28.5. HAU suspended mode It is possible to suspend HASH or HMAC operation to perform a high-prior task first, then after the high-prior task is finished, resume the suspended operation. When suspending the current task, it is necessary to save the context of the current task from registers to memory, and then the task can be resumed by restoring the context from memory to the HAU registers.
- Page 960 GD32W51x User Manual 4. Configure and process the new message. 5. Restore the process before. Restore the content from memory to HAU_INTEN, HAU_CFG and HAU_CTL registers. 6. Resume DMA channel transmission. Reconfigure the DMA channel to transfer data. 7. Resume the message calculation. Set START bit of HAU_CTL register to 1, to restart a new message digest calculation.
- Page 961 GD32W51x User Manual 28.7. Register definition HAU secure access base address: 0x5C06 0400 HAU non-secure access base address: 0x4C06 0400 HAU control register (HAU_CTL) 28.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ALGM[1] Reserved Reserved...
- Page 962 GD32W51x User Manual (CALEN bit is set as 1, or DMA end of transfer) ALGM[0] Algorithm selection bit 0 This bit and bit 18 of CTL are w ritten by softw are to select the SHA-1, SHA-224, SHA256 or the MD5 algorithm: 00: Select SHA-1 algorithm 01: Select MD5 algorithm 10: Select SHA224 algorithm...
- Page 963 GD32W51x User Manual processing. Any new write operation to this register will be extended while the digest calculation is in process until it has been finished. This register has to be accessed by word (32-bit). DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Message data input...
- Page 964 GD32W51x User Manual 0x03: Only bits [31:29] of the last data w ritten to HAU_DI after data sw apping are valid 0x1F: Only bits [31:1] of the last data w ritten to HAU_DI after data sw apping are valid Note: These bits must be configured before setting the CALEN bit. HAU data output register (HAU_DO0..7) 28.7.4.
- Page 965 GD32W51x User Manual DO2[31:16] DO2[15:0] HAU_DO3 Address offset: 0x18 and 0x31C DO3[31:16] DO3[15:0] HAU_DO4 Address offset: 0x1C and 0x320 DO4[31:16] DO4[15:0] HAU_DO5 Address offset: 0x324 DO5[31:16] DO5[15:0] HAU_DO6 Address offset: 0x328 DO6[31:16]...
- Page 966 GD32W51x User Manual DO6[15:0] HAU_DO7 Address offset: 0x32C DO7[31:16] DO7[15:0] Bits Fields Descriptions 31:0 DO0..7[31:0] Message digest result of hash algorithm HAU interrupt enable register (HAU_INTEN) 28.7.5. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CCIE...
- Page 967 GD32W51x User Manual This register has to be accessed by word (32-bit). Reserved Reserved BUSY DMAS rc_w0 rc_w0 Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing 1: Data block is in process DMAS DMA status 0: DMA is disabled (DMAE = 0) and no transfer is processing...
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Page 968: Figure 29-1. Pkcau Module Block Diagram
GD32W51x User Manual Public Key Cryptographic Acceleration Unit (PKCAU) Overview 29.1. Public key encryption is also called asymmetric encryption, asymmetric encryption algorithms use different keys for encryption and decryption. The Public Key Cryptographic Acceleration Unit (PKCAU) can accelerate RSA (Rivest, Shamir and Adleman), Diffie-Hellmann (DH key exchange) and ECC (elliptic curve cryptography) in GF(p) (Galois domain). - Page 969 GD32W51x User Manual Figure 29-1. PKCAU module block diagram PKCAU registers Control/status clear PKCAU_CTL Control PKCAU_STAT logic status PKCAU_STATC interrupt PKCAU PKCAU RAM core (3584 bytes) Operands 29.3.1. If the RSA operand size is ROS, the modulus length is ML, then the data size is ROS = (ML/32+1) words.
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Page 970: Figure 29-2. Flow Chart Of Rsa Algorithm
GD32W51x User Manual Figure 29-2. Flow chart of RSA algorithm Alice Save public Generate key from Bob key pairs message message encryption Public key decryption Private key algorithm from Bob algorithm from Bob ciphertext ciphertext A complete public key crypto system includes key pairs (public and private keys), encryption algorithms and decryption algorithms. -
Page 971: Figure 29-3. Flow Chart Of Ecdsa Sign
GD32W51x User Manual RSA decryption After receiving the ciphertext, Bob decrypts the ciphertext to get the plaintext by the private key. The decryption process is m = c mod n. ECC algorithm 29.3.3. Suppose the message is M, d is the private key, G is the base point of the chosen elliptic curve, Q is a point of the chosen elliptic curve,with a prime order n. -
Page 972: Figure 29-4. Flow Chart Of Ecdsa Verification
GD32W51x User Manual ECDSA verification Before verifying the signature, be sure to get the signer's public key, message, and signature. The process to generate ECDSA signature is shown in Figure 29-4. Flow chart of ECDSA verification. Figure 29-4. Flow chart of ECDSA verification start 0<r<n and 0<s<n? Calculate w=s... -
Page 973: Figure 29-5. Arithmetic Addition
GD32W51x User Manual MODSEL[5:0] Operation m odes 000001 calculate Montgomery parameter only 000010 modular exponentiation (the Montgomery parameter must be preloaded) 000111 RSA CRT exponentiation 001000 Modular inversion 001001 Arithmetic addition 001010 Arithmetic subtraction 001011 Arithmetic multiplication 001100 Arithmetic comparison 001101 Modular reduction 001110... -
Page 974: Figure 29-6. Arithmetic Subtraction
GD32W51x User Manual Figure 29-6. Arithmetic subtraction offset address output offset address input 0x400 0x404 Operand length L 0x408 0x8B4 Operand A 0xA44 Operand B 0xBD0 0xBD0 0≤A<2 , 0≤B<2 , 0≤result<2 , 0<L≤3136. Arithmetic multiplication The arithmetic multiplication operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "001011". -
Page 975: Figure 29-8. Arithmetic Comparison
GD32W51x User Manual comparison. If A=B, the operation result is “result =0x0”; If A>B, the operation result is “result =0x1”; If A<B, the operation result is “result =0x2”. Figure 29-8. Arithmetic comparison Offset address input output Offset address 0x400 0x404 Operand length L 0x408 0x8B4... -
Page 976: Figure 29-10. Modular Addition
GD32W51x User Manual Modular addition The modular addition operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "001110". The operation declaration is shown in Figure 29-10. Modular addition. The operation result is “result = A+B mod n”. Figure 29-10. Modular addition Offset address Offset address output... -
Page 977: Figure 29-11. Modular Subtraction
GD32W51x User Manual Figure 29-11. Modular subtraction Offset address output input Offset address 0x400 0x404 Modulus length M 0x408 0x8B4 Operand A 0xA44 Operand B 0xBD0 0xBD0 A-B mod n 0xD5C / A-B+n mod n Modulus n 0≤A<n, 0≤B<n, 0≤result<n, 0<n<2 , 0<M≤3136. -
Page 978: Figure 29-13. Mutual Mapping Between Montgomery Domain And Natural Domain
GD32W51x User Manual Montgomery multiplication Suppose A, B and C are in natural domain. “x” function is Montgomery multiplication operation. The two main uses of this opreation are as follows: 1. Mutual mapping between Montgomery domain and natural domain. Figure 29-13. Mutual mapping between Montgomery domain and natural As is shown in domain, if A is an integer in natural domain, the Montgomery parameter mont_para is mod n, the result AR = A x mont_para mod n is A in Montgomery domain. -
Page 979: Figure 29-14. Montgomery Multiplication
GD32W51x User Manual Figure 29-14. Montgomery multiplication Offset address output input Offset address 0x400 0x404 Modulus length M 0x408 0x8B4 Operand A 0xA44 0xBD0 Operand B AxB mod n 0xD5C Modulus n 0≤A<n, 0≤B<n, 0<n<2 , 0<M≤3136 (n must be odd integer). Modular exponentiation Normal mode The Modular exponentiation of normal mode operation is selected by configuring... -
Page 980: Figure 29-16. Modular Exponentiation Of Fast Mode
GD32W51x User Manual in PKCAU_CTL register as "000010". The operation declaration is shown in Figure 29-16. Modular exponentiation of fast mode. The operation result is “result = A mod n”. Figure 29-16. Modular exponentiation of fast mode Offset address output input Offset address 0x400... -
Page 981: Figure 29-18. Rsa Crt Exponentiation
GD32W51x User Manual 2． If the modulus n is not prime, only when the greatest common divisor of A and n is 1, the modular inversion output is valid. RSA CRT exponentiation The RSA CRT exponentiation operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "000111". -
Page 982: Figure 29-19. Point On Elliptic Curve Fp Check
GD32W51x User Manual Table 29-3. Range of parameters used by RSA CRT exponentiation operation Param eters Range 0≤d < 2 Operand d 0≤d <2 Operand d 0<q <2 Operand q Input 0<p<2 Prime p 0<q<2 Prime q 0≤A<2 Operand A result = A mod pq 0≤result<pq... -
Page 983: Table 29-5. Range Of Parameters Used By Point On Elliptic Curve Fp Check
GD32W51x User Manual Figure 29-19. Point on elliptic curve Fp check Offset address output input Offset address 0x400 0x400 result 0x404 0x404 Modulus length M 0x408 Sign of curve coefficient 0x40C Curve coefficient |a| 0x460 Curve modulus 0x55C x coordinate of point P 0x5B0 y coordinate of point P 0x7FC... -
Page 984: Figure 29-20. Ecc Scalar Multiplication Of Normal Mode
GD32W51x User Manual Figure 29-20. ECC scalar multiplication of normal mode Offset address output input Offset address 0x400 Length of scalar multiplier k 0x404 Modulus length 0x408 Sign of curve coefficient a 0x40C Curve coefficient |a| 0x460 Curve modulus p 0x508 scalar multiplier k 0x55C... -
Page 985: Figure 29-22. Ecdsa Sign
GD32W51x User Manual Table 29-6. Range of parameters used by ECC scalar multiplication Param eters Range Length of scalar 0<LEN≤640 multiplier k (LEN) 0<M≤640 Modulus length M Sign of curve 0x0: positive coefficient a 0x1: negative input Curve coefficient |a| Absolute value |a|<p Odd prime 0<p≤2 Curve modulus p... -
Page 986: Table 29-7. Range Of Parameters Used By Ecdsa Sign
GD32W51x User Manual Figure 29-22. ECDSA sign PKCAU RAM Offset address output input Offset address 0x400 Curve prime order n length 0x404 Curve modulus p length M 0x408 Sign of curve coefficient a 0x40C Curve coefficient |a| 0x460 Curve modulus p 0x508 Integer k 0x55C... -
Page 987: Figure 29-23. Ecdsa Verification
GD32W51x User Manual Param eters Range 0<r<n Signature part r 0<s<n Signature part s 0x0: no error Signature result: 0x1: Signature part r is 0 ERROR output 0x2: Signature part s is 0 Curve point kG 0≤x <n coordinate x Curve point kG 0≤y <n... -
Page 988: Table 29-8. Range Of Parameters Used By Ecdsa Verification
GD32W51x User Manual of parameters used by ECDSA verification. Table 29-8. Range of parameters used by ECDSA verification Param eters Range Curve prime order n 0<LEN≤640 length (LEN) Curve modulus p 0<M≤640 length (M) Sign of curve 0x0: positive coefficient a 0x1: negative Curve coefficient |a| Absolute value |a|<p... -
Page 989: Table 29-9. Modular Exponentiation Computation Times
GD32W51x User Manual 2. Load the initial data into PKCAU RAM at offset address 0x400; 3. Specify the operation to be performed in MODSEL[5:0] bits in PKCAU_CTL register, then set START bit in PKCAU_CTL register; 4. Wait for the ENDF bit set in PKCAU_STAT register; 5. -
Page 990: Table 29-10. Ecc Scalar Multiplication Computation Times
GD32W51x User Manual Exponent Operand length (in bits) Mode length (in bits) 1024 2048 3072 13651000 Normal 182783000 3072 Fast 181953000 44905000 Table 29-10. ECC scalar multiplication computation times Modulus length (in bits) Mode Normal 626000 951000 1997000 3617000 5762000 13134000 Fast 623000... -
Page 991: Table 29-14. Pkcau Interrupt Requests
GD32W51x User Manual End of operation flag (ENDF) When the operation specified in MODSEL[5:0] bits in the PKCAU_CTL register is completed, the ENDF bit will be set. If the ENDIE bit in PKCAU_CTL register is set, an interrupt will be generated. - Page 992 GD32W51x User Manual Register definition 29.4. PKCAU Secure access base address: 0x5C06 1000 PKCAU Non-secure access base address: 0x4C06 1000 Control register (PKCAU_CTL) 29.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit) ADDRER RAMERR Reserved Reserved...
- Page 993 GD32W51x User Manual 001001: Arithmetic addition 001010: Arithmetic subtraction 001011: Arithmetic multiplication 001100: Arithmetic comparison 001101: Modular reduction 001110: Modular addition 001111: Modular subtraction 010000: Montgomery multiplication 100000: Montgomery parameter computation then ECC scalar multiplication 100010: ECC scalar multiplication only (Montgomery parameter must be loaded first) 100100: ECDSA sign 100110: ECDSA verification...
- Page 994 GD32W51x User Manual ADDRERR Address error. 0: No address error. 1: The accessed address exceeds the expected range of PKCAU RAM, an address error occurs. RAMERR PKCAU RAM error 0: No PKCAU RAM error. 1: When the PKCAU core is using the RAM, AHB accesses the PKCAU RAM, a PKCAU RAM error occurs.
- Page 995 GD32W51x User Manual Softw are can clear the ENDF bit in PKCAU_STAT by w riting 1 to this bit. Reserved Must be kept at reset value. 16:0...
- Page 996 GD32W51x User Manual High-Performance Digital Filter (HPDF) Overview 30.1. A high performance digital filter module (HPDF) for external sigma delta (Σ-Δ) modulator is integrated in GD32W51x. HPDF supports SPI interface and Manchester-coded single-wire interface. The external sigma delta modulator can be connected with MCU by the serial interface, and the serial data stream output by sigma delta modulator can be filtered.
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Page 997: Figure 30-1. Hpdf Block Diagram
GD32W51x User Manual Figure 30-1. HPDF block diagram EXTRG CKIN1 DATAIN1 CKIN0 DATAIN0 CKOUT [1:0] Control unit Interrupts and events: APB BUS 1.end of conversion Configuration registers Channel0 serial Channel1 serial threshold monitor transcevier input data transcevier input data 3.malfunction monitor Clock Mode Clock... - Page 998 GD32W51x User Manual channel digital filter respectively. In addition, as long as the input channel is enabled, the input channel will immediately start receiving serial data. HPDF can enter stop mode by clearing FLTEN during operation. After entering stop mode, the ongoing conversion tasks of the HPDF module will immediately stop, and the configuration registers remains unchanged...
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Page 999: Table 30-2. Spi Interface Clock Configuration
GD32W51x User Manual After the serial output clock source is determined, the output clock frequency division can be controlled by configuring the CKOUTDIV [7:0] bit field in the HPDF_CH0CTL register. When CKOUTDIV[7:0] ≠ 0, the value of the serial output clock divider is CKOUTDIV[7:0]+1. When CKOUTDIV[7:0] = 0, the serial output clock is disabled and the pin of CKOUT remains low. -
Page 1000: Figure 30-2. The Sequence Diagram Of Spi Data Transmission
GD32W51x User Manual SPICKSS[1:0] Clock source SITYP[1:0] Sam pling point Description clock signal The external sigma delta modulator divides the CKOUT CKOUT/2 signal Rising edge of signal into 2 frequencies to (Generated at the each second generate the serial input rising edge of CKOUT signal communication clock.
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