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GOWIN DK START GW5AT-LV60PG484A User Manual

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DK_START_GW5AT-LV60PG484A_V1.1
User Guide
DBUG1276-1.0E, 12/31/2024

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Summary of Contents for GOWIN DK START GW5AT-LV60PG484A

  • Page 1 DK_START_GW5AT-LV60PG484A_V1.1 User Guide DBUG1276-1.0E, 12/31/2024...
  • Page 2 Copyright © 2024 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is the trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 12/31/2024 1.0E Initial version published.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iv List of Tables ....................... v 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 2 1.4 Support and Feedback ....................... 2 2 Development Board Introduction ..............
  • Page 5 Contents 3.5 DDR3 ..........................12 3.5.1 Introduction ........................12 3.5.2 Pin Distribution ....................... 13 3.6 ADC Interface ........................16 3.6.1 Introduction ........................16 3.6.2 Pin Distribution ....................... 16 3.7 SFP Interface ........................17 3.7.1 Introduction ........................17 3.7.2 Pin Distribution ....................... 17 3.8 HDMI Interface ........................
  • Page 6 Contents 3.16.1 Introduction ........................34 3.16.2 Pin Distribution ......................34 DBUG1276-1.0E...

  • Page 7: List Of Figures

    List of Figures List of Figures Figure 2-1 DK_START_GW5AT-LV60PG484A_V1.1 Development Board ........ 3 Figure 2-2 A Development Board Kit ..................4 Figure 2-3 PCB Components...................... 5 Figure 2-4 System Block Diagram ....................5 Figure 3-1 Power Distribution Diagram ..................9 Figure 3-2 Connection Diagram of Download ................
  • Page 8 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ................... 2 Table 3-1 JTAG Pin Distribution ....................10 Table 3-2 Clock Pin Distribution ....................11 Table 3-3 DDR3 Configuration ....................12 Table 3-4 DDR3 Pin Distribution ....................13 Table 3-5 Pin Distribution of ADC Interface ................

  • Page 9: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK_START_GW5AT-LV60PG484A_V1.1 development board (hereinafter referred to as “the development board”) user guide consists of following three parts:  A brief introduction to the features of the development board ...

  • Page 10: Terminology And Abbreviations

    Joint Test Action Group Serial Digital Interface Low Dropout Regulator 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com...

  • Page 11: Development Board Introduction

    Development Board Introduction 2.1 Overview Figure 2-1 DK_START_GW5AT-LV60PG484A_V1.1 Development Board Gowin GW5AT series of FPGA products are the 5 series products of Arora family, with abundant internal resources, high-performance DSP with a new architecture that supports AI operations, high-speed LVDS interface and abundant BSRAM resources.

  • Page 12: A Development Board Kit

    LVDS, SDI-IN, SDI-OUT, Ethernet, HDMI-TX, HDMI-RX, and ADC interfaces, supporting FPGA function evaluation, hardware verification, and software learning and debugging, etc. The development board adopts Gowin GW5AT-LV60PG484A FPGA device. For the internal resources of the chip, see DS981, GW5AT series of FPGA Products Data Sheet.

  • Page 13: Pcb Components

    2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components Current and 148.5MHz Reset GPIO 3.3V Voltage Monitor FPGA UART Download 1.5V DDR3 FPGA SDI OUT 2 Power Socket Power SDI OUT 1 Switch 125MHz 2.5V SFP1 1.8V 50MHz...

  • Page 14: Features

    2 Development Board Introduction 2.5 Features 2.5 Features The key features are as follows:  FPGA Device Gowin GW5AT-LV60PG484A FPGA  Download and Boot Integrate USB download circuit on the development board, download through Mini USB-B interface External SPI Flash Boot ...
  • Page 15 2 Development Board Introduction 2.5 Features 4 GPIOs with 3.3V voltage level standard reserved  LVDS Interface 2-channel LVDS interfaces, each channel including 4 data + 1 clk  I2C Interface 1-channel I2C interface  UART Interface 1-channel UART interface Mini USB-B connector ...

  • Page 16: Development Board Circuit

    3 Development Board Circuit 3.1 FPGA Development Board Circuit 3.1 FPGA Overview For the resources of GW5AT series of FPGA Products, refer to DS981, GW5AT series of FPGA Products Data Sheet. I/O BANK Description For the I/O BANK, package, and pinout information, see UG983, GW5AT series of FPGA Products Package and Pinout User Guide more details.

  • Page 17: Power Distribution

    3 Development Board Circuit 3.2 Power Supply 3.2.2 Power Distribution Figure 3-1 Power Distribution Diagram DC12V VCC1P5_DDR 0.75V DDR3 [TPS51200DRCR] SDRAM 0.75V DC-DC HDMI-TX [TPS54620RHLR] GPIO 5V/4A 200MHz 50MHz DC-DC 3.3V [TPS82130] 148.5MHz 3.3V/2A 125MHz NOR FLASH KEY&LED HDMI-TX (ADV7513) HDMI-RX (ADV7611) USB to UART...

  • Page 18: Download Module

    3 Development Board Circuit 3.3 Download Module 3.3 Download Module 3.3.1 Introduction The development board includes a Mini USB-B download port (J15) designed to program the programs to external SPI FLASH or SRAM. The download connection diagram is show in Figure 3-2. Figure 3-2 Connection Diagram of Download 3.3.2 Pin Distribution Table 3-1 JTAG Pin Distribution...

  • Page 19: Pin Distribution

    3 Development Board Circuit 3.4 Clock Figure 3-3 Clock Connection Diagram 3.4.2 Pin Distribution Table 3-2 Clock Pin Distribution Signal Name FPGA Pin No. BANK I/O Level Description 50MHz single-ended CLK_50MHz 3.3V clock F_CLK_200M_P 3.3V 200MHz differential clock F_CLK_200M_N 3.3V 200MHz differential clock Q0_REFCLKP_1 125MHz differential clock...

  • Page 20: Ddr3

    3 Development Board Circuit 3.5 DDR3 3.5 DDR3 3.5.1 Introduction The development board includes two 2 Gbit DDR3 chips. The signal of DDR3 chip is connected to the BANK9 and BANK10 of FPGA. The specific configurations of DDR3 are as shown in Table 3-3. Table 3-3 DDR3 Configuration Designator Capacity...

  • Page 21: Pin Distribution

    3 Development Board Circuit 3.5 DDR3 3.5.2 Pin Distribution Table 3-4 DDR3 Pin Distribution Signal Name FPGA (U1) Pin No. BANK I/O Level Description DDR3_A0 AA10 1.5V Address DDR3_A1 1.5V Address DDR3_A2 1.5V Address DDR3_A3 1.5V Address DDR3_A4 AA13 1.5V Address DDR3_A5 AB10...
  • Page 22 3 Development Board Circuit 3.5 DDR3 Signal Name FPGA (U1) Pin No. BANK I/O Level Description DDR3_CLK_P 1.5V Differential clock DDR3_CLK_N 1.5V Differential clock DDR3_DQ0 1.5V Data DDR3_DQ1 1.5V Data DDR3_DQ2 1.5V Data DDR3_DQ3 1.5V Data DDR3_DQ4 1.5V Data DDR3_DQ5 1.5V Data DDR3_DQ6...
  • Page 23 3 Development Board Circuit 3.5 DDR3 Signal Name FPGA (U1) Pin No. BANK I/O Level Description DDR3_DQ28 1.5V Data DDR3_DQ29 1.5V Data DDR3_DQ30 1.5V Data DDR3_DQ31 1.5V Data DDR3_LDM0 1.5V Data input mask DDR3_UDM0 1.5V Data input mask DDR3_LDQS0 1.5V Data clock DDR3_LDQS0 1.5V...

  • Page 24: Adc Interface

    3 Development Board Circuit 3.6 ADC Interface 3.6 ADC Interface 3.6.1 Introduction The development board includes input interfaces for ADC signals. The connector uses a 2x2P pin header with 2.54 mm pitch. Figure 3-5 is the ADC interface schematic connection diagram and the anti-aliasing filter circuit.

  • Page 25: Sfp Interface

    3 Development Board Circuit 3.7 SFP Interface 3.7 SFP Interface 3.7.1 Introduction The development board includes two SFP interfaces for SFP or SFP+ modules. The design diagram is shown in Figure 3-6. Figure 3-6 Connection Diagram of SFP Interface 3.7.2 Pin Distribution Table 3-6 Pin Distribution of SFP-1 Interface FPGA Signal Name...

  • Page 26: Table 3-7 Pin Distribution Of Sfp2 Interface

    3 Development Board Circuit 3.7 SFP Interface FPGA Signal Name BANK Description Pin No. Level detection SFP_RS0_1 Rate selection SFP_RS1_1 Rate selection Receiver losts the SFP_LOS_1 3.3V indicator signals. Table 3-7 Pin Distribution of SFP-2 Interface FPGA Signal Name BANK Description Pin No.

  • Page 27: Hdmi Interface

    3 Development Board Circuit 3.8 HDMI Interface 3.8 HDMI Interface 3.8.1 Introduction The development board leads 1-channel HDMI-TX interface and 1- channel HDMI-RX interface. The HDMI input and output communication is implemented via the decoding and encoding chips, respectively. The connection diagram of HDMI interface is as follows.

  • Page 28: Pin Distribution

    3 Development Board Circuit 3.8 HDMI Interface 3.8.2 Pin Distribution Table 3-8 Pin Distribution of HDMI_TX Interface Signal Name FPGA Pin No. BANK I/O Level Description The RGB data row locks 7513_CLK 3.3V the output clock 7513_D0 3.3V RGB data signal 7513_D1 3.3V RGB data signal...

  • Page 29: Table 3-9 Pin Distribution Of Hdmi_Rx Interface

    3 Development Board Circuit 3.8 HDMI Interface Signal Name FPGA Pin No. BANK I/O Level Description Horizontal 7513_HSYNC R17 3.3V synchronization signal 7513_DE 3.3V RGB data enable 7513_SCLK 3.3V IIS interface SCLK 7513_LRCLK 3.3V IIS interface LRCLK 7513_MCLK 3.3V IIS interface MCLK 7513_IIS0 3.3V IIS interface data signal...

  • Page 30: Sdi Interface

    3 Development Board Circuit 3.9 SDI Interface Signal Name FPGA Pin No. BANK I/O Level Description 7611_P16 3.3V RGB data signal 7611_P17 3.3V RGB data signal 7611_P18 3.3V RGB data signal 7611_P19 3.3V RGB data signal 7611_P20 3.3V RGB data signal 7611_P21 3.3V RGB data signal...

  • Page 31: Pin Distribution

    3 Development Board Circuit 3.10 Ethernet Interface Figure 3-9 Connection Diagram of SDI Interface 3G SDI-OUT-1 3G SDI-IN-1 SDI_1_IN_P SDI_1_OUT_P SDI_1_OUT+_BNC SDI_1_IN+_BNC LMH1219 LMH1218 SDI_1_IN_N SDI_1_OUT_N 3G SDI-IN-2 3G SDI-OUT-2 SDI_2_OUT_P SDI_2_IN_P SDI_2_OUT+_BNC SDI_2_IN+_BNC LMH1219 LMH1218 SDI_2_OUT_N SDI_2_IN_N 3.9.2 Pin Distribution Table 3-10 Pin Distribution of SDI Interface Signal Name FPGA Pin No.

  • Page 32: Pin Distribution

    3 Development Board Circuit 3.10 Ethernet Interface 3.10.2 Pin Distribution Table 3-11 Ethernet Interface 1 Pin Distribution Signal Name FPGA Pin No. BANK I/O Level Description PHY1_RXC 3.3V RGMII receive clock PHY1_GTXC 3.3V RGMII transmit clock PHY1_RXD3 3.3V RGMII/MII receive data PHY1_RXDV 3.3V RGMII receive data, valid...

  • Page 33: Mipi Interface

    3 Development Board Circuit 3.11 MIPI Interface Signal Name FPGA Pin No. BANK I/O Level Description PHY2_TXD3 3.3V RGMII transmit data PHY2_TXD2 3.3V RGMII transmit data PHY2_TXD1 3.3V RGMII transmit data PHY2_TXD0 3.3V RGMII transmit data PHY_MDC 3.3V Management data clock PHY_MDIO 3.3V Management data I/O...

  • Page 34: Pin Distribution

    3 Development Board Circuit 3.11 MIPI Interface 3.11.2 Pin Distribution Table 3-13 Pin Distribution of MIPI Interface Signal Name FPGA Pin No. BANK I/O Level Description Pin No. M0_D0N 1.8V MIPI data signal Floating M0_D0P 1. 8V MIPI data signal Floating M0_D1N 1.8V...
  • Page 35 3 Development Board Circuit 3.11 MIPI Interface Signal Name FPGA Pin No. BANK I/O Level Description Pin No. M0_D3P 1.8V MIPI data signal M1_D0N 1.8V MIPI data signal Floating M1_D0P 1.8V MIPI data signal Floating M1_D1N 1.8V MIPI data signal M1_D1P 1.8V MIPI data signal...
  • Page 36 3 Development Board Circuit 3.11 MIPI Interface Signal Name FPGA Pin No. BANK I/O Level Description Pin No. MIPI_GPIO3 3.3V GPIO M1_D3P 1.8V MIPI data signal MIPI_GPIO4 3.3V GPIO Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating VCC3P3 3.3V Power VCC3P3...

  • Page 37: Lvds Interface

    3 Development Board Circuit 3.12 LVDS Interface 3.12 LVDS Interface 3.12.1 Introduction The board leads out two LVDS interfaces connecting 10 pairs of differential signals, including 8 Data and 2 Clk; the interface uses two 2x10P headers with 2.0mm pitch. The connection diagram is shown in Figure 3-12.
  • Page 38 3 Development Board Circuit 3.12 LVDS Interface Signal Name FPGA Pin No. BANK I/O Level Description Pin No. LVDS25_P3 3.3V LVDS data LVDS25_N3 3.3V LVDS data LVDS25_P4 3.3V LVDS data LVDS25_N4 3.3V LVDS data Signal Name FPGA Pin No. BANK I/O Level Description Pin No.

  • Page 39: Uart Interface

    3 Development Board Circuit 3.13 UART Interface Signal Name FPGA Pin No. BANK I/O Level Description Pin No. LVDS25_N8 3.3V LVDS data 3.13 UART Interface 3.13.1 Introduction The UART interface led from the development board uses Mini USB-B connector, which is implemented via USB conversion chips. The connection diagram of UART interface is shown in Figure 3-13.

  • Page 40: I2C Interface

    3 Development Board Circuit 3.14 I2C Interface 3.14 I2C Interface 3.14.1 Introduction The development board includes 1-channel I2C interface as the host communication interface. The host can monitor the power consumption of FPGA VCC, VCCX, SerDes, and each BANK through this interface. The connection diagram of I2C interface is shown in Figure 3-14.

  • Page 41: Key & Led

    3 Development Board Circuit 3.15 Key & LED 3.15 Key & LED 3.15.1 Introduction The development board includes one reset key, which is connected to the general IO of FPGA BANK11. The corresponding IO input voltage of the FPGA is low when the key is pressed while high when the key is not pressed.

  • Page 42: Pin Distribution

    3 Development Board Circuit 3.16 GPIO 3.15.2 Pin Distribution Table 3-17 Pin Distribution of Key Signal Name FPGA Pin No. BANK I/O Level Description F_NRST 3.3V Reset Key Table 3-18 Pin Distribution of Indicator Signal Name FPGA Pin No. BANK I/O Level Description F_LED1...
  • Page 43 3 Development Board Circuit 3.16 GPIO J2 Pin No. Signal Name FPGA Pin No. BANK I/O Level Description F_GPIO6 3.3V GPIO F_GPIO7 3.3V GPIO F_GPIO8 3.3V GPIO F_GPIO9 3.3V GPIO VCC3P3 3.3V Power VCC3P3 3.3V Power DBUG1276-1.0E 35(35)

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