Related Manuals for GOWIN DK USB2.0 GW2AR-LV18QN88PC8I7 GW1NSR-LV4CMG64PC7I6 V3.0
Summary of Contents for GOWIN DK USB2.0 GW2AR-LV18QN88PC8I7 GW1NSR-LV4CMG64PC7I6 V3.0
- Page 1 DK_USB2.0_GW2AR-LV18QN88PC7I6_GW 1NSR-LV4CMG64PC7I6_V3.0 User Guide DBUG408-1.0E, 07/15/2022...
- Page 2 Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is a trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 07/15/2022 1.0E Initial version published.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 1 1.4 Support and Feedback ....................... 2 2 Development Board Introduction .............. - Page 5 Contents 3.5 USB 2.0 interface ......................11 3.5.1 Introduction ........................11 3.5.2 Pinout ..........................11 3.6 GPIO ..........................13 3.6.1 Introduction ........................13 3.6.2 Pinout ..........................14 3.7 LED Module ........................15 3.7.1 Introduction ........................15 3.7.2 Pinout ..........................15 3.8 Keys Module ........................
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Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_USB2.0_GW2AR-LV18QN88PC8I7_GW1NSR-LV4CMG64PC7I6_ V3.0 Development Board ..............................3 Figure 2-2 A Development Board Suite ..................... 5 Figure 2-3 PCB Components ......................6 Figure 2-4 System Block Diagram ..................... 6 Figure 3-5 Connection Diagram of FPGA Download and Configuration ........... 9 Figure 3-6 Connection Diagram of Clock and Reset ................. - Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................2 Table 3-5 FPGA-GW2AR-LV18QN88P Download and Configuration Pinout ........9 Table 3-6 FPGA-GW1NSR-LV4CMG64P Download and Configuration Pinout ........ 9 Table 3-7 GW1NSR-LV4CMG64P Clock and Reset Pinout .............. 11 Table 3-8 GW2AR-LV18QN88P Clock and Reset Pinout ..............
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Page 8: About This Guide
1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose DK_USB2.0_GW2AR-LV18QN88PC8I7_GW1NSR-LV4CMG64PC7I6 _V3.0 development board (hereinafter referred to development board) user guide consists of following three parts: 1. A brief introduction to the features of the development board; 2. An introduction to the development board system architecture and hardware resources;... -
Page 9: Support And Feedback
Low-Voltage Differential Signaling SSRAM Shadow Static Random Access Memory 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com... -
Page 10: Development Board Introduction
GW1NSR-4C and GW2AR-18 series of FPGA, hardware reliability verification, and software learning and debugging. The development board uses Gowin GW2AR-LV18QN88P FPGA products, which are the first generation products of the Arora family. As a DBUG408-1.0E... -
Page 11: A Development Board Kit
FPGA architecture with a 55nm process to make the GW2AR series of FPGA products ideal for high-speed and low-cost applications. The development board uses Gowin GW1NSR-LV4CMG64P FPGA ® products, which are the first generation products of the LittleBee family. -
Page 12: Figure 2-2 A Development Board Suite
2 Development Board Introduction 2.2 A Development Board Kit Figure 2-2 A Development Board Suite ① DK_Motor_GW2A-LV55PG484C8I7_V3.0 development board ② USB Mini B data cable ③ 5V power (Input: 100-240V~50/60Hz 0.5A, Output: DC 5V 2A) DBUG408-1.0E 5(16) -
Page 13: Pcb Components
2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components FPGA OSCGPIO 1.2V JTAG Power: USB2.0 5V IN Flash 1.8V/3.3V USB2.0 1.0V MODE JTAG OSC FPGA GPIO 2.4 System Block Diagram Figure 2-4 System Block Diagram 5V，3.3V，... -
Page 14: Features
2 Development Board Introduction 2.5 Features 2.5 Features The key features are as follows: 1. The FPGA device Gowin GW2AR-LV18QN88P, GW1NSR-LV4CMG64P Max. user I/O : 66, 55 2. Download and Boot Integrate download module on the board, download through JTAG ... -
Page 15: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW2AR FPGA products, please refer to DS226, GW2AR Series of FPGA Products. For the resources of GW1NSR FPGA products, please refer to DS861, GW1NSR Series of FPGA Products. -
Page 16: Pinout
3 Development Board Circuit 3.2 Download Module 2. Set MODE as "011" to download the bitstream file to the external Flash. Set MODE to "000" and power on again. The device will read the FPGA configuration data from the Flash automatically. The connection diagram of download and configuration is as shown in Figure 3-1. -
Page 17: Power Supply
3 Development Board Circuit 3.3 Power Supply Signal Name FPGA Pin No. BANK I/O Level Description F1_TDI 3.3V JTAG Signal F1_TMS 3.3V JTAG Signal 3.3 Power Supply 3.3.1 Introduction The development board is powered via a power adapter. The input parameter is 100-240V~50/60MHz 25VA, and the output is DC +5V 2A. -
Page 18: Pinout
3 Development Board Circuit 3.5 USB 2.0 interface 3.4.2 Pinout Table 3-3 GW1NSR-LV4CMG64P Clock and Reset Pinout Signal Name FPGA Pin No. BANK I/O Level Description F1_CLK 3.3V 12MHz crystal oscillator input F1_IIS_CLK 3.3V 8.192MHz F1_RST_N 3.3V Reset Signal, active Low Table 3-4 GW2AR-LV18QN88P Clock and Reset Pinout Signal Name FPGA Pin No. -
Page 19: Table 3-10 Gw2Ar-Lv18Qn88P Usb 2.0 Module Pinout
3 Development Board Circuit 3.5 USB 2.0 interface Signal Name FPGA Pin No. BANK I/O Level Description signal USB_1N_D-_CP 3.3V USB- signal USB_1N_D+/-_CN 3.3V USB- Reference signal Terminal resistance control at high speed, 1N_Term_p 3.3V USB data pin at full speed and low speed Terminal resistance control at high speed,... -
Page 20: Gpio
3 Development Board Circuit 3.6 GPIO 3.6 GPIO 3.6.1 Introduction There are 40 GPIOs reserved on the development board, including eight 3.3V pins, four ground pins, fourteen GW1NSR-LV4CMG64P pins, and fourteen GW2AR-LV18QN88P pins. The connection diagram is as shown in Figure 3-4. Figure 3-4 Connection Diagram of GPIO DBUG408-1.0E 13(16) -
Page 21: Pinout
3 Development Board Circuit 3.6 GPIO 3.6.2 Pinout Table 3-7 GW1NSR-LV4CMG64P GPIO Pinout Signal Name FPGA Pin No. BANK I/O Level Description 1N_GPIO0 3.3V GPIO0 1N_GPIO1 3.3V GPIO1 1N_GPIO2 3.3V GPIO2 1N_GPIO3 3.3V GPIO3 1N_GPIO4 3.3V GPIO4 1N_GPIO5 3.3V GPIO5 1N_GPIO6 3.3V GPIO6... -
Page 22: Led Module
3 Development Board Circuit 3.7 LED Module 3.7 LED Module 3.7.1 Introduction Two green LEDs on the development board and are used to display the required status. When the output signal of FPGA corresponding pin is low, the LED is lit up. When the output signal is high, the LED is off. The connection diagram is as shown in Figure 3-5. -
Page 23: Pinout
3 Development Board Circuit 3.8 Keys Module Figure 3-6 Key Circuit 3.8.2 Pinout Table 3-11 GW1NSR-LV4CMG64P Keys Module Pinout Signal Name FPGA Pin No. BANK I/O Level Description F1_RST_N 3.3V KEY1 Table 3-12 GW2AR-LV18QN88P Key Module Pinout Signal Name FPGA Pin No. BANK I/O Level Description...
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