Analog Devices AD9779A Quick Start Manual page 7

Quick Start Guide AD9779A/78A/76A-DPG2-EBZ
AD9779A SPI Application
The SPI application is split into several sections. These sections control the different features of the AD9779A but can be left in the default
positions if you are not using the features i.e. internal PLL, multi chip sync, aux DACs . Several of the functions provided by the SPI
application are described here, as they relate to the evaluation board. For complete descriptions of each register, refer to the AD9779A
datasheet. In the interest of continuous quality improvements, the images below may not exactly match your version of the software. In
order to set the registers with the VI you must click the mouse on the arrow under the edit for updating what is selected below or the right
circular arrows continuously updates as features are selected in the various sections of the VI
Comms
The COMMS section, is the section in the top left hand corner and has the software reset, power down and auto powerdown enable
controls.
Filter
The FILTER section just to the right of the COMMs section provides control over the Interpolation Rate (2x,4x,8x or bypass) and Coarse
Modulation via selection of the filter mode with read backs for each. This section also includes the zero stuff feature and inverse Sinc
feature.
DATA
The DATAFMT field selects the number format of the incoming data, between unsigned (Binary) and signed (2's complement), default on
DPG2 is binary but can be switched to 2's complement if desired. The QFirst control selects which DAC receives data first from the
interleaved bus. For use with the DPG2, this should always be set to IQ Pairs and the button should be green next to the IQ pairs. Real
mode is for turning off the Q path for a real type application instead of the default complex mode. Single/interleaved is for changing to
single port and using an interleaved data format. The TX Invert allows inversion of the Tx Enable signal.
DATA Clock
The data clock section includes control for Data clk delay if needed for adjusting the timing on the interface.
PLL Control
The AD9779A has an on-chip PLL. When PLL_ENABLE is turned on, the chip will automatically select the appropriate band using the
Divder1 and Divider0 values. The VCO Frequency must be between 1 and 2 GHz for proper operation. The auto-band select can be
bypassed by enabling PLL MANUAL and entering a band in PLL Band Select. Divider1 and Divider0 must still be chosen appropriately in
this mode of operation.
Main DAC Control
This section controls the two main DACs in the AD9779A. The Full-Scale Current of each DAC can be set with the I DAC Gain and Q
DAC Gain controls. The 512 default is for 20ma outputs. The I Sleep and Q Sleep controls put their respective DAC into a low-power sleep
state. The IDAC and QDAC power down shuts off the DACs and the signal processing circuit also.
Aux DAC Control
The Aux DAC control section is used to program aux DACs for LO and image suppression out the output of the AQM. The default is the
Aux DACs are programmed power down.
SPI Settings Save/load
This section is for saving and reloading your SPI settings so you can use your previous set up. To save a set up slide the save button to turn
on and hit the run arrow at the top. To load a file click on the box for browse or type in the file location and click the button to turn on
and then hit the run arrow to load this file.
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