Analog Devices AD9858PCB Manual

INTRODUCTION
The AD9858 is a 1 GHz direct digital synthesizer (DDS)
featuring a 10-bit DAC, an RF mixer, and on-chip PLL synthesis
blocks. Used in conjunction, the various components of the
AD9858 allow the user to construct translation loops (also
known as offset loops), fractional divider loops, traditional
integer-N PLL loops, as well as frequency synthesis directly
from the DDS. Because different systems require different
connections and different external components, each evaluation
board was designed with a specific application in mind. This
document addresses the evaluation board that allows each of
the frequency synthesis blocks to be used or left unused at the
discretion of the user. Included within is information on system
requirements, installing the evaluation software, menus and
buttons, and window environments. Documentation for the
other boards (fractional-divide loop and translation loop) is
also accessible from the Design Tools section of the Analog
Devices DDS homepage: www.analog.com/dds.
AD9858
DDS LO
J4
REFCLOCK
IN
MIXER
REFCLK
IOUT REF
J3
DAC
OUTPUT
Figure 1. AD9858 DAC Output Evaluation Board
Rev. 0
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J5 LO IN
RF
J7 RF IN
IF
J9 IF OUT
PLL
÷16
DIV
VCO
CP
LPF
J8
COMPARATOR
2 IN
DDS DAC Output Evaluation Board
CIRCUIT OVERVIEW
The DAC-output evaluation board was designed to allow the
user full control over some or all of the functional blocks of the
AD9858. Each of the functional blocks has its inputs and
outputs brought on and off board separately. Users can
configure and connect the DDS block, the PLL block, and the
mixer block in whatever fashion they wish, bounded by the
parametric limitations of the device. For example, if a user
wished to only evaluate the RF mixer, the external reference
(REFCLK) to the DDS core and the PLL inputs could be left
unconnected. This allows the user to evaluate the performance
of the mixer as an individual component.
The DAC output board allows for external REFCLK signals up
to 2 GHz. For REFCLK signals between 1 GHz and 2 GHz, the
on-chip clock divider (divide-by-2) must be used. The user has
control over the output frequency by adjusting the tuning word
of the DDS. The frequency tuning word and reference clock
determine the output frequency of the DDS according to the
following equation:
=
F
o
given that 0 ≤ FTW ≤ 2
turning word. For the AD9858, N = 32.
This equation is for the DDS operating with the divide-by-2
function enabled on the REFCLK path (which is the default
J1
setting). When the divide-by-2 function is not enabled, the
RF
OUT
divisor is simply 2
supplied to the user via an SMA connection.
To evaluate the phase detector/charge pump block, the reference
input of the phase detector (labeled 'comparator 2 in' on the
evaluation board schematic) can be accessed. The output of the
PLL block, the charge pump output signal, is fed to the loop
filter included on the evaluation board. The filtered charge
pump output signal drives the included VCO. The output
frequency of the VCO varies between 1530 MHz and 1630 MHz
and is available via the RF Out connector. The RF Out signal is
divided by 16 and fed back to the other phase detector input.
To evaluate the on-chip RF mixer, users can access the inputs
(RF , LO ) and the output (IF
in in
applications, the DDS, the PLL block, and the RF mixer block
can be interconnected with SMA cables. Thus, the output of the
PLL block, RF Out, could be used as the REFCLK for the DDS
(if the divide-REFCLK-by-2 function of the DDS is enabled).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
AD9858PCB
×
FTW REFCLK
N
2× 2
31
and N is the number of bits in the
N
. The unfiltered output of the DDS is
). To build different
Out
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