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Features
• Low-cost solution for low-speed applications with high
I/O requirements such as keyboards, keyboards with
integrated pointing device, gamepads, and many
others
• USB Specification Compliance
— Conforms to USB Specification, Versions 1.1 and 2.0
— Conforms to USB HID Specification, Version 1.1
— Supports 1 device address and 3 data endpoints
— Integrated USB transceiver
• 8-bit RISC microcontroller
— Harvard architecture
— 6-MHz external ceramic resonator
— 12-MHz internal CPU clock
• Internal memory
— 256 bytes of RAM
— 8 Kbytes of EPROM
• Interface can auto-configure to operate as PS2 or USB
• I/O port
— The CY7C63413C/513C have 24 General Purpose I/O
(GPIO) pins (Port 0 to 2) capable of sinking 7 mA per
pin (typical)
— The CY7C63613C has 12 General Purpose I/O (GPIO)
pins (Port 0 to 2) capable of sinking 7 mA per pin
(typical)
— The CY7C63413C/513C have eight GPIO pins (Port
3) capable of sinking 12 mA per pin (typical) which
can drive LEDs
— The CY7C63613C has four GPIO pins (Port 3) capable
of sinking 12 mA per pin (typical) which can drive
LEDs
— Higher current drive is available by connecting
multiple GPIO pins together to drive a common
output
— Each GPIO port can be configured as inputs with
internal pull-ups or open drain outputs or traditional
CMOS outputs
— The CY7C63513C has an additional eight I/O pins on
a DAC port which has programmable current sink
outputs
— Maskable interrupts on all I/O pins
• 12-bit free-running timer with one microsecond clock
ticks
• Watch Dog Timer (WDT)
• Internal Power-On Reset (POR)
• Improved output drivers to reduce EMI
Cypress Semiconductor Corporation
Document #: 38-08027 Rev. *B
Low-Speed High I/O, 1.5-Mbps USB Controller
•
198 Champion Court
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0 to 70 degrees Celsius
• CY7C63413C available in 40-pin PDIP, 48-pin SSOP, 48-
pin SSOP - Tape reel, all in Lead-Free versions for
production
• CY7C63513C available in 48-pin SSOP Lead-Free
packages for production
• CY7C63613C available in 24-pin SOIC Lead-Free
packages for production
• Industry-standard programmer support
Functional Overview
The CY7C63413C/513C/613C are 8-bit RISC One Time
Programmable (OTP) microcontrollers. The instruction set has
been optimized specifically for USB operations, although the
microcontrollers can be used for a variety of non-USB
embedded applications.
The CY7C63413C/513C features 32 General-Purpose I/O
(GPIO) pins to support USB and other applications. The I/O
pins are grouped into four ports (Port 0 to 3) where each port
can be configured as inputs with internal pull-ups, open drain
outputs, or traditional CMOS outputs. The CY7C63413C/513C
have 24 GPIO pins (Ports 0 to 2) that are rated at 7 mA typical
sink current. The CY7C63413C/513C has 8 GPIO pins (Port
3) that are rated at 12 mA typical sink current, which allows
these pins to drive LEDs.
The CY7C63613C features 16 General-Purpose I/O (GPIO)
pins to support USB and other applications. The I/O pins are
grouped into four ports (Port 0 to 3) where each port can be
configured as inputs with internal pull-ups, open drain outputs,
or traditional CMOS outputs. The CY7C63613C has 12 GPIO
pins (Ports 0 to 2) that are rated at 7 mA typical sink current.
The CY7C63613C has 4 GPIO pins (Port 3) that are rated at
12 mA typical sink current, which allows these pins to drive
LEDs.
Multiple GPIO pins can be connected together to drive a single
output for more drive current capacity. Additionally, each I/O
pin can be used to generate a GPIO interrupt to the microcon-
troller. Note the GPIO interrupts all share the same "GPIO"
interrupt vector.
The CY7C63513C features an additional 8 I/O pins in the DAC
port. Every DAC pin includes an integrated 14-Kohm pull-up
resistor. When a "1" is written to a DAC I/O pin, the output
current sink is disabled and the output pin is driven high by the
internal pull-up resistor. When a "0" is written to a DAC I/O pin,
the internal pull-up is disabled and the output pin provides the
programmed amount of sink
current. A DAC I/O pin can
be used as an input with an
internal pull-up by writing a
"1" to the pin.
,
•
San Jose
CA 95134-1709
CY7C63413C
CY7C63513C
CY7C63613C
•
408-943-2600
Revised January 6, 2006
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Related Manuals for Cypress Semiconductor CY7C63413C
Summary of Contents for Cypress Semiconductor CY7C63413C
- Page 1 Document #: 38-08027 Rev. *B • Operating voltage from 4.0V to 5.5V DC • Operating temperature from 0 to 70 degrees Celsius • CY7C63413C available in 40-pin PDIP, 48-pin SSOP, 48- pin SSOP - Tape reel, all in Lead-Free versions for production •...
- Page 2 This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6 and 12- MHz clocks that remain internal to the microcontroller. The CY7C63413C/513C/613C are offered with single EPROM options. CY7C63413C, CY7C63513C CY7C63613C have 8 Kbytes of EPROM.
-
Page 3: Pin Configuration
P2[5] P2[3] P2[1] PS/2 D– P1[7] PORT P1[5] P1[3] P1[1] DAC[7] DAC[5] P0[7] P0[5] P0[3] P0[1] DAC[3] DAC[1] CY7C63413C 40-pin PDIP See Note 1 P0[0] D– P0[7] P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] P1[0] P2[7] P2[6] P2[5] P2[4]... -
Page 4: Pin Definitions
14-bit Program Counter (PC) The 14-bit Program Counter (PC) allows access for up to 8 kilobytes of EPROM using the CY7C63413C/513C/613C architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. - Page 5 For USB applications, it is strongly recommended that the DSP is loaded after reset just below the USB DMA buffers. Address Modes The CY7C63413C/513C/613C microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. Document #: 38-08027 Rev. *B...
- Page 6 SWAP A,X SWAP A,DSP MOV [expr],A MOV [X+expr],A OR [expr],A OR [X+expr],A AND [expr],A AND [X+expr],A XOR [expr],A XOR [X+expr],A IOWX [X+expr] RETI JACC INDEX CY7C63413C CY7C63513C CY7C63613C operand opcode cycles direct index direct index address address direct index direct...
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Page 7: Memory Organization
0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here (8K - 32 bytes) 0x1FDF 8-KB PROM ends here (CY7C63413C, CY7C63513C, CY7C63613C) CY7C63413C CY7C63513C CY7C63613C Page 7 of 32 [+] Feedback... - Page 8 Data Memory Organization The CY7C63413C/513C/613C microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned after reset Address 8-bit PSP 0x00 8-bit DSP user 0xE8 0xF0 0xF8 Top of RAM Memory 0xFF Document #: 38-08027 Rev. *B...
- Page 9 Watch Dog Reset clear DAC I/O Interrupt enable for each DAC pin Interrupt polarity for each DAC pin One four bit sink current register for each DAC pin Microprocessor status and control CY7C63413C CY7C63513C CY7C63613C Page 9 of 32 [+] Feedback...
- Page 10 LOW to HIGH. In addition to the normal reset 2.048 ms WDR goes high Execution begins at for 2.048 ms Reset Vector 0X00 Figure 3. Watch Dog Reset (WDR) CY7C63413C CY7C63513C CY7C63613C XTALOUT XTALIN voltage to ) and the USB IO are at...
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Page 11: General Purpose I/O Ports
Port Read to Interrupt Controller Figure 4. Block Diagram of a GPIO Line Port 0 Data P0[4] P0[3] Port 1 Data P1[4] P1[3] Port 2 Data P2[4] P2[3] CY7C63413C CY7C63513C CY7C63613C GPIO P0[2] P0[1] P0[0] P1[2] P1[1] P1[0] P2[2] P2[1] P2[0]... - Page 12 Port 1 Interrupt Enable P1[4] P1[3] P1[2] Port 2 Interrupt Enable P2[4] P2[3] P2[2] Port 3 Interrupt Enable P3[4] P3[3] P3[2] CY7C63413C CY7C63513C CY7C63613C P3[1] P3[0] High current outputs 3.2 mA to 16 mA typical DAC[1] DAC[0] P0[1] P0[0] P1[1]...
- Page 13 Config Bit 0 Table 12.GPIO Configuration Register 14 KΩ 4 bits Isink Isink Register to Interrupt Controller Figure 5. Block Diagram of DAC Port CY7C63413C CY7C63513C CY7C63613C Interrupt Polarity disabled disabled + (default) Port 1 Port 0 Port 0 Config Bit 1...
- Page 14 DAC Port Interrupt Enable DAC[4] DAC[3] DAC[2] DAC Port Interrupt Polarity DAC[4] DAC[3] DAC[2] DAC Port Interrupt Polarity Isink[3] Isink[2] CY7C63413C CY7C63513C CY7C63613C High current outputs 3.2 mA to 16 mA typical DAC[1] DAC[0] DAC[1] DAC[0] DAC[1] DAC[0] Isink Value...
-
Page 15: Usb Serial Interface Engine (Sie)
USB. PS/2 Operation PS/2 operation is possible with the CY7C63413C/513C/613C series through the use of firmware and several operating modes. The first enabling feature: 1. USB Bus reset on D+ and D− is an interrupt that can be disabled;... -
Page 16: Usb Device
Address Address Bit 4 Bit 3 USB Device EPA0, Mode Register Acknowledge Mode Bit 3 USB Device Endpoint Mode Register Acknowledge Mode Bit 3 CY7C63413C CY7C63513C CY7C63613C Device Device Address Address Bit 2 Bit 1 Bit 0 Mode Mode Mode... - Page 17 Toggle bit 7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. USB Device Counter Registers Reserved Byte count Byte count Bit 3 Bit 2 CY7C63413C CY7C63513C CY7C63613C Byte count Byte count Bit 1 Bit 0 Page 17 of 32...
-
Page 18: Processor Status And Control Register
Suspend, Wait Reset for Interrupt halted until a reset (Power On or Watch Dog). Notice, when writing to the processor status and control register, the run bit should always be written as a “1.” CY7C63413C CY7C63513C CY7C63613C Timer Timer Timer... - Page 19 ZF are restored and interrupts are enabled when the RETI instruction is executed. Global Interrupt Enable Register Reserved Interrupt Enable USB End Point Interrupt Enable Register Reserved Reserved CY7C63413C CY7C63513C CY7C63613C 1.024-ms 128-µsec USB Bus RST Interrupt Interrupt Interrupt Enable...
- Page 20 The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. CY7C63413C CY7C63513C CY7C63613C Function Page 20 of 32...
-
Page 21: Truth Tables
Control endpoint if it is placed in a non appropriate mode. A ‘check’ on an Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG) of 1. CY7C63413C CY7C63513C CY7C63613C Page 21 of 32... - Page 22 ISR to unlock and get the mode register infor- mation. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction. CY7C63413C CY7C63513C CY7C63613C What the SIE does to Mode bits...
- Page 23 CY7C63413C CY7C63513C CY7C63613C Set End Point Mode response NoChange ignore NoChange ignore NoChange ignore NoChange NoChange NoChange ignore NoChange ignore NoChange Stall...
- Page 24 DVAL COUNT Setup updates updates updates updates updates updates updates updates updates updates updates updates CY7C63413C CY7C63513C CY7C63613C Set End Point Mode response Stall UC UC UC UC ignore UC UC UC UC ignore Stall NoChange ignore NoChange ignore NoChange...
-
Page 25: Absolute Maximum Ratings
14.25 15.75 kΩ 4.9K 9.1K Ohms range, as well as DAC outputs. CC (2) is limited to minimize Ground-Drop noise effects. CY7C63413C CY7C63513C CY7C63613C +0.5V +0.5V Conditions Non USB activity (note 4) USB activity (note 5) = 5.5V Oscillator off, D– > Voh min = 5.0V, ceramic resonator... -
Page 26: Switching Characteristics
–95 To next transition, Figure 12 –150 To paired transition, Figure 12 of 50–600 pF. LOAD CY7C63413C CY7C63513C CY7C63613C Conditions All ports, HIGH to LOW edge Port 3, Vout = 1.0V (note 4) Port 0,1,2, Vout = 2.0V (note 4) Voh = 2.4V (all ports 0,1,2,3) (note 4) - Page 27 Document #: 38-08027 Rev. *B Figure 8. Clock Timing Figure 9. USB Data Signal Timing Consecutive Transitions N * T PERIOD Paired Transitions N * T PERIOD Figure 10. Receiver Jitter Tolerance CY7C63413C CY7C63513C CY7C63613C Page 27 of 32 [+] Feedback...
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Page 28: Ordering Information
SE0 Skew N * T Figure 11. Differential to EOP Transition Skew and EOP Width PERIOD Differential Data Lines Ordering Information EPROM Ordering Code Size CY7C63413C-PVXC 8 KB CY7C63413C-PVXCT 8 KB CY7C63413C-PXC 8 KB CY7C63513C-PVXC 8 KB CY7C63613C-SXC 8 KB CY7C63413C-XC Document #: 38-08027 Rev. - Page 29 721.05 DAC6 618.05 DAC4 516.25 Port0[6] 413.25 Port0[4] 98.00 Port0[2] 98.00 Port0[0] 98.00 DAC2 98.00 DAC0 98.00 XtalOut 98.00 XtalIn CY7C63413C CY7C63513C CY7C63613C 1619.65 3023.60 1719.65 3023.60 1823.10 3023.60 1926.10 3023.60 2066.30 2657.35 2066.30 2554.35 2066.30 2451.35 2066.30 2348.35 2066.30 2245.35...
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Page 30: Package Diagrams
CY7C63413C CY7C63513C CY7C63613C Package Diagrams 48-Lead Shrunk Small Outline Package SP48 51-85061-*C 40-Lead (600-Mil) Molded DIP P2 51-85019-*A Document #: 38-08027 Rev. *B Page 30 of 32 [+] Feedback... - Page 31 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE MIN. 3. DIMENSIONS IN INCHES MAX. 4. PACKAGE WEIGHT 0.65gms 0.394[10.007] 0.419[10.642] SEATING PLANE 0.092[2.336] 0.105[2.667] 0.004[0.101] CY7C63413C CY7C63513C CY7C63613C PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. 0.0091[0.231] 0.015[0.381] 0.0125[0.317] 0.050[1.270] 51-85025-*C...
- Page 32 Document History Page Document Title: CY7C63413C, CY7C63513C, CY7C63613C Low-speed High I/O, 1.5 -Mbps USB Controller Document Number: 38-08027 Issue REV. ECN NO. Date 116224 06/12/02 237148 SEE ECN 418699 See ECN Document #: 38-08027 Rev. *B Orig. of Change Description of Change...
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