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Features
• Fixed-function mass storage device—requires no firmware
• Two power modes: Self-powered and USB bus-powered to
enable bus powered CF readers and truly portable USB
hard drives
• Certified compliant for USB 2.0 (TID# 40490119), the USB
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification
• Operates at high-speed (480 Mbps) or full-speed (12 Mbps)
USB
• Complies with ATA/ATAPI-6 specification
• Supports 48 bit addressing for large hard drives
• Supports ATA security features
• Supports any ATA command with the ATACB function
• Supports mode page 5 for BIOS boot support
• Supports ATAPI serial number VPD page retrieval for Digital
Rights Management (DRM) compatibility
• Supports PIO modes 0, 3, and 4, multiword DMA mode 2,
and UDMA modes 2, 3, and 4
• Uses one small external serial EEPROM for storage of USB
descriptors and device configuration data
• ATA interface IRQ signal support
• Supports one or two ATA/ATAPI devices
Block Diagram
24
MHz
XTAL
VBUS
D+
USB
D-
Cypress Semiconductor Corporation
Document 001-05809 Rev. *A
EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
SCL
2
I
C Bus Master
SDA
PLL
Internal Control Logic
USB 2.0
CY Smart USB
Tranceiver
FS/HS Engine
•
198 Champion Court
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
• Supports CompactFlash and one ATA/ATAPI device
• Supports board-level manufacturing test using the USB I/F
• Can place the ATA interface in high impedance (Hi-Z) to
allow sharing of the ATA bus with another controller (i.e., an
IEEE-1394 to ATA bridge chip or MP3 Decoder)
• Low-power 3.3V operation
• Fully compatible with native USB mass storage class drivers
• Cypress mass storage class drivers available for Windows
(98SE, ME, 2000, XP) and Mac OS X operating systems
Features (CY7C68320C/CY7C68321C only)
• Supports HID interface or custom GPIOs to enable features
such as single button backup, power-off, LED-based notifi-
cation, etc.
• 56-pin QFN and 100-pin TQFP lead-free packages
• CY7C68321C is ideal for battery-powered designs
• CY7C68320C is ideal for self- and bus-powered designs
Features (CY7C68300C/CY7C68301C only)
• Pin-compatible with CY7C68300A (using Backward
Compatibility mode)
• 56-pin SSOP and 56-pin QFN lead-free packages
• CY7C68301C is ideal for battery-powered designs
• CY7C68300C is ideal for self- and bus-powered designs
Misc control signals and GPIO
ATA 3-state Control
ATA Interface
Control
Control Signals
ATA
Interface
Logic
4 kByte FIFO
Data
16 Bit ATA Data
,
•
San Jose
CA 95134-1709
•
408-943-2600
Revised November 30, 2006
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Table of Contents
Related Manuals for Cypress Semiconductor CY7C68300C
Summary of Contents for Cypress Semiconductor CY7C68300C
- Page 1 • Pin-compatible with CY7C68300A (using Backward Compatibility mode) • 56-pin SSOP and 56-pin QFN lead-free packages • CY7C68301C is ideal for battery-powered designs • CY7C68300C is ideal for self- and bus-powered designs C Bus Master Misc control signals and GPIO Internal Control Logic...
- Page 2 AT2LP to initialize ATA/ATAPI devices without software inter- vention. CY7C68300A Compatibility As mentioned above, the CY7C68300C/301C contains a backward compatibility mode that allows it to be used in existing EZ-USB AT2 (CY7C68300A) designs. The backward compatibility mode is enabled by programming the EEPROM with the CY7C68300A signature.
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Page 3: Dmack
The AT2LP is available in different package types to meet a variety of design needs. The CY7C68320C/321C is available in 56-pin QFN and 100-pin TQFP packages to provide the greatest flexibility for new designs. The CY7C68300C/301C is available in 56-pin SSOP and QFN package types to ensure backward compatibility with CY7C68300A designs. - Page 4 Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C68301C) IORDY DMARQ AVCC XTALOUT XTALIN AGND DPLUS DMINUS NOTE: Italic labels denote pin functionality (PU10K) PWR500# Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFN during CY7C68300A compatibility mode. RESET# ARESET#...
- Page 5 Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C68321C) DD13 DD14 DD15 GPIO2 IORDY DMARQ AVCC XTALOUT XTALIN AGND DPLUS DMINUS GPIO1 Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C DD12 DD11 DD10 VBUS_ATA_ENABLE RESET# ARESET# CS1# CS0# GPIO0 EZ-USB AT2LP CY7C68320C INTRQ CY7C68321C 56-pin SSOP...
- Page 6 Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C68321C) IORDY DMARQ AVCC XTALOUT XTALIN AGND DPLUS DMINUS GPIO1 Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFN RESET# ARESET# CS1# CS0# GPIO0 INTRQ DMACK# DIOR# DIOW# Page 6 of 42...
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Page 7: Table Of Contents
Figure 6. 100-pin TQFP Pinout (CY7C68320C/CY7C68321C only) IORDY DMARQ AVCC XTALOUT XTALIN AGND DPLUS DMINUS SYSIRQ PWR500# Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C VBUS_ATA_ENABLE EZ-USB AT2LP CY7C68320A CY7C68321A 100-pin TQFP RESET# ARESET# CS1# CS0# DRVPWRVLD INTRQ VBUSPWRD LOWPWR# DMACK# DIOR#... - Page 8 1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See page 14 2. A ‘#’ sign after the pin name indicates that it is active LOW. Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C 68300C/01C and 68320C/321C pinouts for the 56-pin packages. For information on the CY7C68300A pinout, refer to the CY7C68300A data sheet that is found in the ’EZ-USB...
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Page 9: Vbuspwrd
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) Pin Name TQFP SSOP DIOW# DIOR# DMACK# LOWPWR# VBUSPWRD INTRQ Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Default State Type at Startup Data signal for I C interface. (See page 11). Apply a 2.2k pull up resistor. No connect. - Page 10 DD10 DD11 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 DD12 DD13 DD14 DD15 Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Default State Type at Startup Driven HIGH ATA address. after 2 ms delay Driven HIGH ATA address. after 2 ms delay Input Device presence detect.
- Page 11 C port must be connected to the configuration EEPROM and to 2.2K pull up resistors tied to V . If no EEPROM is used in the design, the SCL and SDA Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Default State Type at Startup Bus-powered ATA pull up voltage source (see “ATAPUEN”...
- Page 12 Table 3. Interrupt Data Bitmap EP1 Data Byte 1 Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C inputs or outputs, with byte 0x09 of the configuration data. The state of any GPIO pin that is not set as an input is reported as ‘0’...
- Page 13 VBUS_ATA_ENABLE is not asserted. Design practices for signal integrity as outlined in the ATA/ATAPI-6 specification must be followed with systems that utilize a ribbon cable interconnect between the AT2LP’s ATA CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C SYSIRQ=1? Latch State of IO Pins Set Int_Data = 1...
- Page 14 While the AT2LP is in reset, all pins are held at their default startup state. Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C PWR500# The AT2LP asserts PWR500# to indicate that VBUS current may be drawn up to the limit specified by the bMaxPower field of the USB configuration descriptors.
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Page 15: Functional Overview
CBWCB remain as defined in the USB Mass Storage Class Bulk-Only Transport Specification. The ATACB 15. Refer to the USB must be 16 bytes in length. The following table and text defines the fields of the ATACB. CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C USB Interrupt Data Byte 0 AT2LP translates... - Page 16 CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Field Description This field indicates to the CY7C68300C/CY7C68301C that the ATACB contains a vendor-specific command block. This value of this field must match the value in EEPROM address 0x04 for the command to be recognized as a vendor-specific ATACB command.
- Page 17 5–12 bATACBTaskFileWriteData 13–15 Reserved Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Field Description This field controls which of the taskfile register read or write accesses occur. Taskfile read data is always 8 bytes in length, and unselected register data are returned as 0x00. Register accesses occur in sequential order as outlined...
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Page 18: Operating Modes
• If an EEPROM signature of 0x4D4D is found, the CY7C68300C/CY7C68301C uses the same pinout and C bus EEPROM format as the CY7C68300A (EZ-USB AT2+). • If an EEPROM signature of 0x534B is found, the AT2LP uses the values stored in the EEPROM to configure the USB descriptors for normal operation. - Page 19 Reserved (0) 14 (0Eh) Reserved (0) 15–30 (0Fh1Eh) Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C ATAPI command for EEPROM accesses (CfgCB) and one for board level testing (MfgCB), as described in the following sections. There is a convenient method available for starting the AT2LP in Board Manufacturing Test Mode to allow reprogramming of EEPROMs without a mass storage device attached.
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Page 20: Drvpwrvld
4 bytes is recommended. To exit Manufacturing Test Mode, a hard reset (toggle RESET#) is required. Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Mfg_read This USB request returns a ’snapshot’ of select AT2LP input pins. - Page 21 (refer to Figure 11). The ‘AT2LP Primer’ tool can be used to Figure 11. Snapshot of ‘AT2LP Blaster’ Utility Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C program AT2LP-based environment and provides for serial number randomization. “Board Manufacturing Test Mode” on page 19...
- Page 22 Enable a delay of up to 120 ms at each read of the DRQ bit where the device data length does not match the host data length. This allows the CY7C68300C/CY7C68301C to work with most devices that incorrectly clear the BUSY bit before a valid status is present.
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Page 23: Areset
UDMA Modes 0x07 Reserved Multi-word DMA mode PIO Modes Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Bit 1 Determines if the AT2LP is to do an SRST reset during drive initialization. At least one reset must be enabled. Do not set SRST to 0 and Skip Pin Reset to 1 at the same time. -
Page 24: Reset
Drive Power Valid Polarity Drive Power Valid Enable 0x09 Reserved General Purpose IO Pin Output Enable Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Bit 7 Button mode (100-pin package only). Sets ATAPUEN, PWR500# and DRVPWRVLD to become button inputs returned on bits 2, 1, and 0 of EP1IN. - Page 25 0x0F Reserved Device Descriptor 0x10 bLength 0x11 bDescriptor Type Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Bits 7:6 Reserved. Must be set to zero. Bits 5:0 These bits select the value driven on the GPIO pins that are configured as outputs in configuration address 0x09.
- Page 26 0x2E bTotalLength (LSB) 0x2F bTotalLength (MSB) 0x30 bNumInterfaces 0x31 bConfiguration Value Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description USB Specification release number in BCD Device class Device subclass Device protocol USB packet size supported for default pipe Vendor ID. Cypress’ Vendor ID may only be used for evalu- ation purposes, and not in released products.
- Page 27 0x4D bDescriptorTypes 0x4E bInterfaceNumber Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Index to the configuration string. This entry must equal half of the address value where the string starts, or 0x00 if the string does not exist.
- Page 28 0x6F Usage 0x70 0x71 Logical_Minimum 0x72 0x73 Logical_Maximum 0x74 Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Alternate setting Number of endpoints used by this interface Class code Sub class Sub Sub class Index of string descriptor Length of this descriptor in bytes...
- Page 29 Channel Descriptor 0x91 bLength 0x92 bDescriptorType 0x93 bChannelID 0x94 bmAttributes Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description 8 bits 2 fields Input (Data, Variable, Absolute) Usage - vendor defined Logical Minimum (–128) Logical Maximum (127) Report Size 8 bits...
- Page 30 0xB2 bString 0xB3 bString 0xB4 bString Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Identifier of the target recipient If Recipient type field of bmAttributes = 1 then bRecipient field is the bInterfaceNumber If Recipient type field of bmAttributes = 2 then...
- Page 31 0xDA bString 0xDB bString 0xDC bString 0xDD bString 0xDE bString Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB Unicode character LSB...
- Page 32 It is a fixed length (24 bytes). Changing this string may cause CD authoring software to incorrectly identify the device.) 0Xxx Device name byte 1 0Xxx Device name byte 2 0Xxx Device name byte 3 Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description Unicode character LSB Unicode character MSB Unicode character LSB Unicode character MSB...
- Page 33 Vendor-specific USB commands allow the AT2LP to address up to 256 bytes of EEPROM data. LOAD_CONFIG_DATA This request enables writes to the AT2LP’s configuration data space. The wIndex field specifies the starting address and the wLength field denotes the data length in bytes. Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration Item Description ASCII Character...
- Page 34 Illegal values for wValue result in an undefined operation. Attempted reads from an I result in an undefined operation. Attempts to read configuration bytes with starting addresses greater than 0xF also, result in an undefined operation. Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C wValue wIndex...
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Page 35: Absolute Maximum Ratings
Crystal Input LOW Voltage IL_X Output Voltage High Output Voltage Low Output Current High Output Current Low Input Pin Capacitance Suspend Current SUSP CY7C68300C/CY7C68320C Suspend Current CY7C68301C/CY7C68321C Supply Current Unconfigured Current UNCONFIG Reset Time After Valid Power RESET Pin Reset After Power Up Document 001-05809 Rev. -
Page 36: Ac Electrical Characteristics
AT2LP and the attached mass storage device is used. The AT2LP automatically determines the transfer rates during drive initialization based upon the values Ordering Information Part Number CY7C68300C-56PVXC 56 SSOP Lead-free for self- and bus-powered designs CY7C68301C-56PVXC 56 SSOP Lead-free for battery-powered designs CY7C68300C-56LFXC... -
Page 37: Package Diagrams
0° MIN. 0.20 MAX. 0.25 GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C 16.00±0.20 14.00±0.10 0.30±0.08 0.65 TYP. SEATING PLANE STAND-OFF 0.05 MIN. NOTE: 0.15 MAX. 1. JEDEC STD REF MS-026 2. - Page 38 Package Diagrams (continued) Figure 13. 56-lead Shrunk Small Outline Package 056 0.720 0.730 0.088 0.092 0.025 Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C .020 0.395 0.420 0.292 DIMENSIONS IN INCHES MIN. 0.299 SEATING PLANE 0.095 .010 0.110 GAUGE PLANE 0.110 0°-8°...
- Page 39 • Minimize reflected signals by avoiding using stubs and vias. • Connect the USB connector shell and signal ground as near to the USB connector as possible. • Use bypass/flyback capacitors on VBUS near the connector. Document 001-05809 Rev. *A CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C SIDE VIEW 1.00[0.039] MAX. 0.08[0.003] 0.05[0.002] MAX.
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Page 40: Other Design Considerations
Power must be applied to the CY7C68300C/CY7C68301C before, or at the same time as the ATA/ATAPI device. If power is supplied to the drive first, the CY7C68300C/CY7C68301C startup in an undefined state. Designs that utilize separate power supplies for the CY7C68300C/CY7C68301C and the ATA/ATAPI device are not recommended. - Page 41 The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C drives have large enough buffers to handle the flow of data to and from it.
- Page 42 Document History Paged Description Title: CY7C68300C/CY7C68301C/CY7C68320C/CY7C68321C EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge Document Number: 001-05809 REV. ECN NO. Issue Date 409321 See ECN 611658 See ECN Document 001-05809 Rev. *A Orig. of Description of Change Change New data sheet.
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