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Cypress Semiconductor CY7C64013C Specification Sheet

Cypress full-speed usb (12-mbps) function specification sheet
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CY7C64013C
CY7C64113C
Full-Speed USB (12-Mbps) Function
Full-Speed USB (12-Mbps) Function
,
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
CA 95134-1709
•
408-943-2600
Document #: 38-08001 Rev. *B
Revised March 3, 2006
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Summary of Contents for Cypress Semiconductor CY7C64013C

  • Page 1 CY7C64013C CY7C64113C Full-Speed USB (12-Mbps) Function Full-Speed USB (12-Mbps) Function Cypress Semiconductor Corporation • 198 Champion Court • San Jose CA 95134-1709 • 408-943-2600 Document #: 38-08001 Rev. *B Revised March 3, 2006 [+] Feedback...

  • Page 2: Table Of Contents

    16.0 INTERRUPTS ...29 16.1 Interrupt Vectors ...30 16.2 Interrupt Latency ...31 16.3 USB Bus Reset Interrupt ...31 16.4 Timer Interrupt ...31 16.5 USB Endpoint Interrupts ...31 Document #: 38-08001 Rev. *B TABLE OF CONTENTS CY7C64013C CY7C64113C Page 2 of 51 [+] Feedback...
  • Page 3 FOSC = 6 MHZ; OPERATING TEMPERATURE = 0 TO 70°C, V 24.0 SWITCHING CHARACTERISTICS 25.0 ORDERING INFORMATION ...48 26.0 PACKAGE DIAGRAMS ...49 Document #: 38-08001 Rev. *B TABLE OF CONTENTS = 4.0V TO 5.25V ...45 (fOSC = 6.0 MHz) ... 46 CY7C64013C CY7C64113C Page 3 of 51 [+] Feedback...
  • Page 4 CY7C64013C CY7C64113C LIST OF FIGURES Figure 6-1. Clock Oscillator On-Chip Circuit ...17 Figure 7-1. Watchdog Reset (WDR) ...18 Figure 9-1. Block Diagram of a GPIO Pin ...19 Figure 9-2. Port 0 Data ...19 Figure 9-3. Port 1 Data ...19 Figure 9-4. Port 2 Data ...19 Figure 9-5.
  • Page 5 Table 19-1. USB Register Mode Encoding ...39 Table 19-2. Details of Modes for Differing Traffic Conditions Document #: 38-08001 Rev. *B LIST OF TABLES Table 19-1 (see for the decode legend) ... 41 CY7C64013C CY7C64113C Page 5 of 51 [+] Feedback...

  • Page 6: Features

    • Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.5V DC • Operating temperature from 0 to 70 degrees Celsius — CY7C64013C available in 28-pin SOIC and 28-pin PDIP packages — CY7C64113C available in 48-pin SSOP packages • Industry-standard programmer support Document #: 38-08001 Rev.

  • Page 7: Functional Overview

    GPIO The CY7C64013C features 19 GPIO pins to support USB and other applications. The I/O pins are grouped into three ports (P0[7:0], P1[2:0], P2[6:2], P3[2:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs.

  • Page 8: Logic Block Diagram

    High Current P3[2:0] Outputs GPIO Additional PORT 3 P3[7:3] High Current Outputs DAC[0] DAC[2] PORT DAC[7] CY7C64113C only SCLK SDATA Interface C-compatible interface enabled by firmware through P2[1:0] or P1[1:0] CY7C64013C CY7C64113C Upstream USB Port Page 8 of 51 [+] Feedback...

  • Page 9: Pin Configurations

    Pin Configurations CY7C64013C 28-pin SOIC XTALOUT P1[1] XTALIN P1[0] P1[2] P3[0] P3[1] P3[2] D+[0] D–[0] P2[2] P2[3] P2[5] P2[4] P0[7] P2[6] P0[5] P0[3] P0[0] P0[1] P0[2] P0[6] P0[4] Document #: 38-08001 Rev. *B TOP VIEW CY7C64013C 28-pin PDIP XTALOUT XTALOUT...

  • Page 10: Product Summary Tables

    GPIO Port 3 Data Interrupt Enable for Pins in Port 0 Interrupt Enable for Pins in Port 1 Interrupt Enable for Pins in Port 2 Interrupt Enable for Pins in Port 3 CY7C64013C CY7C64113C Description Function Page Page 10 of 51...
  • Page 11 USB Address A, Endpoint 3 Configuration USB Address A, Endpoint 4 Counter USB Address A, Endpoint 4 Configuration Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Microprocessor Status and Control Register CY7C64013C CY7C64113C Page Page 11 of 51 [+] Feedback...

  • Page 12: Table 4-3. Instruction Set Summary

    SWAP A,X SWAP A,DSP MOV [expr],A MOV [X+expr],A OR [expr],A OR [X+expr],A AND [expr],A AND [X+expr],A XOR [expr],A XOR [X+expr],A IOWX [X+expr] RETI JACC INDEX CY7C64013C CY7C64113C operand opcode cycles direct index direct index address address direct index direct index...

  • Page 13: Programming Model

    CY7C64013C CY7C64113C Programming Model 14-Bit Program Counter (PC) The 14-bit program counter (PC) allows access to up to 8 KB of PROM available with the CY7C64x13C architecture. The top 32 bytes of the ROM in the 8 Kb part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h.

  • Page 14: Program Memory Organization

    USB address A endpoint 4 interrupt vector 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 C interrupt vector 0x001A Program Memory begins here 0x1FDF 8 KB (-32) PROM ends here (CY7C64013C, CY7C64113C) CY7C64013C CY7C64113C Page 14 of 51 [+] Feedback...

  • Page 15: 8-Bit Accumulator (A)

    Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 18-1. Document #: 38-08001 Rev. *B Address 0x00 Program Stack Growth user selected Data Stack Growth User variables USB FIFO space for five endpoints 0xFF CY7C64013C CY7C64113C Page 15 of 51 [+] Feedback...

  • Page 16: 8-Bit Data Stack Pointer (Dsp)

    ; Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register Address Modes The CY7C64013C and CY7C64113C microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 Data (Immediate) “Data”...

  • Page 17: Clocking

    30 pF Figure 6-1. Clock Oscillator On-Chip Circuit to stabilize at a valid operating voltage before the chip executes code. drops below approximately 2.5V, and remains asserted until V CY7C64013C CY7C64113C level is has risen above approximately rises above this level...

  • Page 18: Suspend Mode

    Document #: 38-08001 Rev. *B 2 ms WATCH No write to WDT Execution begins at register, so WDR Reset Vector 0x0000 goes HIGH Figure 7-1. Watchdog Reset (WDR) CY7C64013C CY7C64113C or Gnd. This also Page 18 of 51 [+] Feedback...

  • Page 19: General-Purpose I/O (Gpio) Ports

    P0.3 Figure 9-2. Port 0 Data P1.5 P1.4 P1.3 Figure 9-3. Port 1 Data P2.5 P2.4 P2.3 Figure 9-4. Port 2 Data CY7C64013C CY7C64113C GPIO *Port 0,1,2: Low I sink Port 3: High I sink ADDRESS 0x00 P0.2 P0.1 P0.0 ADDRESS 0x01 P1.2...

  • Page 20: Gpio Configuration Port

    Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C64013C part always requires that the data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a ‘0.’...

  • Page 21: Gpio Interrupt Enable Ports

    Figure 9-9. Port 2 Interrupt Enable Figure 9-10. Port 3 Interrupt Enable DAC to sink current to drive the output LOW. Figure 10-1 shows a block diagram of sink CY7C64013C CY7C64113C ADDRESS 0x04 P1.2 Intr Enable P1.1 Intr Enable P1.0 Intr Enable...

  • Page 22: Dac Isink Registers

    Controller Figure 10-1. Block Diagram of a DAC Pin Reserved Reserved Reserved Figure 10-2. DAC Port Data Reserved Reserved Isink[3] Figure 10-3. DAC Sink Register CY7C64013C CY7C64113C I/O Pin ADDRESS 0x30 DAC[2] DAC[1] DAC[0] ADDRESS 0x38 -0x3F Isink[2] Isink[1] Isink[0]...

  • Page 23: Dac Port Interrupts

    Reserved Reserved Figure 10-5. DAC Port Interrupt Polarity Timer Bit 5 Timer Bit 4 Timer Bit 3 Figure 11-1. Timer LSB Register CY7C64013C CY7C64113C ADDRESS 0x31 Enable Bit 2 Enable Bit 1 Enable Bit 0 ADDRESS 0x32 Enable Bit 2...

  • Page 24: I 2 C And Hapi Configuration Register

    C-compatible interface and HAPI functions, discussed in detail in Sections 13.0 and LEMPTY DRDY Latch Polarity Polarity Empty C Configuration Register C-compatible options exist due to pin limitations in certain C-compatible operation. CY7C64013C CY7C64113C ADDRESS 0x25 Timer Bit 10 Timer Bit 9 Timer Bit 8 1.024-ms Interrupt 128- s Interrupt µ...

  • Page 25: I 2 C-Compatible Controller

    Figure 13-1. I C Data Register Xmit Mode Addr Figure 13-2. I C Status and Control Register CY7C64013C CY7C64113C C Position C on P2[1:0], 0:SCL, 1:SDA C on P1[1:0], 0:SCL, 1:SDA C on P2[1:0], 0:SCL, 1:SDA C Status and Control Register...
  • Page 26 C-compatible block to initiate a master mode transaction by sending a start bit and C Stop bit is generated. C restart sequence. The I C target address for the restart must be written CY7C64013C CY7C64113C C GPIO pins C Stop bit detected (unless firmware did not C Status and Control register.

  • Page 27: Hardware Assisted Parallel Interface (Hapi)

    If 1, Data Ready is active HIGH, DReadyPin is active LOW. Determines polarity of Latch Empty bit and LatEmptyPin: If 0, Latch Empty is active LOW, LatEmptyPin is active HIGH. If 1, Latch Empty is active HIGH, LatEmptyPin is active LOW. CY7C64013C CY7C64113C C-compatible bus, Page 27 of 51...

  • Page 28: Figure 15-1. Processor Status And Control Register

    Watchdog Reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). The Watchdog Reset does not effect the state of the POR and the Bus Reset Interrupt bits. Document #: 38-08001 Rev. *B USB Bus Reset Power-On Suspend Interrupt Reset CY7C64013C CY7C64113C ADDRESS 0xFF Interrupt Reserved Enable Sense Page 28 of 51 [+] Feedback...

  • Page 29: Interrupts

    C-compatible interface or HAPI operation, or on various GPIO Interrupt DAC Interrupt Reserved Enable enable Reserved EPB1 Interrupt EPB0 Interrupt Enable Enable CY7C64013C CY7C64113C ADDRESS 0X20 1.024-ms 128-µs Interrupt USB Bus RST Interrupt Enable Enable Interrupt Enable ADDRESS 0X21 EPA2 Interrupt...

  • Page 30: Interrupt Vectors

    Hub CLR Hub IRQ Interrupt DAC CLR DAC IRQ Acknowledge GPIO CLR GPIO IRQ C CLR C IRQ Interrupt Priority Encoder CY7C64013C CY7C64113C IRQ Sense Int Enable Sense Controlled by DI, EI, and RETI Instructions Page 30 of 51 [+] Feedback...

  • Page 31: Interrupt Latency

    USB Address A Endpoint 2 interrupt 0x000E USB Address A Endpoint 3 interrupt 0x0010 USB Address A Endpoint 4 interrupt 0x0012 0x0014 0x0016 0x0018 CY7C64013C CY7C64113C Function Reserved DAC interrupt GPIO interrupt C interrupt Page 31 of 51 [+] Feedback...

  • Page 32: Gpio/Hapi Interrupt

    0 = Disable Enable (Bit 5, Register 0x20) Figure 16-4. GPIO Interrupt Structure C-compatible bus to signal the need for firmware interaction. This generally C registers. Refer to Section 13.0 for details on CY7C64013C CY7C64113C IRQout Interrupt Priority Interrupt Encoder...

  • Page 33: Usb Overview

    C-compatible hardware in the idle state. C-compatible bus to generate the interrupt. C interrupt occurs. ) must be placed in series with the D+ and D– lines, as close to CY7C64013C CY7C64113C C register contents may be Page 33 of 51...

  • Page 34: Usb Serial Interface Engine Operation

    D+ Upstream D– Upstream Bus Activity Device Address Device Address Device Address Bit 5 Bit 4 Bit 3 Figure 18-1. USB Device Address Registers CY7C64013C CY7C64113C ADDRESS 0x1F Control Action Control Action Control Action Bit 2 Bit 1 Bit 0 ADDRESSES...

  • Page 35: Usb Device Endpoints

    0xA8 EPA4 0xD8 0xB0 EPA3 0xE0 0xB8 EPA2 0xE8 0xC0 EPA1 0xF0 0xE0 EPA0 0xF8 Endpoint 0 OUT Mode Bit 3 Received CY7C64013C CY7C64113C [1,1] Start Size Label Address Size EPA4 0xB0 EPA3 0xA8 EPA0 0xB8 EPA1 0xC0 EPA2 0xE0...

  • Page 36: Figure 18-3. Usb Non-Control Device Endpoint Mode Registers

    Document #: 38-08001 Rev. *B Reserved Mode Bit 3 Byte Count Bit 5 Byte Count Bit 4 Byte Count Bit 3 Byte Count Bit 2 Byte Count Bit 1 Byte Count Bit 0 CY7C64013C CY7C64113C ADDRESSES 0x14, 0x16, 0x42 0x44...

  • Page 37: Endpoint Mode/Count Registers Update And Locking Mechanism

    4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier. Document #: 38-08001 Rev. *B CY7C64013C CY7C64113C Page 37 of 51 [+] Feedback...

  • Page 38: Figure 18-5. Token/Data Packet Flow Diagram

    NAK/STALL Data Packet UPDATE Host To Device Data Data Packet UPDATE SETUP Host To Device Data Data Packet UPDATE only if FIFO is CY7C64013C CY7C64113C Host To Device Hand Shake Packet UPDATE Device To Host ACK, NAK, STAL Hand Shake...

  • Page 39: Usb Mode Tables

    Is set by SIE on an ACK from mode 1111 (Ack In - Status Out) TX Count check On issuance of an ACK this mode is changed by SIE to 1110 (NAK In - Status Out) CY7C64013C CY7C64113C Comments Page 39 of 51 [+] Feedback...
  • Page 40 Byte Count (bits 0..5, Figure 17-4) Data Valid (bit 6, Figure 17-4) Data0/1 (bit7 Figure 17-4) PID Status Bits (Bit[7..5], Figure 17-2) The validity of the received data CY7C64013C CY7C64113C Interrupt 2 1 0 Response SIE’s Response to the Host...

  • Page 41: Table 19-2. Details Of Modes For Differing Traffic Conditions (See Table 19-1 For The Decode Legend)

    Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup updates updates updates updates updates updates CY7C64013C CY7C64113C Mode Bits Response Intr 0 0 1 ACK NoChange ignore NoChange ignore Mode Bits Response Intr...
  • Page 42 Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup CY7C64013C CY7C64113C 0 1 1 Stall NoChange ignore NoChange ignore NoChange NoChange 0 1 1 Stall 0 1 1 Stall...

  • Page 43: Register Summary

    Received Data Valid Byte Count Byte Count Byte Count Byte Count Bit 5 Bit 4 Bit 3 Bit 2 Mode Bit 3 Mode Bit 2 CY7C64013C CY7C64113C Read/Write/ Default/ Bit 1 Bit 0 Both/- Reset P0.1 P0.0 11111111 BBBBBBBB P1.1 P1.0...

  • Page 44: Sample Schematic

    Enable Interrupt Sense 3.3V Regulator 2.2 µF Vref 1.5K .01 µF Vbus 22x2(R D0– 4.7 nF 250VAC XTALO XTALI 6.000 MHz CY7C64013C CY7C64113C Read/Write/ Default/ Bit 1 Bit 0 Both/- Reset Reserved Reserved Reserved 00000000 Reserved Reserved Reserved 00000000 Reserved...

  • Page 45: Absolute Maximum Ratings

    Including R Resistor All ports, LOW to HIGH edge All ports, HIGH to LOW edge = 3 mA = 8 mA = 1.9 mA (all ports 0,1,2,3) is below approximately 2.5V. CY7C64013C CY7C64113C +0.5V +0.5V Min. Max. Unit 3.15 3.45 –0.4...

  • Page 46: Switching Characteristics (Fosc = 6.0 Mhz)

    = 2.0V DC DAC Port = 6.0 MHz) Description Clock Source DAC Interface [10, 11] [11] [10, 11] [11] [11] [10, 11] Timer Signals CY7C64013C CY7C64113C Min. Max. Unit 24.0 kΩ Min. Max. Unit 6 ±0.25% 166.25 167.08 0.45 t 0.45 t...

  • Page 47: Figure 24-3. Hapi Read By External Interface From Usb Microcontroller

    CY7C64013C CY7C64113C CLOCK Figure 24-1. Clock Timing D− Figure 24-2. USB Data Signal Timing Interrupt Generated CS (P2.6, input) OE (P2.5, input) DATA (output) D[23:0] STB (P2.4, input) OEDR (Ready) DReadyPin (P2.3, output) (Shown for DRDY Polarity=0) Internal Write Internal Addr Port0 Figure 24-3.

  • Page 48: Ordering Information

    (Shown for LEMPTY Polarity=0) Internal Read Internal Addr Figure 24-4. HAPI Write by External Device to USB Microcontroller 25.0 Ordering Information Ordering Code PROM Size CY7C64013C-SXC 8 KB CY7C64013C-PXC 8 KB CY7C64013C-SXCT 8 KB CY7C64113C-PVXC 8 KB Document #: 38-08001 Rev. *B...

  • Page 49: Package Diagrams

    0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.120[3.05] 0.140[3.55] 0.015[0.38] 0.060[1.52] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] SEE LEAD END OPTION CY7C64013C CY7C64113C 51-85061-*C DIMENSIONS IN INCHES [MM] MIN. MAX. REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 0.290[7.36] 0.325[8.25] 0.009[0.23] 3° MIN. 0.012[0.30] 0.310[7.87] 0.385[9.78]...
  • Page 50 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 4. PACKAGE WEIGHT 0.85gms 0.394[10.01] 0.419[10.64] 0.026[0.66] 0.032[0.81] SEATING PLANE 0.092[2.33] 0.105[2.67] 0.004[0.10] CY7C64013C CY7C64113C MIN. MAX. PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.0091[0.23] 0.015[0.38] 0.0125[3.17] 0.050[1.27]...

  • Page 51: Document #: 38-08001 Rev. *B

    Document History Page Document Title: CY7C64013C, CY7C64113C Full-Speed USB (12 Mbps) Function Document Number: 38-08001 Issue Orig. of REV. ECN NO. Date Change 109962 12/16/01 129715 02/05/04 429099 See ECN Document #: 38-08001 Rev. *B Description of Change Change from Spec number: 38-00626 to 38-08001...

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