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1. Features (CY7C68013A/14A/15A/16A)
■
USB 2.0 USB IF high-speed certified (TID # 40460272)
■
Single chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
■
Fit, form and function compatible with the FX2
❐
Pin compatible
❐
Object-code-compatible
❐
Functionally compatible (FX2LP is a superset)
■
Ultra Low power: I
no more than 85 mA in any mode
CC
❐
Ideal for bus and battery powered applications
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Software: 8051 code runs from:
❐
Internal RAM, which is downloaded via USB
❐
Internal RAM, which is loaded from EEPROM
❐
External memory device (128 pin package)
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16 KBytes of on-chip Code/Data RAM
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Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
❐
Buffering options: double, triple, and quad
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Additional programmable (BULK/INTERRUPT) 64 byte
endpoint
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8-bit or 16-bit external data interface
■
Smart Media Standard ECC generation
Cypress Semiconductor Corporation
Document #: 38-08032 Rev. *L
EZ-USB FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller
■
GPIF (General Programmable Interface)
❐
Enables direct connection to most parallel interfaces
❐
Programmable waveform descriptors and configuration reg-
isters to define waveforms
❐
Supports multiple Ready (RDY) inputs and Control (CTL) out-
puts
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Integrated, industry standard enhanced 8051
❐
48 MHz, 24 MHz, or 12 MHz CPU operation
❐
Four clocks per instruction cycle
❐
Two USARTS
❐
Three counter/timers
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Expanded interrupt system
❐
Two data pointers
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3.3V operation with 5V tolerant inputs
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Vectored USB interrupts and GPIF/FIFO interrupts
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Separate data buffers for the Setup and Data portions of a
CONTROL transfer
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Integrated I
■
Four integrated FIFOs
❐
Integrated glue logic and FIFOs lower system cost
❐
Automatic conversion to and from 16-bit buses
❐
Master or slave operation
❐
Uses external clock or asynchronous strobes
❐
Easy interface to ASIC and DSP ICs
■
Available in Commercial and Industrial temperature grade (all
packages except VFBGA)
•
198 Champion Court
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
2
C controller, runs at 100 or 400 kHz
,
•
San Jose
CA 95134-1709
Revised February 8, 2008
• 408-943-2600
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Related Manuals for Cypress Semiconductor CY7C68014A
Summary of Contents for Cypress Semiconductor CY7C68014A
- Page 1 Easy interface to ASIC and DSP ICs ■ Available in Commercial and Industrial temperature grade (all packages except VFBGA) • 198 Champion Court • San Jose CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A CA 95134-1709 • 408-943-2600 Revised February 8, 2008 [+] Feedback [+] Feedback...
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Page 2: Logic Block Diagram
XCVR Enhanced USB core Simplifies 8051 code 1.1 Features (CY7C68013A/14A only) ■ CY7C68014A: Ideal for battery powered applications Suspend current: 100 μA (typ) ❐ ■ CY7C68013A: Ideal for non-battery powered applications Suspend current: 300 μA (typ) ❐... -
Page 3: Functional Overview
3.4 Buses All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multi- plexed on IO ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 24 MHz 12 pf 12 pf 20 ×... - Page 4 Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to the address 0x0043 where it expects to find a “jump” instruction to the USB Interrupt service routine. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A SCON1 SBUF1...
- Page 5 FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes Table 4 shows the...
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Page 6: Wakeup
RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation. For more infor- mation about reset implementation for the FX2 family of products visit http://www.cypress.com. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes Page 6 of 62 [+] Feedback... - Page 7 3.10.3 External Code Memory, EA = 1 The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.3V RESET Powered Reset...
- Page 8 (RD#,WR#) (Ok to populate (OK to populate data memory program here—RD#/WR# memory here— strobes are not PSEN# strobe active) is not active) Data Code C interface boot access CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page 8 of 62 [+] Feedback [+] Feedback...
- Page 9 E700 E6FF 8051 Addressable Registers (512) E500 E4FF Reserved (128) E480 E47F 128 bytes GPIF Waveforms E400 E3FF Reserved (512) E200 E1FF 512 bytes 8051 xdata RAM E000 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page 9 of 62 [+] Feedback [+] Feedback...
- Page 10 An example endpoint configu- ration is the EP2–1024 double buffered; EP6–512 quad buffered (column 8). Figure 5. Endpoint Configuration 1024 1024 1024 1024 1024 1024 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EP2 EP2 1024 1024 1024 1024 1024 1024 1024...
- Page 11 SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 64 int 64 int 64 iso out (2×)
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Page 12: Ctl5
7. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation. 8. After the data has been downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory. Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.15 ECC Generation The EZ-USB can calculate ECCs (Error Correcting Codes) on data that passes across its GPIF or Slave FIFO interfaces. - Page 13 24LC64 24LC128 Table 9. Part Number Conversion Table EZ-USB FX2 Part Number CY7C68013-56PVC CY7C68013A-56PVXC or CY7C68014A-56PVXC CY7C68013-56PVCT CY7C68013A-56PVXCT or CY7C68014A-56PVXCT 56-pin SSOP – Tape and Reel CY7C68013-56LFC CY7C68013A-56LFXC or CY7C68014A-56LFXC CY7C68013-100AC CY7C68013A-100AXC or CY7C68014A-100AXC CY7C68013-128AC CY7C68013A-128AXC or CY7C68014A-128AXC Note 9. This EEPROM does not have address pins.
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Page 14: Pin Assignments
3.20 CY7C68013A/14A and CY7C68015A/16A Differences CY7C68013A is identical to CY7C68014A in form, fit, and functionality. CY7C68015A is identical to CY7C68016A in form, fit, and functionality. CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively and are ideal for power sensitive battery applica- tions. - Page 15 PORTC5/GPIFADR5 PORTC4/GPIFADR4 PORTC3/GPIFADR3 PORTC2/GPIFADR2 PORTC1/GPIFADR1 PORTC0/GPIFADR0 PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 6. Signal Port GPIF Master FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5]...
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Page 16: Table Of Contents
Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment CLKOUT RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 RDY4 RDY5 AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND INT4 *IFCLK RESERVED BKPT Document #: 38-08032 Rev. *L CY7C68013A/CY7C68014A 128-pin TQFP * denotes polarity programmable CY7C68013A, CY7C68014A... - Page 17 Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 RDY4 RDY5 AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND INT4 *IFCLK RESERVED BKPT Document #: 38-08032 Rev. *L PA7/*FLAGD/SLCS# CY7C68013A/CY7C68014A 100-pin TQFP * denotes programmable polarity CY7C68013A, CY7C68014A...
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Page 18: Pa7/*Flagd/Slcs
Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment Document #: 38-08032 Rev. *L CY7C68013A/CY7C68014A 56-pin SSOP PD5/FD13 PD4/FD12 PD6/FD14 PD3/FD11 PD7/FD15 PD2/FD10 PD1/FD9 CLKOUT PD0/FD8 *WAKEUP RDY0/*SLRD RESET# RDY1/*SLWR AVCC PA7/*FLAGD/SLCS# XTALOUT PA6/PKTEND XTALIN PA5/FIFOADR1 AGND PA4/FIFOADR0 AVCC PA3/*WU2 DPLUS PA2/*SLOE... -
Page 19: Pa6/*Pktend
AVCC DPLUS DMINUS AGND *IFCLK/**PE0 RESERVED Document #: 38-08032 Rev. *L CY7C68013A/CY7C68014A & CY7C68015A/CY7C68016A 56-pin QFN * denotes programmable polarity ** denotes CY7C68015A/CY7C68016A pinout CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A RESET# PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1# PA0/INT0# CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA... - Page 20 Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page 20 of 62 [+] Feedback [+] Feedback...
- Page 21 8051 code fetch from external memory. It is active for program memory fetches from 0x4000–0xFFFF when the EA pin is LOW, or from 0x0000–0xFFFF when the EA pin is HIGH. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page 21 of 62...
- Page 22 IFCONFIG[1:0]. PA2 is a bidirectional IO port pin. SLOE is an input-only output enable with program- mable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0]. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page 22 of 62 [+] Feedback [+] Feedback...
- Page 23 IO/Z Multiplexed pin whose function is selected by the (PB4) following bits: IFCONFIG[1..0]. PB4 is a bidirectional IO port pin. FD[4] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page 23 of 62 [+] Feedback [+] Feedback...
- Page 24 FD[8] is the bidirectional FIFO/GPIF data bus. IO/Z Multiplexed pin whose function is selected by the (PD1) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page 24 of 62 [+] Feedback [+] Feedback...
- Page 25 RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page 25 of 62...
- Page 26 IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page 26 of 62 [+] Feedback [+] Feedback...
- Page 27 Input RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page 27 of 62 [+] Feedback...
- Page 28 Ground Ground. No Connect. This pin must be left open. No Connect. This pin must be left open. No Connect. This pin must be left open. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description ® chip from suspending. C interface. Connect to VCC with a 2.2K C peripheral is attached.
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Page 29: Register Summary
INFM1 OEP1 AUTOOUT AUTOIN INFM1 OEP1 AUTOOUT AUTOIN INFM1 OEP1 AUTOOUT AUTOIN LINE15 LINE14 LINE13 LINE12 LINE11 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access xxxxxxxx RW reserved reserved reserved 00000000 R CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW... - Page 30 PFC3 OUT:PFC7 OUT:PFC6 AADJ AADJ AADJ AADJ Skip Skip EDGEPF EDGEPF EDGEPF EDGEPF EP0ACK HSGRANT URES SUSP CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access LINE2 LINE1 LINE0 00000000 R COL0 LINE17 LINE16 00000000 R LINE10 LINE9 LINE8 00000000 R LINE2 LINE1...
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Page 31: Ctl4
CRC13 CRC12 CRC11 CRC7 CRC6 CRC5 CRC4 CRC3 QENABLE QSTATE DISCON WU2POL WUPOL (BC14) (BC13) (BC12) (BC11) CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access SUTOK SUDAV 0xxxxxxx rbbbbbbb EP1IN EP0OUT EP0IN 00000000 RW EP1IN EP0OUT EP0IN GPIFWF GPIFDONE 00000000 RW GPIFWF... - Page 32 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access xxxxxxxx RW BUSY STALL 10000000 bbbbbbrb BUSY STALL 00000000 bbbbbbrb BUSY STALL 00000000 bbbbbbrb EMPTY STALL...
- Page 33 TC28 TC27 TC23 TC22 TC21 TC20 TC19 TC15 TC14 TC13 TC12 TC11 INTRDY TCXRDY5 RDY5 RDY4 RDY3 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access MSTB2 MSTB1 MSTB0 00100000 RW FALLING RISING 00000001 rrrrrrbb 00000010 RW TC26 TC25 TC24 00000000 RW TC18...
- Page 34 SM2_0 REN_0 TB8_0 EP8F EP8E EP6F EP6E EP4F EP4PF EP4EF EP4FF EP8PF EP8EF EP8FF DONE CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access 400KHZ xxxxxxxx [14] xxxxxxxx RW 00000111 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW IDLE 00110000 RW...
- Page 35 Document #: 38-08032 Rev. *L SM0_1 SM1_1 SM2_1 REN_1 TB8_1 EXF2 RCLK TCLK EXEN2 ERESI RESI INT6 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access xxxxxxxx RW xxxxxxxx R RB8_1 TI_1 RI_1 00000000 RW 00000000 RW CPRL2 00000000 RW 00000000 RW...
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Page 36: Absolute Maximum Ratings
34.0 15.5 27.7 10.6 14.6 30.9 27.7 θ j = P* θ θ Jc + θ c = P* CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A θ Junction to Ambient Temperature θ θ Jc + (°C/W) 47.7 45.9 43.2 25.2 58.6 θ θ... -
Page 37: Ac Electrical Characteristics
10. AC Electrical Characteristics 10.1 USB Transceiver USB 2.0 compliant in full-speed and high-speed modes. Note 16. Measured at Max VCC, 25°C. Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Conditions 0< V < VCC = 4 mA = –4 mA Except D+/D–... - Page 38 – t = 43 ns. ACC1 Document #: 38-08032 Rev. *L STBH [18] ACC1 data in 20.83 41.66 83.2 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Unit Notes 48 MHz 24 MHz 12 MHz 10.7 11.1 Page 38 of 62 [+] Feedback [+] Feedback...
- Page 39 STBH STBL SCSL SOEL [19] ACC1 data in Stretch = 1 [19] ACC1 20.83 41.66 83.2 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A data in Unit Notes 48 MHz 24 MHz 12 MHz 10.7 11.1 Page 39 of 62 [+] Feedback [+] Feedback...
- Page 40 WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value. Document #: 38-08032 Rev. *L Figure 14. Data Memory Write Timing Diagram STBH data out Stretch = 1 data out CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A OFF1 OFF1 Unit Notes 10.7 11.2 11.2...
- Page 41 RD# and WR# signals. STBL DATA CAN BE UPDATED BY EXTERNAL LOGIC DATA MUST BE HELD FOR 3 CLK CYLCES STBL CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Section 10.3 STBH STBH Page 41 of 62 [+] Feedback...
- Page 42 Setup time of 50 ns when using internal 48-MHz IFCLK. 22. IFCLK must not exceed 48 MHz. Document #: 38-08032 Rev. *L IFCLK valid XCTL Description 20.83 Description Min. 20.83 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [20, 21] Unit [21] Max. Unit 11.5 10.7 Page 42 of 62...
- Page 43 Clock to FLAGS Output Propagation Delay XFLG Clock to FIFO Data Output Propagation Delay Document #: 38-08032 Rev. *L IFCLK XFLG OEon Description 20.83 18.7 Description Min. 20.83 12.7 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] OEoff [21] Unit 10.5 10.5 [21] Max. Unit 10.5 10.5 13.5...
- Page 44 23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08032 Rev. *L RDpwh RDpwl XFLG OEon OEoff [23] Description CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Unit 10.5 10.5 Page 44 of 62 [+] Feedback [+] Feedback...
- Page 45 Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time XFLG Document #: 38-08032 Rev. *L IFCLK XFLG Description 20.83 10.4 Description 20.83 12.1 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [21] Unit [21] Unit 13.5 Page 45 of 62 [+] Feedback [+] Feedback...
- Page 46 Clock to FLAGS Output Propagation Delay XFLG Document #: 38-08032 Rev. *L WRpwh WRpwl Description XFLG Description 20.83 14.6 Description 20.83 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [23] Unit [20] [21] Unit [21] Unit 13.5 Page 46 of 62 [+] Feedback...
- Page 47 Failing to adhere to this timing results in the FX2 failing to send the one byte or word short packet. PEpwh PEpwl XFLG [23] Description CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 23 shows this scenario. X is the value [20] >= t At least one IFCLK cycle...
- Page 48 Parameter FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG FIFOADR[1:0] to FIFODATA Output Propagation Delay Document #: 38-08032 Rev. *L OEoff OEon Description XFLG Description CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Unit 10.5 10.5 [20] Unit 10.7 14.3 Page 48 of 62...
- Page 49 Table 32. Slave FIFO Asynchronous Address Parameters Parameter FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time RD/WR/PKTEND to FIFOADR[1:0] Hold Time Document #: 38-08032 Rev. *L [21] Description 20.83 [23] Description CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Unit [20] Unit Page 49 of 62 [+] Feedback [+] Feedback...
- Page 50 FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while (time the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] >= t OEoff...
- Page 51 (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 23 for further details on this timing. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] >= t XFLG 31, after the four bytes are written to the FIFO, must be met.
- Page 52 After SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incre- mented. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] RDpwl...
- Page 53 It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines have to held constant during the PKTEND assertion. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] WRpwl WRpwh...
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Page 54: Ordering Information
CY7C68013A-56LFXI CY7C68015A-56LFXC CY7C68013A-56BAXC Development Tool Kit CY3684 Reference Design Kit CY4611B Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Package Type RAM Size 128 TQFP – Lead-Free 100 TQFP – Lead-Free 56 SSOP – Lead-Free 56 QFN – Lead-Free 56 VFBGA –... -
Page 55: Package Diagrams
56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA Package Diagrams Figure 35. 56-lead Shrunk Small Outline Package O56 (51-85062) Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 51-85062-*C Page 55 of 62 [+] Feedback [+] Feedback... - Page 56 3. PACKAGE WEIGHT: 0.162g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # DESCRIPTION LF56 STANDARD LY56 PB-FREE Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A SIDE VIEW 0.08[0.003] 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0°-12° 0.30[0.012] SEATING PLANE 0.50[0.020]...
- Page 57 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1.40±0.05 12°±1°...
- Page 58 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1.40±0.05 12°±1°...
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Page 59: Pcb Layout Recommendations
USB connector. Note 24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. Document #: 38-08032 Rev. *L CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A BOTTOM VIEW Ø0.05 M C Ø0.15 M C A B Ø0.30±0.05(56X) - Page 60 PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 42. X-ray Image of the Assembly CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 42 Page 60 of 62 [+] Feedback...
- Page 61 Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller Document Number: 38-08032 Issue Orig. of REV. ECN NO. Date Change 124316 03/17/03 New data sheet 128461 09/02/03 Added PN CY7C68015A throughout data sheet Modified Removed word “compatible”...
- Page 62 Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller Document Number: 38-08032 Issue Orig. of REV. ECN NO. Date Change 420505 See ECN Remove SLCS from figure in Section 10.10. Removed indications that SLRD can be asserted simultaneously with SLCS in Section 10.17.2 and Section 10.17.3...
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