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Features
True dual-ported memory cells that enable simultaneous
■
access of the same memory location
Synchronous pipelined operation
■
Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit devices
■
Pipelined output mode allows fast operation
■
0.18 micron CMOS for optimum speed and power
■
High speed clock to data access
■
3.3V low power
■
Active as low as 225 mA (typ.)
❐
Standby as low as 55 mA (typ.)
❐
Mailbox function for message passing
■
Global master reset
■
Separate byte enables on both ports
■
Commercial and industrial temperature ranges
■
IEEE 1149.1-compatible JTAG boundary scan
■
256 Ball FBGA (1-mm pitch)
■
Counter wrap around control
■
Internal mask register controls counter wrap-around
❐
Counter-interrupt flags to indicate wrap-around
❐
Memory block retransmit operation
❐
Counter readback on address lines
■
Mask register readback on address lines
■
Dual Chip Enables on both ports for easy depth expansion
■
Seamless migration to next-generation dual-port family
■
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time – Clock to Data
(ns)
Typical Operating Current (mA)
Package
Cypress Semiconductor Corporation
Document Number: 38-06076 Rev. *G
FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36
1 Mbit
2 Mbit
(32K x 36)
(64K x 36)
CYD01S36V
CYD02S36V/36VA
167
167
4.0
4.4
225
225
256 FBGA
256 FBGA
(17 mm x 17 mm)
(17 mm x 17 mm)
•
198 Champion Court
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Synchronous Dual-Port RAM
Functional Description
The FLEx36™ family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit, and
18-Mbit pipelined, synchronous, true dual-port static RAMs that
are high speed, low power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location in
memory. A particular port can write to a certain location while
another port is reading that location. The result of writing to the
same location by more than one port at the same time is
undefined. Registers on control, address, and data lines allow for
minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S36V devices in this family has limited features.
Please see Address Counter and Mask Register Operations
on page 5 for details.
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
4 Mbit
(128K x 36)
CYD04S36V
167
4.0
225
256 FBGA
(17 mm x 17 mm)
(17 mm x 17 mm)
,
•
San Jose
CA 95134-1709
CYD01S36V
9 Mbit
18 Mbit
(256K x 36)
(512K x 36)
CYD09S36V
CYD18S36V
167
133
4.0
5.0
270
315
256 FBGA
256 FBGA
(23 mm x 23 mm)
•
408-943-2600
Revised Decenber 09, 2008
[19]
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Related Manuals for Cypress Semiconductor FLEx36 CYD01S36V
Summary of Contents for Cypress Semiconductor FLEx36 CYD01S36V
-
Page 1: Functional Description
Features True dual-ported memory cells that enable simultaneous ■ access of the same memory location Synchronous pipelined operation ■ Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit devices ■ Pipelined output mode allows fast operation ■ 0.18 micron CMOS for optimum speed and power ■... -
Page 2: Logic Block Diagram
Logic Block Diagram FTSEL CONFIG Block PORTSTD[1:0] DQ [35:0] BE [3:0] BUSY A [18:0] CNT/MSK CNTEN CNTRST Counter Logic CNTINT Mailboxes Note 1. 18-Mbit device has 19 address bits, 9-Mbit device has 18 address bits, 4-Mbit device has 17 address bits, 2-Mbit device has 16 address bits, and 1-Mbit device has 15 address bits. -
Page 3: Pin Configurations
Pin Configurations Figure 1. Pin Diagram - 256-Ball FBGA (Top View) CYD01S36V/CYD02S36V/36VA/CYD04S36V/CYD09S36V/CYD18S36V DQ32L DQ30L DQ28L DQ26L DQ24L DQ33L DQ31L DQ29L DQ27L DQ25L RETL DQ34L DQ35L INTL [2,3] [2,5] WRPL VREFL FTSELL [2,3] [2,4] [2,3] CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE [11] [10] CNTINT... -
Page 4: Pin Definitions
Pin Definitions Left Port Right Port –A –A –BE –BE [2,5] [2,5] BUSY BUSY [11] [11] [10] [10] –DQ –DQ [2,4] [2,4] LowSPD LowSPD [2,4] [2,4] PORTSTD[1:0] PORTSTD[1:0] [2,5] [2,5] READY READY [10] [10] CNT/MSK CNT/MSK [11] [11] [11] [11] CNTEN CNTEN [10]... -
Page 5: Master Reset
Master Reset The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchro- nously to the clocks. An MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). - Page 6 Counter enable (CNTEN) inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast, interleaved memory applications. A port’s burst counter is loaded when the port’s address strobe (ADS) and CNTEN signals are LOW. When the port’s CNTEN is asserted and the ADS is deasserted, the address counter increments on each LOW to HIGH transition of that port’s clock signal.
- Page 7 Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a “1” for a counter bit to change.
- Page 8 Figure 2. Counter, Mask, and Mirror Logic Block Diagram CNT/MSK CNTEN Decode Logic CNTRST MRST Bidirectional Address Lines From Address Lines From Mask Register From Mask From Counter Document Number: 38-06076 Rev. *G CYD02S36V/36VA/CYD04S36V Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment...
- Page 9 Figure 3. Programmable Counter-Mask Register Operation Example: Load Counter-Mask Register = 3F Load Address Counter = 8 Address Register Max + 1 Address Register IEEE 1149.1 Serial Boundary Scan (JTAG) The FLEx36 family devices incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs.
- Page 10 Table 4. Identification Register Definitions Instruction Field Value Revision Number (31:28) Cypress Device ID (27:12) C002h C001h C092h Cypress JEDEC ID (11:1) 034h ID Register Presence (0) Table 5. Scan Register Sizes Register Name Instruction Bypass Identification Boundary Scan Note 24.
- Page 11 Table 6. Instruction Identification Codes Instruction Code EXTEST 0000 BYPASS 1111 IDCODE 1011 HIGHZ 0111 CLAMP 0100 SAMPLE/PRELOAD 1000 NBSRST 1100 RESERVED All other codes Document Number: 38-06076 Rev. *G CYD02S36V/36VA/CYD04S36V Description Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. Places the BYR between TDI and TDO.
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Page 12: Electrical Characteristics
Maximum Ratings [25] Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ... –65°C to +150°C Ambient Temperature with Power Applied ... –55°C to +125°C Supply Voltage to Ground Potential...–0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State ... -
Page 13: Switching Characteristics
= 50Ω R = 50Ω OUTPUT C = 10 pF (a) Normal Load (Load 1) 3.0V ALL INPUT PULSES Switching Characteristics Over the Operating Range Parameter Description Maximum Operating Frequency MAX2 Clock Cycle Time CYC2 Clock HIGH Time Clock LOW Time [30] Clock Rise Time [30]... -
Page 14: Jtag Timing
Switching Characteristics Over the Operating Range (continued) Parameter Description CNT/MSK Hold Time Output Enable to Data Valid [31, 32] OE to Low Z [31, 32] OE to High Z Clock to Data Valid Clock to Counter Address Valid Clock to Mask Register Readback Valid Data Output Hold After Clock HIGH [31, 32]... -
Page 15: Switching Waveforms
JTAG Switching Waveform Test Clock Test Mode Select Test Data-In Test Data-Out Switching Waveforms MRST ADDRESS/ DATA LINES INACTIVE OTHER INPUTS RSINT CNTINT Document Number: 38-06076 Rev. *G CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V TCYC TMSS TMSH TDIS TDIH TDOV TDOX Figure 7. Master Reset ACTIVE CYD01S36V Page 15 of 28... - Page 16 Switching Waveforms (continued) CYC2 BE0–BE3 ADDRESS 1 Latency DATA Notes 33. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 34. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 35.
- Page 17 Switching Waveforms (continued) CYC2 ADDRESS (B1) (B1) DATA OUT(B1) ADDRESS (B2) (B2) DATA OUT(B2) Figure 10. Read-to-Write-to-Read (OE = LOW) CYC2 ADDRESS DATA DATA READ Notes 37. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device from this data sheet. ADDRESS = ADDRESS (B2) 38.
- Page 18 Switching Waveforms (continued) Figure 11. Read-to-Write-to-Read (OE Controlled) CYC2 ADDRESS DATA DATA READ Figure 12. Read with Address Counter Advance CYC2 ADDRESS CNTEN DATA x–1 READ EXTERNAL ADDRESS Document Number: 38-06076 Rev. *G CYD02S36V/36VA/CYD04S36V WRITE COUNTER HOLD READ WITH COUNTER CYD01S36V CYD09S36V/CYD18S36V [36, 39, 41, 42]...
- Page 19 Switching Waveforms (continued) Figure 13. Write with Address Counter Advance CYC2 ADDRESS INTERNAL ADDRESS CNTEN DATA WRITE EXTERNAL ADDRESS Document Number: 38-06076 Rev. *G CYD02S36V/36VA/CYD04S36V WRITE WITH WRITE COUNTER COUNTER HOLD CYD01S36V CYD09S36V/CYD18S36V [42] WRITE WITH COUNTER Page 19 of 28 [+] Feedback...
- Page 20 Switching Waveforms (continued) CYC2 ADDRESS INTERNAL ADDRESS CNTEN SRST HRST CNTRST DATA [45] DATA COUNTER WRITE RESET ADDRESS 0 Notes 43. CE = BE0 – BE3 = LOW; CE = MRST = CNT/MSK = HIGH. 44. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 45.
- Page 21 Switching Waveforms (continued) Figure 15. Readback State of Address Counter or Mask Register CYC2 EXTERNAL ADDRESS –A INTERNAL ADDRESS CNTEN DATA LOAD READBACK EXTERNAL COUNTER ADDRESS INTERNAL ADDRESS Notes 46. CE = OE = BE0 – BE3 = LOW; CE = R/W = CNTRST = MRST = HIGH.
- Page 22 Switching Waveforms (continued) Figure 16. Left_Port (L_Port) Write to Right_Port (R_Port) Read CYC2 L_PORT ADDRESS CKHZ L_PORT DATA CYC2 R_PORT ADDRESS R_PORT DATA Notes 50. CE = OE = ADS = CNTEN = BE0 – BE3 = LOW; CE 51. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t 52.
- Page 23 Switching Waveforms (continued) Figure 17. Counter Interrupt and Retransmit CYC2 CNT/MSK CNTEN COUNTER INTERNAL 3FFFC 3FFFD ADDRESS CNTINT Notes 53. CE = OE = BE0 – BE3 = LOW; CE = R/W = CNTRST = MRST = HIGH. 54. CNTINT is always driven. 55.
- Page 24 Switching Waveforms (continued) Figure 18. MailBox Interrupt Timing CYC2 L_PORT 7FFFF ADDRESS CYC2 R_PORT ADDRESS Table 7. Read/Write and Enable Operation (Any Port) Inputs Notes 57. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. 58.
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Page 25: Ordering Information
Ordering Information 512K × 36 (18-Mbit) 3.3V Synchronous CYD18S36V Dual-Port SRAM Speed( Package Ordering Code MHz) Name CYD18S36V-133BBC BB256B CYD18S36V-133BBI BB256B CYD18S36V-100BBC BB256B CYD18S36V-100BBI BB256B 256K × 36 (9-Mbit) 3.3V Synchronous CYD09S36V Dual-Port SRAM Speed( Package Ordering Code MHz) Name CYD09S36V-167BBC BB256 CYD09S36V-133BBC... -
Page 26: Package Diagrams
Package Diagrams Figure 19. 256-Ball FBGA (17 x 17 mm) BB256 TOP VIEW PIN 1 CORNER 10 11 SEATING PLANE A1 0.36 0.56 A 1.40 MAX. 1.70 MAX. Document Number: 38-06076 Rev. *G CYD02S36V/36VA/CYD04S36V Ø0.05 M C Ø0.25 M C A B Ø0.45±0.05(256X)-CPLD DEVICES (37K &... - Page 27 Package Diagrams (continued) Figure 20. 256-ball FBGA (23 mm x 23 mm x 1.7 mm) BB256B TOP VIEW PIN 1 CORNER 10 11 SEATING PLANE JEDEC MO-192 Document Number: 38-06076 Rev. *G CYD02S36V/36VA/CYD04S36V 13 14 0.20(4X) CYD01S36V CYD09S36V/CYD18S36V Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER +0.10...
- Page 28 Document History Page Document Title: CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Document Number: 38-06076 Orig. of Submission REV. ECN NO. Change 232012 244232 313156 321033 327338 365315 2193427 NXR/AESA 2623658 VKN/PYRS Sales, Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.
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