Cypress Semiconductor CY7C199 Specification Sheet

Features
• High speed
— 10 ns
• Fast t
DOE
• CMOS for optimum speed/power
• Low active power
— 467 mW (max, 12 ns "L" version)
• Low standby power
— 0.275 mW (max, "L" version)
• 2V data retention ("L" version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected

Functional Description

The CY7C199 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A 1024 x 32 x 8
5
ARRAY
A
6
A
7
A
8
A
9
CE
WE
COLUMN
DECODER
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
L
Maximum CMOS
Standby Current (mA)
L
Shaded area contains advance information.
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. **
POWER
DOWN
C199–1
7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45
8 10
120 110 160
90
0.5 0.5
0.05 0.05
• 3901 North First Street
provided by an active LOW Chip Enable (CE) and active LOW
Output Enable (OE) and three-state drivers. This device has
an automatic power-down feature, reducing the power con-
sumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
through I/O ) is written into the memory location addressed by
7
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.

Pin Configurations

DIP / SOJ / SOIC
Top View
A 28
1
5
A
2 27
6
A
26
3
7
A
8 4 25
24
A
5
9
A 23
6
10
A 22
11
7
I/O
A
21
0 12
8
A
20
9
13
A 19
10
I/O
14
1
18
I/O
11
0
17
12
I/O
1
I/O
2
16
I/O 13
2
15
GND
14
I/O
3
OE
22
A
23
I/O
1
4
A
24
2
A
25
3
I/O
5
A
26
4
WE 27
28
I/O V
CC
6
A
1
5
A
2
6
I/O
A 3
7
7
A
4
8
A 5
9
A
6
10
A
7
11
12 15 20
155 150
90 90 90
10 10 10
0.05 0.05
• San Jose
CY7C199
32K x 8 Static RAM
through A
0
LCC
Top View
V
CC
WE
3 2 1 28 27
A
4
4 26
A
8
A
3
5 25
A
9
A
A 6 24
2
10
A A 7
23
1 11
A
8
22
12
OE
A
9 21
13
A
0
A
10 20
14
CE
11 19
I/O
0
I/O
7
12 18
I/O
1
I/O
6 1314151617
I/O
5
I/O
4
I/O
3
C199–2
TSOP I
Top View
(not to scale)
25 35
150 140
80 70
10 10
0.05 0.05
• CA 95134 • 408-943-2600
Revised September 7, 2001
0
).
14
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
C199–3
A
21
0
20
CE
I/O
19
7
I/O
18
6
I/O
17
5
I/O
16
4
I/O
15
3
GND
14
I/O
13
2
I/O
12
1
I/O
11
0
A
10
14
A
9
13
8 A
12
C199–4
45
140
10