Cypress CY2048WAF Specification Sheet

Features
• Flash-programmable capacitor tuning array for low
ppm initial frequency clock output
• Low clock output jitter
— 4 ps typ. RMS period jitter
— ±30 ps typ. peak-to-peak period jitter
• Flash-programmable dividers
• Two-pin programming interface
• On-chip oscillator runs from 10–48-MHz crystal
• Five selectable post-divide options, using reference
oscillator output
• Programmable asynchronous or synchronous OE and
PWR_DWN modes
• 2.7V to 3.6V operation
• Controlled rise and fall times and output slew rate
Block Diagram
(SDATA/VPP)
Die Pad Description
H o riz o n ta l S c rib e
1 V D D
Y (m a x )
2 X O U T
7 C 8 0 3 3 0 A
3 X IN
P D # /O E
4
X (m a x )
Cypress Semiconductor Corporation
Document #: 38-07738 Rev. *A
Flash Programmable Capacitor Tuning Array Die
PD#/OE
XIN
CRYSTAL
XOUT
OSCILLATOR
O U T 6
V e rtic a l
S c rib e
d ie # /re v
5
V S S
• 3901 North First Street
for Crystal Oscillator(XO)
Benefits
• Enables fine-tuning of output clock frequency by
adjusting C of the crystal
Load
• Allows multiple programming opportunities to correct
errors, and control excess inventory
• Enables programming of output frequency after
packaging
• PPM clock output error can be adjusted in package
• Provides flexibility in output configurations and testing
• Enables low-power operation or output enable function
• Provides flexibility for system applications through
selectable instantaneous or synchronous change in
outputs
• Enables encapsulation in small-size, surface-mount
packages
CONFIGURATION
/ 1, 2, 4, 8, 16
VDD
VSS
:
Notes
X(max): 980 µm, Y(max): 988 µm
Scribe: X = 70 µm, Y = 86 µm
Bond pad opening: 85 µm x 85 µm
Pad pitch: 175 µm (min.)
Wafer thickness: 11 mils (Typ.)
,
• San Jose
CY2048WAF
OUT
(SCL)
CA 95134 • 408-943-2600
Revised December 12, 2005
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