Cypress CY62158EV30 Specification Sheet

Features
• Very high speed: 45 ns
— Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62158DV30
• Ultra low standby power
— Typical standby current: 2 µA
— Maximum standby current: 8 µA
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed/power
• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and
[1]
48-pin TSOP I packages
Logic Block Diagram
CE 1
CE 2
Notes
1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.
2. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at
Cypress Semiconductor Corporation
Document #: 38-05578 Rev. *D
, CE , and OE features
1 2
A 0
DATA IN DRIVERS
A 1
A 2
A 3
A 4
A 5
A 6
1024K x 8
A 7
A 8
ARRAY
A 9
A 10
A 11
A 12
COLUMN DECODER
WE
OE
• 198 Champion Court
CY62158EV30 MoBL
8-Mbit (1024K x 8) Static RAM
Functional Description
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Placing the device into standby
mode reduces power consumption significantly when
deselected (CE HIGH or CE
1
output pins (IO through IO ) are placed in a high impedance
0 7
state when the device is deselected (CE
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW and CE
1 2
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. Data on the eight
IO pins (IO through IO ) is then written into the location
0 7
specified on the address pins (A
To read from the device, take Chip Enables (CE
CE HIGH) and OE LOW while forcing the WE HIGH. Under
2
these conditions, the contents of the memory location
specified by the address pins appear on the IO pins. See the
"Truth Table" on page 8 for a complete description of read and
write modes.
POWER
DOWN
http://www.cypress.com.
,
• San Jose CA 95134-1709
[2]
®
) in
LOW). The eight input and
2
HIGH or CE LOW),
1 2
HIGH and WE LOW).
LOW and CE
1
through A ).
0 19
LOW and
1
IO 0
IO 1
IO 2
IO 3
IO 4
IO 5
IO 6
IO 7
• 408-943-2600
Revised April 19, 2007
®
2
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