Cypress CY62137FV30 Specification Sheet

Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■
Wide voltage range: 2.20V–3.60V
■ Pin compatible with CY62137CV/CV25/CV30/CV33,
CY62137V, and CY62137EV30
■ Ultra low standby power
Typical standby current: 1 μA
❐
Maximum standby current: 5 μA (Industrial)
❐
■ Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■
CMOS for optimum speed and power
■ Byte power down feature
■ Available in Pb free 48-Ball VFBGA and 44-pin TSOP II
package

Functional Description

The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
Logic Block Diagram
POWER DOWN
CIRCUIT
Cypress Semiconductor Corporation
Document Number: 001-07141 Rev. *F
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A 128K x 16
6
A
5
RAM Array
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
CE
BHE
BLE
• 198 Champion Court
CY62137FV30 MoBL
2-Mbit (128K x 16) Static RAM
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input and output pins (IO
placed in a high impedance state in the following conditions:
■
Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO through IO
0
specified on the address pins (A
Enable (BHE) is LOW, then data from IO pins (IO
is written into the location specified on the address pins (A
through A ).
16
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
Byte High Enable (BHE) is LOW, then data from memory
appears on IO to IO . See the
8 15
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System
IO
IO
,
• San Jose CA 95134-1709
®
) in portable
through IO
0 15
) is written into the location
7
through A ). If Byte High
0 16
through IO
8
to IO
0
"Truth Table" on page 9 for a
Guidelines.
–IO
0 7
–IO
8 15
BHE
WE
CE
OE
BLE
• 408-943-2600
Revised January 2, 2008
®
) are
)
15
0
. If
7
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