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TPMC851
Tews Technologies TPMC851 Manuals
Manuals and User Guides for Tews Technologies TPMC851. We have
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Tews Technologies TPMC851 manuals available for free PDF download: User Manual
Tews Technologies TPMC851 User Manual (65 pages)
Multifunction I/O
Brand:
Tews Technologies
| Category:
I/O Systems
| Size: 0 MB
Table of Contents
Table of Contents
4
Product Description
8
Figure 1-1 : Block Diagram
9
Technical Specification
10
Table 2-1 : Technical Specification
11
Local Space Addressing
12
PCI9030 Local Space Configuration
12
Local Register Address Space
12
Table 3-1 : Pci9030 Local Space Configuration
12
Table 3-2 : Register Word/Byte Accesses
12
Table 3-3 : Register Address Space
13
Analog Input Registers
14
ADC Control Register ADCCONT (Offset 0X0000)
14
Table 3-4 : Adc Control Register
15
ADC Data Register ADCDATA (Offset 0X0004)
16
Table 3-5 : Adc Data Register
16
Table 3-6 : Adc Data Coding
16
ADC Status Register ADCSTAT (Offset 0X0008)
17
Table 3-7 : Adc Status Register
17
ADC Conversion Start Register ADCCONV (Offset 0X000C)
18
ADC Sequencer Control Register ADCSEQCONT (Offset 0X0010)
19
Table 3-8 : Adc Sequencer Control Register
19
ADC Sequencer Status Register ADCSEQSTAT (Offset 0X0014)
20
Table 3-9 : Adc Sequencer Status Register
20
Table 3-10: Error Flag Irq Generation
20
ADC Sequencer Timer Register ADCSEQTIME (Offset 0X0018)
21
Table 3-11: Adc Sequencer Timer Register
21
ADC Sequencer Instruction RAM (Offset 0X0020 - Offset 0X009C)
22
Table 3-12: Adc Sequencer Instruction Ram Register
22
Table 3-13: Adc Sequencer Instruction Ram Register Positions
23
Analog Output Registers
24
DAC Control Register DACCONT (Offset 0X00C0)
24
Table 3-14: Dac Control Register
24
DAC Sequencer Status Register DACSEQSTAT (Offset 0X00C4)
25
Table 3-15: Dac Sequencer Status Register
25
DAC Sequencer Timer Register DACSEQTIME (Offset 0X00C8)
26
DAC Data Register DACDATA 1-8 (Offset 0X00D0 - Offset 0X00Ec)
26
Table 3-16: Dac Sequencer Timer Register
26
Table 3-17: Dac Data Register
26
Table 3-18: Dac Data Coding
26
Digital I/O Registers
27
Line Direction Register LINEDIR (Offset 0X0100)
27
Table 3-19: Line Direction Register
27
Line Debounce Enable Register LINEDEB (Offset 0X0104)
28
Line Debounce Time Register LINEDBT (Offset 0X0108)
28
Table 3-20: Line Debounce Enable Register
28
Table 3-21: Line Debounce Time Register
28
Line Input Register LINEIN (Offset 0X010C)
29
Table 3-22: Line Input Register
29
Line Output Register LINEOUT (Offset 0X0110)
30
Table 3-23: Line Output Register
30
Line Interrupt Enable Register LINEIEN (Offset 0X0114)
31
Table 3-24: Line Interrupt Enable Register
31
Line Interrupt Status Register LINEIST (Offset 0X0118)
32
Table 3-25: Line Interrupt Status Register
32
Counter Registers
33
Counter Preload Register CNTPRL (Offset 0X0120)
33
Counter Compare Register CNTCMP (Offset 0X0124)
33
Counter Data Register CNTDATA (Offset 0X0128)
33
Table 3-26: Counter Preload Register
33
Table 3-27: Counter Compare Register
33
Table 3-28: Counter Data Register
33
Counter Control Register CNTCONT (Offset 0X012C)
34
Table 3-29: Counter Control Register
35
Counter Status Register CNTSTAT (Offset 0X0130)
36
Table 3-30: Counter Status Register
36
Counter Command Register CNTCOM (Offset 0X0134)
37
Table 3-31: Counter Command Register
37
Interrupt Control Register ICR (Offset 0X0140)
38
Table 3-32: Interrupt Control Register
38
ADC Sequencer Data RAM
39
ADC/DAC Calibration Data ROM
39
Table 3-33: Adc Sequencer Data Ram Space Address Map
39
Table 3-34: Adc/Dac Calibration Rom Data Space Address Map
40
Pci9030 Target Chip
41
PCI Configuration Registers (PCR)
41
PCI9030 Header
41
Table 4-1 : Pci9030 Header
41
PCI Base Address Initialization
42
Table 4-2 : Pci9030 Pci Base Address Usage
42
Local Configuration Register (LCR)
43
Table 4-3 : Pci9030 Local Configuration Register
43
Configuration EEPROM
44
Local Software Reset
44
Table 4-4 : Configuration Eeprom Tpmc851-10R
44
Configuration Hints
45
Big / Little Endian
45
Table 5-1 : Local Bus Little/Big Endian
45
Programming Hints
47
Data Correction
47
ADC Correction Formula
47
DAC Correction Formula
48
ADC Operating Modes
48
Manual Mode
48
Sequencer Mode
49
Sequencer Errors
50
Table 6-1 : Sequencer Errors
50
Application Examples
51
Fastest Conversion of an Arbitrary Single Channel
51
Fastest Conversion of a Specific Single Channel
51
Figure 6-1 : Flow: Fastest Conversion of an Arbitrary Single Channel
51
Figure 6-2 : Flow: Fastest Conversion of a Specific Single Channel
52
Periodic Conversion of Multiple Channels
53
Figure 6-3 : Flow: Periodic Conversion of Multiple Channels
53
Continuous Conversion of Multiple Channels
54
Figure 6-4 : Flow: Continuous Conversion of Multiple Channels
54
DAC Operating Modes
55
Immediate Update
55
Simultaneous Update
55
Table 6-2 : Dac Load Modes
55
Digital TTL I/O
56
Counter Operating Modes
57
Input Modes
57
Timer Mode
57
Direction Count
57
Up/Down Count
57
Table 6-3 : Input Modes
57
Table 6-4 : Clock Prescaler
57
Table 6-5 : Count Directions
57
Quadrature Count
58
Count Modes
58
Divide-By-N
58
Single Cycle
58
Control Modes
58
Figure 6-5: Quadrature Signals
58
No Control Mode
59
Load Mode
59
Latch Mode
59
Gate Mode
59
Reset Mode
59
Configuration Examples
59
Watchdog Timer
59
Table 6-6 : Input Control Mode Events
59
Table 6-7: Gate Mode
59
Event Counting
60
Input Pulse Width Measurement
60
Mechanical System Positioning
60
Interrupts
60
Interrupt Sources
60
Table 6-8 : Interrupt Sources
61
Installation
62
ADC Input Wiring
62
Figure 7-1 : Adc Input Wiring
62
DAC Output Wiring
63
TTL I/O Interface
63
Figure 7-2 : Dac Output Wiring
63
Figure 7-3 : Ttl I/O Interface
63
Pin Assignment - I/O Connector
64
Table 8-1 : Pin Assignment I/O Connector
64
Important Notes
65
Dummy Conversions after Power-Up
65
Open Multiplexer Inputs
65
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Tews Technologies TPMC851 User Manual (65 pages)
16 bit ADC/DAC, TTL I/O, Counter
Brand:
Tews Technologies
| Category:
I/O Systems
| Size: 1 MB
Table of Contents
Table of Contents
4
Product Description
7
Figure 1-1 : Block Diagram
8
Technical Specification
9
Table 2-1 : Technical Specification
10
Handling and Operation Instructions
11
ESD Protection
11
Addressing
12
PCI Configuration Space
12
PCI Address Space Overview
12
Table 4-1 : Pci Controller Header
12
Table 4-2 : Pci Address Space Overview
12
Configuration EEPROM
13
Table 4-3 : Configuration Eeprom Tpmc851-10R
13
PCI Controller Register Space
14
PCI Controller Configuration Register Map
14
Table 4-4 : Pci Controller Configuration Register Map
14
Local Register Address Space
15
Table 4-5 : Local Register Address Space
16
Analog Input Registers
17
Table 4-6 : Adc Control Register
18
Table 4-7 : Adc Data Register
18
Table 4-8 : Adc Data Coding
19
Table 4-9 : Adc Status Register
20
Table 4-10 : Adc Sequencer Control Register
21
Table 4-11 : Adc Sequencer Status Register
22
Table 4-12 : Error Flag Irq Generation
22
Table 4-13 : Adc Sequencer Timer Register
23
Table 4-14 : Adc Sequencer Instruction Ram Register
23
Table 4-15 : Adc Sequencer Instruction Ram Register Positions
25
Analog Output Registers
26
Table 4-16 : Dac Control Register
26
Table 4-17 : Dac Sequencer Status Register
27
Table 4-18 : Dac Sequencer Timer Register
27
Digital I/O Registers
28
Table 4-19 : Dac Data Register
28
Table 4-20 : Dac Data Coding
28
Table 4-21 : Line Direction Register
29
Table 4-22 : Line Debounce Enable Register
29
Table 4-23 : Line Debounce Time Register
30
Table 4-24 : Line Input Register
30
Table 4-25 : Line Output Register
31
Table 4-26 : Line Interrupt Enable Register
32
Table 4-27 : Line Interrupt Status Register
33
Counter 1 Registers
34
Table 4-28 : Counter 1 Preload Register
34
Table 4-29 : Counter 1 Compare Register
34
Table 4-30 : Counter 1 Data Register
34
Table 4-31 : Counter 1 Control Register
36
Table 4-32 : Counter 1 Status Register
37
Table 4-33 : Counter 1 Command Register
37
Interrupt Control Register ICR (Offset 0X0140)
38
Table 4-34 : Interrupt Control Register
38
Counter 2 Registers
39
Table 4-35 : Counter 2 Preload Register
39
Table 4-36 : Counter 2 Compare Register
39
Table 4-37 : Counter 2 Data Register
39
Table 4-38 : Counter 2 Control Register
41
Table 4-39 : Counter 2 Status Register
42
Board Status Register
43
Table 4-40 : Counter 2 Command Register
43
Table 4-41 : Temperature Register
43
Table 4-42 : Scratchpad Register
43
Table 3-43 : Firmware Identification Register
43
ADC Sequencer Data RAM
44
ADC/DAC Correction Data ROM
44
Table 4-44 : Adc Sequencer Data Ram Space Address Map
44
Table 4-45 : Adc/Dac Correction Data Rom Address Map
45
Configuration Hints
46
Local Software Reset
46
Programming Hints
47
Data Correction
47
ADC Correction Formula
47
DAC Correction Formula
48
ADC Operating Modes
48
Manual Mode
48
Sequencer Mode
49
Table 6-1 : Sequencer Errors
50
Application Examples
51
Figure 6-1 : Flow: Fastest Conversion of an Arbitrary Single Channel
51
Figure 6-2 : Flow: Fastest Conversion of a Specific Single Channel
52
Figure 6-3 : Flow: Periodic Conversion of Multiple Channels
53
Figure 6-4 : Flow: Continuous Conversion of Multiple Channels
54
DAC Operating Modes
55
Immediate Update
55
Simultaneous Update
55
Table 6-2 : Dac Load Modes
55
Digital TTL I/O
56
Counter Operating Modes
57
Input Modes
57
Control Modes
57
Table 6-3 : Input Modes
57
Table 6-4 : Clock Prescaler
57
Table 6-5 : Count Direction
57
Count Modes
58
Figure 6-5 : Quadrature Signals
58
Table 6-6 : Input Control Mode Events
59
Table 6-7 : Gate Mode
59
Configuration Examples
60
Interrupts
61
Interrupt Sources
61
Table 6-8 : Interrupt Sources
61
Installation
62
ADC Input Wiring
62
Figure 7-1 : Adc Input Wiring
62
DAC Output Wiring
63
TTL Digital I/O Interface
63
Figure 7-2 : Dac Output Wiring
63
Figure 7-3 : Ttl I/O Interface
63
Pin Assignment - I/O Connector
64
Table 8-1 : Pin Assignment I/O Connector
64
Important Notes
65
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