Characteristics - Omron CPM1A Operation Manual

Specifications

2-1-2 Characteristics

Item CPM1A-10CDR-j(-V1)
CPM1A-10CDT-j(-V1)
CPM1A-10CDT1-j(-V1)
Control method Stored program method
I/O control method Cyclic scan with direct output; immediate refresh processing
Programming Ladder diagram
language
Instruction length
1 step per instruction, 1 to 5 words per instruction
Types of instructions
Basic instructions:
Special instructions:
Execution time Basic instructions:
Special instructions:
Program capacity 2,048 words
Max. I/O CPU Unit 10 points
capacity capac y only
With ---
Expansion
I/O Units
Input bits 00000 to 00915
Output bits 01000 to 01915
Work bits 512 bits: 20000 to 23115 (Words IR 200 to IR 231)
Special bits (SR area) 384 bits: 23200 to 25515 (Words IR 232 to IR 255)
Temporary bits (TR 8 bits (TR0 to TR7)
area)
Holding bits (HR area) 320 bits: HR 0000 to HR 1915 (Words HR 00 to HR 19)
Auxiliary bits (AR 256 bits: AR 0000 to AR 1515 (Words AR 00 to AR 15)
area)
Link bits (LR area) 256 bits: LR 0000 to LR 1515 (Words LR 00 to LR 15)
Timers/Counters 128 timers/counters (TIM/CNT 000 to TIM/CNT 127)
Data memory Read/Write: 1,024 words (DM 0000 to DM 1023)
Read-only: 512 words (DM 6144 to DM 6655)
Interrupt processing External interrupts: 2
(see note 2)
Interval timer 1 (0.5 to 319,968 ms in Scheduled Interrupt Mode or Single Interrupt Mode)
interrupts
Memory protection HR and read/write DM area contents; and counter values maintained during power
interruptions.
Memory backup Flash memory:
The program, read-only DM area, and PC Setup area are backed up without a battery.
Capacitor backup:
The read/write DM area, error log area, HR area, and counter values are backed up by a
capacitor for 20 days at 25_C. The capacitor backup time depends on the ambient
temperature. See the graph on the following page for details.
Self-diagnostic CPU Unit failure (watchdog timer), I/O bus error, and memory failure
functions
Program checks No END instruction, programming errors (continuously checked during operation)
High-speed counter One high-speed counter: 5 kHz single-phase or 2.5 kHz two-phase (linear count method)
Quick-response inputs The same inputs are used for quick-response inputs and external interrupt inputs.
(Min. input pulse width: 0.2 ms)
CPM1A-20CDR-j(-V1)
CPM1A-20CDT-j(-V1)
CPM1A-20CDT1-j(-V1)
14
77 types, 135 instructions
0.72 to 16.2 µs
16.3 µs (MOV instruction)
20 points
---
100-ms timers: TIM 000 to TIM 127
10-ms timers (high-speed counter): TIM 000 to TIM 127 (see note 1)
(the timer numbers used are the same as for the 100-ms timers)
Decrementing counters and reversible counters
External interrupts: 4
Increment mode: 0 to 65,535 (16 bits)
Up/Down mode: –32,767 to 32,767 (16 bits)
CPM1A-30CDR-j(-V1) CPM1A-40CDR-j(-V1)
CPM1A-30CDT-j(-V1) CPM1A-40CDT-j(-V1)
CPM1A-30CDT1-j(-V1) CPM1A-40CDT1-j(-V1)
30 points 40 points
50, 70, or 90 points 60, 80, or 100 points
Words not used for input or output bits can be p
used for work bits. d f k bi
Section 2-1
p
23