Freescale Semiconductor MPC500 Series Manuals

Manuals and User Guides for Freescale Semiconductor MPC500 Series. We have 1 Freescale Semiconductor MPC500 Series manual available for free PDF download: Reference Manual

Freescale Semiconductor MPC500 Series Reference Manual

Freescale Semiconductor MPC500 Series Reference Manual (354 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 3 MB

Table of Contents

Table of Contents
3
Features
21
Block Diagram
23
Pin Connections
24
Memory Map
26
- Signal Descriptions
  27
Pin List
27
Pin Characteristics
28
Power Connections
30
Pins with Internal Pull-Ups and Pulldowns
30
Signal Descriptions
31
- Bus Arbitration and Reservation Support Signals
  33
  - Bus Request (BR)
    34
  - Bus Grant (BG)
    34
  - Bus Busy (BB)
    35
  - Cancel Reservation (CR)
    35
- Address Phase Signals
  36
  - Address Bus (ADDR[0:29])
    36
  - Write/Read (WR)
    36
  - Burst Indicator (BURST)
    36
  - Byte Enables (BE[0:3])
    37
  - Transfer Start (TS)
    37
  - Address Acknowledge (AACK)
    38
  - Burst Inhibit (BI)
    38
  - Address Retry (ARETRY)
    39
  - Address Type (AT[0:1])
    39
  - Cycle Types (CT[0:3])
    40
- Data Phase Signals
  40
  - Data Bus (DATA[0:31])
    40
  - Burst Data in Progress (BDIP)
    41
  - Transfer Acknowledge (TA)
    41
  - Transfer Error Acknowledge (TEA)
    42
  - Data Strobe (DS)
    42
- Development Support Signals
  43
- Chip-Select Signals
  45
  - Chip Select for System Boot Memory (CSBOOT)
    45
  - Chip Selects for External Memory (CS[0:11])
    45
- Clock Signals
  45
- Reset Signals
  47
  - Reset (RESET)
    47
  - Reset Output (RESETOUT)
    47
- SIU General-Purpose Input/Output Signals
  47
  - Ports a and B (PA[0:7], PB[0:7])
    47
  - Ports I, J, K, and L
    48
  - Port M (PM[3:7])
    48
- Interrupts and Port Q Signals
  48
  - Interrupt Requests (IRQ[0:6])
    48
  - Port Q (PQ[0:6])
    49
- JTAG Interface Signals
  49
  - Test Data Input (TDI)
    49
  - Test Data Output (TDO)
    49
  - Test Mode Select (TMS)
    49
  - Test Clock (TCK)
    49
  - Test Reset (TRST)
    50
  - Central Processing Unit
    51
RCPU Features
51
RCPU Block Diagram
51
Instruction Sequencer
52
Independent Execution Units
54
- Branch Processing Unit (BPU)
  55
- Integer Unit (IU)
  55
- Load/Store Unit (LSU)
  56
- Floating-Point Unit (FPU)
  56
RCPU Programming Model
57
Levels of the Powerpc Architecture
57
Powerpc UISA Register Set
60
Powerpc VEA Register Set - Time Base
67
Powerpc OEA Register Set
68
Instruction Set
75
Exception Model
82
- Exception Classes
  82
- Ordered Exceptions
  82
- Unordered Exceptions
  82
- Precise Exceptions
  83
- Exception Vector Table
  83
Instruction Timing
84
Instruction Cache

87
- Instruction Cache Features
  87
- Instruction Cache Organization
  88
- Instruction Cache Programming Model
  89
- Cache Operation
  91
- Cache Commands
  92
System Interface Unit

97
- SIU Block Diagram
  97
- SIU Address Map
  98
- SIU Module Configuration
  100
- External Bus Interface
  108
  - Features
    108
  - External Bus Signals
    109
  - Basic Bus Cycle
    111
    
    Read Cycle Flow
    111
    
    Write Cycle Flow
    113
  - Basic Pipeline
    114
  - Bus Cycle Phases
    116
    
    Arbitration Phase
    116
    
    Address Phase
    116
    
    Data Phase
    117
  - Burst Cycles
    118
    
    Termination of Burst Cycles
    119
    
    Burst Inhibit Cycles
    119
  - Decomposed Cycles and Address Wrapping
    120
  - Preventing Speculative Loads
    121
  - Accesses to 16-Bit Ports
    123
  - Address Retry
    124
  - Transfer Error Acknowledge Cycles
    125
  - Cycle Types
    125
  - Show Cycles
    127
  - Storage Reservation Support
    128
    
    Powerpc Architecture Reservation Requirements
    129
    
    E-Bus Storage Reservation Implementation
    129
    
    Reservation Storage Signals
    130
- Chip Selects
  131
  - Chip-Select Features
    132
  - Chip-Select Block Diagram
    132
  - Chip-Select Pins
    133
  - Chip-Select Registers and Address Map
    134
    
    Chip-Select Base Address Registers
    137
    
    Chip-Select Option Registers
    137
  - Chip-Select Regions
    142
  - Multi-Level Protection
    144
    
    Main Block and Sub-Block Pairings
    145
    
    Programming the Sub-Block Option Register
    145
    
    Multi-Level Protection for CSBOOT
    145
  - Access Protection
    146
    
    Supervisor Space Protection
    146
    
    Data Space Protection
    146
    
    Write Protection
    147
  - Cache Inhibit Control
    147
  - Handshaking Control
    147
  - Wait State Control
    147
  - Port Size
    148
  - Chip-Select Pin Control
    149
    
    Pin Configuration
    149
    
    Byte Enable Control
    149
    
    Region Control
    150
  - Interface Types
    150
    
    Interface Type Descriptions
    151
    
    Turn-Off Times for Different Interface Types
    153
    
    Interface Type and BI Generation
    153
  - Chip-Select Operation Flowchart
    154
  - Pipe Tracking
    154
    
    Pipelined Accesses to the same Region
    155
    
    Pipelined Accesses to Different Regions
    156
  - Chip-Select Timing Diagrams
    158
    
    Asynchronous Interface
    158
    
    Asynchronous Interface with Latch Enable
    159
    
    Synchronous Interface with Asynchronous OE
    159
    
    Synchronous Interface with Early Synchronous OE
    160
    
    Synchronous Interface with Synchronous OE, Early Overlap
    161
    
    Synchronous Burst Interface
    162
  - Burst Handling
    164
  - Chip-Select Reset Operation
    165
- Clock Submodule
  166
  - Clock Submodule Signal Descriptions
    167
  - Clock Power Supplies
    168
  - System Clock Sources
    169
  - Phase-Locked Loop
    170
    
    Crystal Oscillator
    170
    
    Phase Detector
    171
    
    Charge Pump and Loop Filter
    171
    
    Vco
    172
    
    Multiplication Factor Divider
    172
    
    Clock Delay
    172
  - CLKOUT Frequency Control
    172
    
    Multiplication Factor (MF) Bits
    173
    
    Reduced Frequency Divider (RFD[0:3])
    175
  - Low-Power Modes
    176
    
    Normal Mode
    176
    
    Single-Chip Mode
    176
    
    Doze Mode
    177
    
    Sleep Mode
    177
    
    Exiting Low-Power Mode
    177
  - System Clock Lock Bits
    178
  - Power-Down Wake up
    178
  - Time Base and Decrementer Support
    179
    
    Time Base and Decrementer Clock Source
    179
    
    Time Base/Decrementer and Freeze Assertion
    179
    
    Decrementer Clock Enable (DCE) Bit
    180
  - Clock Resets
    180
    
    Loss of PLL Lock
    180
    
    Loss of Oscillator
    180
  - System Clock Control Register (SCCR)
    181
  - System Clock Lock and Status Register (SCLSR)
    183
- System Protection
  184
  - System Protection Features
    184
  - System Protection Registers
    185
  - Periodic Interrupt Timer (PIT)
    185
    
    PIT Clock Frequency Selection
    186
    
    PIT Time-Out Period Selection
    187
    
    PIT Enable Bits
    188
    
    PIT Interrupt Request Level and Status
    188
    
    Periodic Interrupt Control and Select Register
    188
    
    Periodic Interrupt Timer Register
    189
  - Hardware Bus Monitor
    189
    
    Bus Monitor Timing
    190
    
    Bus Monitor Lock
    190
    
    Bus Monitor Enable
    190
    
    Bus Monitor Control Register
    190
- Reset Operation
  191
  - Reset Sources
    191
  - Reset Flow
    192
    
    External Reset Request Flow
    192
    
    Internal Reset Request Flow
    194
    
    Reset Behavior for Different Clock Modes
    196
  - Configuration During Reset
    197
    
    Data Bus Configuration Mode
    198
    
    Internal Default Mode
    198
    
    Data Bus Reset Configuration Word
    198
  - Power-On Reset
    200
- General-Purpose I/O
  201
  - Port M
    203
  - Ports a and B
    204
  - Ports I, J, K, and L
    206
  - Port Replacement Unit (PRU) Mode
    209
    
    Peripheral Control Unit
    211
- PCU Block Diagram
  211
- PCU Address Map
  212
- Module Configuration
  212
- Software Watchdog
  213
- Interrupt Controller
  215
  - Interrupt Controller Operation
    215
  - Interrupt Sources
    217
    
    External Interrupt Requests
    217
    
    Periodic Interrupt Timer Interrupts
    217
    
    Interrupt Request Multiplexing
    217
  - Interrupt Controller Registers
    218
    
    Pending Interrupt Request Register
    219
    
    Enabled Active Interrupt Requests Register
    219
    
    Interrupt Enable Register
    220
    
    Pit/Port Q Interrupt Levels Register
    220
- Port Q
  221
  - Port Q Edge Detect/Data Register
    221
  - Port Q Pin Assignment Register
    222
    
    Port Q Pin Assignment Fields
    223
    
    Port Q Edge Fields
    223
Static Ram Module

225
- Features
  225
- Placement of SRAM in Memory Map
  225
- SRAM Registers
  227
Development Support

229
- Program Flow Tracking
  229
- Watchpoint and Breakpoint Support
  239
  - Watchpoints
    241
    
    Restrictions on Watchpoint Detection
    241
    
    Byte and Half-Word Working Modes
    242
    
    Generating Six Compare Types
    243
    
    I-Bus Support Detailed Description
    244
    
    L-Bus Support Detailed Description
    245
    
    Treating Floating-Point Numbers
    247
  - Internal Breakpoints
    248
    
    Breakpoint Counters
    248
    
    Trap-Enable Programming
    248
    
    Ignore First Match
    249
  - External Breakpoints
    249
  - Breakpoint Masking
    249
- Development Port
  250
  - Development Port Signals
    251
    
    Development Serial Clock
    251
    
    Development Serial Data in
    251
    
    Development Serial Data out
    251
  - Development Port Registers
    253
    
    Development Port Shift Register
    253
    
    Trap Enable Control Register
    254
  - Development Port Clock Mode Selection
    254
  - Development Port Transmissions
    258
  - Trap-Enable Input Transmissions
    258
  - CPU Input Transmissions
    259
  - Serial Data out of Development Port - Non-Debug Mode
    259
  - Serial Data out of Development Port - Debug Mode
    260
    
    Valid Data Output
    260
    
    Sequencing Error Output
    261
    
    CPU Exception Output
    262
    
    Null Output
    262
  - Use of the Ready Bit
    262
- Debug Mode Functions
  263
  - Enabling Debug Mode
    263
  - Entering Debug Mode
    264
  - Debug Mode Operation
    264
  - Freeze Function
    265
  - Exiting Debug Mode
    265
  - Checkstop State and Debug Mode
    265
- Development Port Transmission Sequence
  266
  - Port Usage in Debug Mode
    266
  - Debug Mode Sequence Diagram
    268
  - Port Usage in Normal (Non-Debug) Mode
    269
- Examples of Debug Mode Sequences
  270
  - Prologue Instruction Sequence
    270
  - Epilogue Instruction Sequence
    270
  - Peek Instruction Sequence
    271
  - Poke Instruction Sequence
    271
- Software Monitor Support
  271
- Development Support Registers
  273
- Ieee 1149.1-Compliant Interface
  
  289
  - JTAG Interface Block Diagram
    289
  - JTAG Signal Descriptions
    290
  - Instruction Register
    291
    
    Extest (0000)
    292
    
    Bypass (1111)
    293
    
    Sample/Preload (1110)
    294
    
    Clamp (0011)
    294
    
    Highz (0010)
    295
    
    Extest_Pullup (0001)
    295
    
    Idcode (1101)
    296
    
    Tmscan (1100)
    296
  - Operating Frequency
    291
  - TAP Controller
    291
  - Restrictions
    296
  - Boundary Scan Descriptor Language (BSDL)
    297
  - Non-IEEE 1149.1-1990 Operation
    297
- Appendix A
  
  307
- Mpc509 Electrical Characteristics
  
  307

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