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Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 User’s Manual V850ES/GB1 VENUS 32-/16-bit Single-Chip Microcontroller with CAN Interface Hardware µPD703223, µPD703224, µPD70F3224, µPD703225, µPD703226, µPD70F3226 Document No. U15872EE2V1UM00 Date Published November 2005  NEC Electronics Corporation 2005 Printed in Germany...
Page 4 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 5 • The information in this document is current as of November, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country.
Page 6 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7: Preface
Preface Readers This manual is intended for users who want to understand the functions of the V850ES/GB1 (nickname VENUS). Purpose This manual presents the hardware manual of V850ES/GB1. Organization This system specification describes the following sections: • Pin function •...
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Page 9: Table Of Contents
Table of Contents Preface ............5 Chapter 1 Introduction.
Page 10 Exception Trap ............119 4.5.1 Illegal op code definition .
Page 11 6.4.4 8-Bit Timer Operation ..........223 6.4.5 Operating as interval timer (16 bits) .
Page 12 10.7 Message Buffer Configuration ......... . 350 10.8 Transmit Buffer Structure .
Page 13 11.4.2 Input voltage and conversion results ....... . 418 11.4.3 A/D converter operation mode .
Page 14 Appendix A Instruction Set List..........483 Appendix B Index .
Page 15 List of Figures Figure 1-1: Pin Configuration of the µPD70F322x, µPD70322x ............ 24 Figure 1-2: Block Diagram of the V850ES/GB1 Microcontroller ............ 26 Figure 2-1: Pin I/O Circuits ......................46 Figure 3-1: CPU Register Set ......................48 Figure 3-2: Program counter (PC) Format ..................49 Figure 3-3: Interrupt: context saving registers (EIPC, EIPSW) Format..........
Page 16 Figure 4-27: Key Return Block Diagram ..................128 Figure 5-1: Clock Generator Block Diagram ................129 Figure 5-2: Main System Clock Oscillator..................130 Figure 5-3: RC Oscillator Circuit ....................131 Figure 5-4: Crystal Oscillator circuit ..................... 131 Figure 5-5: Processor Clock Control Register Format (1/2)............132 Figure 5-6: Power Save Mode Register Format ................
Page 17 Figure 6-46: Timer Input Select Block Diagram ................212 Figure 6-47: Timer Input Select Control Register Format .............. 213 Figure 6-48: Block Diagram of Timer 50, Timer 51................ 215 Figure 6-49: Block Diagram of Timer 52 ..................215 Figure 6-50: Timer 51 as clock source for CSI00 ................
Page 18 Figure 9-34: Clocked Serial Interface Mode Registers (CSIM0, CSIM1) ........298 Figure 9-35: Clocked Serial Interface Clock Selection Registers (CSIC0, CSIC1) (1/2) ..... 299 Figure 9-36: Clocked Serial Interface Reception Buffer Registers (SIRB0, SIRB1) ....301 Figure 9-37: Clocked Serial Interface Reception Buffer Registers (SIRB0L1, SIRB1L1) .... 302 Figure 9-38: Clocked Serial Interface Transmission Buffer Registers (SOTB0, SOTB1) ....
Page 19 Figure 10-41: DCAN Error Status Register (CANES0) (1/3) ............374 Figure 10-42: Transmit Error Counter Register (TEC0) ..............377 Figure 10-43: Receive Error Counter Register (REC0) ..............377 Figure 10-44: Message Count Register (MCNT0) (1/2) ..............378 Figure 10-45: Bit Rate Prescaler Register (BRPRS0) (1/2) ............380 Figure 10-46: Synchronization Control Registers 0 and 1 (SYNC00, SYNC10 (1/5) .....
Page 20 Figure 12-30: Port 5 Pull-up Resistor Option register (PU5)............451 Figure 12-31: Port 7 (P7, P7L and P7H)..................452 Figure 12-32: Port NMI (PNMI) ......................454 Figure 12-33: Port DL (PDL, PDLL and PDLH) ................455 Figure 12-34: Port DL mode register (PMDL, PMDLL and PMDLH) ..........456 Figure 12-35: Port DH (PDH)......................
Page 21 List of Tables Table 1-1: Product Versions ......................22 Table 2-1: Pin List..........................29 Table 2-2: Pin state related to V850ES/GB1 state ................32 Table 3-1: Program Registers ......................49 Table 3-2: System Register Numbers ..................... 50 Table 3-3: Saturated Operation Results ..................54 Table 3-4: Setup values for VSWC....................
Page 22 Table 13-1: Hardware Status on RESET Pin Input or Occurrence of WDTRES ......464 Table 13-2: RAM Usage after RESET Release................465 Table 14-1: Correspondence Between CORCN Register Bits and CORADn Registers ....469 Table 15-1: Serial interface pins ...................... 479 Table 15-2: List of Communication Systems ..................
Page 23: Introduction
Chapter 1 Introduction 1.1 General The V850ES/GB1 VENUS single chip microcontroller is a member of NEC's V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control applications. The V850 CPU offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit CISC CPUs.
Page 24: Device Features
Chapter 1 Introduction 1.2 Device Features • - Core: V850ES - Number of instructions: - Min. instruction execution time: 62.50 ns (@ f = 16 MHz) - General registers: 32 bits x 32 • Instruction set: - V850ES - Multiply instructions (on-chip hardware multiplex excluding multiplication in 1 to 4 clocks) 16 bits ×...
Page 25: Application Fields
Chapter 1 Introduction • Serial Interfaces - 3-wire mode: 2 channels - UART mode: 2 channels Note • DCAN Interface: 1 channel • Timers - 16-bits dual time-base timer 1 channel - 16-bits capture/compare timer 1 channel - 8-bit timers (PWM function and cascadable): 3 channels - Watch timer: 1 channel - Watchdog timer:...
Page 26: Pin Configuration (Top View)
PDH5 P01/INTP1 PDH4 P02/INTP2 PDH3 PDH2 P03/INTP3 P04/INTP4 PDH1 PDH0 P05/INTP5 PCM3 DD50 REGC0 REGC1 SS30 SS31 PCM2 V850/GB1 "VENUS" PCM1/CLKOUT RESET PCM0 Note 2 CL1/XT1 SS51 Note 2 CL2/XT2 DD51 PDL15 P06/INTP6 PDL14 Note 1 P10/SI00 P11/SO00 PDL13 P12/SCK00...
Page 27 Chapter 1 Introduction Pin Identification ANI0 to ANI11 Analog Input RESET Reset Input Analog Power Supply RXD60, RXD61 UART Receive Data Analog Ground SCK00, SCK01 Synchronous Interface Clock CLKOUT Processor Clock Output SI00, SI01 Synchronous Interface Input CRXD0 CAN Receive Data SO00, SO01 Synchronous Interface Output CTXD0...
Page 28: Internal Architecture
Chapter 1 Introduction 1.5 Internal Architecture 1.5.1 Block Diagram of V850ES/GB1 Figure 1-2: Block Diagram of the V850ES/GB1 Microcontroller power supply Interrupt Controller CPU Core INTP0 to INTP8 TIG00 to TIG05 16-bit Timer Barrel Hardware TMG0 Shifter Multiplier TOG01 to TOG04 Flash/ control System...
Page 29: On-Chip Units
Chapter 1 Introduction 1.5.2 On-chip units The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the barrel shifter (32 bits), help accelerate processing of complex instructions.
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Page 31: Pin Functions
Chapter 2 Pin Functions 2.1 List of Pin Functions The names and functions of this product’s pins are listed below. Table 2-1: Pin List (1/4) Function Soft- Driver ware Type Name Default Alternate Pull Up Analog Supply Analog Ground P00/INTP0 External interrupt input INTP0 P01/INTP1 External interrupt input INTP1...
Page 32 Chapter 2 Pin Functions Table 2-1: Pin List (2/4) Function Soft- Driver ware Type Name Default Alternate Pull Up P40/KR0 Key Return Input 0 Key Return Input 1 P41/KR1/ TimerG0 Capture Trigger 0 TIG00 TimerG0 Compare Output 0 Key Return Input 2 P42/KR2/ TimerG0 Capture Trigger 1 TIG01/TOG01...
Page 33 Chapter 2 Pin Functions Table 2-1: Pin List (3/4) Function Soft- Driver ware Type Name Default Alternate Pull Up Flash Devices: Programming Voltage Input ROM Devices: Internal Connection PDL14 Port DL: 16-bit input/output port PDL15 Power Supply I/O Buffers DD51 I/O Buffers Ground SS51 PCM0...
Page 34: Table 2-2: Pin State Related To V850Es/Gb1 State
Chapter 2 Pin Functions Table 2-1: Pin List (4/4) Function Soft- Driver ware Type Name Default Alternate Pull Up P711/ANI11 ANI11 P710/ANI10 ANI12 P79/ANI9 ANI9 P78/ANI8 ANI8 P77/ANI7 ANI7 P76/ANI6 ANI7 − Port 7: 12-bit input port P75/ANI5 ANI6 P74/ANI4 ANI5 P73/ANI3 ANI3...
Page 35: Description Of Pin Functions
Chapter 2 Pin Functions 2.2 Description of Pin Functions P00 to P06 (Port 0) … Input/output Port 0 is an 7-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, P00 to P06 operate as external interrupt request input pins.
Page 36 Chapter 2 Pin Functions P10 to P15 (Port 1) … Input/output Port 1 is an 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, P10 to P14 operate as serial interface (CSI00, UART60) input/output and furthermore P13 operates as maskable external interrupt request input pin.
Page 37 Chapter 2 Pin Functions P20 to P25 (Port 2) … Input/Output Port 2 is a 6-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, P20 to P25 operate as serial interface (CSI01, UART61) input/output and furthermore P20 operates as maskable external interrupt request input pin.
Page 38 Chapter 2 Pin Functions P30 to P36 (Port 3) … Input/Output Port 3 is a 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode P30 to P32 operate as 8-bit PWM or Timer 5 input/output and P33 to P34 operate as Timer C input/output.
Page 39 Chapter 2 Pin Functions P40 to P47 (Port 4) … Input/output Port 4 is a 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode P40 to P47 operate as inputs for the key return function or as Timer G input/output.
Page 40 Chapter 2 Pin Functions P50 to P57 (Port 5) … Input/output Port 5 is a 8-bit input/output port in which input or output can be set in 1-bit units. Besides functioning as an input/output port, in control mode P54 and P55 operate as data lines for the CAN network.
Page 41 Chapter 2 Pin Functions P70 to P711 (Port 7) … Input Port 7 is a 12-bit input-only port. Besides functioning as an input port, P70 to P711 operate as analog input pins to the A/D con- verter. (a) Port mode P7 is a 12-bit input-only port.
Page 42 Chapter 2 Pin Functions PCS0 to PCS1 (Port CS) … Input/output Port CS is a 2-bit input/output port in which input or output can be set in 1-bit units. (c) Port mode PCS0 and PCS1 can be set to input or output in 1-bit units using the port 5 mode register (PMCS). User’s Manual U15872EE2V1UM00...
Page 43 Chapter 2 Pin Functions PCT0, PCT1, PCT4 and PCT6 (Port CT) … Input/output Port CT is a 4-bit input/output port in which input or output can be set in 1-bit units. (a) Port mode PCT0, PCT1, PCT4 and PCT6 can be set to input or output in 1-bit units using the port CT mode register (PMCT).
Page 44 Chapter 2 Pin Functions (10) PDH0 to PDH5 (Port DH) … Input/output Port DH is a 6-bit input/output port in which input or output can be set in 1-bit units. (a) Port mode PDH0 to PDH5 can be set to input or output in 1-bit units using the port DH mode register (PMDH).
Page 45 Chapter 2 Pin Functions (11) PDL0 to PDL15 (Port DL) … Input/output Port DL is a 16-bit input/output port in which input or output can be set in 1-bit units. (a) Port mode PDH0 to PDH15 can be set to input or output in 1-bit units using the port DL mode register (PMDL).
Page 46 Chapter 2 Pin Functions (12) PCM0 to PCM3 (Port CM) … Input/output Port CM is a 4-bit input/output port. Besides functioning as an input/output port, in control mode, PCM1 operates as system clock out- put. (a) Port mode PCM is a 4-bit input/output port. (b) Control mode PCM1 can be set to port or control mode using PMCM.
Page 47 Chapter 2 Pin Functions (13) V /IC (Flash Memory Programming Voltage) High voltage apply pin for FLASH programming mode setting. Connect to V in normal operating mode.To use this pin for on board flash programming connect this pin with a pull down resistor to (14) RESET (Reset) …...
Page 48: Figure 2-1: Pin I/O Circuits
Chapter 2 Pin Functions Figure 2-1: Pin I/O Circuits Type 2 Type 5-A Pullup P-ch enable Data P-ch IN/OUT Output N-ch disable Input enable Type 5-K Type 5-W Pullup P-ch enable Data P-ch IN/OUT Data P-ch Output N-ch disable IN/OUT Output N-ch disable...
Page 49: Cpu Functions
Chapter 3 CPU Functions The CPU of the V850ES/GB1 is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control. 3.1 Features • Number of instructions: • Minimum instruction execution time: 62.5 ns (@ 16 MHz operation, 4.0 V to 5.5 V) •...
Page 50: Cpu Register Set
Chapter 3 CPU Functions 3.2 CPU Register Set The CPU registers of the V850ES/GB1 can be classified into two categories: a general-purpose pro- gram register set and a dedicated system register set. All the registers have 32-bit width. For detailed description of V850ES core, refer to V850ES Core Architecture Manual (Document No.
Page 51: Program Register Set
Chapter 3 CPU Functions 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable.
Page 52: System Register Set
Chapter 3 CPU Functions 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2: System Register Numbers Operand Specification System Register...
Page 53: Figure 3-3: Interrupt: Context Saving Registers (Eipc, Eipsw) Format
Chapter 3 CPU Functions Context saving registers (EIPC, EIPSW) There are two context saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the content of the program counter (PC) is saved to EIPC and the content of the program status word (PSW) is saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the content is saved to the NMI con- text saving registers (FEPC, FEPSW)).
Page 54: Figure 3-4: Nmi: Context Saving Registers (Fepc, Fepsw) Format
Chapter 3 CPU Functions NMI context saving registers (FEPC, FEPSW) There are two NMI context saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the content of the program counter (PC) is saved to FEPC and the content of the program status word (PSW) is saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable inter- rupt occurs is saved to FEPC, except for the DIVH instruction.
Page 55: Figure 3-6: Program Status Word (Psw) Format
Chapter 3 CPU Functions Program status word (PSW) A program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the content of this register is changed using the LDSR instruction, the new content become valid immediately following completion of the LDSR instruction execution.
Page 56: Figure 3-7: Callt Context Saving Registers (Ctpc, Ctpsw) Format
Chapter 3 CPU Functions Table 3-3: Saturated Operation Results Flag status Saturated Operation result status operation result Maximum positive value exceeded 7FFFFFFFH Maximum negative value exceeded 80000000H Positive (maximum value not exceeded) Holds value Actual before operation operation result Negative (maximum value not exceeded) CALLT: context saving registers (CTPC, CTPSW) There are two CALLT context saving registers, CTPC and CTPSW.
Page 57: Figure 3-8: Exception/Debug Trap Context Saving Registers (Dbpc, Dbpsw) Format
Chapter 3 CPU Functions Exception/debug trap context saving registers (DBPC, DBPSW) There are two exception/debug trap context saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the content of the program counter (PC) is saved to DBPC, and the program status word (PSW) content is saved to DBPSW. The value saved to DBPC consist of the address of the next instruction after the instruction exe- cuted when an exception trap or debug trap occurs.
Page 58: Operation Modes
Chapter 3 CPU Functions 3.3 Operation Modes The V850ES/GB1 has the following operating modes. Normal operating mode After the system has been released from the reset state, execution branches to the reset entry address of the internal ROM, and instruction processing is started. Flash memory programming mode The internal flash memory can be written or erased when a 7.8 V voltage is applied to the V pin.
Page 59: Address Space
Chapter 3 CPU Functions 3.4 Address Space 3.4.1 CPU address space The CPU of the V850ES/GB1 uses a 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When addressing instruction, a linear address space (program space) of up to 64 MB is supported.
Page 60: Image
Chapter 3 CPU Functions 3.4.2 Image When addressing an instruction, up to 16 MB of linear address space (program space) and Internal RAM area are supported. For operand addressing (data access), up to 4 GB of linear address space (data area) is supported. On this 4 GB address space, however, 64 images of the same 64 MB physical address spaces can be seen.
Page 61: Wrap-Around Of Cpu Address Space
Chapter 3 CPU Functions 3.4.3 Wrap-around of CPU address space Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0.
Page 62: Memory Map
Chapter 3 CPU Functions 3.4.4 Memory map Memory map for 128 KB ROM version (µPD70F3224, µPD703224, µPD70F3226, µPD703226) is shown in Figure 3-14. Memory map for 96 KB ROM version (µPD703223, µPD703225) is shown in Figure 3-15. Figure 3-14: Memory map for 128 KB ROM version (µPD70F3224, µPD703224, µPD70F3226, µPD703226) 3FF FFFFH 3FF FFFFH...
Page 63: Figure 3-15: Memory Map For 96 Kb Rom Version (Μpd703223, Μpd703225)
Chapter 3 CPU Functions Figure 3-15: Memory map for 96 KB ROM version (µPD703223, µPD703225) 3FF FFFFH 3FF FFFFH On-chip peripheral I/O area (4 KB) 3FF F000H (80 KB) 3FF EFFFH Internal RAM area 3FE C000H (4 KB) 3FE BFFFH 3FF E000H 3FF DFFFH Reserved...
Page 64: Figure 3-16: Program Memory Map
Chapter 3 CPU Functions Figure 3-16: Program Memory Map 03FF FFFFH Access-prohibited area (Program fetch disabled area) 03FF F000H 03FF EFFFH Internal RAM area (80 KB) 03FE C000H 03FE BFFFH Access-prohibited area (Program fetch disabled area) 0010 0000H 000F FFFFH Internal ROM area (1 MB) 0000 0000H...
Page 65: Areas
Chapter 3 CPU Functions 3.4.5 Areas Internal ROM area An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM/internal flash memory (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in the following products. Addresses 0020000H to 00FFFFFH are an access-prohibited area.
Page 66: Figure 3-18: Internal Rom Area (96 Kb)
Chapter 3 CPU Functions (b) Internal ROM/internal flash memory area (96 KB) A 96 KB area from 0000000H to 0017FFFH is provided in the following products. Addresses 0018000H to 00FFFFFH are an access-prohibited area. • µPD703223, 703225 Figure 3-18: Internal ROM Area (96 KB) 00F FFFFH Access-prohibited area...
Page 67: Figure 3-19: Internal Ram Area (6 Kb)
Chapter 3 CPU Functions Internal RAM area An area of 80 KB maximum from 3FEC000H to 3FFEFFFH is reserved for the internal RAM area. (a) Internal RAM (6 KB) A 6 KB area from 3FFD8000H to 3FFEFFFH is provided as physical internal RAM. Addresses 3FEC000H to 3FFD7FFH are an access-prohibited area.
Page 68: Figure 3-20: Internal Ram (4 Kb)
Chapter 3 CPU Functions (b) Internal RAM area (4 KB) A 4 KB area from 3FFE000H to 3FFEFFFH is provided as physical internal RAM in the following products. Addresses 3FEC000H to 3FFDFFFH are an access-prohibited area. • µPD703223, 703225 Figure 3-20: Internal RAM (4 KB) 3FF EFFFH Internal RAM area (4 KB) 3FF E000H...
Page 69: Figure 3-21: On-Chip Peripheral I/O Area
Chapter 3 CPU Functions On-chip peripheral I/O area A 4 KB area from 3FEC000H to 3FEEFFFH is provided as the on-chip peripheral I/O area. Figure 3-21: On-Chip Peripheral I/O Area 3FE EFFFH On-chip peripheral I/O area (4 KB) 3FE C000H Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode specification and state monitoring are mapped to the on-chip peripheral I/O area.
Page 70: Figure 3-22: Programmable Peripheral Area Control Register Bpc
Chapter 3 CPU Functions Programmable peripheral area The programmable peripheral area is 12 KB wide and is used to map the CAN registers and RAM. Access to this area is controlled by the BPC register. BPC is a read/write 16-bit accessible register. Figure 3-22: Programmable peripheral area control register BPC Address At Reset...
Page 71: Areas Access Time
Chapter 3 CPU Functions 3.4.6 Areas access time Number of access clocks The number of basic clocks necessary for accessing each resources is as follow: Resource (bus width) Bus Cycle Type Internal ROM (32 bits) Internal RAM (32 bits) Peripheral I/O (16 bits) Instruction fetch Note Disabled...
Page 72: Special Registers
Chapter 3 CPU Functions 3.4.7 Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program behaviour occurs. The V850ES/GB1 has the following two special registers. • Power save control register (PSC) • Processor clock control register (PCC) Moreover, there is also a command register (PRCMD), which is a protection register for write operations to the special registers.
Page 73: Figure 3-25: System Status Register Format
Chapter 3 CPU Functions System status register (SYS) The SYS register is an 8-bit register to which the PRERR flag showing the generation of protection errors is assigned. If a write operation to a special register has not been executed in the correct sequence including the access to the command register (PRCMD), the write operation to the planned register is not executed, a protection error is generated and the PRERR flag is set to 1.
Page 74 Chapter 3 CPU Functions Examples for setting data in a special register Data setting in the PSC register follows the following sequence: <1> Prepare data that shall be set in the PSC register in any general register <2> The content of the general register prepared in <1> is written to the command register (PRCMD) using the store instruction (ST/SST).
Page 75: Cautions
Chapter 3 CPU Functions 3.4.8 Cautions Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 76 Chapter 3 CPU Functions Result of MULU or MUL instruction may be illegal (a) Description: If an interrupt occurs during execution of an instruction “mul/mulu Rd, Rx, Rd” that uses the same register for the 1st and 3rd operands, the operation result (register value of the 3rd operand) may be illegal.
Page 77 Chapter 3 CPU Functions <2>Countermeasure for NEC V850 Compiler The NEC V850 compiler generates the assembly pattern in following cases: • The explicit use of the assembly pattern in user assembly source The assembly pattern is neither generated inline by the compiler nor used in any library function. <3>Countermeasure for IAR Embedded Workbench V850 EWV850 generates the assembly pattern in following cases: •...
Page 78: Peripheral I/O Registers (Sfr)
Chapter 3 CPU Functions 3.4.9 Peripheral I/O registers (SFR) The following tables list the Venus Special Function Registers (SFR’s). Table 3-5: Peripheral I/O registers (1/6) Accessibility After Address Special Function Register Name Symbol Reset 1-bit 8-bit 16-bit × × FFFFF004...
Page 79 Chapter 3 CPU Functions Table 3-5: Peripheral I/O registers (2/6) Accessibility After Address Special Function Register Name Symbol Reset 1-bit 8-bit 16-bit × × FFFFF126 Interrupt control register P1IC × × FFFFF128 Interrupt control register P2IC × × FFFFF12A Interrupt control register P3IC ×...
Page 80 Chapter 3 CPU Functions Table 3-5: Peripheral I/O registers (3/6) Accessibility After Address Special Function Register Name Symbol Reset 1-bit 8-bit 16-bit × FFFFF205 A/D conversion result register H ADCRH undefined × × FFFFF2C0 Key return mode register × × FFFFF400 Port 0 register undefined...
Page 81 Chapter 3 CPU Functions Table 3-5: Peripheral I/O registers (4/6) Accessibility After Address Special Function Register Name Symbol Reset 1-bit 8-bit 16-bit × FFFFF646 8-bit timer 50 mode control register TMC50 × FFFFF647 8-bit timer 51 mode control register TMC51 ×...
Page 82 Chapter 3 CPU Functions Table 3-5: Peripheral I/O registers (5/6) Accessibility After Address Special Function Register Name Symbol Reset 1-bit 8-bit 16-bit FFFFF848 Correction address register 2 CORAD2 32-bit access 00000000H × FFFFF848 Correction address register 2L CORAD2L 0000H × FFFFF84A Correction address register 2H CORAD2H 0000H...
Page 83 Chapter 3 CPU Functions Table 3-5: Peripheral I/O registers (6/6) Accessibility After Address Special Function Register Name Symbol Reset 1-bit 8-bit 16-bit × FFFFFD02 CSI00 receive buffer register L SIRB0L × FFFFFD04 CSI00 transmit buffer register SOTB0 0000H × FFFFFD04 CSI00 transmit buffer register L SOTB0L ×...
Page 84: Can Ram And Registers
Chapter 3 CPU Functions 3.4.10 CAN RAM and registers Table 3-6: CAN RAM mapping (1/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC000H undefined × × 3FEC001H undefined × × 3FEC002H undefined × × 3FEC003H undefined ×...
Page 85 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (2/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC020H undefined × × 3FEC021H undefined × × 3FEC022H undefined × × 3FEC023H undefined × × 3FEC024H undefined ×...
Page 86 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (3/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC040H undefined × × 3FEC041H undefined × × 3FEC042H undefined × × 3FEC043H undefined × × 3FEC044H undefined ×...
Page 87 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (4/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC060H undefined × × 3FEC061H undefined × × 3FEC062H undefined × × 3FEC063H undefined × × 3FEC064H undefined ×...
Page 88 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (5/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC080H undefined × × 3FEC081H undefined × × 3FEC082H undefined × × 3FEC083H undefined × × 3FEC084H undefined ×...
Page 89 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (6/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC0A0H undefined × × 3FEC0A1H undefined × × 3FEC0A2H undefined × × 3FEC0A3H undefined × × 3FEC0A4H undefined ×...
Page 90 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (7/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC0C0H undefined × × 3FEC0C1H undefined × × 3FEC0C2H undefined × × 3FEC0C3H undefined × × 3FEC0C4H undefined ×...
Page 91 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (8/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC0E0H undefined × × 3FEC0E1H undefined × × 3FEC0E2H undefined × × 3FEC0E3H undefined × × 3FEC0E4H undefined ×...
Page 92 Chapter 3 CPU Functions Table 3-6: CAN RAM mapping (9/9) Accessibility Reset Address CAN Buffer Name Value 1-bit 8-bit 16-bit × × 3FEC100H undefined × × 3FEC101H undefined × × 3FEC102H undefined × × 3FEC103H undefined × × 3FEC104H undefined ×...
Page 93: Table 3-7: Can Registers Mapping
Chapter 3 CPU Functions Table 3-7: CAN registers mapping Accessibility Reset Address CAN register name Symbol Value 1-bit 8-bit 16-bit × × 3FEC120H DCAN Control 0 DCANC0 × × 3FEC121H CAN Control 0 CANC0 × 3FEC122H Transmission Control 0 TCR0 ×...
Page 94 [MEMO] User’s Manual U15872EE2V1UM00...
Page 95: Interrupt/Exception Processing Function
Chapter 4 Interrupt/Exception Processing Function 4.1 Outline The V850ES/GB1 Venus is provided with a dedicated interrupt controller for interrupt servicing, which realizes a high-performance interrupt function that can service interrupt requests from a total of 42 sources. An interrupt is an event that occurs asynchronously (independently of program execution), and an exception is an event that occurs synchronously (dependently on program execution).
Page 96: Table 4-1: Interrupt Source List
Chapter 4 Interrupt/Exception Processing Function Interrupt/exception sources are listed in Table 4-1. Table 4-1: Interrupt Source List (1/2) Interrupt Interrupt Exception Handler Type Class Name Trigger Control Request Code Address Register Flag Name Reset Interrupt RESET Reset input, WDTRES 0000H 00000000H Interrupt NMI pin input...
Page 97 Chapter 4 Interrupt/Exception Processing Function Table 4-1: Interrupt Source List (2/2) Interrupt Interrupt Exception Handler Type Class Name Trigger Control Request Code Address Register Flag Name DCAN0 End of Buffer1 INTCT01 01F0H 000001F0H CT01IC CT01IF Transmission INTCSI0 CSI00 end of transfer 0200H 00000200H CSI0IC...
Page 98: Non-Maskable Interrupt
Chapter 4 Interrupt/Exception Processing Function 4.2 Non-Maskable Interrupt The non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (DI state). The NMI is not subject to priority control and takes precedence over all the other interrupts. Non-maskable interrupts of the V850ES/GB1 are available for the following two requests: •...
Page 99: Operation
Chapter 4 Interrupt/Exception Processing Function 4.2.1 Operation If the non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: Saves the current PC to FEPC. Saves the current PSW to FEPSW. Writes exception code 0010H to the higher half-word (FECC) of ECR. Sets the NP and ID bits of PSW and clears the EP bit.
Page 100: Figure 4-2: Acknowledging Non-Maskable Interrupt Request
Chapter 4 Interrupt/Exception Processing Function Figure 4-2: Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is executing: Main routine (PSW. NP = 1) NMI request NMI request NMI request pending because PSW. NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is executing: Main routine...
Page 101: Restore
Chapter 4 Interrupt/Exception Processing Function 4.2.2 Restore Execution is restored from the non-maskable interrupt service by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers con- trol to the address of the restored PC. Restores the values of PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0 and the NP bit of PSW is 1.
Page 102: Np Flag
Chapter 4 Interrupt/Exception Processing Function 4.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execu- tion. This flag is set when the NMI interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged.
Page 103: Edge Detection Function Of Nmi Pin
Chapter 4 Interrupt/Exception Processing Function 4.2.5 Edge detection function of NMI pin The NMI pin valid edge can be selected from falling edge or rising edge. The bit ESNMI in the register INTM2 specifies the valid edge of the non-maskable interrupt (NMI). The INTM2 register can be read/written in 1-bit or 8-bit units.
Page 104: Maskable Interrupts
Chapter 4 Interrupt/Exception Processing Function 4.3 Maskable Interrupts The V850ES/GB1 has 40 maskable interrupt sources. Maskable interrupt requests can be masked by interrupt control registers. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 105: Figure 4-6: Maskable Interrupt Servicing
Chapter 4 Interrupt/Exception Processing Function Figure 4-6: Maskable Interrupt Servicing INT input Interrupt acceptance Mask? PSW. ID = 0 Interrupt enable mode? Priority higher than that of interrupt currently serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request...
Page 106: Restore
Chapter 4 Interrupt/Exception Processing Function 4.3.2 Restore To restore execution from the maskable interrupt servicing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 107: Priorities Of Maskable Interrupts
Chapter 4 Interrupt/Exception Processing Function 4.3.3 Priorities of maskable interrupts The V850ES/GB1 provides multiple interrupt service that acknowledges an interrupt while servicing another interrupt. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by interrupt priority level specification bits (xxnPR bits in the Interrupt Control Register xxnIC).
Page 108: Figure 4-8: Example Of Interrupt Nesting Service (1/2)
Chapter 4 Interrupt/Exception Processing Function Figure 4-8: Example of Interrupt Nesting Service (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the priority of (level 3) (level 2) b is higher than that of a and interrupts are enabled.
Page 109 Chapter 4 Interrupt/Exception Processing Function Figure 4-8: Example of Interrupt Nesting Process (2/2) Main routine Servicing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is kept pending because its Interrupt request k priority is lower than that of i.
Page 110: Figure 4-9: Example Of Servicing Interrupt Requests Simultaneously Generated
Chapter 4 Interrupt/Exception Processing Function Figure 4-9: Example of Servicing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request b and c are Servicing of interrupt request b Interrupt request c (level 1) acknowledged first according to their priorities.
Page 111: Interrupt Control Register (Xxnic)
Chapter 4 Interrupt/Exception Processing Function 4.3.4 Interrupt control register (xxnIC) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units. Caution: Write access to xxnIC registers may cause spurious interrupt to be generated.
Page 112: Interrupt Mask Registers (Imrn)
Chapter 4 Interrupt/Exception Processing Function 4.3.5 Interrupt Mask Registers (IMRn) In addition to the individual bitwise manipulation capability offered by the xxnMK bits, VENUS allows the manipulation of the interrupt masks with the Interrupt Mask Registers IMRn (n = 0 to 2).
Page 113: Figure 4-12: Interrupt Mask Register Format Imr1
Chapter 4 Interrupt/Exception Processing Function Figure 4-12: Interrupt Mask Register Format IMR1 (a) When using 16-bit access to IMR1, use IMR1 After Address reset IMR1 ST1MK SR1MK SRE1MK ST0MK SR0MK SRE0MK CSI1MK CSI0MK FFFF F102H FFFFH CT01MK CT00MK CR0MK CE0MK KRMK P8MK P7MK...
Page 114: Figure 4-13: Interrupt Mask Register Format Imr2
Chapter 4 Interrupt/Exception Processing Function Figure 4-13: Interrupt Mask Register Format IMR2 (a) When using 16-bit access to IMR2, use IMR2 After Address reset IMR2 FFFF F104H FFFFH WTMK WTIMK TM52MK TM51MK TM50MK CCC01MK CCC00MK COVF0MK (b) When using 8-bit access, use IMR2L for the LSB byte. After Address reset...
Page 115: In-Service Priority Register (Ispr)
Chapter 4 Interrupt/Exception Processing Function 4.3.6 In-service priority register (ISPR) This register holds the priority levels of the maskable interrupts currently acknowledged. When an inter- rupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the end of the interrupt service.
Page 116: Global Interrupt Mask: Id (Interrupt Disable)
Chapter 4 Interrupt/Exception Processing Function 4.3.7 Global interrupt mask: ID (Interrupt Disable) The global interrupt mask (ID) of the PSW controls the enabling and disabling of maskable interrupt requests. As a status flag, it also displays the current maskable interrupt acknowledgment condition. Figure 4-15: Interrupt Disable Flag (ID) After Symbol...
Page 117: Edge Detection Function
Chapter 4 Interrupt/Exception Processing Function 4.3.8 Edge detection function Valid edges of the INTP0 to INTP8 pins can be selected for each pin from the falling, rising, or both edges. Valid edge of the NMI pins can be selected from the falling or rising edge. The choice between rising and falling edge is controlled by the INTMn register (n = 0 to 2).
Page 118: Software Exception
Chapter 4 Interrupt/Exception Processing Function 4.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and is always accepted. • TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Family User’s Manual Architecture. 4.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine:...
Page 119: Restore
Chapter 4 Interrupt/Exception Processing Function 4.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 120: Ep Flag
Chapter 4 Interrupt/Exception Processing Function 4.4.3 EP flag The EP flag in PSW is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs, and the interrupt is disabled. Figure 4-21: EP Flag (EP) After Symbol Reset...
Page 121: Exception Trap
4.5 Exception Trap The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V850ES/GB1 Venus, an illegal op code exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap. • Illegal op code exception: occurs if the sub op code field of an instruction to be executed next is not a valid op code.
Page 122: Operation
Chapter 4 Interrupt/Exception Processing Function 4.5.2 Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the han- dler routine: Saves the current PC to EIPC. Saves the current PSW to EIPSW. Writes an exception code (0060H) to the lower 16 bits (EICC) of ECR. Sets the EP and ID bits of PSW.
Page 123: Restore
Chapter 4 Interrupt/Exception Processing Function 4.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers con- trol to the address of the restored PC.
Page 124: Priority Control
Chapter 4 Interrupt/Exception Processing Function 4.6 Priority Control 4.6.1 Priorities of interrupts and exceptions Table 4-2: Priorities of Interrupts and Exceptions RESET TRAP ILGOP ∗ ∗ ∗ ∗ RESET × ← ← ← × ↑ ← ← × ↑ ↑ ←...
Page 125: Multiple Interrupt Processing
Chapter 4 Interrupt/Exception Processing Function 4.6.2 Multiple interrupt processing Multiple interrupt servicing is a function that allows the nesting of interrupts. If a higher priority interrupt is generated and acknowledged, it will be allowed to stop a current interrupt service routine in progress. Execution of the original routine will resume once the higher priority interrupt routine is completed.
Page 126 Chapter 4 Interrupt/Exception Processing Function To generate exception in service program Service program of maskable interrupt or exception • Saves EIPC to memory or register • Saves EIPSW to memory or register • EI instruction (enables interrupt acknowledge- ment) ← Acknowledges exception such as TRAP instruction.
Page 127: Interrupt Response Time
Chapter 4 Interrupt/Exception Processing Function 4.7 Interrupt Response Time Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive interrupt requests, at least 4 clocks must be placed between each interrupt. •...
Page 128: Periods In Which Interrupts Are Not Acknowledged By Cpu
Chapter 4 Interrupt/Exception Processing Function 4.8 Periods in which Interrupts are Not Acknowledged by CPU An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between interrupt non-sample instruction and next instruction. Interrupt request non-sample instruction •...
Page 129: Key Interrupt Function
Chapter 4 Interrupt/Exception Processing Function 4.9 Key Interrupt Function Key interrupt can be generated by inputting a falling edge to key input pins (KR0 to KR7) by means of setting the key return mode register (KRM). The key return mode register (KRM) is an 8-bit register. The KRMn bit controls the KRN signals in 1-bit units (arbitrary setting from 0 to 8 bits is possible).
Page 130: Figure 4-27: Key Return Block Diagram
Chapter 4 Interrupt/Exception Processing Function Figure 4-27: Key Return Block Diagram P40/KR0 P41/KR1/TIG00 P42/KR2/TIG01/TOG01 P43/KR3/TIG02/TOG02 INTKR P44/KR4/TIG03/TOG03 P45/KR5/TIG04/TOG04 P46/KR6/TIG05 P47/KR7 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) User’s Manual U15872EE2V1UM00...
Page 131: Clock Generator
The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and the peripheral hardware. V850ES/GB1 VENUS has a dual system clock oscillator and is provided with two operating modes for reduced power consumption: •...
Page 132: Main System Clock Oscillator
Chapter 5 Clock Generator 5.2 Main System Clock Oscillator The main system clock oscillator oscillates with a crystal or ceramic resonator connected to the X1 and X2 pins. A maximum 16 MHz system clock can be generated by connecting a 16 MHz crystal resonator or ceramic resonator to the X1 and X2 pins.
Page 133: Subsystem Clock Oscillator
Chapter 5 Clock Generator 5.3 Subsystem Clock Oscillator Depending of the version (see Table 1-1: “Product Versions” on page 22), either a RC Sub clock oscillator either a crystal resonator can be connected to the sub clock oscillator for very low frequency operation.
Page 134: Control Registers
Chapter 5 Clock Generator 5.4 Control Registers Venus clock generator has the following control registers: • PCC (processor clock control register) • PSC (power save mode control register) • PSMR (Power save mode register) PCC and PSC are special registers that can only be written using a specific sequence of instruction.
Page 135 Chapter 5 Clock Generator Figure 5-5: Processor Clock Control Register Format (2/2) CPU clock (f ) status / flag CPU operates with main system clock CPU operates with sub system clock Remark: The CLS bit is a Read Only bit. Selection of CPU clock (f OSTS clock source used as clock source for...
Page 136: Psmr - Power Save Mode Register
Chapter 5 Clock Generator 5.4.2 PSMR - Power save mode register This is a 8-bit register to specify power save mode. Read/Write is possible by 8-bit or 1-bit memory operation instructions. All contents are set to “00H” by RESET input and bit 1 to 6 is fixed to 0 by hardware.
Page 137: Psc - Power Save Control Register
Chapter 5 Clock Generator 5.4.3 PSC - Power save control register This register controls power save mode. This register is a special register: any write access can only be done just after a dummy write to PRCMD register (see Chapter 3.4.7 “Special registers” on page 70). Read access to PSC are possible without any write access to PRCMD.
Page 138: Osts: Oscillation Stabilization Register
Chapter 5 Clock Generator 5.4.4 OSTS: Oscillation stabilization register This register controls the oscillation stabilization time after RESET, WATCH and STOP mode release. The input frequency f of the OSTS is either f or f depending of CK3 bit of PCC register. Figure 5-8: Oscillation Stabilization Register Format Address After RESET...
Page 139: Processor Clock Output
Chapter 5 Clock Generator 5.4.5 Processor clock output It is possible to output the CPU Clock on pin CLKOUT. The processor clock output frequency is equal to the selected CPU frequency f . Corresponding ports registers have to be set accordingly: PMCCM1 bit of PMCCM must be set to 1.
Page 140: System Operating Modes
Chapter 5 Clock Generator 5.5 System Operating Modes Venus can operate in the following modes: • Main clock operation • Sub clock operation mode • Main / Sub HALT mode • Main / Sub WATCH mode • STOP mode Figure 5-9: System Operating and Standby Modes Block Diagram...
Page 141: Main Clock Operation Mode
Chapter 5 Clock Generator 5.5.1 Main clock operation mode In this mode, main clock oscillator supplies the CPU. CPU frequency is selected through CK2-CK0 bits of PCC register. Available clock frequencies are f /2, f /4, f /8, f /16 and f /32.
Page 142: Examples Of Clock Switching
Chapter 5 Clock Generator 5.5.3 Examples of clock switching Setting example for switch from main clock operation to sub clock operation Verify that f > f × 4 by reading CKn bits. If the above condition is not Frequency Verification met, please change CK2, CK1, CK0 to meet the conditions.
Page 143: Halt Mode
Chapter 5 Clock Generator 5.5.4 HALT mode In this mode, the supply of the operating clock to the CPU is stopped, and other on-chip peripheral func- tions continue to operate. Combining this mode with the normal operating mode to provide intermittent operations enables the overall system power consumption to be reduced.
Page 144: Table 5-2: Operation After Releasing Halt Mode By Interrupt Request
Chapter 5 Clock Generator HALT mode release The HALT mode is released by an unmasked maskable interrupt request, a NMI request, RESET signal input or Watchdog timer reset. (a) Release by interrupt or NMI request The HALT mode is released unconditionally by an •...
Page 145: Watch Mode
Chapter 5 Clock Generator 5.5.5 WATCH mode In this mode, the sub clock oscillator and the main clock oscillator continue to operate. The main clock is no more supplied to the CPU, but the watchdog timer and the watch timer continue to operate.
Page 146: Table 5-3: Operating Status In Watch Mode
Chapter 5 Clock Generator Table 5-3: Operating Status in WATCH Mode Entering WATCH mode from Sub operating mode Items Main Main running Main stopped operating mode (MCK = 0) (MCK = 1) Stopped Main oscillator Operates Operates Stopped Sub clock oscillator Operates UART6n Stopped...
Page 147: Table 5-4: Operation After Releasing Watch Mode By Interrupt Request
When Sub clock is used as CPU clock, then minimum OSTS time must be set at 4 clock cycles minimum at WATCH mode release. Caution: When selecting OSTS time, customer has to refer to the Venus Electrical Specifica- tion document to check what are the minimum wake up time from WATCH mode and STOP mode release.
Page 148 Chapter 5 Clock Generator (b) Release by Watchdog timer reset The device operation is the same as normal reset operation. (c) Release by RESET pin The device operation is the same as normal reset operation. User’s Manual U15872EE2V1UM00...
Page 149: Stop Mode
Retains all internal data before entering STOP mode, such Internal data as CPU registers, status, data, and on-chip RAM. Caution: Please refer to the VENUS Electrical Specification Document for minimum wake up time after STOP mode release. User’s Manual U15872EE2V1UM00...
Page 150: Table 5-6: Operation After Releasing Stop Mode By Interrupt Request
Chapter 5 Clock Generator STOP mode release The STOP mode can be released by a non-maskable interrupts request, an unmasked maskable interrupt request, Watchdog timer reset or RESET signal input. (a) Release by interrupt or NMI The STOP mode is released unconditionally by •...
Page 151 Chapter 5 Clock Generator (b) Release by Watchdog timer reset The device operation is the same as normal reset operation. (c) Release by RESET pin The device operation is the same as normal reset operation. User’s Manual U15872EE2V1UM00...
Page 152: Securing Oscillation Stabilization Time
Chapter 5 Clock Generator 5.5.7 Securing Oscillation Stabilization Time When the STOP or WATCH mode is released, the time set by the oscillation stabilization time selection register (OSTS) elapses before execution of the first instruction. After a power-up reset, or if the STOP or WATCH mode has been released by RESET pin input, the time is given by the reset value of the OSTS register: 2 (8.192 ms at f = 16 MHz).
Page 153: Timers
Chapter 6 Timers 6.1 16-bit Timer G0 (TMG0) 6.1.1 Features (Timer G0) The 6-channel 16-bit multi purpose Timer G0 operates as • Pulse interval and frequency measurement counter • event counter • Interval timer • Programmable pulse output • PWM output timer Remark: In this Timer G0 chapter following indexes were consequently used •...
Page 154: Function Overview (Timer G0)
Chapter 6 Timers 6.1.2 Function overview (Timer G0) • 16-bit timer/counter: 2 channels (TMG00, TMG01) • Capture/compare register: 6 - 16-bit - 1 register is assigned to each counter - 4 registers are freely assignable to one of the 2 counters •...
Page 155: Figure 6-1: Block Diagram Of Timer G0
Chapter 6 Timers Figure 6-1: Block Diagram of Timer G0 INTTMG00 1/16 COUNT0 TMG00 (16-bit) 1/32 Clear 1/64 1/128 INTGCC00 1/256 Noise Elimination GCC00 (16-bit) TIG00 Edge Detection capture/compare INTGCC01 TOG01 Noise Elimination GCC01 (16-bit) TIG01 Edge Detection capture/compare INTGCC02 DCAN SOFOUT RXD60 TOG02...
Page 156: Basic Configuration
Chapter 6 Timers 6.1.3 Basic configuration The basic configuration is shown below. Table 6-1: Timer G0 Configuration List Generated Capture Timer Output Timer Count Clock Register Interrupt Signal Trigger TMG00 INTTMG00 TMG01 INTTMG01 GCC00 INTGCC00 TIG00 GCC01 INTGCC01 TIG01 TOG01 /16, Timer G0 /32,...
Page 157: Figure 6-4: Capture/Compare Register Gcc00
Chapter 6 Timers GCC00 and GCC05: capture/compare registers with fixed counter assignment The GCC00 (GCC05) register is a 16-bit capture/compare register of Timer G0. This register is assigned to the counter register TMG00 (TMG01). In the capture mode, GCC00 (GCC05) captures the TMG00 (TMG01) count value if an edge is detected at pin TIG00 (TIG05).
Page 158: Figure 6-6: Capture/Compare Registers Gcc0M (M = 1 To 4)
Chapter 6 Timers GCC01 to GCC04: capture/compare registers with free counter assignment and with PWM output capability The GCC01 to GCC04 registers are 16-bit capture/compare registers of Timer G0. They can be assigned to one of the 2 counters TMG00 or TMG01. In the capture mode, these registers capture the value of TMG00 when the TBG0m-bit (m = 1 to 4) of the TMGCM0H register = 0.
Page 159: Control Registers
Chapter 6 Timers 6.1.4 Control Registers Timer G0 Mode Register High (TMGM0H) This register can be read/written in 8- or 1-bit units. Figure 6-7: Timer G0 Mode Register High (TMGM0H) Initial Address value TMGM0H POWERG0 OLDE0 CSE012 CSE011 CSE010 CSE002 CSE001 CSE000 FFFFF661H 00H Bit Position Bit Name Function...
Page 160: Figure 6-8: Timer G0 Mode Register Low (Tmgm0L)
Chapter 6 Timers Timer G0 Mode Register Low (TMGM0L) This register can be read/written in 8- or 1-bit units. Figure 6-8: Timer G0 Mode Register Low (TMGM0L) Initial Address value TMGM0L CCSG05 CCSG00 CLRG01 TMG01E CLRG00 TMG00E FFFF F660H 00H Bit Name Function Position...
Page 161: Figure 6-9: Timer G0 Channel Mode Register (Tmgcm0H, Tmgcm0L)
Chapter 6 Timers Timer G0 Channel Mode Register High and Low (TMGCM0H, TMGCM0L) This register specifies the assigned counter (TMG00 or TMG01) for the capture/compare registers GCC0m (m = 1 to 4). Furthermore it specifies the edge detection for the TIG0n input pins (n = 0 to 5).
Page 162: Figure 6-10: Timer G0 Output Control Register (Octlg0H, Octlg0L)
Chapter 6 Timers Timer G0 output control register (OCTLG0H/OCTLG0L) This register controls the timer outputs from the TOG0m pins (m = 1 to 4) and the capture or com- pare modes for the free assignable GCC0m registers. This register can be read/written in 8- or 1-bit units. Figure 6-10: Timer G0 Output Control Register (OCTLG0H, OCTLG0L) Initial Address...
Page 163: Figure 6-11: Timer G0 Status Register (Tmgst0)
Chapter 6 Timers Time base status register (TMGST0) The TMGST0 register indicates the status of TMG00 and TMG01. This register can be read in 8- or 1-bit units. Figure 6-11: Timer G0 Status Register (TMGST0) Initial Address value TMGST0 ENFG01 ENF00 CCFG05 CCFG04 CCFG03 CCFG02 CCFG01 CCFG00 FFFF F666H 00H Bit Position Bit Name...
Page 164: Output Delay Operation
Chapter 6 Timers 6.1.5 Output delay operation When the OLDE0 bit is set, different delays of count clock period are added to the TOG0m-pins: delay Output-pin (count clock periods) TOG01 TOG02 TOG03 TOG04 The figure below shows the timing for the case where the count clock is set to f /2, and 0FFFH is set to GCC00.
Page 165: Explanation Of Basic Operation
Chapter 6 Timers 6.1.6 Explanation of Basic Operation Overview of the mode settings The Timer G0 includes 2 channels of 16-bit counters (TMG00/TMG01), which can operate as independently timebases. TMG00 (TMG01) can be set by CCSG00 (CCSG05) in the - free running mode or the - match and clear mode.
Page 166: Operation In Free Running Mode
Chapter 6 Timers 6.1.7 Operation in free running mode This operation mode is the standard mode for Timer G0 operations. In this mode the 2 counters TMG00 and TMG01 are counting up from 0x0000 to 0xFFFF, generate an overflow and continue counting. (For a description of the match and clear mode, see section 6.1.8) Capture operation (free running) Basic settings (m = 1 to 4):...
Page 167: Figure 6-13: Timing When Both Edges Of Tig00 Are Valid (Free Running)
Chapter 6 Timers Using CCFG0n: CCFG0n is updated when GCC0n is read. So the value of CCFG0n should be read after GCC0n is read. So, when GCC0n is used as capture register, the procedure below should be used: <1> After INTCCG0n (edge detection interrupt) generation, read first the corresponding GCC0n regis- ter.
Page 168: Figure 6-14: Timing Of Capture Trigger Edge Detection (Free Running)
Chapter 6 Timers (b) Timing of capture trigger edge detection The TIG0n inputs are fitted with an edge-detection and a noise-elimination circuit. Because of this circuit, 3 periods to less than 4 periods of the count clock are required from selected edge input until an interrupt signal is generated and capture operation is performed.
Page 169: Figure 6-15: Timing Of Starting Capture Trigger Edge Detection
Chapter 6 Timers (c) Timing of starting capture trigger edge detection A capture trigger input signal (TIG0n) is synchronized in the noise eliminator for internal use. Edge detection starts when 1 count clock period (1/f ) has been input after timer count COUNTn operation starts.
Page 170: Figure 6-16: Timing Of Compare Mode (Free Running)
Chapter 6 Timers Compare operation (free running) Basic settings (m = 1 to 4): Value Remark CCSG00 free running mode CCSG05 SWFG0m disable TOG0m Compare mode CCSG0m for GCC0m assign counter for GCC0m TBG0m 0: TMG00 1: TMG01 Example: Interval timer (free running) Setting method interval timer: Select one of GCC01 to GCC04 compare register, and assign the corresponding counter with the TBG0m bit in the TMGCM0H register...
Page 171: Figure 6-17: Timing When Gcc01 Is Rewritten During Operation (Free Running)
Chapter 6 Timers (a) When the value 0000H is set in GCC0m INTCCG0m is generated when the value of the counter becomes 0001H. INTTMG00/INTTMG01 is generated when the value of the counter changes from FFFFH to 0000H. Note, however, that even if no data is set in GCC0m, INTCCG0m is generated immediately after the counter starts (GCC0m holds 0 after reset).
Page 172 Chapter 6 Timers PWM output (free running) Basic settings (m = 1 to 4): Value Remark CCSG00 free running mode CCSG05 SWFG0m enable TOG0m compare mode CCSG0m for GCC0m assign counter for GCC0m TBG0m 0: TMG00 1: TMG01 PWM setting method: Select one of GCC01 to GCC04 compare register, and assign the corresponding counter with the TBG0m bit in the TMGCM0H register Select a count clock in the TMGM0H register,...
Page 173: Figure 6-18: Timing Of Pwm Operation (Free Running)
Chapter 6 Timers PWM operation: When the value of the counter matches the value of GCC0m, • TOG0m is deactivated • a match interrupt (INTCCG0m) is generated. • The counter is not cleared, but continues count-up operation. When the counter overflows, •...
Page 174: Figure 6-19: Timing When 0000H Is Set In Gcc0M (Free Running)
Chapter 6 Timers (a) When 0000H is set in GCC0m (m = 1 to 4) When 0000H is set in GCC0m, TOG0m is tied to the inactive level. The figure below shows the state of TOG01 when 0000H is set in GCC01, and TMG00 is selected. Figure 6-19: Timing when 0000H is set in GCC0m (free running) ENFG0 FFFFH...
Page 175: Figure 6-20: Timing When Ffffh Is Set In Gcc0M (Free Running)
Chapter 6 Timers (b) When FFFFH is set in GCC0m (m = 1 to 4) When FFFFH is set in GCC0m, TOG0m outputs the inactive level for one clock period immediately after counter overflow (except the first overflow). The figure below shows the state of TOG01 when FFFFH is set in GCC01, and TMG00 is selected.
Page 176: Figure 6-21: Timing When Gcc0M Is Rewritten During Operation (Free Running)
Chapter 6 Timers (c) When GCC0m is rewritten during operation (m = 1 to 4) The new comparison value is effective when the next counter overflow (following the write opera- tion in the GCC0m register) occurs. The figure below shows a case where GCC01 is rewritten from 5555H to AAAAH during counting. (TMG00 is selected for GCC01).
Page 177: Operation In Match And Clear Mode
Chapter 6 Timers 6.1.8 Operation in Match and clear mode The match and clear mode is mainly used to reduce the full scale of the counters (TMG00, TMG01). Therefore the value of the fixed assigned register GCC00 (GCC05) is used for comparison with the counter value TMG00 (TMG01).
Page 178: Figure 6-22: Timing When Both Edges Of Tig0M Are Valid (Match And Clear)
Chapter 6 Timers (a) Example: Capture where both edges of TIG0m are valid (match and clear) For the timing chart TMG00 is selected as the counter corresponding to TIG01, and 0FFFH is set in GCC00. Figure 6-22: Timing when both edges of TIG0m are valid (match and clear) Count-up signal 0000H 0001H...
Page 179 Chapter 6 Timers Compare operation (match and clear) Basic settings (m = 1 to 4): Value Remark CCSG00 match and clear mode CCSG05 SWFG0m disable TOG0m Compare mode CCSG0m for GCC0m assign counter for GCC0m TBG0m 0: TMG00 1: TMG01 (a) Example: Interval timer (match and clear) Setting Method An usable compare register is one of GCC01 to GCC04, and the corresponding counter must be...
Page 180: Figure 6-23: Timing Of Compare Operation (Match And Clear)
Chapter 6 Timers Figure 6-23: Timing of compare operation (match and clear) ENFG0 0FFFH 0FFFH 0FFFH Match TMG00 GCC01 INTGCC01 INTGCC00 In this example, TMG00 is selected, 0FFFH is set in GCC00. The value N is set in GCC01, with N < 0FFFH. (b) When 0000H is set in GCC00 or GCC05 (match and clear) When 0000H is set in GCC00 (GCC05), the value of the counter TMG00 (TMG05) is fixed at 0000H, and the counter does not operate.
Page 181: Figure 6-24: Timing When Gcc0M Is Rewritten During Operation (Match And Clear)
Chapter 6 Timers (f) When GCC0m (m = 1 to 4) is rewritten during operation (match and clear) When the value of GCC01 is changed from 0555H to 0AAAH, the operation described below is performed. TMG00 is selected as the counter. Figure 6-24: Timing when GCC0m is rewritten during operation (match and clear) Count ENFG0...
Page 182 Chapter 6 Timers PMW output (match and clear) Basic settings (m = 1 to 4): Value Remark CCSG00 match and clear mode CCSG05 SWFG0m enable TOG0m Compare mode CCSG0m for GCC0m assign counter for GCC0m TBG0m 0: TMG00 1: TMG01 Setting Method: Select one of GCC01 to GCC04 compare register, and assign the corresponding counter with the TBG0m bit in the TMGCM0H register...
Page 183: Figure 6-25: Timing Of Pwm Operation (Match And Clear)
Chapter 6 Timers In the following example, the counter TMG00 is assigned to GCC01, 0FFFH is set in GCC00 and the value N is set to GCC01, with N < 0FFFH. Figure 6-25: Timing of PWM operation (match and clear) ENFG0 0FFFH 0FFFH...
Page 184: Figure 6-26: Timing When 0000H Is Set In Gcc0M (Match And Clear)
Chapter 6 Timers (c) When 0000H is set in GCC0m (match and clear) When 0000H is set in GCC0m, TOG0m is tied to the inactive level. The figure below shows the state of TOG01 when TMG00 is assigned to GCC01, 0000H is set in GCC01, and 0FFFH is set in GCC00.
Page 185: Figure 6-27: Timing When The Same Value As Set In Gcc00/Gcc05 Is Set In Gcc0M (Match And Clear)
Chapter 6 Timers (d) When the same value as set in GCC00 or GCC05 is set in GCC0m (match and clear) When the same value as set in GCC00 (GCC05) is set in GCC0m, TOG0m outputs the inactive level for only one clock period immediately after each match and clear event (excluding the first match and clear event).
Page 186: Figure 6-28: Timing When The Value Of Gcc0M Exceeding Gcc00 Or Gcc05 (Match And Clear)
Chapter 6 Timers (e) When a value exceeding the value set in GCC00 or GCC05 is set in GCC0m (match and clear) When a value exceeding the value set in GCC00 (GCC05) is set in GCC0m, TOG0m starts and continues output of the active level immediately after the first match and clear event (until count operation stops.) The figure shows the state of TOG01 when TMG00 is selected, 0FFFH is set in GCC00, and 1FFFH is set in GCC01.
Page 187: Figure 6-29: Timing When Gcc0M Is Rewritten During Operation (Match And Clear)
Chapter 6 Timers (f) When GCC0m is rewritten during operation (match and clear) When GCC01 is rewritten from 0555H to 0AAAH, the operation shown below is performed. The figure below shows a case where 0FFFH is set in GCC00, and TMG00 is selected for GCC01. Figure 6-29: Timing when GCC0m is rewritten during operation (match and clear) ENFG0 0FFFH...
Page 188: Edge Noise Elimination
Chapter 6 Timers 6.1.9 Edge noise elimination The edge detection circuit has a noise elimination function. This function regards: • a pulse not wider than one count clock period as a noise, and does not detect it as an edge. •...
Page 189: Precautions Timer G0
Chapter 6 Timers 6.1.10 Precautions Timer G0 When POWERG0 bit of TMGM0H register is set The rewriting of the CSE0x2 to CSE0x0 bits (x = 0, 1) of the TMGM0H register is prohibited. These bits set the prescaler for the Timer G0 counter TMG00 or TMG01. The rewriting of the CCSG0n bits (n = 0 to 5) if the OCTLG0H register is prohibited.
Page 190 Chapter 6 Timers Timing The delay of each timer output TOG0m (m = 1 to 4) varies according to the setting of the count clock with the CSE0x2 to CSE0x0 bits (x = 0, 1). In capture operation 3 to 4 periods of the count clock (f ) signal are required from the TIG0n COUNT pin (n = 0 to 5) until a capture interrupt is generated.
Page 191: 16-Bit Timer C (Tmc0)
Chapter 6 Timers 6.2 16-bit Timer C (TMC0) 6.2.1 Features (Timer C0) One channel of Timer C0 is implemented. Timer C0 (TMC0) is a 16-bit timer/counter that can perform the following operations. • 2 capture/compare registers • Programmable pulse generator function •...
Page 192: Function Overview (Timer C0)
Chapter 6 Timers 6.2.2 Function overview (Timer C0) • 16-bit timer/counter (TMC0): 1 channel • Capture/compare registers: 2 • Count clock division selectable by prescaler (maximum frequency of count clock: 8 MHz) • Prescaler divide ratio from /256 • Interrupt request sources - Capture/compare match interrupt requests: 2 sources In case of capture register: - INTCCC00 generated by TIC00 input...
Page 193: Figure 6-31: Block Diagram Of Timer C0
Chapter 6 Timers Figure 6-31: Block Diagram of Timer C0 Clear & start 1/16 COUNT 16-bit Counter INTCOVF0 1/32 1/64 1/128 1/256 DCAN SOFOUT RXD60 ITC00 Noise Elimination TIC00 Edge Detection CCC00 TOC0 CCC01 RXD61 ITC01 Noise Elimination TIC01 INTCCC00 Edge Detection INTCCC01 Notes: 1.
Page 194: Basic Configuration
Chapter 6 Timers 6.2.3 Basic configuration Table 6-2: Timer C0 Configuration List Read/ Generated Capture Timer Output Timer Count Clock Register Write Interrupt Signal Trigger Set / Reset TMC0 Read INTCOVF0 Read/ CCC00 INTCCC00 INTCCC00 TOC0 Set Timer C0 write /32, /64, Read/...
Page 195 Chapter 6 Timers Selection of the count clock TMC0 operates as a free running timer. The internal clock prescaler can be specified with the CS2, CS1 and CS0 bits of the Timer C0 con- trol register 0 (TMCC00), and one of the following count clocks can be selected: /2, f /4, f /8, f...
Page 196: Figure 6-33: Capture/Compare Registers Of Tmc0 (Ccc0N) (N = 0, 1)
Chapter 6 Timers Capture/compare registers (CCC00 and CCC01) These capture/compare registers are 16-bit registers. They can be used as capture registers or compare registers according to the CMS1 and CMS0 bit specifications of Timer C0 control register 1 (TMCC01). These registers can be read/written in 16-bit units (However, write operations can only be per- formed in compare mode).
Page 197 Chapter 6 Timers (a) Setting CCC0n registers to capture registers (CMS1 and CMS0 of TMCC01 = 0) When these registers are set to capture registers, the valid edges of the corresponding external interrupt signals TIC0n (n = 0,1) are detected as capture triggers. The timer TMC0 is synchronized with the capture trigger, and the value of TMC0 is latched in the CCC00 or CCC01 registers (cap- ture operation).
Page 198: Control Registers
Chapter 6 Timers 6.2.4 Control registers Timer C0 control register 0 TMCC00 The TMCC0n register controls the operation of TMC0. These registers can be read/written in 8- or 1-bit units. Cautions: 1. The CAE bit and TMCCCE0 bit cannot be set at the same time. Be sure to set the CAE bit prior to setting the TMCCCE0 bit.
Page 199 Chapter 6 Timers Figure 6-34: Timer C0 control Register 0 TMCC00 (2/2) Count Clock Resolution Max. counting PWM frame (KHz) (µs) time (ms) frequency (Hz) /2 (8000) 0.125 8.192 122.07 /4 (4000) 0.250 16.384 61.03 /8 (2000) 32.768 30.51 /16 (1000) 65.536 15.25 /32 (500)
Page 200: Figure 6-35: Timer C0 Control Register 1 Tmcc01 (1/2)
Chapter 6 Timers Timer C0 control register 1 TMCC01 The TMCC01 register controls the operation of TMC0. This register can be read/written in 8- or 1-bit units. Figure 6-35: Timer C0 control Register 1 TMCC01 (1/2) Initial Address value TMCC01 ENTO CCLR CMS1...
Page 201 Chapter 6 Timers Figure 6-35: Timer C0 control Register 1 TMCC01 (2/2) Bit Position Bit name Function Selects operation mode of capture/compare register CCC01. CMS1 0: Register operates as capture register. 1: Register operates as compare register. Selects operation mode of capture/compare register CCC00. CMS0 0: Register operates as capture register.
Page 202: Figure 6-36: Valid Edge Selection Register Sesc0
Chapter 6 Timers Valid edge selection register (SESC0) This register specifies the valid edge of external interrupt requests from an external TIC0n pin (n = 0 to 1). The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin.
Page 203: Operation
Chapter 6 Timers 6.2.5 Operation Count operation Timer C0 can function as a 16-bit free running timer. When it operates as a free running timer and the CCC0n register and the TMC count value match, an interrupt signal is generated and the timer output signal (TOC0) can be set or reset. Also, a capture operation that holds the TMC0 count value in the CCC0n register is performed, synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger.
Page 204: Figure 6-38: Timing Of Interrupt Operation After Overflow
Chapter 6 Timers Overflow After the TMC0 register has counted the count clock from 0000H to FFFFH, the next count clock causes the OVF bit of the TMCC00 register to be set to "1", and an overflow interrupt (INTCOVF0) to be generated at the same time. However, if the CCC00 register is set to compare mode (CMS0 = 1) and to the value FFFFH, when match clearing is enabled (CCLR = 1) the TMC0 counter register is considered to be cleared and the OVF bit is not set to "1"...
Page 205: Figure 6-39: Timing Of Capture For Pulse Cycle Measurement (Rising Edge)
Chapter 6 Timers Capture operation The TMC0 register has two capture/compare registers. These are the CCC00 and CCC01 regis- ters. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMCC01 register. If the CMS1 and CMS0 bits of the TMCC01 register are set to "0", the registers operate as capture registers.
Page 206: Figure 6-40: Timing Of Capture For Pulse Width Measurement (Both Edges)
Chapter 6 Timers (b) Example: capture for pulse cycle measurement If both the rising and falling edges are set as capture triggers, the input pulse width from an exter- nal source can be measured. Figure 6-40: Timing of capture for pulse width measurement (both edges) (TMC0 count values) TMC0 Count start...
Page 207 Chapter 6 Timers (c) Example: Cycle measurement By setting the TMCC00 and TMCC01 registers as described below TMC0 can measure the cycle of signals input to the TIC00 pin. The valid edge of the TIC00 pin is selected according to the IES01 and IES00 bits of the SESC0 register.
Page 208: Figure 6-41: Timing Of Cycle Measurement Operation
Chapter 6 Timers Calculation: The cycle of signals input to the TIC0n pin is calculated by obtaining the difference between the TMC0 register’s count value (Dx) that was captured in the CCC0n register according to the x-th valid edge input of the TIC0n pin and the TMC0 register’s count value (D(x+1)) that was captured in the CCC0n register according to the (x+1)-th valid edge input of the TIC0n pin and multiplying the value of this difference by the cycle of the clock control signal.
Page 209: Figure 6-42: Timing Of Compare Operation
Chapter 6 Timers Compare operation The TMC0 register has two capture/compare registers. These are the CCC00 and CCC01 regis- ters. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMCC01 register: If "1" is set in the CMS1 and CMS0 bits of the TMCC01 register, the registers operate as compare registers.
Page 210: Figure 6-43: Timing Of Interval Timer Operation
Chapter 6 Timers (a) When CCC0n register is set to 0000H If the CCC0n register is set to 0000H, the 0000H after the TMC0 register counts up from FFFFH to 0000H is judged as a match. The 0000H when the TMC0 register begins counting is not judged as a match.
Page 211: Figure 6-44: Timing Of Pwm Output Operation (Overview)
Chapter 6 Timers PWM output Timer C0 has one timer output pin (TOC0). An external pulse output (TOC0) can be generated when a match of the two compare registers (CCC00 and CCC01) and the TMC0 register is detected. If a match is detected when the TMC0 count value and the CCC00 value are compared, the output level of the TOC0 pin is set.
Page 212: Figure 6-45: Timing Example Of Pwm Output Operation (Detail)
Chapter 6 Timers (a) Example PWM output By setting the TMCC00 and TMCC01 registers as described below TMC0 can output a PWM sig- nal of an arbitrary frequency with the values that were set in advance in the CCC00 and CCC01 registers determining the intervals.
Page 213: Precautions Timer C0
Chapter 6 Timers 6.2.6 Precautions Timer C0 Various precautions concerning Timer C0 are shown below. If a conflict occurs between the reading of the CCC0n register and a capture operation when the CCC0n register is used in capture mode, an external trigger valid edge is detected and an external interrupt request signal (INTCCC0n) is generated however, timer value is not stored in the CCC0n register.
Page 214: Timer Input Select
Chapter 6 Timers 6.3 Timer Input Select 6.3.1 UART6N and DCAN Connection to Timer Inputs Timer input select allow to connect RXD60 & RXD61 pins and SOFOUT signal from DCAN to Timer G0 or Timer C0. Connection is controlled by TIS register. Figure 6-46: Timer Input Select Block Diagram Noise Elimination TIC00...
Page 215: Timer Input Select Control Register
Chapter 6 Timers 6.3.2 Timer input select control register Figure 6-47: Timer Input Select Control Register Format Address After reset TISD1 TISD0 TISC1 TISC0 TISB1 TISB0 TISA1 TISA0 FFFF F6F0H TISD1 TISD0 Connection to ITIG03 Input from TIG03 Input from RXD61 Reserved.
Page 216: 8-Bit Timer 50, Timer 51, Timer 52
Chapter 6 Timers 6.4 8-bit Timer 50, Timer 51, Timer 52 6.4.1 Functions • 8-bit timer Timer 5n (n = 0, 1, 2) has the following two modes: - Mode using timer alone (individual mode) - Mode using cascade connection (16-bit resolution) •...
Page 217: Figure 6-48: Block Diagram Of Timer 50, Timer 51
Chapter 6 Timers Figure 6-48: Block Diagram of Timer 50, Timer 51 Internal Bus 8-bit Compare Register (CR5n) Match INTTM5n Output Control TI5n / TO5n 8-bit Timer Circuit Register n (TM5n) Clear * Clear * : Clear signal Mode Invalid Internal Bus Valid Interwal timer...
Page 218: Figure 6-50: Timer 51 As Clock Source For Csi00
Chapter 6 Timers Furthermore the Timer 51 can be used as a clock source for the CSI00 peripheral. Therefore an inter- nal output connection is used to supply the input to the prescaler of the CSI00 prescaler. Figure 6-50: Timer 51 as clock source for CSI00 CSI00 internal TM51...
Page 219: Configuration
Chapter 6 Timers 6.4.2 Configuration Timer 5n is constructed from the following hardware. Table 6-4: Timers 5n Configuration Item Configuration 8-bit counters (TM50, TM51, TM52) Timer registers 16-bit counter: only when connecting in cascade (TM5051) 8-bit compare registers (CR50, CR51, CR52)R Registers 16-bit compare register: only when connecting in cascade (CR5051) Timer inputs...
Page 220: Figure 6-52: Tm50, Tm51 Compare Registers (Cr50, Cr51)
Chapter 6 Timers 8-bit compare registers 0, 1 and 2 (CR50, CR51, CR52) The value set in CR5n is always compared to the count in the 8-bit counter (TM5n). If the two val- ues match, an interrupt request (INTTM5n) is generated (except in the PWM mode). These are 8-bit read/write registers.
Page 221: Timer 5N Control Register
Chapter 6 Timers 6.4.3 Timer 5n control register The following two registers controls Timer 5n. - Timer clock select registers (TCL50, TCL51, TCL52) - 8-bit timer mode control register (TMC50, TMC51, TMC52) Timer 5n clock select registers (TCL50, TCL51, TCL52) These registers set the count clock of timer 5n.
Page 222: Figure 6-54: Timer 5 Clock Select Registers (Tcl52)
Chapter 6 Timers Figure 6-54: Timer 5 Clock Select Registers (TCL52) Address After reset TCL52 TCL522 TCL521 TCL520 FFFF F652H Resolution Max. Counting PWM Frame TCL522 TCL521 TCL520 Count Clock Selection (µs) Time (µs) Frequency (KHz) TI52 falling edge TI52 rising edge 0.125 31.25 3.906...
Page 223: Figure 6-55: Timer 5 Mode Control Registers (Tmc50, Tmc51) (1/2)
Chapter 6 Timers Timer 5 mode control registers (TMC50, TMC51, TMC52) The TMC5n register makes the following six settings. (1) Controls the counting by the 8-bit counter TM5n (2) Selects the operating mode of the 8-bit counter TM5n (3) Selects the individual mode or cascade connection mode (4) Sets the state of the timer output flip-flop (5) Controls the timer flip-flop or selects the active level in the PWM (free running) mode (6) Controls timer output...
Page 224 Chapter 6 Timers Figure 6-55: Timer 5 Mode Control Registers (TM50 to TM52) (2/2) Note Note Setting State of Timer Output Flip-Flop LVS5n LVR5n Not change Reset timer output flip-flop to 0 Set timer output flip-flop to 1 Setting prohibited Note: LVS5n and LVR5n are read-only bits: they are always read as 0s Free running Mode Match and Clear Mode...
Page 225: 8-Bit Timer Operation
Chapter 6 Timers 6.4.4 8-Bit Timer Operation Operating as an interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupts at the interval of the preset count in the 8-bit compare register (CR5n). If the count in the 8-bit counter TM5n matches the value set in CR5n, simultaneous to clearing the value of TM5n to 0 and continuing the count, the interrupt request signal (INTTM5n) is generated (the TM5nIF interrupt request flip-flop in the TM5nIC register is set).
Page 226 Chapter 6 Timers Figure 6-56: Timing of Interval Timer Operation (2/3) (b) When CR5n = 00H Count clock TM5n 00H CR5n TCE5n INTTM5n TO5n Interval time Remark: n = 0, 1, 2 (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n...
Page 227 Chapter 6 Timers Figure 6-56: Timing of Interval Timer Operation (3/3) (d) Operated by CR5n transition (M < N) Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n transition TM5n overflows since M < N Remark: n = 0, 1 (e) Operated by CR5n transition (M > N) Count clock M -1 TM5n...
Page 228: Figure 6-57: Timing Of External Event Counter Operation
Chapter 6 Timers Operating as external event counter The external event counter counts the number of external clock pulses that are input to TI5n. Each time a valid edge specified with the timer clock select register (TCL5n) is input, the counter TM5n increments.
Page 229: Figure 6-58: Timing Of Square Wave Output Operation Timing
Chapter 6 Timers Operating as square wave output (8-bit resolution) A square wave having any frequency is output at the interval preset in the 8-bit compare register (CR5n). By setting TOE5n bit of the 8-bit timer mode control register (TMC5n) to "1", the output state of TO5n is inverted with the count preset in CR5n as the interval.
Page 230 Chapter 6 Timers Operating as 8-bit PWM output By setting the TCE5n6 bit of the 8-bit timer mode control register (TMC5n) to "1", the timer oper- ates as a PWM output. Pulses with the duty factor determined by the value set in the 8-bit compare register (CR5n) is out- put from TO5n.
Page 231: Figure 6-59: Timing Of Pwm Output
Chapter 6 Timers Figure 6-59: Timing of PWM Output (a) Basic operation (active level = H) Count clock TM5n CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level (b) When CR5n = 0 Count clock TM5n 00H 01H CR5n TCE5n INTTM5n TO5n...
Page 232: Figure 6-60: Timing Of Operation Based On Cr5N Transitions (1/2)
Chapter 6 Timers (b) Operation based on CR5n transitions Figure 6-60: Timing of Operation Based on CR5n Transitions (1/2) (a) When the CR5n value changes from N to M before TM5n overflows Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n transition (N<M or N>M) After the next overflow M will be use for match (b) When the CR5n value changes from N to M after TM5n overflows Count clock...
Page 233 Chapter 6 Timers Figure 6-60: Timing of Operation Based on CR5n Transitions (2/2) (c) When the CR5n value changes from N to M during two clocks (00H, 01H) immediately after TM5n overflows Count clock TM5n CR5n TCE5n INTTM5n TO5n CRn0 transition (N<M or N>M) It doesn’t change anything if the value changes immediately (within 2 clocks) after the overflow or later.
Page 234: Operating As Interval Timer (16 Bits)
Chapter 6 Timers 6.4.5 Operating as interval timer (16 bits) Cascade connection (16-bit timer) mode By setting bit 4 (CMS51) of the 8-bit timer mode control register (TMC51) of Timer 51 to "1", the timers 50 and 51 enter the timer/counter mode with 16-bit resolution, with TM50 as low-order 8 bits register and TM51 as high-order 8 bits register.
Page 235: Figure 6-61: Cascade Connection Mode With 16 Bit Resolution
Chapter 6 Timers Figure 6-61: Cascade connection mode with 16 bit resolution Count clock TM50 TM51 CR50 CR51 TCE50 TCE51 INTTM50 Interval time TO5n Enable operation starting count Interrupt generation level inverted Operation Counter cleared stopped User’s Manual U15872EE2V1UM00...
Page 236: Precautions Timer 5
Chapter 6 Timers 6.4.6 Precautions Timer 5 Error when the timer starts The time until the match signal is generated after the timer starts has a maximum error of one clock. The reason is the starting of the 8-bit counter (TM5n) is asynchronous with respect to the count pulse.
Page 237 Chapter 6 Timers Timer 5n and the STOP mode Except when the TI5n input is selected, always set TCE5n = 0 before entering the STOP mode. TM5n read out during timer operation The count clock is temporarily stopped during the read operation of the TM5n (n = 0, 1, 2) register. So avoid too high frequency (regarding the count clock) read operations.
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Page 239: Watch Timer
Chapter 7 Watch Timer 7.1 Function The watch timer has the following functions: • Watch timer (interrupt intervals from 488 µs up to 0.5 s) • Interval timer (interrupt intervals from 488 µs up to 65.5 ms) The watch timer and interval timer functions can be used at the same time. Figure 7-1 shows the block diagram of the watch timer.
Page 240: Configuration
Chapter 7 Watch Timer 7.2 Configuration The watch timer consists of the following hardware: Table 7-1: Configuration of Watch Timer Item Configuration Counter 5 bits × 1 Prescaler 11 bits × 1 Control register Watch timer mode control register (WTM) 7.3 Watch Timer Control Register The watch timer mode control register (WTM) controls the watch timer.
Page 241 Chapter 7 Watch Timer Figure 7-2: Watch Timer Mode Control Register (WTM) (2/2) WTM7 Selects main input frequency from prescaler = 32 KHz @f = 16 MHz) (Sub-system clock) 5-bit Prescaler interval time selection for interval timer function WTM7 = 0 WTM7 = 1 WTM6 WTM5...
Page 242: Operations
Chapter 7 Watch Timer 7.4 Operations 7.4.1 Operation as watch timer The count operation of the first stage 11 bits counter is enabled by setting the WTM0 bit of the watch timer mode control register (WTM) to “1”. (When WTM0 is cleared to “0”, the 11-bit prescaler and 5-bit counter are cleared, and the watch timer stops the count operation.) The watch timer is then monitored by the bit WTM1: •...
Page 243: Watch Timer And Interval Timer Simultaneously
Chapter 7 Watch Timer 7.4.3 Watch timer and Interval timer simultaneously Operation of Watch timer and Interval timer can be used simultaneously. Figure 7-3: Example Watch Timer and Interval Timer simultaneously 0x0F or 0x1F 0x0F or 0x1F 5-bit counter Overflow Overflow Start Count clock...
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Page 245: Watchdog Timer
Chapter 8 Watchdog Timer 8.1 Features The watchdog timer counts an input clock signal, selectable from the main oscillator or the sub-system oscillator. Upon overflow, the watchdog timer can generate • a non-maskable interrupt request signal (WDTNMI) • a system reset signal (WDTRES) (default setting) •...
Page 246: Figure 8-1: Block Diagram Of Watchdog Timer
Chapter 8 Watchdog Timer Figure 8-1: Block Diagram of Watchdog Timer Timer Counter INTWDT WDTRES WDTNMI WDM1 WDM0 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Watchdog timer mode register (WDTM) Internal bus Remark: INTWDT: Request signal for maskable interrupt through watchdog timer overflow WDTNMI: Request signal for non-maskable interrupt through watchdog timer overflow WDTRES:...
Page 247: Configuration
Chapter 8 Watchdog Timer 8.2 Configuration Watchdog timer consists of the following hardware. Table 8-1: Configuration of Watchdog Timer Item Configuration Watchdog timer mode register (WDTM) Control register Watchdog timer enable register (WDTE) 8.2.1 Watchdog Timer control registers Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of watchdog timer.
Page 248: Table 8-2: Watchdog Timer Clock Selection
Chapter 8 Watchdog Timer Table 8-2: Watchdog Timer Clock Selection WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Count Frequency (KHz) Interrupt Period (ms) (61.035) 16.384 32.768 (30.517) 65.536 (15.259) (7.6294) 131.072 (3.8147) 262.144 524.288 (1.9073) 1048.57 (0.9537) 2097.15 (0.4768) (64.000) 15.625 31.250 (32.000) 62.500 (16.000)
Page 249: Figure 8-3: Watchdog Timer Enable Register (Wdte) Format
Chapter 8 Watchdog Timer Watchdog timer enable register (WDTE) The counter of the watchdog timer is cleared and counting restarted by writing “ACH” to WDTE. WDTE is set by an 8-bit memory manipulation instruction. RESET input sets WDTE to 9AH. Figure 8-3: Watchdog timer enable register (WDTE) Format Address After reset...
Page 250: Operation
Chapter 8 Watchdog Timer 8.3 Operation Watchdog timer automatically starts in the reset mode following reset release. The WDTM register can be written only once after system reset. To configure the watchdog timer, write the operation mode and the interval time to the WDTM register using 8-bit memory manipulation instructions.
Page 251: Watchdog Timer As Interval Timer
Chapter 8 Watchdog Timer 8.3.2 Watchdog timer as interval timer This mode can be selected by writing the corresponding settings in WDTM register. An interrupt, rather than a reset request, will be generated in the following cases: • at overflow of the timer •...
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Page 253: Serial Interface Function
Chapter 9 Serial Interface Function 9.1 Features The serial interface function provides three types of serial interfaces combining a total of 5 transmit/receive channels. All five channels can be used simultaneously. The three interface formats are as follows. • Asynchronous serial interfaces (UART60, UART61): 2 channels •...
Page 254: Serial Interface Uart6N
Chapter 9 Serial Interface Function 9.2 Serial Interface UART6n 9.2.1 Functions of Serial Interfaces UART6n (UART60, UART61) Serial interfaces UART6n have the following two modes. Operation STOP mode This mode is used when serial transfer is not executed; it can reduce the power consumption. For details, refer to Chapter 9.2.5 (1)“Operation STOP mode”...
Page 255: Figure 9-1: Lin Transmission Operation
Chapter 9 Serial Interface Function Figures 9-1 and 9-2 outline the transmission and reception operations of LIN. Figure 9-1: LIN Transmission Operation Tuning Checksum Wakeup break field Tuning field Match field Data field Data field field signal frame Sleep Note 2 Data Data Data...
Page 256: Figure 9-2: Lin Reception Operation
Chapter 9 Serial Interface Function Figure 9-2: LIN Reception Operation Checksum Wakeup Tuning Data filed field signal frame break field Tuning field Match field Data filed Sleep Data Data Data ID reception Note 5 reception reception Note 2 reception reception 13 bits reception RX6n...
Page 257: Figure 9-3: Port Configuration For Lin Reception Operation
Chapter 9 Serial Interface Function Figure 9-3: Port Configuration for LIN Reception Operation P13/RXD60/INTP7 P20/RXD61/INTP8 RXDn input Port latch Port mode and Port control P13/P20 and PMC13/PMC20 P13/P20 INTP7/INTP8 input P33/TIC00 ITIC00 P30/TIC01 ITIC01 P43/TIG02 input ITIG02 P44/TIG03 DCAN ITIG03 SOFOUT Port mode and Port control Port latch...
Page 258: Configuration Of Serial Interface Uart6N
Chapter 9 Serial Interface Function 9.2.2 Configuration of Serial Interface UART6n Serial interface UART6n consists of the following hardware. Table 9-1: Configuration of Serial Interface UART6n Item Configuration Receive buffer register (RXBn) Receive shift register (RXSn) Registers Transmit buffer register (TXBn) Transmit shift register (TXSn) Asynchronous serial interface operation mode register (ASIMn) Asynchronous serial interface reception error status register (ASISn)
Page 259 Chapter 9 Serial Interface Function Receive buffer register (RXBn) This 8-bit register stores parallel data converted by the receive shift register. Receive shift register (RXSn) This register converts the serial data input to the RXD6n pin into parallel data. RXSn cannot be directly manipulated by a program. Transmit buffer register (TXBn) This buffer register is used to set transmitted data.
Page 260: Reception And Transmit Buffer Registers
Chapter 9 Serial Interface Function 9.2.3 Reception and Transmit buffer registers Receive buffer register (RXBn) The RXBn register is an 8-bit buffer register that stores received data (n = 0, 1). Each time 1 byte of data has been received, new received data is transferred to this register from receive shift register (RXSn).
Page 261: Figure 9-6: Format Of Transmit Buffer Register (Txbn)
Chapter 9 Serial Interface Function Transmit buffer register (TXBn) The TXBn register is an 8-bit buffer register that stores data to transmit (n = 0, 1). Transmission is started when data is written to TXBn. This register can be read or written by an 8-bit memory manipulation instruction.
Page 262: Registers Controlling Serial Interface Uart6N
Chapter 9 Serial Interface Function 9.2.4 Registers Controlling Serial Interface UART6n Serial interface UART6n is controlled by the following six registers. • Asynchronous serial interface operation mode register (ASIMn) • Asynchronous serial interface reception error status register (ASISn) • Asynchronous serial interface transmission status register (ASIFn) •...
Page 263 Chapter 9 Serial Interface Function Figure 9-7: Format of Asynchronous Serial Interface Operation Mode register (ASIMn) (2/2) RXEn Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS1n PS0n Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity.
Page 264: Figure 9-8: Format Of Asynchronous Serial Interface Reception Error Status Register (Asisn)
Chapter 9 Serial Interface Function Asynchronous serial interface reception error status register (ASISn) This register indicates an error status on completion of reception by serial interface UART6n. It includes three error flag bits (PEn, FEn, OVEn). This read-only register can be read only with 8-bit memory manipulation instructions. RESET input clears this register to 00H if bit 7 (POWERn) and bit 5 (RXEn) of ASIMn = 0.
Page 265: Figure 9-9: Format Of Asynchronous Serial Interface Transmission Status Register (Asifn)
Chapter 9 Serial Interface Function Asynchronous serial interface transmission status register (ASIFn) This register indicates the status of transmission by serial interface UART6n. It includes two status flag bits (TXBFn and TXSFn). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXBn register after data has been transferred from the TXBn register to the TXSn register.
Page 266: Figure 9-10: Format Of Clock Selection Register (Cksrn)
Chapter 9 Serial Interface Function Clock selection register (CKSRn) This register selects the base clock of serial interface UART6n. CKSRn can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark: CKSRn can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWERn) and bit 6 (TXEn) of ASIMn = 1 or bit 7 (POWERn) and bit 5 (RXEn) of ASIMn = 1).
Page 267: Figure 9-11: Format Of Baud Rate Generator Control Register (Brgcn)
Chapter 9 Serial Interface Function Baud rate generator control register (BRGCn) This register selects the base clock of serial interface UART6n. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark: BRGCn can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWERn) and bit 6 (TXEn) of ASIMn = 1 or bit 7 (POWERn) and bit 5 (RXEn) of ASIMn = 1).
Page 268: Figure 9-12: Format Of Asynchronous Serial Interface Control Register (Asicln) (1/2)
Chapter 9 Serial Interface Function Asynchronous serial interface control register (ASICLn) This register controls the serial transfer operations of serial interface UART6n. ASICLn can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. RESET input sets this register to16H. Remark: ASICLn can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWERn) and bit 6 (TXEn) of ASIMn = 1 or bit 7 (POWERn) and...
Page 269 Chapter 9 Serial Interface Function Figure 9-12: Format of Asynchronous Serial Interface Control register (ASICLn) (2/2) SBTTn SBF transmission trigger SBF transmission trigger SBL2n SBL1n SBL0n SBF transmission output width control SBF is output with 13-bits length. SBF is output with 14-bits length. SBF is output with 15-bits length.
Page 270: Operation Of Serial Interface Uart6N
Chapter 9 Serial Interface Function 9.2.5 Operation of serial interface UART6n This section explains the two modes of serial interface UART6n. Operation STOP mode In this mode, serial transfer cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. (a) Register setting The operation stop mode is set by asynchronous serial interface operation mode register (ASIMn).
Page 271 Chapter 9 Serial Interface Function Figure 9-13: Register ASIMn in Operation STOP Mode (2/2) TXEn Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission RXEn Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception Cautions: 1. At startup, set POWERn to 1 and then set TXEn to 1. Clear TXEn to 0 first, and then clear POWERn to 0.
Page 272: Figure 9-14: Register Asimn In Asynchronous Serial Interface (Uart) Mode (1/2)
Chapter 9 Serial Interface Function Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 273 Chapter 9 Serial Interface Function Figure 9-14: Register ASIMn in Asynchronous serial interface (UART) mode (2/2) TXEn Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission RXEn Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS1n PS0n Transmission operation...
Page 274: Figure 9-15: Register Asisn In Asynchronous Serial Interface (Uart) Mode
Chapter 9 Serial Interface Function • Asynchronous serial interface reception error status register (ASISn) This register indicates an error status on completion of reception by serial interface UART6n. It includes three error flag bits (PEn, FEn, OVEn). This read-only register can be set only by 8-bit memory manipulation instructions. RESET input clears this register to 00H if bit 7 (POWERn) and bit 5 (RXEn) of ASIMn = 0.
Page 275: Figure 9-16: Register Asifn In Asynchronous Serial Interface (Uart) Mode
Chapter 9 Serial Interface Function • Asynchronous serial interface transmission status register (ASIFn) This register indicates the status of transmission by serial interface UART6n. It includes two status flag bits (TXBFn and TXSFn). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXBn register after data has been transferred from the TXBn register to the TXSn register.
Page 276: Figure 9-17: Register Asicln In Asynchronous Serial Interface (Uart) Mode (1/2)
Chapter 9 Serial Interface Function • Asynchronous serial interface control register (ASICLn) This register controls the serial transfer operations of serial interface UART6n. ASICLn can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction. RESET input sets this register to16H. Remark: ASICLn can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWERn) and bit 6 (TXEn) of ASIMn = 1 or bit 7 (POWERn) and...
Page 277 Chapter 9 Serial Interface Function Figure 9-17: Register ASICLn in Asynchronous serial interface (UART) mode (2/2) SBTTn SBF transmission trigger SBF transmission trigger SBL2n SBL1n SBL0n SBF transmission output width control SBF is output with 13-bits length. SBF is output with 14-bits length. SBF is output with 15-bits length.
Page 278: Figure 9-18: Format Of Normal Uart Transmitted/Received Data
Chapter 9 Serial Interface Function Communication operation (a) Normal transmitted/received data format Figure 9-18 shows the format of the transmitted/received data. Figure 9-18: Format of Normal UART transmitted/received Data (a) LSB-first transmission/reception 1 data frame Start Parity Stop bit Character bits (b) MSB-first transmission/reception 1 data frame Start...
Page 279: Figure 9-19: Example Of Normal Uart Transmitted/Received Data Format
Chapter 9 Serial Interface Function Figure 9-19: Example of Normal UART transmitted/received Data Format (a) Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H 1 data frame Start Parity Stop (b) Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H 1 data frame Start Parity...
Page 280 Chapter 9 Serial Interface Function (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 281: Figure 9-20: Normal Transmission Completion Interrupt Request Timing
Chapter 9 Serial Interface Function (c) Normal transmission The TXD6n pin outputs a high level when bit 7 (POWERn) of asynchronous serial interface mode register (ASIMn) is set to 1. If bit 6 (TXEn) of ASIMn is then set to 1, transmission is enabled. Transmission can be started by writing transmitted data to transmit buffer register (TXBn).
Page 282: Table 9-2: Write Processing And Writing To Txbn During Execution Of Continuous Transmission
Chapter 9 Serial Interface Function (d) Continuous transmission When transmit shift register (TXSn) has started the shift operation, the next transmitted data can be written to transmit buffer register (TXBn). As a result, data can be transmitted without intermis- sion even while an interrupt that has occurred after transmission of one data frame is being serv- iced, thus an efficient communication rate is realized.
Page 283: Figure 9-21: Processing Flow Of Continuous Transmission
Chapter 9 Serial Interface Function Figure 9-21 shows the processing flow of continuous transmission. Figure 9-21: Processing Flow of Continuous Transmission Set registers. Write transmit data to TXBn register. Read ASIFn register. TXBFn = 0? Interrupt occurs. Transfer executed necessary number of times? Read ASIFn Read ASIFn...
Page 284: Figure 9-22: Timing Of Starting Continuous Transmission
Chapter 9 Serial Interface Function Figure 9-22 shows the timing of starting continuous transmission, and Figure 9-23 shows the timing of ending continuous transmission. Figure 9-22: Timing of Starting Continuous Transmission TXD6n Start Data (1) Parity Stop Start Data (2) Parity Stop Start...
Page 285: Figure 9-23: Timing Of Ending Continuous Transmission
Chapter 9 Serial Interface Function Figure 9-23: Timing of Ending Continuous Transmission Start Start TXD6n Data (n) Parity Stop Data (n–1) Parity Stop Stop INTSTn TXBn Data (n–1) Data (n) TXSn Data (n–1) Data (n) TXBFn TXSFn POWERn or TXEn Remark: TXD6n: TXD6n pin (output)
Page 286: Figure 9-24: Reception Completion Interrupt Request Timing
Chapter 9 Serial Interface Function (e) Normal reception Reception is enabled and the RXD6n pin input is sampled when bit 7 (POWERn) of asynchronous serial interface mode register (ASIMn) is set to 1 and then bit 5 (RXEn) of ASIMn is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6n pin input is detected.
Page 287: Figure 9-25: Reception Error Interrupt
Chapter 9 Serial Interface Function (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register (ASISn) is set as a result of data reception, a reception error interrupt request (INTSRn/INTSREn) is generated.
Page 288: Figure 9-26: Noise Filter Circuit
Chapter 9 Serial Interface Function (g) Noise filter of received data The RXD6n signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 289: Figure 9-28: Sbf Reception
Chapter 9 Serial Interface Function (i) SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN protocol, refer to Figure 9-2, “LIN Reception Operation,” on page 254. Reception is enabled when bit 7 (POWERn) of asynchronous serial interface mode register (ASIMn) is set to 1 and then bit 5 (RXEn) of ASIMn is set to 1.
Page 290: Dedicated Baud Rate Generator
Chapter 9 Serial Interface Function 9.2.6 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6n. Separate 8-bit counters are provided for transmission and reception. Configuration of baud rate generator •...
Page 291: Figure 9-29: Configuration Of Baud Rate Generator
Chapter 9 Serial Interface Function Figure 9-29: Configuration of Baud Rate Generator POWERn POWERn, TXEn (or RXEn) Clock Selector 8-bit counter XCLK Match detector Baud rate CKSRn: TPS3n to TPS0n BRGCn: MDL67n to MDL60n Remark: POWERn: Bit 7 of asynchronous serial interface mode register (ASIMn) TXEn: Bit 6 of ASIMn RXEn:...
Page 292: Figure 9-30: Clock Selection Register (Cksrn) Format
Chapter 9 Serial Interface Function Generation of serial clock A serial clock can be generated by using clock selection register (CKSRn) and baud rate genera- tor control register (BRGCn). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS3n to TPS0n) of CKSRn. Bits 7 to 0 (BRG7 to BRG0) of BRGCn can be used to select the division value of the 8-bit counter.
Page 293: Figure 9-31: Baud Rate Generator Control Register (Brgcn) Format
Chapter 9 Serial Interface Function (b) Baud rate generator control register (BRGCn) This register selects the base clock of serial interface UART6n. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark: BRGCn can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWERn) and bit 6 (TXEn) of ASIMn = 1 or bit 7 (POWERn) and bit 5 (RXEn) of ASIMn = 1).
Page 294 Chapter 9 Serial Interface Function (c) Baud rate The baud rate can be calculated by the following expression. • Baud rate = f / (2 * k) [bps], or k = INT (f / (2 * target baud rate)) XCLK XCLK : Frequency of base clock (Clock) selected by TPS3n to TPS0n bits of CKSRn register XCLK...
Page 295: Table 9-4: Set Data Of Baud Rate Generator
Chapter 9 Serial Interface Function Example of setting baud rate Table 9-4: Set Data of Baud Rate Generator = 16.0 MHz = 10.0 MHz = 8.38 MHz Baud TPS3n to Effective TPS3n to Effective TPS3n to Effective Rate [bps] ERR[%] ERR[%] ERR[%] TPS0n...
Page 296: Figure 9-32: Transfer Rate During Continuous Transmission
Chapter 9 Serial Interface Function Transfer rate during continuous transmission When data is continuously transmitted, the transfer rate from a stop bit to the next start bit is extended by two clocks from the normal value. However, the result of transfer is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 297: Clocked Serial Interfaces 0, 1 (Csi00, Csi01)
Chapter 9 Serial Interface Function 9.3 Clocked Serial Interfaces 0, 1 (CSI00, CSI01) 9.3.1 Features • High-speed transfer: Maximum 4 Mbps (at 16 MHz system clock) • Master mode or slave mode can be selected • Transmission data length: 8 bits or 16 bits •...
Page 298: Configuration
Chapter 9 Serial Interface Function 9.3.2 Configuration CSIn is controlled via the clocked serial interface mode register (CSIMn) (n = 0, 1). Transmission/reception of data is performed with reading SIOn register (n = 0, 1). Clocked serial interface mode registers (CSIM0, CSIM1) The CSIMn register is an 8-bit register that specifies the operation of CSIn.
Page 299: Figure 9-33: Block Diagram Of Clocked Serial Interfaces
Chapter 9 Serial Interface Function (12) Serial clock control circuit Controls the serial clock supply to the shift register. Also controls the clock output to the SCK0n pin when the internal clock is used. (13) Serial clock counter Counts the serial clock output or input during transmission/reception operation, and checks whether 8-bit data transmission/reception has been performed.
Page 300: Control Registers
Chapter 9 Serial Interface Function 9.3.3 Control registers Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register controls the CSI0n operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Figure 9-34: Clocked Serial Interface Mode Registers (CSIM0, CSIM1) Initial Address...
Page 301: Figure 9-35: Clocked Serial Interface Clock Selection Registers (Csic0, Csic1) (1/2)
Chapter 9 Serial Interface Function Clocked serial interface clock selection registers 0, 1 (CSICn) The CSICn register is an 8-bit register that controls the CSIn transfer operation (n = 0, 1). This register can be read/written in 8-bit or 1-bit units. Figure 9-35: Clocked Serial Interface Clock Selection Registers (CSIC0, CSIC1) (1/2) Initial Address...
Page 302 Chapter 9 Serial Interface Function Figure 9-35: Clocked Serial Interface Clock Selection Registers (CSIC0, CSIC1) (2/2) Bit Position Bit Name Function Specifies input clock for CSI00 CKS2n CKS1n CKS0n Input Clock Mode Master mode Master mode Master mode CKS22 Master mode CKS20 Master mode /256...
Page 303: Figure 9-36: Clocked Serial Interface Reception Buffer Registers (Sirb0, Sirb1)
Chapter 9 Serial Interface Function Clocked serial interface reception buffer registers (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores received data. When the receive-only mode is set (TRMDn bit of CSIMn register = 0, n = 0,1), the reception oper- ation is started by reading data from the SIRBn register.
Page 304: Figure 9-37: Clocked Serial Interface Reception Buffer Registers (Sirb0L1, Sirb1L1)
Chapter 9 Serial Interface Function Clocked serial interface LSB reception buffer registers (SIRB0L, SIRB1L) The SIRBnL register is an 8-bit buffer register that stores received data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBnL register.
Page 305: Figure 9-38: Clocked Serial Interface Transmission Buffer Registers (Sotb0, Sotb1)
Chapter 9 Serial Interface Function Clocked serial interface LSB transmission buffer registers (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmitted data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBnL register.
Page 306: Figure 9-39: Clocked Serial Interface Transmission Buffer Registers (Sotbnl)
Chapter 9 Serial Interface Function Clocked serial interface LSB transmission buffer registers (SOTB0L, SOTB1L) The SOTBnL register is an 8-bit buffer register that stores transmitted data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBnL register.
Page 307: Figure 9-40: Clocked Serial Interface Initial Transmission Buffer Registers 0, 1 (Sotbfn)
Chapter 9 Serial Interface Function Clocked serial interface initial transmission buffer registers (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units.
Page 308: Figure 9-41: Clocked Serial Interface Initial Transmission Buffer Registers (Sotbfnl)
Chapter 9 Serial Interface Function Clocked serial interface LSB initial transmission buffer registers (SOTBF0L, SOTBF1L) The SOTBFnL register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFnL register. The SOTBFnL register is the same as the lower bytes of the SOTBFn register.
Page 309: Figure 9-42: Serial I/O Shift Registers (Sio0, Sio1)
Chapter 9 Serial Interface Function Serial I/O shift registers (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOn register is read. These registers are read-only, in 16-bit units.
Page 310: Figure 9-43: Serial I/O Shift Registers (Sio0L, Sio1L)
Chapter 9 Serial Interface Function (10) Serial I/O LSB shift registers (SIO0L, SIO1L) The SIOnL register is an 8-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOnL register is read. These registers are read-only, in 8-bit units.
Page 311: Operation
Chapter 9 Serial Interface Function 9.3.4 Operation Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMDn bit of CSIMn register = 0), transfer is started by reading the received data buffer register (SIRBn/SIRBnL) (n = 0, 1). In the transmission/reception mode (TRMDn bit of CSIMn register = 1), transfer is started by Note 2 writing...
Page 312: Figure 9-44: Timing Chart In Single Transfer Mode (Dapn = 0) (1/2)
Chapter 9 Serial Interface Function Figure 9-44: Timing Chart in Single Transfer Mode (DAPn = 0) (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKPn bit = 0, DAPn bit = 0 SCK0n (input/output) SO0n...
Page 313 Chapter 9 Serial Interface Function Figure 9-44: Timing Chart in Single Transfer Mode (DAPn = 1) (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKPn bit = 0, DAPn bit = 1 SCK0n (input/output) SO0n...
Page 314: Figure 9-45: Timing Chart According To Clock Phase Selection (1/2)
Chapter 9 Serial Interface Function (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKPn bit of CSICn register) and data phase selection (DAPn bit of CSICn register) under the following con- ditions.
Page 315 Chapter 9 Serial Interface Function Figure 9-45: Timing Chart According to Clock Phase Selection (2/2) (c) When CKPn bit = 0, DAPn bit = 1 SCK0n (input/output) SI0n (input) DO6 DO5 DO4 DO3 DO2 DO1 SO0n (output) Reg_R/W INTCSIn interrupt CSOTn bit (d) When CKPn bit = 1, DAPn bit = 1 SCK0n (input/output)
Page 316: Figure 9-46: Timing Chart Of Interrupt Request Signal Output In Delay Mode (1/2)
Chapter 9 Serial Interface Function (c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1) INTCSIn is set (1) upon completion of data transmission/reception. Caution: The delay mode (CSITn bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B).
Page 317 Chapter 9 Serial Interface Function Figure 9-46: Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKPn bit = 1, DAPn bit = 1 Input clock SCK0n (input/output) SI0n (input) SO0n (output) Reg_WR INTCSIn interrupt CSOTn bit Delay Remarks: 1.
Page 318: Figure 9-47: Repeat Transfer (Receive-Only) Timing Chart
Chapter 9 Serial Interface Function Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTOn bit of CSIMn register = 1) and the receive-only mode (TRMDn bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3>...
Page 319 Chapter 9 Serial Interface Function In the case of the repeat transfer mode, two transfer requests are set at the start of the first trans- fer. Following the transmission/reception completion interrupt request (INTCSIn), transfer is con- tinued if the SIRBn register can be read within the next transfer reservation period. If the SIRBn register cannot be read, transfer ends and the SIRBn register does not receive the new value of the SIOn register.
Page 320: Figure 9-48: Repeat Transfer (Transmission/Reception) Timing Chart
Chapter 9 Serial Interface Function Figure 9-48: Repeat Transfer (Transmission/Reception) Timing Chart SCK0n (input/output) dout-1 dout-2 dout-3 dout-4 dout-5 SO0n (output) din-1 din-2 din-3 din-4 din-5 SI0n (input) SOTBFnL dout-1 register SOTBnL dout-2 dout-3 dout-4 dout-5 register SIOnL din-5 register SIRBnL din-1 din-2...
Page 321: Figure 9-49: Timing Chart Of Next Transfer Reservation Period (1/2)
Chapter 9 Serial Interface Function (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 9-49. Figure 9-49: Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, operation mode: CKPn bit = 0, DAPn bit = 0 SCK0n (input/output) INTCSIn...
Page 322: Figure 9-50: Transfer Request Clear And Register Access Contention
Chapter 9 Serial Interface Function Figure 9-49: Timing Chart of Next Transfer Reservation Period (2/2) (d) When data length: 16 bits, operation mode: CKPn bit = 0, DAPn bit = 1 SCK0n (input/output) INTCSIn interrupt Reservation period: 14.5 SCK0n cycles Remark: n = 0, 1 (d) Cautions...
Page 323: Figure 9-51: Interrupt Request And Register Access Contention
Chapter 9 Serial Interface Function - In case of contention between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error results in a transfer error (refer to Figure 9-51). In the transmission/reception mode, the value of the SOTBFn register is re-transmitted, and illegal data is sent.
Page 324: Output Pins
Chapter 9 Serial Interface Function 9.3.5 Output pins SCK0n pin When the CSIn operation is disabled (CSIEn bit of CSIMn register = 0), the SCK0n pin output sta- tus is as follows (n = 0 to 2). CKPn CKS2n CKS1n CKS0n SCK0n Pin Output Don’t care...
Page 325: Tm51 Output As Dedicated Baud Rate Generator For Csi00
Chapter 9 Serial Interface Function 9.3.6 TM51 output as dedicated baud rate generator for CSI00 Selecting TM51 as the baud rate generator The CSI00 serial clock can be selected between TM51 as an baud rate generator output or inter- nal system clock ( ) with prescaler.
Page 326 [MEMO] User’s Manual U15872EE2V1UM00...
Page 327: Chapter 10 Dcan
Chapter 10 DCAN 10.1 Outline Description Remark: The following indices were consequently used: • m = 2, 4 (address offset index for the 2 Mask Buffers) • r = 02 to 11 (address offset index for the 16 Receive Buffers) •...
Page 328: Protocol Mode Function
Chapter 10 DCAN 10.2.1 Protocol Mode Function Standard format mode • This mode supports an 11-bit message identifier thus making it possible to differentiate between 2048 types of messages. Extended format mode • In the extended format mode, the identifier has 29 bits. It is built by the standard identifier (11 bits) and an extended identifier (18 bits).
Page 329: Data Frame / Remote Frame
Chapter 10 DCAN 10.2.3 Data Frame / Remote Frame Figure 10-2: Data Frame Data frame (11 + 1) (29 + 3) 0 ... 64 Bus idle Interframe space End of frame ACK field CRC field Data field Control field Arbitration field Start of frame Figure 10-3: Remote Frame Remote frame...
Page 330: Figure 10-4: Data Frame
Chapter 10 DCAN Description of each field "R" indicates recessive level. "D" indicates dominant level. Start of frame: The start of data frame and remote frame are indicated. Figure 10-4: Data Frame Interframe space Start of frame Arbitration field on bus idle 1 bit •...
Page 331: Figure 10-6: Arbitration Field/Extended Format Mode
Chapter 10 DCAN Figure 10-6: Arbitration Field/Extended Format Mode Arbitra tion field Control field Identifier Identifier ID28 . . . ID18 ID17 . . . ID0 (1 bit) (1 bit) (1 bit) (11 bits) (18 bits) • ID28 - ID0 is the identifier. •...
Page 332: Figure 10-7: Control Field (Standard Format Mode)
Chapter 10 DCAN Control field: The data byte number DLC in the data field specifies the number of databytes in the current frame (DLC=0 to 8). Figure 10-7: Control Field (Standard Format Mode) Arbitration field Control field Data field DLC3 DLC2DLC1DLC0 Figure 10-8: Control Field (Extended Format Mode) Arbitration field Control field...
Page 333: Figure 10-9: Data Field
Chapter 10 DCAN Data field: This field carries the data bytes to be sent. The number of data bytes is defined by the DLC value. Figure 10-9: Data Field Control field Data field CRC field Data Data (8 bits) (8 bits) CRC field: This field consists of a 15-bit CRC sequence to check the transmission error and a CRC delimiter.
Page 334: Figure 10-11: Ack Field
Chapter 10 DCAN ACK field: For check of normal reception. Figure 10-11: ACK Field ACK field CRC field End of frame ACK slot ACK delimiter (1 bit) (1 bit) • Receive node sets the ACK slot to dominant level if no error was detected. End of frame: Indicates the end of the transmission/reception.
Page 335: Figure 10-13: Interframe Space/Error Active
Chapter 10 DCAN Interframe space: This sequence is inserted after data frames, remote frames, error frames, and overload frames in the serial bitstream on the bus to indicate start or end of a frame. The length of the interframe space depends on the error state (active or passive) of the node. (a) Error active: Consists of 3 bits intermission and bus idle.
Page 336: Error Frame
Chapter 10 DCAN 10.2.4 Error Frame • This frame is sent from a node if an error is detected. • The type of an Error Frame is defined by its error flag: ACTIVE ERROR FLAG or PASSIVE ERROR FLAG. Which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node.
Page 337: Overload Frame
Chapter 10 DCAN 10.2.5 Overload Frame • This frame is started at the first bit of the intermission when the reception node is busy with exploiting the receive operation and is not ready for further reception. • When a bit error is detected in the intermission, also an overload frame is sent following the next bit after the bit error detection.
Page 338: Function
Chapter 10 DCAN 10.3 Function 10.3.1 Arbitration If two or more nodes happen to start transmission in coincidence, the access conflict is solved by a bit- wise arbitration mechanism during transmission of the ARBITRATION FIELD. When a node starts transmission: •...
Page 339: Multi Master
Chapter 10 DCAN 10.3.3 Multi Master As the bus priority is determined by the identifier, any node can be the bus master. 10.3.4 Multi Cast Any message can be received by any node (broadcast). 10.3.5 Sleep Mode/Stop Function This is a function to put the CAN controller in waiting mode to achieve low power consumption. The SLEEP mode of the DCAN complies to the method described in ISO 11898.
Page 340: Error Control Function
Chapter 10 DCAN 10.3.6 Error Control Function Error types Table 10-10: Error Types Description of Error Detection State Type Detection Transmission/ Detection Method Field/Frame Condition Reception Comparison of output Bit that output data on the bus at the Disagreement Transmission/ Bit error level and level on the bus start of frame to the end of frame,...
Page 341: Table 10-12: Types Of Error
Chapter 10 DCAN Error state (a) Types of error state • Three types of error state: These are error active, error passive and bus off. • The transmission error counter (TEC) and the reception error counter (REC) control the error state.
Page 342: Table 10-13: Error Counter
Chapter 10 DCAN (b) Error counter • Error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counters are updated during the first bit of an error flag. Table 10-13: Error Counter Transmission Error Reception Error State...
Page 343: Baud Rate Control Function
Chapter 10 DCAN 10.3.7 Baud Rate Control Function Nominal bit time (8 to 25 time quanta) • Definition of 1 data bit time is as follows. Figure 10-17: Nominal Bit Time (8 to 25 Time Quanta) Nominal bit time Sync Prop Phase Phase...
Page 344: Figure 10-18: Adjusting Synchronization Of The Data Bit
Chapter 10 DCAN Adjusting synchronization of the data bit • The transmission node transmits data synchronized to the transmission node bit timing. • The reception node adjusts synchronization at recessive to dominant edges on the bus. Depending on the protocol this synchronization can be a hard or soft synchronization. (a) Hard synchronization This type of synchronization is performed when the reception node detects a start of frame in the bus idle state.
Page 345: Figure 10-19: Bit Synchronization
Chapter 10 DCAN (b) Soft synchronization When a recessive to dominant level change on the bus is detected, a soft synchronization is performed. • If the phase error is larger than the programmed SJW value, the node will adjust the timing by applying this SJW-value.
Page 346: State Shift Chart
Chapter 10 DCAN 10.3.8 State Shift Chart Figure 10-20: Transmission State Shift Chart Reception Start of frame Bit error Arbitration field RTR = 1 Bit error Control field Reception RTR = 0 Bit error Data field Bit error CRC field ACK error ACK field Bit error...
Page 347: Figure 10-21: Reception State Shift Chart
Chapter 10 DCAN Figure 10-21: Reception State Shift Chart Transmission Start of frame Transmission Stuff error Arbitration field RTR = 1 Stuff error Control field RTR = 0 Stuff error Data field CRC error, stuff error CRC field ACK error, bit error ACK field Bit error, form error End of frame...
Page 348: Figure 10-22: Error State Shift Chart
Chapter 10 DCAN Figure 10-22: Error State Shift Chart (a) Transmission Error active TEC > TEC < 127 Error passive TEC > Bus off TEC = 0 TEC = Transmission error counter (b) Reception Error active REC > 128 Error passive REC <...
Page 349: Connection With Target System
Chapter 10 DCAN 10.4 Connection with Target System The DCAN Macro has to be connected to the CAN bus with an external transceiver. Figure 10-23: Connection to the CAN Bus CTxD CANL DCAN Macro Transceiver CRxD CANH User’s Manual U15872EE2V1UM00...
Page 350: Dcan Controller Configuration
Chapter 10 DCAN 10.5 DCAN Controller Configuration The DCAN-module consists of the following hardware. Item Configuration Message definition In RAM area 1 (CTXD0) DCAN input/output 1 (CRXD0) DCAN control register (DCANC0) CAN control register (CANC0) Transmit control register (TCR0) Receive message register (RMES0) DCAN error status register (CANES0) Transmit error counter (TEC0) Control registers...
Page 351: Special Function Register For Dcan-Module
Chapter 10 DCAN 10.6 Special Function Register for DCAN-module Table 10-15: Table of DCAN0 SFR’s Bit Manipulation Units Register Name Symbol After Reset Address 1-bit 8-bit 16-bit × × DCAN control register DCANC0 3FEC120H × × CAN control register CANC0 3FEC121H ×...
Page 352: Message Buffer Configuration
Chapter 10 DCAN 10.7 Message Buffer Configuration Note 2 Register Name After Reset Address Offset 000H to 00FH Transmit buffer 0 010H to 01FH Transmit buffer 1 020H to 02FH Receive buffer 0 / Mask 0 030H to 03FH Receive buffer 1 040H to 04FH Receive buffer 2 / Mask 1 050H to 05FH...
Page 353: Transmit Buffer Structure
Chapter 10 DCAN 10.8 Transmit Buffer Structure The DCAN channel has 2 independent transmit buffers. The two buffers have a 16 byte data structure for standard and extended frames with the ability to send up to 8 data bytes per message. The structure of the transmit buffer is similar to the structure of the receive buffers.
Page 354: Transmit Message Buffer Format
Chapter 10 DCAN 10.9 Transmit Message Buffer Format Note Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address TCON DLC3 DLC2 DLC1 DLC0 Unused IDTX0 ID standard part IDTX1 ID standard part IDTX2 ID extended part IDTX3...
Page 355: Transmit Message Definition
Chapter 10 DCAN 10.9.1 Transmit Message Definition The memory location labelled TCON includes the information of the RTR bit and the bits of the control field of a data or remote frame. TCON is set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-24: Transmit Message Definition Register (TCON) Address- Symbol...
Page 356: Transmit Identifier Definition
Chapter 10 DCAN 10.9.2 Transmit Identifier Definition These memory locations set the message identifier in the arbitration field of the CAN protocol. IDTX0 to IDTX4 register can be set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-25: Transmit Identifier Register Address- Symbol After Reset R/W...
Page 357: Transmit Data Definition
Chapter 10 DCAN 10.9.3 Transmit Data Definition These memory locations set the transmit message data of the data field in the CAN frame. DATA0 to DATA7 can be set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-26: Transmit Data Address- Symbol After Reset R/W...
Page 358: Receive Buffer Structure
Chapter 10 DCAN 10.10 Receive Buffer Structure The DCAN has up to 16 receive buffers. The number of used buffers is defined by the MCNT0 register. Unused receive buffers can be used as application RAM for the CPU. The received data is stored directly in this RAM area.
Page 359: Receive Message Buffer Format
Chapter 10 DCAN 10.11 Receive Message Buffer Format Address- Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note 1 offset IDCON DSTAT IDREC0 ID standard part Note 2 IDREC1 ID standard part RTRREC IDREC2 ID extended part...
Page 360: Receive Control Bits Definition
Chapter 10 DCAN 10.11.1 Receive Control Bits Definition The memory location labelled IDCON defines the kind of frame (data or remote frame with standard or extended format) that is monitored for the associated buffer. Notification by the receive interrupt upon successful reception can be selected for each receive buffer separately.
Page 361: Receive Status Bits Definition
Chapter 10 DCAN 10.11.2 Receive Status Bits Definition The memory location labelled DSTAT sets the receive status bits of the arbitration field of the CAN protocol. DSTAT can be set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-28: Receive Status Bits Register (DSTAT) (1/2) Address- Symbol After Reset R/W...
Page 362 Chapter 10 DCAN Figure 10-28: Receive Status Bits Register (DSTAT) (2/2) Reserved Bit 0 Reserved bit 0 of received message was “0” Reserved bit 0 of received message was “1” Data Length Code Selection DLC3 DLC2 DLC1 DLC0 of Receive Message 0 data bytes 1 data bytes 2 data bytes...
Page 363 Chapter 10 DCAN Caution: The access to clear the DN flag is a read-modify-write operation on the DCAN mem- ory and it is split into 2 separate bus cycles. If the DCAN macro receives a message it will set the MUC bit of the respective message buffer. In case the read access by the CPU is interleaved with the setting of the MUC bit by the DCAN macro, both access- ing the same message buffer, the MUC bit will be inadvertently reset by the second bus cycle of the CPU read access.
Page 364: Receive Identifier Definition
Chapter 10 DCAN 10.11.3 Receive Identifier Definition These memory locations define the receive identifier of the arbitration field of the CAN protocol. IDREC0 to IDREC4 can be set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-29: Receive Identifier Register Address- Symbol After Reset R/W...
Page 365: Receive Message Data Part
Chapter 10 DCAN 10.11.4 Receive Message Data Part These memory locations set the receive message data part of the CAN protocol. DATA0 to DATA7 can be set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-30: Receive Data Address- Symbol After Reset R/W...
Page 366: Mask Function
Chapter 10 DCAN 10.12 Mask Function Table 10-17: Mask Function Register Address- Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note offset MCON Unused MREC0 ID standard part MREC1 ID standard part MREC2 ID extended part MREC3...
Page 367: Identifier Compare With Mask
Chapter 10 DCAN 10.12.1 Identifier Compare with Mask The identifier compare with mask provides the possibility to exclude some bits from the comparison process. That means each bit is ignored when the corresponding bit in the mask definition is set to one. The setup of the mask control register (MASKC0) defines which receive buffer is used as a mask and which receive buffer uses which mask for comparison.
Page 368: Mask Identifier Control Register (Mcon)
Chapter 10 DCAN The following information is stored in the receive buffer: • Identifier (11 or 29 bit as defined by IDE bit) • Remote bit (RTRREC) if both frames types (data or remote) can be received by this buffer •...
Page 369: Mask Identifier Definition
Chapter 10 DCAN 10.12.3 Mask Identifier Definition These memory locations set the mask identifier definition of the DCAN. MREC0 to MREC4 can be set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-33: Mask Identifier Register (MREC) Address- Symbol After Reset R/W Note...
Page 370: Operation Of The Dcan Controller
Chapter 10 DCAN 10.13 Operation of the DCAN Controller 10.13.1 DCAN Control Register (DCANC0) Depending on the integration of the DCAN into particular products, there exists a DCAN Control regis- ter (DCANC0) that enables or disables a DCAN channel. DCANC0 can be set with an 1-bit or an 8-bit memory manipulation instruction. Figure 10-34: DCAN Control Register (DCANC0) Symbol After Reset...
Page 371: Can Control Register (Canc0)
Chapter 10 DCAN 10.13.2 CAN Control Register (CANC0) The operational modes are controlled via the CAN control register CANC0. CANC0 can be set with an 1-bit or an 8-bit memory manipulation instruction. For bit numbers in brackets a bit access is provided. Figure 10-35: CAN Control Register (CANC0) (1/2) Symbol <4>...
Page 372 Chapter 10 DCAN Figure 10-35: CAN Control Register (CANC0) (2/2) SLEEP0 Sleep/Stop Request for CAN protocol Normal operation CAN protocol goes to sleep or stop mode depending on STOP The clock supply to the DCAN is switched off during initialisation, DCAN Sleep, and DCAN Stop mode. All modes are only accepted while CAN protocol is in idle state, whereby the CRXD pin must be reces- sive (= high level).
Page 373: Figure 10-36: Dcan Time Stamp Support
Chapter 10 DCAN Figure 10-36: DCAN Time Stamp Support Last bit of EOF Data CRC EOF SOFOUT T-FF Capture Register Receive Buffer 4 SOFSEL SOFE Clear SOFC DCAN 16 Bit Timer The generation of an SOFOUT signal can be used for time measurements and for global time base syn- chronisation of different CAN nodes as a prerequisite for time triggered communication.
Page 374: Figure 10-37: Time Stamp Function
Chapter 10 DCAN Figure 10-37: Time Stamp Function Object n Object n Other valid or invalid message Valid message Valid message Enable SOF Edge for capture Edge for capture Figure 10-38: SOFOUT Toggle Function Any valid or Any valid or Any valid or invalid message invalid message...
Page 375: Figure 10-40: Transmission/Reception Flag
Chapter 10 DCAN Figure 10-40: Transmission/Reception Flag Transmission Flag No transmission Note Transmission active on CAN bus Note: Transmission is active until intermission is completed. Reception Flag No data on the CAN bus Reception active on the CAN bus The TXF bit and RXF bit of CANC0 register show the present status of the DCAN on the bus. If both bits are cleared, the bus is in idle state.
Page 376: Dcan Error Status Register
Chapter 10 DCAN 10.13.3 DCAN Error Status Register This register shows the status of the DCAN. CANES0 has to be set with an 8-bit memory manipulation instruction. Figure 10-41: DCAN Error Status Register (CANES0) (1/3) Symbol After Reset Address INIT- Note CANES0 BOFF RECS...
Page 377 Chapter 10 DCAN Figure 10-41: DCAN Error Status Register (CANES0) (2/3) TECS Transmission error counter status Transmission error counter < 96 Transmission error counter ≥ 96 / Warning level for error passive reached TECS is updated after each reception. An interrupt is generated when TECS changes its value. INITSTATE Operational status of the DCAN CAN is in normal operation...
Page 378: Table 10-18: Possible Reactions Of The Dcan
Chapter 10 DCAN Figure 10-41: DCAN Error Status Register (CANES0) (3/3) OVER Overrun Condition Normal operation Overrun occurred during access to RAM The overrun condition is set whenever the CAN can not perform all RAM accesses that are necessary for comparing and storing received data or fetching transmitted data. Typically, the overrun condition is encountered when the frequency for the macro is too low compared to the programmed baud rate.
Page 379: Can Transmit Error Counter
Chapter 10 DCAN 10.13.4 CAN Transmit Error Counter This register shows the transmit error counter. TEC0 register can be read with an 8-bit memory manipulation instruction. Figure 10-42: Transmit Error Counter Register (TEC0) Symbol After Reset Address TEC0 TEC7 TEC6 TEC5 TEC4 TEC3...
Page 380: Message Count Register
Chapter 10 DCAN 10.13.6 Message Count Register With this register the number of receive message buffers is defined. Automatically the RAM area of the receive message buffers, which are handled by the DCAN-module, is allocated. MCNT0 can be read with an 8-bit memory manipulation instruction. Figure 10-44: Message Count Register (MCNT0) (1/2) Symbol After Reset...
Page 381 Chapter 10 DCAN Figure 10-44: Message Count Register (MCNT0) (2/2) Note TLRES Reset function for CAN Protocol Machine No Reset is issued Reset of CAN protocol machine is issued if DCAN is in bus off state, DCAN will enter INIT state (CANC.0 = 1 && CANES.3 = 1) Note: Issuing TLRES bit may violate the minimum recovery time as defined in ISO-11898.
Page 382: Baud Rate Generation
Chapter 10 DCAN 10.14 Baud Rate Generation 10.14.1 Bit Rate Prescaler Register This register sets the clock for the DCAN (internal DCAN clock) and the number of clocks per time quantum (TQ). BRPRS0 can be set with an 8-bit memory manipulation instruction. Figure 10-45: Bit Rate Prescaler Register (BRPRS0) (1/2) Symbol After Reset...
Page 383 Chapter 10 DCAN Figure 10-45: Bit Rate Prescaler Register (BRPRS0) (2/2) BRPRSn defines the number of DCAN clocks applied for one TQ. For BRPRSn two modes are available depending on the TLMODE bit in the SYNC10 register. Setting of BRPRSx (x = 5 to 0) for TLMODE = 0: Note BRPRS5 BRPRS4...
Page 384: Synchronization Control Registers 0 And 1
Chapter 10 DCAN 10.14.2 Synchronization Control Registers 0 and 1 These registers define the CAN bit timing. They define the length of one data bit on the CAN bus, the position of the sample point during the bit timing, and the synchronization jump width. The range of resynchronization can be adapted to different CAN bus speeds or network characteristics.
Page 385 Chapter 10 DCAN Figure 10-46: Synchronization Control Registers 0 and 1 (SYNC00, SYNC10) (2/5) The position of the sample point within the bit timing is defined by SPT0n through SPT4n. SPT4 SPT3 SPT2 SPT1 SPT0 Sample Point Position Other than under Setting prohibited 2 x TQ 3 x TQ...
Page 386 Chapter 10 DCAN Figure 10-46: Synchronization Control Registers 0 and 1 (SYNC00, SYNC10) (3/5) SJW0 and SJW1 define the synchronization jump width as specified in ISO 11898. Synchronisation Jump SJW1 SJW0 Width 1 x TQ 2 x TQ 3 x TQ 4 x TQ Limits on defining the bit timing Note...
Page 387 Chapter 10 DCAN Figure 10-46: Synchronization Control Registers 0 and 1 (SYNC00, SYNC10) (4/5) With TLMODE = 0 the following register settings apply: Register value Description Bit fields BRPRS0 = 00h Clock selector = fx PRMx = 00b BRPRSx = 000000b SYNC00 = A7h CAN Bit in TQ = 8 DBTx = 00111b...
Page 388 Chapter 10 DCAN Figure 10-46: Synchronization Control Registers 0 and 1 (SYNC00, SYNC10) (5/5) SAMP defines the number of sample points per bit as specified in the ISO-11898. SAMP Bit Sampling Sample receive data one time at receive point Sample receive data three times and take majority decision at sample point SOFC works in conjunction with the SOFEn and SOFSEL bits in the CAN Control Register CANC0.
Page 389: Function Control
Chapter 10 DCAN 10.15 Function Control 10.15.1 Transmit Control Transmit Control Register This register controls the transmission of the DCAN-module. The transmit control register (TCR0) provides complete control over the two transmit buffers and their status. It is possible to request and abort transmission of both buffers independently.
Page 390 Chapter 10 DCAN Figure 10-47: Transmit Control Register (TCR0) (2/2) The TXAx bits (x = 0, 1) have a dual function: 1. The CPU can request an abort by writing a “1” into the bit. 2. The DCAN signals whether such an request is still pending. The bit is cleared at the same time when the TXRQx bit (x = 0, 1) is cleared.
Page 391: Receive Control
Chapter 10 DCAN An error during the transmission does not influence the transmit request status. The DCAN will auto- matically retry the transfer. Cautions: 1. The bits are cleared when the INITn bit in CANC0 is set. A transmission already started will be finished but not retransmitted in case of an error.
Page 392: Mask Control
Chapter 10 DCAN 10.15.3 Mask Control The mask control register defines whether the DCAN compares all identifier bits or if some bits are not used for comparison. This functionality is provided by the use of the mask information. The mask infor- mation defines for each bit of the identifier whether it is used for comparison or not.
Page 393: Table 10-19: Mask Operation Buffers
Chapter 10 DCAN Figure 10-49: Mask Control Register (MASKC0) (2/2) SSHT Function Single shot mode disabled Single shot mode enabled; no re-transmission when an error occurs. Transmit message will not be queued for a second transmit request when the arbitration was lost Single shot mode enabled;...
Page 394 Chapter 10 DCAN Priority of receive buffers during compare It is possible that more than one receive buffer is configured to receive a particular message. For this case an arbitrary rule for the storage of the message into one of several matching receive buffers becomes effective.
Page 395: Performance Of The Dcan
Chapter 10 DCAN 10.15.4 Performance of the DCAN For the access to the DCAN SFRs some host CPU cores (V850x) provide a programmable waiting time. After reset of the host CPU the access is typically configured to the slowest speed. The user needs to assign the fastest speed (i.e.
Page 396: Interrupt Information
Chapter 10 DCAN 10.16 Interrupt Information 10.16.1 Interrupt Vectors Each instance of the DCAN macro supports four interrupt sources as shown in the following table. Table 10-20: Interrupt Sources Function Source Error counter states (Bus off, RX and TX warning level) Error Interrupt Overrun error Wake up...
Page 397: Error Interrupt
Chapter 10 DCAN 10.16.4 Error Interrupt The error interrupt is generated when any of the following conditions are fulfilled: • Transmission error counter reaches or leaves bus off state; i.e BOFF bit of CANESn register changes its state. • Transmission error counter status (TECS bit of CANES0 register) changes its state. •...
Page 398: Power Saving Modes
Chapter 10 DCAN 10.17 Power Saving Modes 10.17.1 CPU Halt Mode CPU Halt mode is only usable when the DCAN was set to initialization state, sleep mode or stop mode beforehand. Entering the CPU Halt Mode is not allowed when the DCAN is in normal mode, i.e. online to the CAN bus.
Page 399 Chapter 10 DCAN The following example sketches the general approach on how to enter the DCAN Sleep mode. Note that the function may not return for infinite time when the CAN bus is busy. The user may apply time out controls to avoid excessive run-times.
Page 400: Dcan Stop Mode
Chapter 10 DCAN 10.17.5 DCAN Stop Mode The CPU requests this mode from DCAN. The procedure equals the request for DCAN Sleep mode. The DCAN will signal with the WAKE bit, if the request was granted or if it is not possible to enter the DCAN Stop mode due to ongoing bus activities.
Page 401: Functional Description By Flowcharts
Chapter 10 DCAN 10.18 Functional Description by Flowcharts 10.18.1 Initialization Figure 10-50: Initialization Flow Chart RESET Software Init set INIT=1 in CANC BRPRS SYNC0/1 Initilialize message and mask data MCNT MASKC Write for BRPRS Clear INIT=0 in CANC SYNC0/1 MCNT MASKC is now disabled End Initialization...
Page 402: Transmit Preparation
Chapter 10 DCAN 10.18.2 Transmit Preparation Figure 10-51: Transmit Preparation Transmit Wait or Abort or TXRQn Try other Buffer Write data Select Priority TXRQn = 1 End Transmit User’s Manual U15872EE2V1UM00...
Page 403: Abort Transmit
Chapter 10 DCAN 10.18.3 Abort Transmit Figure 10-52: Transmit Abort Transmission Abort TXAn TXRQn TXCn Transmit was successful Transmit before was aborted ABORT End Transmission Abort User’s Manual U15872EE2V1UM00...
Page 404: Handling By The Dcan
Chapter 10 DCAN 10.18.4 Handling by the DCAN Figure 10-53: Handling of Semaphore Bits by DCAN-Module Data Storage Warns that data will be changed Write DN = 1 MUC = 1 Only for buffers that are declared for mask operation Write Identifier bytes...
Page 405: Receive Event Oriented
Chapter 10 DCAN 10.18.5 Receive Event Oriented Figure 10-54: Receive with Interrupt, Software Flow Receive Interrupt scans RMES or DN bits to find message Uses CLR1 Command Clear DN bit read or process data Data was changed by CAN during the DN = 0 processing MUC = 0...
Page 406: Receive Task Oriented
Chapter 10 DCAN 10.18.6 Receive Task Oriented Figure 10-55: Receive, Software Polling Receive Polled Uses CLR1 command Clear DN bit Read or process data Data was changed by CAN during the DN = 0 processing MUC = 0 End Receive Polled User’s Manual U15872EE2V1UM00...
Page 407: Figure 10-56: Receive, Software Polling In Case Of Data New Flag Limitation
Chapter 10 DCAN Figure 10-56: Receive, Software Polling in case of Data New Flag Limitation Receive Polled Uses CLR1 command Clear DN bit Read data Wait loop Data was changed by CAN during the processing DNn = 0 MUCn = 0 End Receive Polled Some DCAN implementations for particular products have a limitation on the function of the DN flag.
Page 408: Cautions
Chapter 10 DCAN 10.18.7 Cautions DCAN Extended IDentifier Limitation Description: Under very specific conditions, using messages with ExtID within a network, messages may get lost or their transferred data can be stored in not assigned message buffers using the DCAN CAN macro. Applications only using messages with standard Identifier part, are not affected by the above described limitation.
Page 409: Chapter 11 A/D Converter
Chapter 11 A/D Converter 11.1 A/D Converter Functions The A/D converter is an 10-bit resolution converter that converts analog inputs into digital values. It can control up to 12 analog input channels (ANI0 to ANI11). This A/D converter has the following functions: A/D conversion with 10-bit resolution One channel of analog input is selected from ANI0 to ANI11, and A/D conversion is repeatedly executed with a resolution of 10 bits.
Page 410: Figure 11-2: Power-Fail Detection Function Block Diagram
Chapter 11 A/D Converter Figure 11-2: Power-Fail Detection Function Block Diagram ANI11 ANI10 ANI9 enable (by Software) ANI8 ANI7 mode (by Software) Compare ANI6 Comparator Register ANI5 ANI4 ANI3 Internal Bus ANI2 Selector ANI1 ANI0 INTAD (A/D conversion termination interrupt) (power fail / power on detection interrupt) User’s Manual U15872EE2V1UM00...
Page 411: A/D Converter Configuration
Chapter 11 A/D Converter 11.2 A/D Converter Configuration A/D converter consists of the following hardware. Table 11-1: A/D Converter Configuration Item Configuration Analog 12 channels (ANI0 to ANI11) input Successive approximation register (SAR) Register A/D converter mode register (ADCR) A/D converter mode register (ADM) Control reg- Analog input channel specification register (ADS) ister...
Page 412 Chapter 11 A/D Converter ANI0 to ANI11 pins These are eight analog input pins to input analog signals to the A/D converter. ANI0 to ANI11 are alternate-function pins that can also be used for digital input. Caution: Use ANI0 to ANI11 input voltages within the specification range. If a voltage higher than AV or lower than AV is applied, the conversion value of that channel...
Page 413: A/D Converter Control Registers
Chapter 11 A/D Converter 11.3 A/D Converter Control Registers The following 4 types of registers are used to control A/D converter: • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • Power-fail compare mode register (PFM) •...
Page 414: Figure 11-3: A/D Converter Mode Register (Adm) Format
Chapter 11 A/D Converter A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, conversion start/stop and external trigger. This register can be read/written in 8 bit or 1-bit units. Possible values for ADM for secure conversion result are defined in the Data Sheet (DS). Figure 11-3: A/D Converter Mode Register (ADM) Format Initial Symbol...
Page 415: Figure 11-4: Analog Input Channel Specification Register (Ads) Format
Chapter 11 A/D Converter Analog input channel specification register (ADS) This register specifies the analog voltage input port for A/D conversion. This register can be read/written in 8 bit units. Figure 11-4: Analog Input Channel Specification Register (ADS) Format Initial Symbol Address value...
Page 416: Figure 11-5: Power-Fail Compare Mode Register (Pfm) Format
Chapter 11 A/D Converter Power-fail compare mode register (PFM) The power-fail compare mode register (PFM) controls a comparison operation. This register can be read/written in 8 bit or 1-bit units. Figure 11-5: Power-Fail Compare Mode Register (PFM) Format Initial Symbol Address value PFEN...
Page 417: Figure 11-7: A/D Conversion Result Registers (Adcr)
Chapter 11 A/D Converter A/D conversion result register (ADCR) The ADCR register is a 10-bit register that holds the result of the A/D conversion. When reading 16 bits of data of an A/D conversion result from an ADCR register, only the upper 10 bits are valid and the lower 6 bits are always read 0.
Page 418: A/D Converter Operations
Chapter 11 A/D Converter 11.4 A/D Converter Operations 11.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 419: Figure 11-8: Basic Operation Of 10-Bit A/D Converter
Chapter 11 A/D Converter Figure 11-8: Basic Operation of 10-bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (to 0) by software.
Page 420: Input Voltage And Conversion Results
Chapter 11 A/D Converter 11.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression: INT (V x 1024 + 0.5)
Page 421: Figure 11-9: Relation Between Analog Input Voltage And A/D Conversion Result
Chapter 11 A/D Converter Figure 11-9: Relation between Analog Input Voltage and A/D Conversion Result 1023 1022 1021 A/D conversion result (ADCR) 2047 2045 1022 2046 1023 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 Input voltage/AV User’s Manual U15872EE2V1UM00...
Page 422: A/D Converter Operation Mode
Chapter 11 A/D Converter 11.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from among ANI0 to ANI11 with the analog input channel specification register (ADS) and A/D conversion is performed.
Page 423: Figure 11-10: A/D Conversion
Chapter 11 A/D Converter Figure 11-10: A/D Conversion ADM rewrite ADCS = 1 ADS1 rewrite ADCS = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended; Stop Conversion results are not stored ADCR ANIn ANIn ANIm INTAD (PFEN = 0) INTAD (PFEN = 1) First conversion Condition satisfied...
Page 424: A/D Converter Precautions
Chapter 11 A/D Converter 11.5 A/D Converter Precautions Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by setting the ADCS bit of the A/D converter mode register (ADM) to “0” to stop conver- sion, as shown in the following figure.
Page 425: Figure 11-12: Analog Input Pin Handling
Chapter 11 A/D Converter Figure 11-12: Analog Input Pin Handling If there is a possibility that noise equal to or higher than AV equal to or lower than AV may enter, clamp with a diode with a small V value (0.3 V or lower). Reference voltage input...
Page 426: Figure 11-13: A/D Conversion End Interrupt Request Generation Timing
Chapter 11 A/D Converter Figure 11-13: A/D Conversion End Interrupt Request Generation Timing ADS rewrite ADS rewrite ADIF is set but ANIm conversion (start of ANIm conversion) has not ended. (start of ANIn conversion) A/D conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn...
Page 427: Chapter 12 Port Functions
• Input or output can be specified in bit units. 12.2 Port Configuration The V850ES/GB1 Venus incorporates a total of 84 input/output ports, named ports P0 through P7, PCS, PCT, PCM, PDL and PDH. The configuration is shown below. Figure 12-1: Port Configuration...
Page 428: Table 12-1: Functions Of Each Port
Chapter 12 Port Functions Functions of each port The V850ES/GB1 has the ports shown below. Any port can operate in 8-bit or 1-bit units and can provide a variety of controls. Moreover, besides its function as a port, each has functions as the input/output pins of on-chip peripheral I/O in control mode.
Page 429: Table 12-2: Functions Of Each Port Pin On Reset And Registers Concerned By The Use Of The Port
Chapter 12 Port Functions Functions of each port pin on reset and registers that set port or control mode Table 12-2: Functions of each port pin on reset and registers concerned by the use of the port (1/3) Pin Function Port Mode Setting Pin Name...
Page 430 Chapter 12 Port Functions Table 12-2: Functions of each port pin on reset and registers concerned by the use of the port (2/3) Pin Function Port Mode Setting Pin Name after Reset If not used Name Registers Single Chip Mode Input: Independently connect to or V via resistor...
Page 431 Chapter 12 Port Functions Table 12-2: Functions of each port pin on reset and registers concerned by the use of the port (3/3) Pin Function Port Mode Setting Pin Name after Reset If not used Name Registers Single Chip Mode PDL0 PDL1 PDL2...
Page 432: Port Block Diagram
Chapter 12 Port Functions 12.2.1 Port block diagram Figure 12-2: Port Structure Type A Block Diagram PUmn PUmn DD51 PMCmn PMCmn PMmn P-ch PMmn Peripheral output Pxmn Peripheral input Address Only for port with alternate function Remark: There are following values: for m = 0, n = 0, 1, 2, 3, 4, 5, 6 for m = 1,...
Page 433: Figure 12-3: Port Structure Type B Block Diagram
Chapter 12 Port Functions Figure 12-3: Port Structure Type B Block Diagram PUmn DD51 PUmn PMmn P-ch PMmn Pxmn Address Remark: There are following values: for m = 1, n = 5 for m = 2, n = 5 for m = 5, n = 0, 1, 2, 3, 6, 7 User’s Manual U15872EE2V1UM00...
Page 434: Figure 12-4: Port Structure Type C Block Diagram
Chapter 12 Port Functions Figure 12-4: Port Structure Type C Block Diagram Remark: There are following values: for m = 7, n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 for m = NMI, n = 0 User’s Manual U15872EE2V1UM00...
Page 435: Figure 12-5: Port Structure Type D Block Diagram
Chapter 12 Port Functions Figure 12-5: Port Structure Type D Block Diagram PMmn PMmn Address Remark: There are following values: for m = CS, n = 0, 1 for m = CT, n = 0, 1, 4, 6 for m = DH, n = 0, 1, 2, 3, 4, 5 for m = CM, n = 0, 2, 3 for m = DL,...
Page 436: Figure 12-6: Port Structure Type E Block Diagram
Chapter 12 Port Functions Figure 12-6: Port Structure Type E Block Diagram PCM1 PMCCM1 PCM1 PMCM1 CLKOUT PCM1 PCM1 PMC1 PCM1 Address User’s Manual U15872EE2V1UM00...
Page 437: Pin Functions Of Each Port
Chapter 12 Port Functions 12.3 Pin Functions of Each Port 12.3.1 Port 0 Port 0 is a 7-bit input/output port in which control, input or output can be specified in 1-bit units. P0 can be read or written in 8- or 1-bit units. Figure 12-7: Port 0 (P0) Address At Reset...
Page 438: Figure 12-8: Port 0 Mode Control Register (Pmc0)
Chapter 12 Port Functions Operation in control mode The use as alternate function is defined by the Port 0 Mode Control Register PMC0. The PMC0 register can be read or written in 8-bit or 1-bit units. Figure 12-8: Port 0 Mode Control Register (PMC0) Address At Reset PMC0...
Page 439: Figure 12-9: Port 0 Mode Register (Pm0)
Chapter 12 Port Functions Operation in port mode When used as input/output port (PMC0n = 0), each bit P0n can be set in input/output mode using the port 0 mode register (PM0). Port 0 mode register (PM0) This register can be read or written in 8-bit or 1-bit units. Figure 12-9: Port 0 Mode Register (PM0) Address At Reset...
Page 440: Port 1
Chapter 12 Port Functions 12.3.2 Port 1 Port 1 is a 6-bit input/output port in which control, input or output can be specified in 1-bit units. P1 can be read or written in 8-bit or 1-bit units. Figure 12-11: Port 1 (P1) Address At Reset FFFF F402H...
Page 441: Figure 12-12: Port 1 Mode Control Register (Pmc1)
Chapter 12 Port Functions Operation in control mode The use as alternate function is defined by the Port 1 Mode Control Register PMC1. The PMC1 register can be read or written in 8-bit or 1-bit units. Figure 12-12: Port 1 Mode Control Register (PMC1) Address At Reset PMC1...
Page 442: Figure 12-13: Port 1 Mode Register (Pm1)
Chapter 12 Port Functions Operation in port mode When used as input/output port (PMC1n = 0), each bit P1n can be set in input/output mode using the port 1 mode register (PM1). (a) Port 1 mode register (PM1) This register can be read or written in 8-bit or 1-bit units. Figure 12-13: Port 1 Mode Register (PM1) Address At Reset...
Page 443: Port 2
Chapter 12 Port Functions 12.3.3 Port 2 Port 2 is a 6-bit input/output port in which control, input or output can be specified in 1-bit units. P2 can be read or written in 8-bit or 1-bit units. Figure 12-15: Port 2 (P2) Address At Reset FFFF F404H...
Page 444: Figure 12-16: Port 2 Mode Control Register (Pmc2)
Chapter 12 Port Functions Operation in control mode The use as alternate function is defined by the Port 2 Mode Control Register PMC2. The PMC2 register can be read or written in 8-bit or 1-bit units. Figure 12-16: Port 2 Mode Control Register (PMC2) Address At Reset PMC2...
Page 445: Figure 12-17: Port 2 Mode Register (Pm2)
Chapter 12 Port Functions Operation in port mode When used as input/output port (PMC2n = 0), each bit P2n can be set in input/output mode using the port 2 mode register (PM2). (a) Port 2 mode register (PM2) This register can be read or written in 8-bit or 1-bit units. Figure 12-17: Port 2 Mode Register (PM2) Address At Reset...
Page 446: Port 3
Chapter 12 Port Functions 12.3.4 Port 3 Port 3 is a 5-bit input/output port in which control, input or output can be specified in 1-bit units. P3 can be read or written in 8-bit or 1-bit units. Figure 12-19: Port 3 (P3) Address At Reset FFFF F406H...
Page 447: Figure 12-20: Port 3 Mode Control Register (Pmc3)
Chapter 12 Port Functions Operation in control mode The use as alternate function is defined by the Port 3 Mode Control Register PMC3. The PMC3 register can be read or written in 8-bit or 1-bit units. Figure 12-20: Port 3 Mode Control Register (PMC3) Address At Reset PMC3...
Page 448: Figure 12-21: Port 3 Mode Register (Pm3)
Chapter 12 Port Functions Operation in port mode When used as input/output port (PMC3n = 0), each bit P3n can be set in input/output mode using the port 3 mode register (PM3). (a) Port 3 mode register (PM3) This register can be read or written in 8-bit or 1-bit units. Figure 12-21: Port 3 Mode Register (PM3) Address At Reset...
Page 449: Port 4
Chapter 12 Port Functions 12.3.5 Port 4 Port 4 is a 8-bit input/output port in which control, input or output can be specified in 1-bit units. P4 can be read or written in 8-bit or 1-bit units. Figure 12-23: Port 4 (P4) Address At Reset FFFF F408H...
Page 450: Figure 12-24: Port 4 Mode Control Register (Pmc4)
Chapter 12 Port Functions Operation in control mode The use as alternate function is defined by the Port 4 Mode Control Register PMC4. The PMC4 register can be read or written in 8-bit or 1-bit units. Figure 12-24: Port 4 Mode Control Register (PMC4) Address At Reset PMC4...
Page 451: Figure 12-25: Port 4 Mode Register (Pm4)
Chapter 12 Port Functions Operation in port mode When used as input/output port (PMC4n = 0), each bit P4n can be set in input/output mode using the port 4 mode register (PM4). (a) Port 4 mode register (PM4) This register can be read or written in 8-bit or 1-bit units. Figure 12-25: Port 4 Mode Register (PM4) Address At Reset...
Page 452: Port 5
Chapter 12 Port Functions 12.3.6 Port 5 Port 5 is a 8-bit input/output port in which control, input or output can be specified in 1-bit units. P5 can be read or written in 8-bit or 1-bit units. Figure 12-27: Port 5 (P5) Address At Reset FFFF F40AH...
Page 453: Figure 12-29: Port 5 Mode Register (Pm5)
Chapter 12 Port Functions Operation in port mode When used as input/output port (PMC5n = 0), each bit P5n can be set in input/output mode using the port 5 mode register (PM5). (a) Port 5 mode register (PM5) This register can be read or written in 8-bit or 1-bit units. Figure 12-29: Port 5 Mode Register (PM5) Address At Reset...
Page 454: Port 7
Chapter 12 Port Functions 12.3.7 Port 7 Port 7 is a 12-bit input port. P7 can be read in 16-bit, 8-bit or 1-bit units. A read operation from P7 returns the input pin P7n levels (n = 0 to 11), with upper 4 bits forced to 0. P7H is the high-order byte of the P7 register, whose 4 upper bits are always 0.
Page 455 Chapter 12 Port Functions Operation in control mode Port Alternate Pin Name Remarks ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 Port 7 Analog/Digital Converter inputs ANI6 ANI7 ANI8 ANI9 P710 ANI10 P711 ANI11 Port 7 is set in input mode at any time. Operation in port mode Port 7 is a 12-bit input port which can be read with 16-bit, 8-bit or 1-bit wise operations.
Page 456: Port Nmi
Chapter 12 Port Functions 12.3.8 Port NMI Port NMI is a 8-bit input port. When read, PNMI shows the level of the NMI input pin in bit 0 (PNMI0). The others 7 bits are always read as 0. Figure 12-32: Port NMI (PNMI) Address At Reset PNMI...
Page 457: Port Dl
Chapter 12 Port Functions 12.3.9 Port DL Port DL is a 16-bit input/output port in which input or output can be specified in 1-bit units. PDL can be read or written in 16-bit, 8-bit or 1-bit units. Figure 12-33: Port DL (PDL, PDLL and PDLH) Address At Reset PDL15...
Page 458: Figure 12-34: Port Dl Mode Register (Pmdl, Pmdll And Pmdlh)
Chapter 12 Port Functions Operation in port mode Each bit PDLn can be set in input/output mode using the port DL mode register (PMDL). (a) Port DL mode register (PMDL) This register can be read or written in 16-bit, 8-bit or 1-bit units. Figure 12-34: Port DL mode register (PMDL, PMDLL and PMDLH) Address At Reset...
Page 459: Port Dh
Chapter 12 Port Functions 12.3.10 Port DH Port DH is a 6-bit input/output port in which input or output can be specified in 1-bit units. PDH can be read or written in 8-bit or 1-bit units. Figure 12-35: Port DH (PDH) Address At Reset PDH5...
Page 460: Port Cs
Chapter 12 Port Functions 12.3.11 Port CS Port CS is a 2-bit input/output port in which input or output can be specified in 1-bit units. PCS can be read or written in 8-bit or 1-bit units. Figure 12-37: Port CS (PCS) Address At Reset PCS1...
Page 461: Port Ct
Chapter 12 Port Functions 12.3.12 Port CT Port CT is a 4-bit input/output port in which input or output can be specified in 1-bit units. PCT can be read or written in 8-bit or 1-bit units. Figure 12-39: Port CT (PCT) Address At Reset PCT6...
Page 462: Port Cm
Chapter 12 Port Functions 12.3.13 Port CM Port CM is a 4-bit input/output port in which input or output can be specified in 1-bit units. PCM can be read or written in 8-bit or 1-bit units. Figure 12-41: Port CM (PCM) Address At Reset PCM3...
Page 463: Figure 12-43: Port Cm Mode Register (Pmcm)
Chapter 12 Port Functions Operation in port mode Each bit PCMn can be set in input/output mode using the port CM mode register (PMCM). (a) Port CM mode register (PMCM) This register can be read or written in 8-bit or 1-bit units. Figure 12-43: Port CM mode register (PMCM) Address At Reset...
Page 464 [MEMO] User’s Manual U15872EE2V1UM00...
Page 465: Chapter 13 Reset Function
Chapter 13 RESET Function 13.1 Overview The following reset functions are available. • Reset function by RESET pin input • Reset function by overflow of the watchdog timer (WDTRES) When the RESET pin goes high, the reset status is released, and the CPU starts executing the pro- gram.
Page 466: Operation
Chapter 13 RESET Function 13.3 Operation The system is reset, initializing each hardware unit, when a low level is input to the RESET pin or if watchdog timer overflows (WDTRES). While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power consumption of the system can be reduced.
Page 467: Ram Usage After Reset Release
Chapter 13 RESET Function 13.4 RAM Usage After RESET Release The internal firmware uses part of the internal RAM after the internal system reset is released. There- fore the contents of some areas of the RAM are not retained even when power-on reset is executed. The possible used RAM areas after RESET are: Table 13-2: RAM Usage after RESET Release Part number (RAM)
Page 468: Figure 13-3: Operation On Power Application
Chapter 13 RESET Function Figure 13-3: Operation on Power Application Initialized to f /8 operation RESET Analog delay Internal system reset signal Oscillation stabilization time count Overflow of OSTS (timer for oscillation stabilization) User’s Manual U15872EE2V1UM00...
Page 469: Chapter 14 Rom Correction Function
Chapter 14 ROM Correction Function 14.1 Overview The ROM correction function is used to replace part of the program in the mask ROM with a program in internal RAM. By using this function, instruction bugs found in the mask ROM can be corrected at up to four places. Figure 14-1: Block Diagram of ROM Correction Instruction address bus Correction...
Page 470: Control Registers
Chapter 14 ROM Correction Function 14.2 Control Registers 14.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) These registers are used to set the first address (correction address) of the instruction to be corrected in the ROM. The program can be corrected at up to four places because four correction address register n (CORADn) are provided (n = 0 to 3).
Page 471: Correction Control Register (Corcn)
Chapter 14 ROM Correction Function 14.2.2 Correction control register (CORCN) This register disables or enables the correction operation of the correction address register n (CORADn) (n = 0 to 3). Each channel can be enabled or disabled by this register. This register is set by using an 8-bit or 1-bit memory manipulation instruction.
Page 472: Rom Correction Operation And Program Flow
Chapter 14 ROM Correction Function 14.3 ROM Correction Operation and Program Flow If the address to be corrected and the fetch address of the internal ROM match, the fetch code is replaced by the DBTRAP instruction. When the DBTRAP instruction is executed, execution branches to address 00000060H. Software processing after branching causes the result of ROM correction to be judged (the fetch address and ROM correction operation are confirmed) and execution to branch to the correction software.
Page 473: Figure 14-4: Rom Correction Operation And Program Flow
Chapter 14 ROM Correction Function Figure 14-4: ROM Correction Operation and Program Flow Reset & start Initialize microcontroller Read data for setting ROM correction from external memory Set CORADn register Set CORCN register Fetch address = CORADn Change fetch code to DBTRAP instruction Execute fetch code DBTRAP instruction...
Page 474 [MEMO] User’s Manual U15872EE2V1UM00...
Page 475: Chapter 15 Flash Memory (Μpd70F322X Only)
Chapter 15 Flash Memory (µPD70F322x only) The V850ES/GB1 VENUS provides a 128 KB flash memory. An instruction fetch from the flash memory takes one clock. The flash memory can be programmed using a dedicated flash writer. The following can be considered as the development environment and the application using a flash memory: •...
Page 476: Writing By Flash Writer
Chapter 15 Flash Memory (µPD70F322x only) 15.2 Writing by Flash writer Writing can be performed either on-board or off-board by the dedicated flash writer. On-board programming The contents of the flash memory is rewritten after the µPD70F322x is mounted on the target sys- tem.
Page 477: Communication System
Chapter 15 Flash Memory (µPD70F322x only) 15.4 Communication System The communication between the dedicated flash writer and the µPD70F322x is performed by serial communication using CSI. Transfer rate: up to 1.0 Mbps (MSB first) Figure 15-2: Flash Writer Communication via CSI0 DD50 SS30 SS31...
Page 478: Figure 15-3: Flash Writer Communication Via Uart
Chapter 15 Flash Memory (µPD70F322x only) UART Transfer rate: 4,800 bps to 76,800 bps (LSB first) Figure 15-3: Flash Writer Communication via UART SS31 SS30 RESET RESET P13/INTP7/RXD60 Dedicated flash programmer µPD70F322x P12/TXD60 User’s Manual U15872EE2V1UM00...
Page 479: Flash Programming Circuitry
Chapter 15 Flash Memory (µPD70F322x only) 15.5 Flash Programming Circuitry The following schematic shows the minimal circuitry. The V pin have to be connected via a pull down resistor of 10 K to ground. Figure 15-4: Minimal Circuitry for Flash programming Flash Master Cable 1...
Page 480: Pin Handling
Chapter 15 Flash Memory (µPD70F322x only) 15.6 Pin Handling When performing on-board writing, all required signals on the target system have to be made accessi- ble to the dedicated flash writer. Also, it has to be ensured that the modes are set correctly and the V signal, which is required to enter the programming mode can be controlled by the flash writer.
Page 481: Serial Interface Pins
Chapter 15 Flash Memory (µPD70F322x only) 15.6.2 Serial interface pins The following shows the pins used by the serial interface. Table 15-1: Serial interface pins Serial Interface Pins Used CSI0 SO00, SI00, SCK00 UART TXD60, RXD60 When connecting a dedicated flash writer to a serial interface pin, which is connected to other devices on-board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc.
Page 482: Figure 15-7: Malfunction Of Other Input Pins
Chapter 15 Flash Memory (µPD70F322x only) Malfunction of the other device When connecting a flash writer (output or input) to a serial interface pin (input or output) con- nected to another device (input), the signal output to the other device may cause the device to malfunction.
Page 483: Reset Pin
Chapter 15 Flash Memory (µPD70F322x only) 15.6.3 RESET pin When connecting the reset signals of the dedicated flash writer to the RESET pin which is connected to the reset signal generation circuit on-board, conflict of signals may happen. To avoid the conflict of sig- nals, isolate the connection to the reset signal generation circuit.
Page 484: Programming Method
Chapter 15 Flash Memory (µPD70F322x only) 15.7 Programming Method 15.7.1 Flash memory control To manipulate the flash memory the µPD70F322x has to operate in a special flash memory program- ming mode. This mode can be entered either by applying the programming voltage of 7.8 V to the V before the reset is release.
Page 485 Appendix A Instruction Set List A.1 Convention (a) Register symbols used to describe operands Register Symbol Explanation reg1 General registers: Used as source registers General registers: Used mainly as destination registers. Also used as reg2 source register in some instructions. General registers: Used mainly to store the remainders of division reg3 results and the higher order 3 bits of multiplication results.
Page 486 Appendix A Instruction Set List (c) Register symbols used in operation Register Symbol Explanation ← Input for GR [ ] General register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 487 Appendix A Instruction Set List (e) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (f) Condition codes Condition Condition Code Name Condition Formula Explanation (cccc)
Page 488 Appendix A Instruction Set List A.2 Instruction Set (In Alphabetical Order) (1/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT × × × × reg1,reg2 rrrrr001110RRRRR GR[reg2]←GR[reg2] + GR[reg1] × × × × imm5,reg2 rrrrr010010iiiii GR[reg2]←GR[reg2] + sign-extend(imm5) rrrrr110000RRRRR ×...
Page 489 Appendix A Instruction Set List (2/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT 0000011110dddddd disp22 PC←PC + sign-extend(disp22) ddddddddddddddd0 Note 7 adr←GR[reg1] + sign-extend(disp16) Note rrrrr111000RRRRR LD.B disp16[reg1],reg2 GR[reg2]←sign-extend(Load-memory(adr,Byte)) dddddddddddddddd rrrrr11110bRRRRR adr←GR[reg1] + sign-extend(disp16) Note LD.BU disp16[reg1],reg2 dddddddddddddd1...
Page 490 Appendix A Instruction Set List (3/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT if PSW.EP=1 then PC ←EIPC PSW ←EIPSW else if PSW.NP=1 0000011111100000 RETI then PC ←FEPC 0000000101000000 PSW ←FEPSW else PC←EIPC PSW ←EIPSW GR[reg2]←GR[reg2] arithmetically shift right rrrrr111111RRRRR ×...
Page 491 Appendix A Instruction Set List (4/4) Execution Flags Clock Mnemonic Operand Opcode Operation CY OV S Z SAT adr←(PC+2) + (GR [reg1] logically shift left by 1) PC←(PC+2) + (sign-extend SWITCH reg1 00000000010RRRRR (Load-memory (adr,Half-word))) logically shift left by 1 GR[reg1]←sign-extend reg1 00000000101RRRRR...
Page 492 Appendix A Instruction Set List 16. ff = 00: Load sp in ep. 10: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18.
Page 493 Appendix B Index A/D conversion result registers 0 to 11 ..........415 ADCR0 to ADCR11.
Page 494 Appendix B Index REC0 ............... . 349 RMES0 .
Page 495: Table C-1: Revision History
Appendix C Revision History The following shows the revision history up to present. Application portions signifies the chapter of each edition. Table C-1: Revision History (1/2) Edition No. Major items revised Revised Sections Modification of driver type for NMI pin Modification of Pin Name P11/SO00 Chapter 2.1, Table 2-1 Modification of Pin Name P21/TXD61...
Page 496 Appendix C Revision History Table C-1: Revision History (2/2) Edition No. Major items revised Revised Sections Chapter 12.3.10, Modification of Figure 12-35 and 12-36: Bits Figures 12-35 and 12-36 Modification of Figure 15-4: Connection REGC0/REGC1 Chapter 15.5, Figure 15-4 EE2V1 Add RAM usage after RESET release Chapter 13.3 and 13.4 User’s Manual U15872EE2V1UM00...
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