Renesas mPD70F3480 Manuals

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Renesas mPD70F3480 User Manual (1600 pages)

32-bit Single-Chip Microcontroller

Brand: Renesas | Category: Microcontrollers | Size: 11 MB

Table of Contents
10
Chapter 1 Introduction

24
- General
  24
- Features
  27
- Application Fields
  29
- Ordering Information
  30
- V850E/Sj3-H
  30
- V850E/Sk3-H
  31
- Pin Configuration (Top View)
  31
- V850E/Sj3-H
  31
- V850E/Sk3-H
  34
- Function Block Configuration
  37
- Internal Block Diagram
  37
- Internal Units
  41
Chapter 2 Pin Functions

45
Chapter 3 Cpu Function

76
- Features
  76
- CPU Register Set
  77
- Program Register Set
  78
- System Register Set
  79
- Operation Modes
  86
- Specifying Operation Mode
  86
- Address Space
  87
- CPU Address Space
  87
- Wraparound of CPU Address Space
  88
- Memory Map
  89
- Areas
  93
- Recommended Use of Address Space
  102
- Peripheral I/O Registers
  106
- Programmable Peripheral I/O Registers
  125
- Special Registers
  126
- Cautions
  130
Chapter 4 Port Functions

135
- Features
  135
- V850E/Sj3-H
  135
- V850E/Sk3-H
  135
- Basic Port Configuration
  136
- V850E/Sj3-H
  136
- V850E/Sk3-H
  137
- Port Configuration
  138
- Port 0
  143
- Port 1
  147
- Port 2 (V850E/SK3-H Only)
  148
- Port 3
  150
- Port 4
  159
- Port 5
  163
- Port 6
  169
- Port 7
  177
- Port 8
  179
- Port 9
  184
- Port 13 (V850E/SK3-H Only)
  192
- Port 14 (V850E/SK3-H Only)
  193
- Port 15 (V850E/SK3-H Only)
  194
- Port CD
  196
- Port CM
  198
- Port CS
  200
- Port CT
  202
- Port DH
  204
- Port DL
  206
- Block Diagrams
  209
- Port Register Settings When Alternate Function Is Used
  272
- Cautions
  286
- Cautions on Setting Port Pins
  286
- Cautions on Bit Manipulation Instruction for Port N Register (Pn)
  289
- Cautions on On-Chip Debug Pins
  290
- Cautions on P05/INTP2/DRST Pin
  290
- Cautions on P53 Pin When Power Is Turned on
  290
- Hysteresis Characteristics
  290
- Cautions on Separate Bus Mode
  291
- Cautions on Reading Port N Registers (Pn: N = 3 to 5, 8) (V850E/SJ3-H Only)
  291
- Cautions on Setting Port N Mode Control Registers (Pmcn: N = 3 to 5, 8)
  291
Chapter 5 Bus Control Function

292
- Features
  292
- Bus Control Pins
  293
- Pin Status When Internal ROM, Internal RAM, On-Chip Peripheral I/O, or Expanded Internal RAM Is Accessed
  294
- Pin Status in each Operation Mode
  294
- Memory Block Function
  295
- Chip Select Control Function
  298
- External Bus Interface Mode Control Function
  303
- Bus Access
  304
- Number of Clocks for Access
  304
- Bus Size Setting Function
  305
- Access by Bus Size
  306
- Wait Function
  313
- Programmable Wait Function
  313
- External Wait Function
  316
- Relationship between Programmable Wait and External Wait
  317
- Programmable Address Wait Function
  318
- Idle State Insertion Function
  320
- Bus Hold Function
  321
- Functional Outline
  321
- Bus Hold Procedure
  322
- Operation in Power Save Mode
  322
- Bus Priority
  323
- Bus Timing
  324
Chapter 6 Clock Generation Function

330
- Overview
  330
- Clock Mode
  331
- Clock Mode 1
  331
- Clock Mode 2
  331
- Clock Mode 3
  331
- Clock Mode 4
  343
- Clock Mode Setting
  346
- Registers
  347
- Operation
  357
- Operation of each Clock
  357
- Clock Output Function
  358
- Procedure for Setting Clock Generation Function for Using Clock Mode 1
  359
- Procedure for Setting Clock Generation Function for Using Clock Modes 2, 3, and 4
  362
Chapter 7 16-Bit Timer/Event Counter P (Tmp)

366
- Overview
  366
- TMP0 to TMP6
  366
- TMP7 and TMP8
  366
- Functions
  367
- TMP0 to TMP6
  367
- TMP7 and TMP8
  367
- Configuration
  368
- TMP0 to TMP6
  368
- TMP7 and TMP8
  371
- Registers
  374
- Timer Output Operations
  396
- Operation
  397
- Interval Timer Mode (Tpnmd2 to Tpnmd0 Bits = 000)
  406
- External Event Count Mode (Tpnmd2 to Tpnmd0 Bits = 001)
  418
- External Trigger Pulse Output Mode (Tpnmd2 to Tpnmd0 Bits = 010)
  427
- One-Shot Pulse Output Mode (Tpnmd2 to Tpnmd0 Bits = 011)
  439
- PWM Output Mode (Tpnmd2 to Tpnmd0 Bits = 100)
  446
- Free-Running Timer Mode (Tpnmd2 to Tpnmd0 Bits = 101)
  455
- Pulse Width Measurement Mode (Tpnmd2 to Tpnmd0 Bits = 110)
  473
- Encoder Count Function (Only for TMP7 and TMP8)
  479
- Encoder Compare Mode (Tpmmd3 to Tpmmd0 Bits = 1000)
  493
- Selector Function
  501
- Cautions
  503
Chapter 8 16-Bit Timer/Event Counter Q (Tmq)

504
- Overview
  504
- Functions
  504
- Configuration
  505
- Registers
  508
- Timer Output Operations
  523
- Operation
  524
- Interval Timer Mode (TQ0MD2 to TQ0MD0 Bits = 000)
  532
- External Event Count Mode (TQ0MD2 to TQ0MD0 Bits = 001)
  543
- External Trigger Pulse Output Mode (TQ0MD2 to TQ0MD0 Bits = 010)
  553
- One-Shot Pulse Output Mode (TQ0MD2 to TQ0MD0 Bits = 011)
  566
- PWM Output Mode (TQ0MD2 to TQ0MD0 Bits = 100)
  575
- Free-Running Timer Mode (TQ0MD2 to TQ0MD0 Bits = 101)
  586
- Pulse Width Measurement Mode (TQ0MD2 to TQ0MD0 Bits = 110)
  607
- Selector Function
  612
- Cautions
  613
Chapter 9 16-Bit Interval Timer M (Tmm)

614
- Overview
  614
- Configuration
  615
- Register
  617
- Operation
  618
- Interval Timer Mode
  618
- Cautions
  622
Chapter 10 Watch Functions

623
- Overview
  623
- Configuration
  624
- Prescaler 3
  625
- Function
  625
- Configuration
  625
- Registers
  626
- Watch Timer Functions
  628
- Functions
  628
- Configuration
  628
- Control Registers
  630
- Operation
  632
- Real-Time Counter (RTC)
  634
- Function
  634
- Configuration
  635
- Registers
  638
- Operation
  651
Chapter 11 Functions of Watchdog Timer 2

663
- Functions
  663
- Configuration
  664
- Registers
  665
- Operation
  669
Chapter 12 Real-Time Output Function (Rto)

670
- Function
  670
- Configuration
  671
- Registers
  673
- Operation
  675
- Usage
  676
- Cautions
  676
Chapter 13 A/D Converter

677
- Overview
  677
- Functions
  677
- Configuration
  678
- Registers
  681
- Operation
  692
- Basic Operation
  692
- Conversion Operation Timing
  693
- Trigger Mode
  694
- Operation Mode
  696
- Power-Fail Compare Mode
  700
- Cautions
  705
- How to Read A/D Converter Characteristics Table
  710
Chapter 14 D/A Converter

714
- Functions
  714
- Configuration
  714
- Registers
  715
- Operation
  717
- Operation in Normal Mode
  717
- Operation in Real-Time Output Mode
  717
- Cautions
  718
Chapter 15 Asynchronous Serial Interface a (Uarta)

719
- Port Settings of UARTA0 to UARTA5
  719
- For V850E/SJ3-H
  719
- For V850E/SK3-H
  721
- Features
  723
- Configuration
  724
- Registers
  727
- Interrupt Request Signals
  734
- Operation
  735
- Data Format
  735
- SBF Transmission/Reception Format
  737
- SBF Transmission
  739
- SBF Reception
  740
- UART Transmission
  741
- Continuous Transmission Procedure
  742
- UART Reception
  744
- Reception Errors
  745
- Parity Types and Operations
  747
- Receive Data Noise Filter
  748
- Dedicated Baud Rate Generator
  749
- Cautions
  759
Chapter 16 Asynchronous Serial Interface B (Uartb)

761
- Features
  761
- Configuration
  762
- Control Registers
  766
- Interrupt Request Signals
  786
- Control Modes
  789
- Operation
  793
- Data Format
  793
- Transmit Operation
  794
- Continuous Transmission Operation
  797
- Receive Operation
  798
- Reception Error
  801
- Parity Types and Corresponding Operation
  802
- Receive Data Noise Filter
  803
- Dedicated Baud Rate Generator (BRG)
  805
- Control Flow
  811
- Cautions
  820
Chapter 17 3-Wire Variable-Length Serial I/O B (Csib)

822
Chapter 18 3-Wire Variable-Length Serial I/O E (Csie)

880
- Port Setting of CSIE0 and CSIE1
  880
- Pd70F3931, 70F3932, 70F3933)
  880
- V850E/Sk3-H
  881
- Features
  882
- Configuration
  883
- Control Registers
  887
- Baud Rate Generator N (Brgn)
  897
- Operation
  899
- How to Use
  920
- Cautions
  927
Chapter 19 I C Bus

929
- Port Settings of I C00 to I C05
  929
- For V850E/SJ3-H
  929
- For V850E/SK3-H
  931
- Features
  933
- Configuration
  934
- Registers
  938
- I C Bus Mode Functions
  956
- Pin Configuration
  956
- C Bus Definitions and Control Methods
  957
- Start Condition
  958
- Addresses
  959
- Transfer Direction Specification
  960
- Ack
  961
- Stop Condition
  962
- Wait State
  963
- Wait State Cancellation Method
  965
- I C Interrupt Request Signals (Intiicn)
  966
- Master Device Operation
  967
- Slave Device Operation (When Receiving Slave Address (Address Match))
  970
- Slave Device Operation (When Receiving Extension Code)
  974
- Operation Without Communication
  978
- Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
  979
- Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
  981
- Interrupt Request Signal (Intiicn) Generation Timing and Wait Control
  988
- Address Match Detection Method
  989
- Error Detection
  989
- Extension Code
  990
- Arbitration
  991
- Wakeup Function
  992
- Communication Reservation
  993
- When Communication Reservation Function Is Enabled (Iicfn.iicrsvn Bit = 0)
  993
- When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
  997
- Cautions
  998
- Communication Operations
  1000
- Master Operation in Single Master System
  1001
- Master Operation in Multimaster System
  1002
- Slave Operation
  1005
- Timing of Data Communication
  1009
CHAPTER 20 Iebus CONTROLLER

1016
- Functions
  1016
- Communication Protocol of Iebus
  1016
- Determination of Bus Mastership (Arbitration)
  1017
- Communication Mode
  1017
- Communication Address
  1017
- Broadcast Communication
  1018
- Transfer Format of Iebus
  1018
- Transfer Data
  1028
- Bit Format
  1030
- Configuration
  1031
- Registers
  1033
- Interrupt Operations of Iebus Controller
  1063
- Interrupt Control Block
  1063
- Example of Identifying Interrupt
  1065
- Interrupt Source List
  1068
- Communication Error Source Processing List
  1069
- Interrupt Request Signal Generation Timing and Main CPU Processing
  1071
- Master Transmission
  1071
- Master Reception
  1073
- Slave Transmission
  1075
- Slave Reception
  1077
- Interval of Occurrence of Interrupt Request Signal for Iebus Control
  1079
- Caution
  1083
Chapter 21 Can Controller

1084
- Overview
  1084
- Features
  1084
- Overview of Functions
  1085
- Configuration
  1086
- CAN Protocol
  1087
- Frame Format
  1087
- Frame Types
  1088
- Data Frame and Remote Frame
  1088
- Error Frame
  1096
- Overload Frame
  1097
- Functions
  1098
- Determining Bus Priority
  1098
- Bit Stuffing
  1098
- Multi Masters
  1098
- Multi Cast
  1098
- CAN Sleep Mode/Can Stop Mode Function
  1099
- Error Control Function
  1099
- Baud Rate Control Function
  1106
- Connection with Target System
  1110
- Internal Registers of CAN Controller
  1111
- CAN Controller Configuration
  1111
- Register Access Type
  1112
- Register Bit Configuration
  1146
- Registers
  1150
- Bit Set/Clear Function
  1186
- CAN Controller Initialization
  1188
- Initialization of CAN Module
  1188
- Initialization of Message Buffer
  1188
- Redefinition of Message Buffer
  1188
- Transition from Initialization Mode to Operation Mode
  1189
- Resetting Error Counter Cnerc of CAN Module
  1190
- Message Reception
  1191
- Reading Reception Data
  1192
- Receive History List Function
  1193
- Mask Function
  1195
- Multi Buffer Receive Block Function
  1197
- Remote Frame Reception
  1198
- Message Transmission
  1199
- Transmit History List Function
  1201
- Automatic Block Transmission (ABT)
  1203
- Transmission Abort Process
  1205
- Remote Frame Transmission
  1206
- Power Saving Modes
  1207
- CAN Sleep Mode
  1207
- CAN Stop Mode
  1209
- Example of Using Power Saving Modes
  1210
- Interrupt Function
  1211
- Diagnosis Functions and Special Operational Modes
  1212
- Receive-Only Mode
  1212
- Single-Shot Mode
  1213
- Self-Test Mode
  1214
- Transmission/Reception Operation in each Operation Mode
  1215
- Time Stamp Function
  1216
- Baud Rate Settings
  1218
- Bit Rate Setting Conditions
  1218
- Representative Examples of Baud Rate Settings
  1222
- Operation of CAN Controller
  1226
Chapter 22 Dma Function (Dma Controller)

1252
- Features
  1252
- Configuration
  1253
- Registers
  1254
- Transfer Targets
  1263
- Transfer Modes
  1263
- Transfer Types
  1264
- DMA Channel Priorities
  1265
- Time Related to DMA Transfer
  1265
- DMA Transfer Start Factors
  1266
- DMA Abort Factors
  1267
- End of DMA Transfer
  1267
- Operation Timing
  1267
- Cautions
  1272
Chapter 23 Crc Function

1275
- Functions
  1275
- Configuration
  1275
- Registers
  1276
- Operation
  1277
- Usage Method
  1278
Chapter 24 Interrupt/Exception Processing Function

1280
- Features
  1280
- Non-Maskable Interrupts
  1286
- Operation
  1288
- Restore
  1289
- NP Flag
  1290
- Maskable Interrupts
  1291
- Operation
  1291
- Restore
  1293
- Priorities of Maskable Interrupts
  1294
- Interrupt Control Register (Xxicn)
  1298
- Interrupt Mask Registers 0 to 6, 7L (IMR0 to IMR6, IMR7L)
  1302
- In-Service Priority Register (ISPR)
  1305
- ID Flag
  1306
- Watchdog Timer Mode Register 2 (WDTM2)
  1306
- Software Exception
  1307
- Operation
  1307
- Restore
  1308
- EP Flag
  1309
- Exception Trap
  1310
- Illegal Opcode Definition
  1310
- Debug Trap
  1312
- External Interrupt Request Input Pins (NMI and INTP0 to INTP9)
  1314
- Noise Elimination
  1314
- Edge Detection
  1314
- Interrupt Acknowledge Time of CPU
  1325
- Periods in Which Interrupts Are Not Acknowledged by CPU
  1327
- Cautions
  1327
Chapter 25 Key Interrupt Function

1328
- Function
  1328
- Register
  1329
- Cautions
  1329
Chapter 26 Standby Function

1331
- Overview
  1331
- Registers
  1332
- HALT Mode
  1336
- Setting and Operation Status
  1336
- Releasing HALT Mode
  1336
- IDLE1 Mode
  1338
- Setting and Operation Status
  1338
- Releasing IDLE1 Mode
  1338
- IDLE2 Mode
  1341
- Setting and Operation Status
  1341
- Releasing IDLE2 Mode
  1342
- Securing Setup Time When Releasing IDLE2 Mode
  1344
- STOP Mode
  1345
- Setting and Operation Status
  1345
- Releasing STOP Mode
  1345
- Securing Oscillation Stabilization Time When Releasing STOP Mode
  1348
- Subclock Operation Mode
  1349
- Setting and Operation Status
  1349
- Releasing Subclock Operation Mode
  1349
- Sub-IDLE Mode
  1352
- Setting and Operation Status
  1352
- Releasing Sub-IDLE Mode
  1353
- Status Transition Diagram
  1356
Chapter 27 Reset Functions

1360
- Overview
  1360
- Registers to Check Reset Source
  1362
- Operation
  1363
- Reset Operation Via RESET Pin
  1363
- Reset Operation by Watchdog Timer 2 (WDT2RES)
  1365
- Reset Operation by Low-Voltage Detector (LVIRES)
  1367
- Reset Operation by Clock Monitor (CLMRES)
  1368
- Operation after Reset Release
  1370
- Reset Function Operation Flow
  1371
Chapter 28 Clock Monitor

1372
- Functions
  1372
- Configuration
  1372
- Register
  1373
- Operation
  1374
Chapter 29 Low-Voltage Detector

1377
- Functions
  1377
- Configuration
  1377
- Registers
  1378
- Operation
  1380
- To Use for Internal Reset Signal (LVIRES)
  1380
- To Use for Interrupt (INTLVI)
  1381
- RAM Retention Voltage Detection Operation
  1382
- Emulation Function
  1383
Chapter 30 Regulator

1384
- Overview
  1384
- Operation
  1385
Chapter 31 Rom Correction Function

1386
- Overview
  1386
- Registers
  1387
- ROM Correction Operation and Program Flow
  1390
- Cautions
  1392
Chapter 32 Flash Memory

1393
- Features
  1393
- Memory Configuration
  1394
- Functional Outline
  1396
- Rewriting by Dedicated Flash Memory Programmer
  1399
- Programming Environment
  1399
- Communication Mode
  1400
- Flash Memory Control
  1408
- Selection of Communication Mode
  1409
- Communication Commands
  1410
- Pin Connection
  1411
- Rewriting by Self Programming
  1416
- Overview
  1416
- Features
  1417
- Standard Self Programming Flow
  1420
- Flash Functions
  1421
- Pin Processing
  1421
- Internal Resources Used
  1422
Chapter 33 Option Byte Function

1423
- Option Byte (0000007AH)
  1424
- Option Byte (0000007BH)
  1425
Chapter 34 On-Chip Debug Function

1427
- Debugging with DCU
  1428
- Connection Circuit Example
  1428
- Interface Signals
  1429
- R> 34.1.3 Maskable Functions
  1431
- Register
  1431
- Operation
  1433
- Cautions
  1434
- Debugging Without Using DCU
  1435
- Circuit Connection Examples
  1435
- Maskable Functions
  1437
- Securement of User Resources
  1438
- Cautions
  1445
- ROM Security Function
  1446
- Security ID
  1446
- Setting
  1447
Chapter 35 Electrical Specifications

1449
- Absolute Maximum Ratings
  1449
- Capacitance
  1451
- Operating Conditions
  1451
- Oscillator Characteristics
  1452
- Main Clock Oscillator Characteristics
  1452
- Subclock Oscillator Characteristics
  1455
- PLL Characteristics
  1456
- SSCG Characteristics
  1456
- Internal Oscillator Characteristics
  1456
- Regulator Characteristics
  1457
- DC Characteristics
  1458
- I/O Level
  1458
- Supply Current
  1460
- Data Retention Characteristics
  1461
- AC Characteristics
  1462
- CLKOUT Output Timing
  1463
- Bus Timing
  1464
- Basic Operation
  1477
- Flash Memory Programming Characteristics
  1488
Chapter 36 Package Drawings

1490
Chapter 37 Recommended Soldering Conditions

1492
Appendix A Development Tools

1494
- Software Package
  1499
- Language Processing Software
  1499
- Control Software
  1499
- Debugging Tools (Hardware)
  1500
- When Using IECUBE QB-V850ESX3H
  1500
- When Using On-Chip Debug Emulator IE-V850E1-CD-NW
  1503
- When Using MINICUBE QB-V850MINI
  1504
- R> A.4.4 When Using MINICUBE2 QB-MINI2
  1505
- Debugging Tools (Software)
  1506
- Embedded Software
  1507
- Flash Memory Writing Tools
  1508
Appendix B Register Index

1509
Appendix C Instruction Set List

1529
- Conventions
  1529
- Instruction Set (in Alphabetical Order)
  1532
Appendix D List of Cautions

1539
Appendix E Revision History

1594
- Major Revisions in this Edition
  1594
- Revision History of Previous Editions
  1598

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Renesas mPD70F3480 User Manual (1600 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generation Function

Chapter 7 16-Bit Timer/Event Counter P (Tmp)

Chapter 8 16-Bit Timer/Event Counter Q (Tmq)

Chapter 9 16-Bit Interval Timer M (Tmm)

Chapter 10 Watch Functions

Chapter 11 Functions of Watchdog Timer 2

Chapter 12 Real-Time Output Function (Rto)

Chapter 13 A/D Converter

Chapter 14 D/A Converter

Chapter 15 Asynchronous Serial Interface a (Uarta)

Chapter 16 Asynchronous Serial Interface B (Uartb)

Chapter 17 3-Wire Variable-Length Serial I/O B (Csib)

Chapter 18 3-Wire Variable-Length Serial I/O E (Csie)

Chapter 19 I C Bus

CHAPTER 20 Iebus CONTROLLER

Chapter 21 Can Controller

Chapter 22 Dma Function (Dma Controller)

Chapter 23 Crc Function

Chapter 24 Interrupt/Exception Processing Function

Chapter 25 Key Interrupt Function

Chapter 26 Standby Function

Chapter 27 Reset Functions

Chapter 28 Clock Monitor

Chapter 29 Low-Voltage Detector

Chapter 30 Regulator

Chapter 31 Rom Correction Function

Chapter 32 Flash Memory

Chapter 33 Option Byte Function

Chapter 34 On-Chip Debug Function

Chapter 35 Electrical Specifications

Chapter 36 Package Drawings

Chapter 37 Recommended Soldering Conditions

Appendix A Development Tools

Appendix B Register Index

Appendix C Instruction Set List

Appendix D List of Cautions

Appendix E Revision History

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