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Renesas V850ES/JF3-L User Manual

Renesas V850ES/JF3-L User Manual

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V850ES/JF3-L

32

RENESAS MCU

V850ES/JF3-L Microcontrollers

μPD70F3735

μPD70F3736

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.4.00 Sep 2010

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Summary of Contents for Renesas V850ES/JF3-L

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 How to Use This Manual Readers This manual is intended for users who wish to understand the functions of the V850ES/JF3-L and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JF3-L shown in the Organization below.
Page 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 6 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JF3-L Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/JF3-L Hardware User’s Manual This manual...
Page 7 Silicon Storage Technology, Inc. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America.
Page 8: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION........................1 General ............................1 Features............................3 Application Fields........................4 Ordering Information.........................4 Pin Configuration (Top View) ....................5 Function Block Configuration ....................7 1.6.1 Internal block diagram........................7 1.6.2 Internal units ..........................8 CHAPTER 2 PIN FUNCTIONS ........................11 List of Pin Functions .......................11 Pin States ..........................18 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins ..19 Cautions ...........................22 CHAPTER 3 CPU FUNCTION .........................23...
Page 9 Block Diagrams........................96 Port Register Settings When Alternate Function Is Used ..........124 Cautions ..........................131 4.6.1 Cautions on setting port pins ....................131 4.6.2 Cautions on bit manipulation instruction for port n register (Pn)..........134 4.6.3 Cautions on on-chip debug pins....................135 4.6.4 Cautions on P05/INTP2/DRST pin...................135 4.6.5 Cautions on P10 and P53 pins when power is turned on............135...
Page 10 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) ..........198 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) ........206 7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)..........218 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) ..............225 7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) ............234 7.5.7...
Page 11 12.3 Registers ..........................385 12.4 Operation..........................387 12.5 Usage ............................. 388 12.6 Cautions ..........................388 CHAPTER 13 A/D CONVERTER ......................389 13.1 Overview..........................389 13.2 Functions..........................389 13.3 Configuration ........................390 13.4 Registers ..........................393 13.5 Operation..........................404 13.5.1 Basic operation ........................404 13.5.2 Conversion operation timing ....................405 13.5.3...
Page 12 16.4 Registers ..........................468 16.5 Interrupt Request Signals....................475 16.6 Operation..........................476 16.6.1 Single transfer mode (master mode, transmission mode)............476 16.6.2 Single transfer mode (master mode, reception mode) .............478 16.6.3 Single transfer mode (master mode, transmission/reception mode) ........480 16.6.4 Single transfer mode (slave mode, transmission mode) ............482 16.6.5 Single transfer mode (slave mode, reception mode)..............484 16.6.6...
Page 13 17.14 Communication Reservation....................570 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......570 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......574 17.15 Cautions ..........................575 17.16 Communication Operations ....................576 17.16.1 Master operation in single master system................577 17.16.2 Master operation in multimaster system ..................577 17.16.3 Slave operation........................581 17.17 Timing of Data Communication ..................
Page 14 19.9 Cautions ..........................649 CHAPTER 20 KEY INTERRUPT FUNCTION ..................650 20.1 Function..........................650 20.2 Register ..........................651 20.3 Cautions ..........................651 CHAPTER 21 STANDBY FUNCTION ....................652 21.1 Overview..........................652 21.2 Registers ..........................654 21.3 HALT Mode..........................659 21.3.1 Setting and operation status ....................659 21.3.2 Releasing HALT mode......................659...
Page 15 24.2 Configuration ........................698 24.3 Registers ..........................699 24.4 Operation..........................701 24.4.1 To use for internal reset signal....................701 24.4.2 To use for interrupt ........................702 CHAPTER 25 CRC FUNCTION......................703 25.1 Functions..........................703 25.2 Configuration ........................703 25.3 Registers ..........................704 25.4 Operation..........................
Page 16 29.3.1 Security ID ..........................751 29.3.2 Setting .............................752 CHAPTER 30 ELECTRICAL SPECIFICATIONS ................. 753 CHAPTER 31 PACKAGE DRAWINGS ....................783 CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS............785 APPENDIX A DEVELOPMENT TOOLS....................786 Software Package ......................... 788 Language Processing Software ..................788 Control Software........................788 Debugging Tools (Hardware) ....................
Page 17: Chapter 1 Introduction
RENESAS MCU Sep 30, 2010 CHAPTER 1 INTRODUCTION The V850ES/JF3-L is one of the products in the Renesas Electronics V850 single-chip microcontrollers designed for low-power operation for real-time control applications. General The V850ES/JF3-L is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.
Page 18 V850ES/JF3-L CHAPTER 1 INTRODUCTION Table 1-1. V850ES/Jx3-L Product List Generic Name V850ES/JF3-L V850ES/JG3-L μ μ μ μ Part Number PD70F3735 PD70F3736 PD70F3737 PD70F3738 Internal Flash memory 128 KB 256 KB 128 KB 256 KB memory 8 KB 16 KB 8 KB...
Page 19: Features
V850ES/JF3-L CHAPTER 1 INTRODUCTION Features Minimum instruction execution time: 50 ns (operating with main clock (f ) of 20 MHz: V = 2.7 to 3.6 V) 200 ns (operating with main clock (f ) of 5 MHz: V = 2.2 to 3.6 V) μ...
Page 20: Application Fields
80-pin plastic LQFP (fine pitch) (12 × 12) PD70F3736GK-GAK-AX 256 KB μ 80-pin plastic LQFP (14 × 14) PD70F3735GC-GAD-AX 128 KB μ 80-pin plastic LQFP (14 × 14) PD70F3736GC-GAD-AX 256 KB Remark V850ES/JF3-L microcontrollers are lead-free products. R01UH0017EJ0400 Rev.4.00 Page 4 of 816 Sep 30, 2010...
Page 21: Pin Configuration (Top View)
V850ES/JF3-L CHAPTER 1 INTRODUCTION Pin Configuration (Top View) 80-pin plastic LQFP (fine pitch) (12 × 12) 80-pin plastic LQFP (14 × 14) μ μ PD70F3735GK-GAK-AX PD70F3735GC-GAD-AX μ μ PD70F3736GK-GAK-AX PD70F3736GC-GAD-AX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61...
Page 22 V850ES/JF3-L CHAPTER 1 INTRODUCTION Pin names A16, A17: Address bus PCM0 to PCM3: Port CM AD0 to AD15: Address/data bus PCT0, PCT1, Port CT ADTRG: A/D trigger input PCT4, PCT6: ANI0 to ANI7: Analog input PDH0, PDH1: Port DH ANO0:...
Page 23: Function Block Configuration
V850ES/JF3-L CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram Flash memory INTC Instruction INTP to INTP7 Note 1 queue HLDRQ 16-bit timer/ TIQ00 to TIQ03 Multiplier 32-bit barrel HLDAK counter Q: 16 × 16 → 32 shifter ASTB...
Page 24: Internal Units
V850ES/JF3-L CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
Page 25 Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface The V850ES/JF3-L includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire variable-length serial interface B (CSIB), and an I C bus interface (I In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins.
Page 26 V850ES/JF3-L CHAPTER 1 INTRODUCTION (19) Ports The following general-purpose port functions and control pin functions are available. Port Alternate Function 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset 1-bit I/O D/A converter analog output 8-bit I/O External interrupt, serial interface, timer I/O...
Page 27: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS List of Pin Functions The names and functions of the pins in the V850ES/JF3-L are described below. There are three types of pin I/O buffer power supplies: AV , AV , and EV .
Page 28 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/2) Pin Name Pin No. Function Alternate Function Port 0 5-bit I/O port INTP0/ADTRG Input/output can be specified in 1-bit units. INTP1 N-ch open-drain output can be specified in 1-bit units. Note INTP2/DRST 5 V tolerant.
Page 29 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Function Alternate Function Port 9 KR6/TXDA1 9-bit I/O port KR7/RXDA1 Input/output can be specified in 1-bit units. TIP21/TOP21 N-ch open-drain output can be specified in 1-bit units. SIB1/TIP20/TOP20 5 V tolerant. (only P90, P91, P96)
Page 30 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/4) Pin Name Pin No. Function Alternate Function Output Address bus for external memory PDH0 PDH1 Address bus/data bus for external memory PDL0 PDL1 PDL2 PDL3 PDL4 PDL5/FLMD1 PDL6 PDL7 PDL8 PDL9...
Page 31 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Pin No. Function Alternate Function DRST Input Debug reset input. 5 V tolerant. P05/INTP2 − − Positive power supply for external (same potential as V − − Ground potential for external (same potential as V −...
Page 32 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Pin No. Function Alternate Function SCKB0 Serial clock I/O (CSIB0 to CSIB2) N-ch open-drain output selectable. SCKB1 5 V tolerant (SCKB0, SCKB2 only). SCKB2 P55/KR5/RTP05/DMS SCL00 Serial clock I/O (I C00, I...
Page 33 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Pin No. Function Alternate Function TOQ00 Output Timer output (TMQ0) P53/SIB2/TIQ00/KR3/RTP03/ N-ch open-drain output selectable. 5 V tolerant. TOQ01 P50/TIQ01/KR0/RTP00 TOQ02 P51/TIQ02/KR1/RTP01 TOQ03 P52/TIQ03/KR2/RTP02/DDI TXDA0 Output Serial transmit data output (UARTA0 to UARTA2) N-ch open-drain output selectable.
Page 34: Pin States
V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Note 2 Pin Name When Power During Reset HALT Mode IDLE1, IDLE2, STOP...
Page 35: Pin I/O Circuit Types, I/O Buffer Power Supplies, And Connection Of Unused Pins
V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins (1/2) Alternate Function Pin No. I/O Circuit Type Recommended Connection 10-D Input: Independently connect to EV or EV via a resistor. INTP0/ADTRG Output: Leave open.
Page 36 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function Pin No. I/O Circuit Type Recommended Connection KR6/TXDA1 10-D Input: Independently connect to EV or EV via a resistor. KR7/RXDA1 Output: Leave open. TIP21/TOP21 SIB1/TIP20/TOP20 SOB1 10-G SCKB1 10-D P913 INTP4 P914...
Page 37 V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 Type 10-N Data P-ch IN/OUT IN/OUT Open drain N-ch Output disable Schmitt-triggered input with hysteresis characteristics Note Input Type 5 enable OCDM0 bit N-ch Data P-ch IN/OUT Type 11-G...
Page 38: Cautions
V850ES/JF3-L CHAPTER 2 PIN FUNCTIONS Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P10/ANO0 pin • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin R01UH0017EJ0400 Rev.4.00 Page 22 of 816 Sep 30, 2010...
Page 39: Chapter 3 Cpu Function
V850ES/JF3-L CHAPTER 3 CPU FUNCTION CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JF3-L is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. Features Minimum instruction execution time: 50 ns (operating with main clock (f ) of 20 MHz: V = 2.7 to 3.6 V)
Page 40: Cpu Register Set
CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/JF3-L can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual.
Page 41: Program Register Set
V850ES/JF3-L CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable.
Page 42: System Register Set
V850ES/JF3-L CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below.
Page 43 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
Page 44 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
Page 45 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
Page 46 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
Page 47 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.
Page 48: Operation Modes
In this mode, the internal flash memory can be programmed by using a flash programmer. (3) On-chip debug mode The V850ES/JF3-L is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications. For details, see CHAPTER 29 ON-CHIP DEBUG FUNCTION.
Page 49: Address Space
V850ES/JF3-L CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.
Page 50: Wraparound Of Cpu Address Space
V850ES/JF3-L CHAPTER 3 CPU FUNCTION 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.
Page 51: Memory Map
0 0 0 0 0 0 0 0 H 0 0 0 0 0 0 0 0 H Notes 1. The V850ES/JF3-L has 18 address pins, so the external memory area appears as a repeated 256 KB image. 2. Fetch access and read access to addresses 00000000H to 000FFFFFH is made to the internal ROM area.
Page 52 0 0 0 F F F F F H (1 MB) 0 0 0 0 0 0 0 0 H Note The V850ES/JF3-L has 18 address pins, so the external memory area appears as a repeated 256 KB image. R01UH0017EJ0400 Rev.4.00...
Page 53: Areas
V850ES/JF3-L CHAPTER 3 CPU FUNCTION 3.4.4 Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (128 KB) μ 128 KB are allocated to addresses 00000000H to 0001FFFFH in the PD70F3735.
Page 54 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. (a) Internal RAM (8 KB) μ 8 KB are allocated to addresses 03FFD000H to 03FFEFFFH of the PD70F3735. Accessing addresses 03FF0000H to 03FFCFFFH is prohibited.
Page 55 15 MB (00100000H to 00FFFFFFH) are allocated as the external memory area. For details, see CHAPTER 5 BUS CONTROL FUNCTION. Caution The V850ES/JF3-L has 18 address pins (AD0 to AD15, A16, A17), so the external memory area appears as a repeated 256 KB image.
Page 56: Recommended Use Of Address Space
Recommended use of address space The architecture of the V850ES/JF3-L requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
Page 57 (2) Data space With the V850ES/JF3-L, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.
Page 58 0 0 0 3 F F F F H Internal ROM 0 0 0 0 0 0 0 0 H Note The V850ES/JF3-L has 18 address pins, so the external memory area appears as a repeated 256 KB image. Remarks 1.
Page 59: Peripheral I/O Registers
V850ES/JF3-L CHAPTER 3 CPU FUNCTION 3.4.6 Peripheral I/O registers (1/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note FFFFF004H Port DL register 0000H √ √ Note FFFFF004H Port DL register L PDLL √ √ Note FFFFF005H Port DL register H PDLH √...
Page 60 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (2/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF0D2H DMA addressing control register 1 DADC1 0000H √ FFFFF0D4H DMA addressing control register 2 DADC2 0000H √ FFFFF0D6H DMA addressing control register 3...
Page 61 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (3/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF14CH Interrupt control register TP5CCIC0 √ √ FFFFF14EH Interrupt control register TP5CCIC1 √ √ FFFFF150H Interrupt control register TM0EQIC0 √ √ FFFFF1 Interrupt control register CB0RIC/IICIC1 √...
Page 62 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (4/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF21CH A/D conversion result register 6 ADA0CR6 Undefined √ FFFFF21DH A/D conversion result register 6H ADA0CR6H Undefined √ FFFFF21EH A/D conversion result register 7...
Page 63 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (5/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF446H Port 3 mode control register PMC3 0000H √ √ FFFFF446H Port 3 mode control register L PMC3L √ √ FFFFF447H Port 3 mode control register H PMC3H √...
Page 64 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (6/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF5A2H TMP1 I/O control register 0 TP1IOC0 √ √ FFFFF5A3H TMP1 I/O control register 1 TP1IOC1 √ √ FFFFF5A4H TMP1 I/O control register 2 TP1IOC2 √...
Page 65 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (7/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF810H DMA trigger factor register 0 DTFR0 √ √ FFFFF812H DMA trigger factor register 1 DTFR1 √ √ FFFFF814H DMA trigger factor register 2 DTFR2 √...
Page 66 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (8/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFFC33H External interrupt rising edge specification register 9H INTR9H √ √ FFFFFC60H Port 0 function register √ FFFFFC66H Port 3 function register 0000H √...
Page 67 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (9/9) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFD90H IIC shift register 1 IIC1 √ √ FFFFFD92H IIC control register 1 IICC1 √ FFFFFD93H Slave address register 1 SVA1 √ √ FFFFFD94H...
Page 68: Special Registers
3.4.7 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JF3-L has the following seven special registers. • Power save control register (PSC) • Clock control register (CKC) •...
Page 69 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3>...
Page 70 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
Page 71 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 72: Cautions
CHAPTER 3 CPU FUNCTION 3.4.8 Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JF3-L. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
Page 73 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred.
Page 74 V850ES/JF3-L CHAPTER 3 CPU FUNCTION (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 75: Chapter 4 Port Functions
Input/output specifiable in 1-bit units Basic Port Configuration The V850ES/JF3-L features a total of 66 I/O ports consisting of ports 0, 1, 3 to 5, 7, 9, CM, CT, DH, and DL. The port configuration is shown below. Figure 4-1. Port Configuration Diagram...
Page 76: Port Configuration
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-2. Port Configuration Item Configuration Control register Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CM, CT, DH, DL) Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DH, DL)
Page 77 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
Page 78 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
Page 79 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1- bit units.
Page 80 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode “0” PMn register Input mode “1” Alternate function (when two alternate functions are available) “0”...
Page 81: Port 0
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-4. Port 0 Alternate-Function Pins Pin Name Pin No.
Page 82 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) After reset: FFH Address: FFFFF420H PM06 PM05 PM04 PM03 PM02 PM0n I/O mode control (n = 2 to 6) Output mode Input mode (3) Port 0 mode control register (PMC0)
Page 83 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (4) Port 0 function control register (PFC0) After reset: 00H Address: FFFFF460H PFC0 PFC03 PFC03 Specification of P03 pin alternate function INTP0 input ADTRG input (5) Port 0 function register (PF0) After reset: 00H Address: FFFFFC60H...
Page 84: Port 1
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 is a 1-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pin. Table 4-5. Port 1 Alternate-Function Pin Pin Name Pin No.
Page 85: Port 3
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-6. Port 3 Alternate-Function Pins Pin Name Pin No.
Page 86 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 0000H (output latch) Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H P3 (P3H) (P3L) Output data control (in output mode) (n = 0 to 5, 8, 9) Outputs 0 Outputs 1 Caution Be sure to set bits 15 to 10, 7, and 6 to “0”.
Page 87 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H PMC3 (PMC3H) PMC39 PMC38 (PMC3L) PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode...
Page 88 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 0000H Address: PFC3 FFFFF466H, PFC3L FFFFF466H, PFC3L FFFFF467H PFC3 (PFC3H) PFC39 PFC38 (PFC3L) PFC35 PFC34 PFC33 PFC32 Caution Be sure to set bits 15 to 10, 7, 6, 1, and 0 to “0”.
Page 89 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (6) Port 3 alternate function specifications PFC39 Specification of P39 pin alternate function RXDA2 input SCL00 I/O PFC38 Specification of P38 pin alternate function TXDA2 output SDA00 I/O PFC35 Specification of P35 pin alternate function...
Page 90 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) After reset: 0000H Address: PF3 FFFFFC66H, PF3L FFFFFC66H, PF3H FFFFFC67H PF39 PF38 PF3 (PF3H) (PF3L) PF35 PF34 PF33 PF32 PF31 PF30 PF3n Control of normal output or N-ch open-drain output (n = 0 to 5, 8, 9)
Page 91: Port 4
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-7. Port 4 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name...
Page 92 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 Specification of P42 pin operation mode I/O port SCKB0 I/O PMC41 Specification of P41 pin operation mode I/O port...
Page 93: Port 5
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-8. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name...
Page 94 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (2) Port 5 mode register (PM5) After reset: FFH Address: FFFFF42AH PM55 PM54 PM53 PM52 PM51 PM50 PM5n I/O mode control (n = 0 to 5) Output mode Input mode (3) Port 5 mode control register (PMC5)
Page 95 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) After reset: 00H Address: FFFFF46AH PFC5 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50 Remark For details of alternate function specification, see 4.3.5 (6) Port 5 alternate function specifications. (5) Port 5 function control expansion register (PFCE5)
Page 96 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS PFCE52 PFC52 Specification of P52 pin alternate function Setting prohibited Note TIQ03 input/KR2 input TOQ03 input RTP02 output PFCE51 PFC51 Specification of P51 pin alternate function Setting prohibited Note TIQ02 input/KR1 input TOQ02 output RTP01 output...
Page 97: Port 7
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 7 Port 7 is a 8-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-9. Port 7 Alternate-Function Pins Pin Name Pin No.
Page 98: Port 9
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-10. Port 9 Alternate-Function Pins Pin Name Pin No.
Page 99 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (2) Port 9 mode register (PM9) After reset: FFFFH Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H PM9 (PM9H) PM915 PM914 PM913 PM99 PM98 (PM9L) PM97 PM96 PM91 PM90 PM9n I/O mode control (n = 0, 1, 6 to 9, 13 to 15)
Page 100 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC99 PMC98 (PMC9L) PMC97 PMC96 PMC91 PMC90 PMC915 Specification of P915 pin operation mode...
Page 101 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) After reset: 0000H Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H PFC9 (PFC9H) PFC915 PFC914 PFC913 PFC99 PFC98 (PFC9L) PFC97 PFC96 PFC91 PFC90 Caution Be sure to set bits 12 to 10 and 5 to 2 to “0”.
Page 102 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specifications Caution When port 9 is specified as an alternate function by the PMC9.PMC9n bit with the PFC9 and PFCE9 registers maintaining the initial value, the output becomes undefined. Therefore, to specify port 9 as an alternate function, set the PFC9n or PFCE9m bit to 1 first and then set the PMC9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15, m = 0, 1, 6, 7, 14, 15).
Page 103 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS PFCE91 PFC91 Specification of P91 pin alternate function Setting prohibited KR7 input Note RXDA1 input/KR7 input Setting prohibited PFCE90 PFC90 Specification of P90 pin alternate function Setting prohibited KR6 input TXDA1 output Setting prohibited Note The RXDA1 and KR7 pins must not be used at the same time. When using the RXDA1 pin, do not use the KR7 pin.
Page 104: Port Cm
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.8 Port CM Port CM is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-11. Port CM Alternate-Function Pins Pin Name Pin No.
Page 105 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H Address: FFFFF04CH PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 Specification of PCM3 pin operation mode I/O port HLDRQ input PMCCM2 Specification of PCM2 pin operation mode...
Page 106: Port Ct
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.9 Port CT Port CT is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-12. Port CT Alternate-Function Pins Pin Name Pin No.
Page 107 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 00H Address: FFFFF04AH PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0 PMCCT6 Specification of PCT6 pin operation mode I/O port ASTB output PMCCT4 Specification of PCT4 pin operation mode...
Page 108: Port Dh
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.3.10 Port DH Port DH is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-13. Port DH Alternate-Function Pins Pin Name Pin No.
Page 109: Port Dl
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 00H Address: FFFFF046H PMCDH PMCDH1 PMCDH0 PMCDHn Specification of PDHn pin operation mode (n = 0, 1) I/O port Am output (address bus output) (m = 16, 17) Caution Be sure to set bits 7 to 2 to “0”.
Page 110 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H PDL (PDLH) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1...
Page 111 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn...
Page 112: Block Diagrams
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Block Diagrams Figure 4-3. Block Diagram of Type A-1 PMmn PORT Address P-ch A/D input signal N-ch R01UH0017EJ0400 Rev.4.00 Page 96 of 816 Sep 30, 2010...
Page 113 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A-2 PMmn PORT Address P-ch D/A output signal N-ch R01UH0017EJ0400 Rev.4.00 Page 97 of 816 Sep 30, 2010...
Page 114 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type D-1 PMCmn PMmn PORT Address Input signal when alternate function is used R01UH0017EJ0400 Rev.4.00 Page 98 of 816 Sep 30, 2010...
Page 115 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D-2 PMCmn PMmn Output signal when alternate function is used PORT Address R01UH0017EJ0400 Rev.4.00 Page 99 of 816 Sep 30, 2010...
Page 116 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-3 PMCmn Output enable signal of address/data bus Output buffer off signal PMmn Output signal when alternate function is used PORT Address Input enable signal of address/data bus Input signal when alternate function is used R01UH0017EJ0400 Rev.4.00...
Page 117 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type E-2 PFmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Address R01UH0017EJ0400 Rev.4.00 Page 101 of 816 Sep 30, 2010...
Page 118 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type E-3 PFmn Output enable signal when alternate function is used PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 119 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type G-1 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 120 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type G-3 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address R01UH0017EJ0400 Rev.4.00 Page 104 of 816...
Page 121 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type G-5 PFmn Output enable signal when alternate function is used PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used...
Page 122 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type G-6 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used P-ch PORT N-ch Address Note Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 123 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type G-12 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address Note Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 124 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type L-1 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1 when Edge Noise detection elimination alternate function is used Notes 1.
Page 125 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type N-1 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1 when Edge Noise alternate function is used...
Page 126 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type N-2 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note 2 Address Input signal when...
Page 127 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type N-4 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1-1 when Edge Noise elimination detection alternate function is used...
Page 128 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type U-16 PFmn Output enable signal when alternate function is used PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used PORT P-ch N-ch Note Address Input signal 1 when...
Page 129 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type U-5 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1-1 when...
Page 130 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type U-6 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note...
Page 131 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type U-7 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging...
Page 132 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of Type U-8 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note...
Page 133 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type U-9 PFmn OCDM0 OCDM0 Output enable signal when alternate function is used PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when...
Page 134 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type U-17 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used P-ch PORT N-ch Address Note Input signal 1 when Noise elimination alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 135 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type U-18 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used PORT P-ch N-ch Address Note Noise elimination RXDA1 Note Hysteresis characteristics are not available in port mode.
Page 136 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of Type U-19 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 137 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of Type U-20 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used PORT P-ch N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 138 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of Type U-15 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used...
Page 139 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of Type AA-1 PFmn External reset signal OCDM0 OCDM0 INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address N-ch Input signal when on-chip debugging...
Page 140: Port Register Settings When Alternate Function Is Used
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin.
Page 141 Table 4-15. Settings When Port Pins Are Used for Alternate Functions (1/6) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name...
Page 142 Table 4-15. Settings When Port Pins Are Used for Alternate Functions (2/6) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name...
Page 143 Table 4-15. Settings When Port Pins Are Used for Alternate Functions (3/6) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name...
Page 144 Table 4-15. Settings When Port Pins Are Used for Alternate Functions (4/6) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name...
Page 145 Table 4-15. Settings When Port Pins Are Used for Alternate Functions (5/6) Pin Name Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name...
Page 146 Table 4-15. Settings When Port Pins Are Used for Alternate Functions (6/6) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name...
Page 147: Cautions
4.6.1 Cautions on setting port pins (1) In the V850ES/JF3-L, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode), set by the PMCn register. In regards to this register setting sequence, note with caution the following.
Page 148 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order Setting Contents Pin States Pin Level <1> Initial value Port mode (input)
Page 149 V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS Figure 4-31. Example of Switching from P02 to NMI (Incorrect) 0 → 1 PMC0 PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Rising edge detector P02/NMI PMC02 bit = 0: Low level ↓...
Page 150: Cautions On Bit Manipulation Instruction For Port N Register (Pn)
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850ES/JF3-L. <1> The Pn register is read in 8-bit units.
Page 151: Cautions On On-Chip Debug Pins
V850ES/JF3-L CHAPTER 4 PORT FUNCTIONS 4.6.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used.
Page 152: Chapter 5 Bus Control Function
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JF3-L is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. Features A multiplexed bus output with a minimum of 3 bus cycles supported...
Page 153: Bus Control Pins
5.2.2 Pin status in each operation mode For the pin status of the V850ES/JF3-L in each operation mode, see 2.2 Pin States. R01UH0017EJ0400 Rev.4.00 Page 137 of 816...
Page 154: Memory Block Function
0 0 0 0 0 0 0 0 H 0 0 0 0 0 0 0 0 H Notes 1. The V850ES/JF3-L has 18 address pins, so the external memory area appears as a repeated 256 KB image. 2. This area is an external memory area in the case of a data write access.
Page 155: Bus Access
Each external memory area selected by memory block n can be set by using the BSC register. However, the bus size can be set to 8 bits and 16 bits only. The external memory area of the V850ES/JF3-L is selected by memory blocks 0 to 3. (1) Bus size configuration register (BSC) The BSC register can be read or written in 16-bit units.
Page 156: Access By Bus Size
5.4.3 Access by bus size The V850ES/JF3-L accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits.
Page 157 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External data Byte data...
Page 158 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access Address Address Address 2n + 1...
Page 159 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External data...
Page 160 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External data...
Page 161 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data...
Page 162 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4...
Page 163: Wait Function
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION Wait Function 5.5.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space.
Page 164: External Wait Function
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION 5.5.2 External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT).
Page 165: Relationship Between Programmable Wait And External Wait
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin.
Page 166: Programmable Address Wait Function
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION 5.5.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each memory block area (memory blocks 0 to 3).
Page 167: Idle State Insertion Function
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the memory block. By inserting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access).
Page 168: Bus Hold Function
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function 5.7.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 169: Bus Hold Procedure
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION 5.7.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5>...
Page 170: Bus Priority
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and instruction fetch (successive).
Page 171: Bus Timing
V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A17, A16 ASTB WAIT AD15 to AD0 Idle state Programmable External wait wait 8-bit Access Odd Address Even Address...
Page 172 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A17, A16 ASTB WAIT AD15 to AD0 WR1, WR0 Programmable External wait wait 8-bit Access Odd Address Even Address AD15 to AD8...
Page 173 V850ES/JF3-L CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) Note Note CLKOUT HLDRQ HLDAK A17, A16 Undefined Undefined Undefined Undefined AD15 to AD0 ASTB Note This idle state (TI) does not depend on the BCC register settings.
Page 174: Chapter 6 Clock Generation Function
V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION CHAPTER 6 CLOCK GENERATION FUNCTION Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode = 2.5 to 10 MHz (f = 2.5 to 10 MHz) • In PLL mode = 2.5 to 5 MHz (f...
Page 175: Configuration
V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION Configuration Figure 6-1. Clock Generator FRC bit Timer M clock Subclock Watch timer clock, oscillator watchdog timer 2 clock /2 to f Watch timer clock Prescaler 3 IDLE CLS, CK3 control MFRC PLLON bits...
Page 176 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator Connecting the ceramic/crystal resonator to the X1 and X2 pins, the main clock oscillator oscillates to generates the following frequencies (f • In clock-through mode = 2.5 to 10 MHz •...
Page 177: Registers
V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units.
Page 178 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION After reset: 03H Address: FFFFF828H < > < > < > Note MFRC Use of subclock on-chip feedback resistor Used Not used Main clock oscillator control Oscillation enabled Oscillation stopped • Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop.
Page 179 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started.
Page 180 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses.
Page 181 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units.
Page 182: Operation
V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock Register Setting and PCC Register Operation Status CLK Bit = 0, MCK Bit = 0...
Page 183: Pll Function
6.5.1 Overview In the V850ES/JF3-L, an operating clock that is 4 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions.
Page 184 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.7 Special registers). The CKC register controls the internal system clock in the PLL mode.
Page 185 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status.
Page 186 V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units.
Page 187: Usage
V850ES/JF3-L CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.3 Usage (1) When PLL is used • After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
Page 188: Chapter 7 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/JF3-L has eight timer/event counter channels, TMP0 to TMP2 and TMP5. Overview An outline of TMPn is shown below.
Page 189: Configuration
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Configuration TMPn includes the following hardware. Table 7-1. Configuration of TMPn Item Configuration Timer register 16-bit counter Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0, CCR1 buffer registers...
Page 190 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPnCNT register is read at this time, 0000H is read.
Page 191: Registers
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Registers The registers that control TMPn are as follows. • TMPn control register 0 (TPnCTL0) • TMPn control register 1 (TPnCTL1) • TMPn I/O control register 0 (TPnIOC0) • TMPn I/O control register 1 (TPnIOC1) •...
Page 192 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 193 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) After reset: 00H Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H, TP2CTL1 FFFFF5B1H, TP5CTL1 FFFFF5E1H <6> <5> TPnCTL1 TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0 (n = 0 to 2, 5) TPnEST Software trigger control − Generate a valid signal for external trigger input.
Page 194 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit units.
Page 195 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). This register can be read or written in 8-bit or 1-bit units.
Page 196 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin).
Page 197 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units.
Page 198 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit.
Page 199 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated.
Page 200 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit.
Page 201 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated.
Page 202 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read.
Page 203: Operation
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Operation TMPn can perform the following operations. Operation TPnCTL1.TPnEST Bit TIPn0 Pin Capture/Compare Compare Register (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write...
Page 204: Interval Timer Mode (Tpnmd2 To Tpnmd0 Bits = 000)
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the specified interval if the TPnCTL0.TPnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOPn0 pin.
Page 205 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 206 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output...
Page 207 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal <1> <2> <1> Count operation start flow...
Page 208 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock of the second clock or later, and the output of the TOPn0 pin is inverted.
Page 209 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted.
Page 210 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 211 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register Figure 7-6. Configuration of TPnCCR1 Register TPnCCR1 register Output CCR1 buffer register TOPn1 pin controller Match signal INTTPnCC1 signal Clear Count clock Output 16-bit counter TOPn0 pin...
Page 212 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. At the same time, the output of the TOPn1 pin is inverted.
Page 213 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed.
Page 214: External Event Count Mode (Tpnmd2 To Tpnmd0 Bits = 001)
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number of edges have been counted.
Page 215 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 216 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (f) TMPn capture/compare register 0 (TPnCCR0) If D is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request signal (INTTPnCC0) is generated when the number of external event counts reaches (D + 1).
Page 217 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal <1> <2> <1> Count operation start flow...
Page 218 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TPnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TPnCTL1.TPnMD2 to...
Page 219 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 220 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPnCCR1 register Figure 7-13. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Match signal INTTPnCC1 signal Clear Edge TIPn0 pin 16-bit counter detector Match signal INTTPnCC0 signal TPnCE bit...
Page 221 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match.
Page 222: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 010)
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
Page 223 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-17. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software...
Page 224 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting...
Page 225 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input Select valid edge of...
Page 226 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input)
Page 227 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> PnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed.
Page 228 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected.
Page 229 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level width to the TPnCCR1 register.
Page 230 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically.
Page 231 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with TPnCCR1 register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting.
Page 232 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with TPnCCR0 register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection.
Page 233 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 234: One-Shot Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 011)
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin.
Page 235 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used)
Page 236 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1)
Page 237 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input Select valid edge of...
Page 238 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register...
Page 239 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the set value.
Page 240 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 241: Pwm Output Mode (Tpnmd2 To Tpnmd0 Bits = 100)
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1.
Page 242 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register NTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output...
Page 243 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Setting of Registers in PWM Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note 1 Select count clock 0: Stop counting 1: Enable counting...
Page 244 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting in PWM Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input. (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 245 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output...
Page 246 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed.
Page 247 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected.
Page 248 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically.
Page 249 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 250: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 Bits = 101)
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Page 251 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the TOPnm pin is inverted.
Page 252 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated.
Page 253 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1...
Page 254 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (2/2) (d) TMPn I/O control register 1 (TPnIOC1) TPnIS3 TPnIS2 TPnIS1 TPnIS0 TPnIOC1 Select valid edge of TIPn0 pin input Select valid edge of TIPn1 pin input...
Page 255 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit...
Page 256 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before the TPnCE (TPnCKS0 to TPnCKS2 bits) bit is set to 1.
Page 257 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000...
Page 258 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before the TPnCE (TPnCKS0 to TPnCKS2 bits) bit is set to 1.
Page 259 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected.
Page 260 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected and for calculating an interval.
Page 261 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
Page 262 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag...
Page 263 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag...
Page 264 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 265 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register INTTPnOV signal TPnOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 266 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8- bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 267: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 Bits = 110)
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
Page 268 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input 0000H TPnCCRm register INTTPnCCm signal INTTPnOV signal Cleared to 0 by TPnOVF bit CLR instruction...
Page 269 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1)
Page 270 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOVF TPnOPT0 Overflow flag (f) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 271 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input 0000H 0000H TPnCCR0 register INTTPnCC0 signal <1>...
Page 272 V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8- bit data (bit 0 is 0) to the TPnOPT0 register.
Page 273: Timer Output Operations
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.8 Timer output operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 7-4. Timer Output Control in Each Mode Operation Mode TOPn1 Pin TOPn0 Pin...
Page 274: Selector Function
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Selector Function In the V850ES/JF3-L, the capture trigger input for TMP1 can be selected from the input signal via the port/timer alternate-function pin (TIP10/TIP11) and the peripheral I/O (TMP/UARTA) input signal via the UARTA reception alternate- function pin (RXDA0/RXDA1).
Page 275: Cautions
V850ES/JF3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TPnCCR0 and TPnCCR1 registers, or the capture operation may not be performed (capture interrupt does not occur) if the capture trigger is input immediately after the TPnCE bit is set to 1.
Page 276: Chapter 8 16-Bit Timer/Event Counter Q (Tmq)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850ES/JF3-L incorporates TMQ0. Overview An outline of TMQ0 is shown below. • Clock selection: 8 ways •...
Page 277: Configuration
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Configuration TMQ0 includes the following hardware. Table 8-1. Configuration of TMQ0 Item Configuration Timer register 16-bit counter Registers TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) TMQ0 counter read buffer register (TQ0CNT)
Page 278 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TQ0CNT register. When the TQ0CTL0.TQ0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TQ0CNT register is read at this time, 0000H is read.
Page 279: Registers
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Registers The registers that control TMQ0 are as follows. • TMQ0 control register 0 (TQ0CTL0) • TMQ0 control register 1 (TQ0CTL1) • TMQ0 I/O control register 0 (TQ0IOC0) • TMQ0 I/O control register 1 (TQ0IOC1) •...
Page 280 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) TMQ0 control register 0 (TQ0CTL0) The TQ0CTL0 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 281 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) TMQ0 control register 1 (TQ0CTL1) The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 282 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) TMQ0 I/O control register 0 (TQ0IOC0) The TQ0IOC0 register is an 8-bit register that controls the timer output (TOQ00 to TOQ03 pins). This register can be read or written in 8-bit or 1-bit units.
Page 283 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQ00 to TIQ03 pins). This register can be read or written in 8-bit or 1-bit units.
Page 284 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIQ00 pin) and external trigger input signal (TIQ00 pin).
Page 285 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (6) TMQ0 option register 0 (TQ0OPT0) The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units.
Page 286 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQ0 capture/compare register 0 (TQ0CCR0) The TQ0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS0 bit.
Page 287 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR0 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQ0CC0) is generated.
Page 288 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQ0 capture/compare register 1 (TQ0CCR1) The TQ0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS1 bit.
Page 289 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR1 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated.
Page 290 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQ0 capture/compare register 2 (TQ0CCR2) The TQ0CCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS2 bit.
Page 291 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR2 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated.
Page 292 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQ0 capture/compare register 3 (TQ0CCR3) The TQ0CCR3 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS3 bit.
Page 293 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR3 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated.
Page 294 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (11) TMQ0 counter read buffer register (TQ0CNT) The TQ0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQ0CTL0.TQ0CE bit = 1, the count value of the 16-bit timer can be read.
Page 295: Operation
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Operation TMQ0 can perform the following operations. Operation TQ0CTL1.TQ0EST Bit TIQ00 Pin Capture/Compare Compare Register (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write...
Page 296: Interval Timer Mode (Tq0Md2 To Tq0Md0 Bits = 000)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTQ0CC0) is generated at the specified interval if the TQ0CTL0.TQ0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOQ00 pin.
Page 297 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOQ00 pin is inverted. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 298 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output...
Page 299 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Interval timer mode operation flow Figure 8-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register TOQ00 pin output INTTQ0CC0 signal <1> <2> <1> Count operation start flow...
Page 300 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Interval timer mode operation timing (a) Operation if TQ0CCR0 register is set to 0000H If the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated at each count clock of the second clock or later, and the output of the TOQ00 pin is inverted.
Page 301 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQ0CCR0 register To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 302 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-6. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer Output TOQ01 pin register controller Match signal INTTQ0CC1 signal TQ0CCR2 register Output CCR2 buffer...
Page 303 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is less than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. At the same time, the output of the TOPQ0k pin is inverted.
Page 304 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the count value of the 16-bit counter does not match the value of the TQ0CCRk register. Consequently, the INTTQ0CCk signal is not generated, nor is the output of the TOQ0k pin changed.
Page 305: External Event Count Mode (Tq0Md2 To Tq0Md0 Bits = 001)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified number of edges have been counted.
Page 306 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 307 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2) (f) TMQ0 capture/compare register 0 (TQ0CCR0) If D is set to the TQ0CCR0 register, the counter is cleared and a compare match interrupt request signal (INTTQ0CC0) is generated when the number of external event counts reaches (D + 1).
Page 308 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) External event count mode operation flow Figure 8-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal <1> <2> <1> Count operation start flow...
Page 309 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TQ0CCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TQ0CTL1.TQ0MD2 to...
Page 310 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting the TQ0CCR0 register To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 311 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-13. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer register Match signal INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer register Match signal INTTQ0CC2 signal...
Page 312 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is smaller than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. Remark k = 1 to 3 ≥...
Page 313 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is not generated because the count value of the 16-bit counter and the value of the TQ0CCRk register do not match.
Page 314: External Trigger Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 010)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter Q starts counting, and outputs a PWM waveform from the TOQ01 to TOQ03 pins.
Page 315 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-17. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used)
Page 316 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQ0k pin.
Page 317 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0 TQ0CTL1 0, 1, 0: External trigger pulse output mode...
Page 318 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 Select valid edge of external trigger input Select valid edge of...
Page 319 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in external trigger pulse output mode Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input)
Page 320 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Writing of the TQ0CCR1 START Setting of TQ0CCR2,...
Page 321 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected.
Page 322 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register.
Page 323 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is FFFFH, the INTTQ0CCk signal is generated periodically.
Page 324 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTQ0CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0k pin is asserted, and the counter continues counting.
Page 325 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQ0k pin is extended by time from generation of the INTTQ0CC0 signal to trigger detection.
Page 326 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the external trigger pulse output mode differs from the timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
Page 327: One-Shot Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 011)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter Q starts counting, and outputs a one-shot pulse from the TOQ01 to TOQ03 pins.
Page 328 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used)
Page 329 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16- bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0k pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger.
Page 330 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Register Setting in One-Shot Pulse Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 Note Note TQ0IOC0 0: Disable TOQ00 pin output...
Page 331 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Register Setting in One-Shot Pulse Output Mode (3/3) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
Page 332 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in one-shot pulse output mode Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register...
Page 333 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <1> Count operation start flow <2> TQ0CCR0 to TQ0CCR3 register setting change flow As rewriting the TQ0CCRm register START immediately forwards...
Page 334 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQ0CCRm register To change the set value of the TQ0CCRm register to a smaller value, stop counting once, and then change the set value.
Page 335 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Generation timing of compare match interrupt request signal (INTTQ0CCk) The generation timing of the INTTQ0CCk signal in the one-shot pulse output mode is different from other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 336: Pwm Output Mode (Tq0Md2 To Tq0Md0 Bits = 100)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOQ01 to TOQ03 pins when the TQ0CTL0.TQ0CE bit is set to 1.
Page 337 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-25. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (software trigger) TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Active Active...
Page 338 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQ0k pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Page 339 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Setting of Registers in PWM Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 Note Note TQ0IOC0 0: Disable TOQ00 pin output...
Page 340 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting in PWM Output Mode (3/3) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 and TQ0CCR3)
Page 341 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in PWM output mode Figure 8-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal TOQ00 pin output...
Page 342 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1, TQ0CCR3 register setting change flow Only writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed...
Page 343 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC1 signal is detected.
Page 344 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) To transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level width to the TQ0CCR1 register.
Page 345 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is FFFFH, the INTTQ0CCk signal is generated periodically.
Page 346 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the PWM output mode differs from the timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 347: Free-Running Timer Mode (Tq0Md2 To Tq0Md0 Bits = 101)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. At this time, the TQ0CCRm register can be used as a compare register or a capture register, depending on the setting of the TQ0OPT0.TQ0CCS0 and TQ0OPT0.TQ0CCS1 bits.
Page 348 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to TOQ03 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQ0CCRm register, a compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is inverted.
Page 349 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal (INTTQ0CCm) is generated.
Page 350 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Register Setting in Free-Running Timer Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1...
Page 351 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Register Setting in Free-Running Timer Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output...
Page 352 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Register Setting in Free-Running Timer Mode (3/3) (e) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 Select valid edge of external event count input (f) TMQ0 option register 0 (TQ0OPT0)
Page 353 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit...
Page 354 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Initial setting of these registers Register initial setting is performed before the TQ0CTL0 register TQ0CE bit is set to 1.
Page 355 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) When using capture/compare register as capture register Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000...
Page 356 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TQ0CTL0 register is performed before the TQ0CE (TQ0CKS0 to TQ0CKS2 bits) bit is set to 1.
Page 357 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQ0CCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQ0CCm signal has been detected.
Page 358 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQ0CCRm register must be re-set in the interrupt servicing that is executed when the INTTQ0CCm signal is detected.
Page 359 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQ0CCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTQ0CCm signal has been detected and for calculating an interval.
Page 360 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRm register in synchronization with the INTTQ0CCm signal, and calculating the difference between the read value and the previously read value.
Page 361 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
Page 362 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag...
Page 363 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag...
Page 364 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 365 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register INTTQ0OV signal TQ0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 366 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8- bit data (bit 0 is 0) to the TQ0OPT0 register. To accurately detect an overflow, read the TQ0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 367: Pulse Width Measurement Mode (Tq0Md2 To Tq0Md0 Bits = 110)
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. Each time the valid edge input to the TIQ0m pin has been detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H.
Page 368 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input 0000H TQ0CCRm register INTTQ0CCm signal INTTQ0OV signal Cleared to 0 by TQ0OVF bit CLR instruction...
Page 369 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMQ0 control register 1 (TQ0CTL1)
Page 370 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMQ0 option register 0 (TQ0OPT0) TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0 TQ0OVF TQ0OPT0 Overflow flag (f) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register.
Page 371 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in pulse width measurement mode Figure 8-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input 0000H 0000H TQ0CCR0 register INTTQ0CC0 signal <1>...
Page 372 V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8- bit data (bit 0 is 0) to the TQ0OPT0 register.
Page 373: Timer Output Operations
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.8 Timer output operations The following table shows the operations and output levels of the TOQ00 and TOQ01 pins. Table 8-6. Timer Output Control in Each Mode Operation Mode TOQn0 Pin TOQn1 Pin...
Page 374: Cautions
V850ES/JF3-L CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TQ0CCR0, TQ0CCR1, TQ0CCR2, and TQ0CCR3 registers, or the capture operation may not be...
Page 375: Chapter 9 16-Bit Interval Timer M (Tmm)
V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Overview • Interval function • 8 clocks selectable • 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.) • Compare register × 1 (The compare register cannot be written during timer counter operation.)
Page 376: Configuration
V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Configuration TMM0 includes the following hardware. Table 9-1. Configuration of TMM0 Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 control register 0 (TM0CTL0) Figure 9-1. Block Diagram of TMM0...
Page 377: Register
V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Register (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 378: Operation
V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Operation Caution Do not set the TM0CMP0 register to FFFFH. 9.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the specified interval if the TM0CTL0.TM0CE bit is set to 1.
Page 379 V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Figure 9-4. Register Setting for Interval Timer Mode Operation (a) TMM0 control register 0 (TM0CTL0) TM0CE TM0CKS2 TM0CKS1 TM0CKS0 TM0CTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMM0 compare register 0 (TM0CMP0) If the TM0CMP0 register is set to D, the interval is as follows.
Page 380 V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal <1> <2> <1> Count operation start flow...
Page 381 V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TM0CMP0 register to FFFFH. (a) Operation if TM0CMP0 register is set to 0000H If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock.
Page 382: Cautions
V850ES/JF3-L CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.4.2 Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1, depending on the count clock selected. Selected Count Clock...
Page 383: Chapter 10 Watch Timer Functions
V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS CHAPTER 10 WATCH TIMER FUNCTIONS 10.1 Functions The watch timer has the following functions. • Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock.
Page 384: Configuration
V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS 10.2 Configuration The block diagram of the watch timer is shown below. Figure 10-1. Block Diagram of Watch Timer Internal bus PRSM0 register BGCE0 BGCS01 BGCS00 Clear PRSCM0 register 3-bit Clock prescaler control Match...
Page 385 V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS (1) Clock control This block controls supplying and stopping the operating clock (f ) when the watch timer operates on the main clock. (2) 3-bit prescaler This prescaler divides f to generate f /2, f...
Page 386: Control Registers
V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS 10.3 Control Registers The following registers are provided for the watch timer. • Prescaler mode register 0 (PRSM0) • Prescaler compare register 0 (PRSCM0) • Watch timer operation mode register (WTM) (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls the generation of the watch timer count clock.
Page 387 V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF8B1H...
Page 388 V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS (3) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 389 V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS (2/2) WTM7 WTM3 WTM2 Selection of set time of watch flag (0.5 s: f (0.25 s: f μ (977 s: f μ (488 s: f (0.5 s: f (0.25 s: f μ (977 s: f μ...
Page 390: Operation
V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS 10.4 Operation 10.4.1 Operation as watch timer The watch timer generates an interrupt request signal (INTWT) at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz) or main clock.
Page 391: Operation As Interval Timer
V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS 10.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals specified by a preset count value. The interval time can be selected by the WTM4 to WTM7 bits of the WTM register.
Page 392: Cautions
V850ES/JF3-L CHAPTER 10 WATCH TIMER FUNCTIONS Figure 10-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s)
Page 393: Chapter 11 Functions Of Watchdog Timer 2
V850ES/JF3-L CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.1 Functions Watchdog timer 2 has the following functions. • Default-start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) →...
Page 394: Configuration
V850ES/JF3-L CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 11-1. Block Diagram of Watchdog Timer 2 to f to f INTWDT2 Clock to f Output 16-bit input Selector...
Page 395: Registers
V850ES/JF3-L CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release.
Page 396 V850ES/JF3-L CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 Table 11-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.) Clock 41.0 ms 18.6 ms 10.2 ms 81.9 ms 37.2 ms 20.5 ms...
Page 397: Operation
V850ES/JF3-L CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register. The WDTE register can be read or written in 8-bit units.
Page 398: Chapter 12 Real-Time Output Function (Rto)
Because RTO can output signals without jitter, it is suitable for controlling a stepper motor. In the V850ES/JF3-L, one 6-bit real-time output port channel is provided. The real-time output port can be set to the port mode or real-time output port mode in 1-bit units.
Page 399: Configuration
V850ES/JF3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.2 Configuration The block diagram of RTO is shown below. Figure 12-1. Block Diagram of RTO Real-time output Real-time output buffer register 0H RTP04, latch 0H (RTBH0) RTP05 Real-time output Real-time output buffer register 0L...
Page 400 V850ES/JF3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold preset output data. These registers are mapped to independent addresses in the peripheral I/O register area.
Page 401: Registers
V850ES/JF3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.3 Registers RTO is controlled using the following two registers. • Real-time output port mode register 0 (RTPM0) • Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units.
Page 402 V850ES/JF3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 12-3.
Page 403: Operation
V850ES/JF3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits).
Page 404: Usage
V850ES/JF3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. • Set the alternate-function pins of port 5 Set the PFC5.PFC5m bit and PFCE5.PFCE5m bit to 1, and then set the PMC5.PMC5m bit to 1 (m = 0 to 5).
Page 405: Chapter 13 A/D Converter
V850ES/JF3-L CHAPTER 13 A/D CONVERTER CHAPTER 13 A/D CONVERTER 13.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 8 analog input signal channels (ANI0 to ANI7). The A/D converter has the following features.
Page 406: Configuration
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.3 Configuration The block diagram of the A/D converter is shown below. Figure 13-1. Block Diagram of A/D Converter REF0 ANI0 Sample & hold circuit ADA0CE bit ANI1 ANI2 Voltage comparator & Compare voltage ADA0CE bit...
Page 407 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (1) Successive approximation register (SAR) The SAR register compares the voltage value of the analog input signal with the output voltage of the compare voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB).
Page 408 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AV and AV and generates a voltage for REF0 comparison with the analog input signal. (13) ANI0 to ANI7 pins These are analog input pins for the 8 A/D converter channels and are used to input analog signals to be converted into digital signals.
Page 409: Registers
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used.
Page 410 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (2/2) Specification of external trigger (ADTRG pin) input valid edge ADA0ETS1 ADA0ETS0 No edge detection Falling edge detection Rising edge detection Detection of both rising and falling edges Trigger mode specification ADA0TMD Software trigger mode...
Page 411 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this bit to 00H.
Page 412 V850ES/JF3-L CHAPTER 13 A/D CONVERTER Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) ADA0 ADA0 ADA0 A/D Conversion Time Stabilization Time = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz f...
Page 413 V850ES/JF3-L CHAPTER 13 A/D CONVERTER Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0 ADA0 ADA0 A/D Conversion Time Conversion Time = 20 MHz f = 16 MHz f = 12 MHz f = 10 MHz...
Page 414 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset:...
Page 415 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units.
Page 416 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access.
Page 417 V850ES/JF3-L CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (ADA0CRn register) is as follows. × 1,024 + 0.5) SAR = INT ( REF0 = SAR × 64...
Page 418 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 419 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 420: Operation
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.
Page 421: Conversion Operation Timing
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.5.2 Conversion operation timing Figure 13-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Second conversion Setup Sampling A/D conversion Wait Setup Sampling Processing state...
Page 422: Trigger Mode
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.5.3 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
Page 423 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI7) specified by the ADA0S register is started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare register connected to the timer.
Page 424: Operation Mode
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.5.4 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI7 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits.
Page 425 V850ES/JF3-L CHAPTER 13 A/D CONVERTER Figure 13-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4...
Page 426 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
Page 427 V850ES/JF3-L CHAPTER 13 A/D CONVERTER Figure 13-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion (ANI0)
Page 428: Power-Fail Compare Mode
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter).
Page 429 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 430 V850ES/JF3-L CHAPTER 13 A/D CONVERTER Figure 13-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2...
Page 431 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 432 V850ES/JF3-L CHAPTER 13 A/D CONVERTER Figure 13-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data ANI1 Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3...
Page 433: Cautions
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI7 pins Input the voltage within the specified range to the ANI0 to ANI7 pins.
Page 434 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
Page 435 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (7) AV REF0 (a) The AV pin is used as the power supply pin of the A/D converter and also supplies power to the alternate- REF0 function ports. In an application where a backup power supply is used, be sure to supply the same voltage as to the AV pin as shown in Figure 13-15.
Page 436 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (9) Standby mode Because the A/D converter stops operating in the STOP mode, conversion results are invalid, so power consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion results after the STOP mode is released are invalid.
Page 437: How To Read A/D Converter Characteristics Table
V850ES/JF3-L CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 438 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 439 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale − 3/2 LSB). Figure 13-19. Full-Scale Error...
Page 440 V850ES/JF3-L CHAPTER 13 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 441: Chapter 14 D/A Converter
V850ES/JF3-L CHAPTER 14 D/A CONVERTER CHAPTER 14 D/A CONVERTER 14.1 Functions The D/A converter has the following functions. 8-bit resolution × 1 channel (DA0CS0) R-2R ladder method μ Settling time: 3 s max. (when AV is 2.7 to 3.6 V and external load is 20 pF) REF1 ×...
Page 442: Registers
V850ES/JF3-L CHAPTER 14 D/A CONVERTER The D/A converter includes the following hardware. Table 14-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DA0M) D/A conversion value setting register 0 (DA0CS0) 14.3 Registers The registers that control the D/A converter are as follows.
Page 443 V850ES/JF3-L CHAPTER 14 D/A CONVERTER (2) D/A conversion value setting register 0 (DA0CS0) The DA0CS0 register sets the analog voltage value output to the ANO0 pin. This register can be read or written in 8-bit units. Reset sets this register to 00H.
Page 444: Operation
V850ES/JF3-L CHAPTER 14 D/A CONVERTER 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CS0 register as the trigger. The setting method is described below. <1> Set the DA0M.DA0MD0 bit to 0 (normal mode).
Page 445: Cautions
CHAPTER 14 D/A CONVERTER 14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/JF3-L. (1) Do not change the set value of the DA0CS0 register while the trigger signal is being issued in the real-time output mode.
Page 446: Chapter 15 Asynchronous Serial Interface A (Uarta)
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1 Mode Switching of UARTA2 and I In the V850ES/JF3-L, UARTA2 and I C00 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA2 in advance, using the PMC3 and PFC3 registers, before use.
Page 447: Features
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.2 Features Transfer rate: 300 bps to 625 kbps (using internal system clock of 20 MHz and dedicated baud rate generator) Full-duplex communication: Internal UARTAn receive data register (UAnRX) Internal UARTAn transmit data register (UAnTX)
Page 448: Configuration
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.3 Configuration The block diagram of the UARTAn is shown below. Figure 15-2. Block Diagram of Asynchronous Serial Interface An Internal bus INTUAnT INTUAnR Transmission Reception unit UAnTX UAnRX unit Receive Transmit...
Page 449 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn.
Page 450: Registers
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.4 Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units.
Page 451 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnDIR Transfer direction selection MSB-first transfer LSB-first transfer • This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0.
Page 452 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register. This register can be read or written in 8-bit or 1-bit units.
Page 453 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnSLS2 UAnSLS1 UAnSLS0 SBF transmit length selection 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
Page 454 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H <2> <1> <7> <0> UAnSTR UAnTSF UAnPE UAnFE UAnOVE (n = 0 to 2) UAnTSF Transfer status flag • When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set.
Page 455 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
Page 456: Interrupt Request Signals
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. • Reception complete interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is reception complete interrupt request signal then transmission enable interrupt request signal.
Page 457: Operation
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6 Operation 15.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-3, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 458 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-3. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H...
Page 459: Sbf Transmission/Reception Format
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.2 SBF transmission/reception format The V850ES/JF3-L has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
Page 460 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-5. LIN Reception Manipulation Outline Wake-up Sync Check signal break Sync Identifier DATA DATA frame field field field field field field Note 2 Data Data Note 5 SF reception ID reception...
Page 461: Sbf Transmission
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit).
Page 462: Sbf Reception
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.4 SBF reception The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1.
Page 463: Uart Transmission
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 464: Continuous Transmission Procedure
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 465 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-10. Continuous Transmission Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn UAnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1)
Page 466: Uart Reception
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed.
Page 467: Reception Errors
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output when an error occurs.
Page 468 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) When reception errors occur, perform the following procedures depending upon the kind of error. • Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit.
Page 469: Parity Types And Operations
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.9 Parity types and operations Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 470: Receive Data Noise Filter
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.10 Receive data noise filter This filter samples the RXDAn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data.
Page 471: Dedicated Baud Rate Generator
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 472 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H.
Page 473 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units.
Page 474 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. UCLK Baud rate = [bps] 2 × k When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate using the above equation).
Page 475 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) To set the baud rate, perform the following calculation for setting the UAnCTL1 and UAnCTL2 registers (when using internal clock). <1> Set k to fxx/(2 × target baud rate) and m to 0.
Page 476 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 477 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following.
Page 478 V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 479: Cautions
V850ES/JF3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.8 Cautions (1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped.
Page 480: Chapter 16 3-Wire Variable-Length Serial I/O (Csib)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.1 Mode Switching of CSIB0 and I In the V850ES/JF3-L, CSIB0 and I C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set CSIB0 in advance, using the PMC4 and PFC4 registers, before use.
Page 481: Features
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.2 Features Transfer rate: 8 Mbps max. Master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface Interrupt request signals (INTCBnT, INTCBnR) Serial clock and data phase switchable Transfer data length selectable in 1-bit units between 8 and 16 bits...
Page 482: Configuration
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.3 Configuration The following shows the block diagram of CSIBn. Figure 16-2. Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR Phase control CCLK BRGm CBnTX SCKBn Phase...
Page 483 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status.
Page 484: Registers
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.4 Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation.
Page 485 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/3) Note CBnDIR Specification of transfer direction mode (MSB/LSB) MSB-first transfer LSB-first transfer Note CBnTMS Transfer mode specification Single transfer mode Continuous transfer mode [In single transfer mode] The reception complete interrupt (INTCBnR) occurs when communication is complete.
Page 486 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3/3) CBnSCE Specification of start transfer disable/enable Communication start trigger invalid Communication start trigger valid • In master mode This bit enables or disables the communication start trigger. (a) In single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode The setting of the CBnSCE bit has no influence on communication operation.
Page 487 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 488 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H.
Page 489 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 490 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only.
Page 491: Interrupt Request Signals
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5 Interrupt Request Signals CSIBn can generate the following two types of interrupt request signals. • Reception complete interrupt request signal (INTCBnR) • Transmission enable interrupt request signal (INTCBnT) Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower.
Page 492: Operation
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6 Operation 16.6.1 Single transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits CCLK (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 493 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5...
Page 494: Single Transfer Mode (Master Mode, Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits CCLK (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 495 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5...
Page 496: Single Transfer Mode (Master Mode, Transmission/Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits CCLK (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 497 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5...
Page 498: Single Transfer Mode (Slave Mode, Transmission Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer CCLK data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 499 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4...
Page 500: Single Transfer Mode (Slave Mode, Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.5 Single transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer CCLK data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 501 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4...
Page 502: Single Transfer Mode (Slave Mode, Transmission/Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer CCLK data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 503 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 504: Continuous Transfer Mode (Master Mode, Transmission Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits CCLK (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 505 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6...
Page 506: Continuous Transfer Mode (Master Mode, Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits CCLK (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 507 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read Start reception INTCBnR interrupt generated? CBnOVE bit = 1?
Page 508 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SOBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6...
Page 509: Continuous Transfer Mode (Master Mode, Transmission/Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits CCLK (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 510 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register Start transmission/reception INTCBnT interrupt (6), (11) generated? (11) Is data being transmitted...
Page 511 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7...
Page 512 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (11) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CBnTX register.
Page 513: Continuous Transfer Mode (Slave Mode, Transmission Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer CCLK data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 514 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5...
Page 515: Continuous Transfer Mode (Slave Mode, Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer CCLK data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 516 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read SCKBn pin input started? Reception start INTCBnR interrupt generated?
Page 517 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6...
Page 518: Continuous Transfer Mode (Slave Mode, Transmission/Reception Mode)
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer CCLK data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000)
Page 519 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register SCKBn pin input started? Start transmission/reception INTCBnT interrupt (6), (11)
Page 520 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7...
Page 521 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (12) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the CBnTX register, the INTCBnR signal is generated. Clear the CBnTSF bit to 0 to end transmission/reception.
Page 522: Reception Error
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.13 Reception error When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (INTCBnR) is generated again when the next receive operation is completed before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag (CBnSTR.CBnOVE) is...
Page 523: Clock Timing
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.14 Clock timing (1/2) (i) Communication type 1 (CBnCKP and CBnDAP bits = 00) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (ii) Communication type 3 (CBnCKP and CBnDAP bits = 10)
Page 524 V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (iii) Communication type 2 (CBnCKP and CBnDAP bits = 01) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (iv) Communication type 4 (CBnCKP and CBnDAP bits = 11)
Page 525: Output Pins
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.7 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn Pin Output High impedance...
Page 526: Baud Rate Generator
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.8 Baud Rate Generator The BRG1, BRG2 and CSIB0 to CSIB2 baud rate generators are connected as shown in the following block diagram. BRG1 BRG1 CSIB0 CSIB1 BRG2 BRG2 CSIB2 (1) Prescaler mode registers 1, 2 (PRSM1, PRSM2) The PRSM1 and PRSM2 registers control generation of the baud rate signal for CSIB.
Page 527: Baud Rate Generation
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Prescaler compare registers 1, 2 (PRSCM1, PRSCM2) The PRSCM1 and PRSCM2 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H.
Page 528: Cautions
V850ES/JF3-L CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.9 Cautions When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed.
Page 529: Chapter 17 I C Bus
C Bus and Other Serial Interfaces 17.1.1 UARTA2 and I C00 mode switching In the V850ES/JF3-L, UARTA2 and I C00 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I C00 in advance, using the PMC3 and PFC3 registers, before use.
Page 530: Csib0 And I 2 C01 Mode Switching
C BUS 17.1.2 CSIB0 and I C01 mode switching In the V850ES/JF3-L, CSIB0 and I C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I C01 in advance, using the PMC4 and PFC4 registers, before use.
Page 531: Features
V850ES/JF3-L CAPTER 17 I C BUS 17.2 Features C00 and I C01 have the following two modes. • Operation stopped mode • I C (Inter IC) bus mode (multimasters supported) (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption.
Page 532: Configuration
V850ES/JF3-L CAPTER 17 I C BUS 17.3 Configuration The block diagram of the I C0n is shown below. Figure 17-3. Block Diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n...
Page 533 V850ES/JF3-L CAPTER 17 I C BUS A serial bus configuration example is shown below. Figure 17-4. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2...
Page 534 V850ES/JF3-L CAPTER 17 I C BUS C0n includes the following hardware (n = 0, 1). Table 17-1. Configuration of I Item Configuration Registers IIC shift register n (IICn) Slave address register n (SVAn) Control registers IIC control register n (IICCn)
Page 535 V850ES/JF3-L CAPTER 17 I C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) •...
Page 536: Registers
V850ES/JF3-L CAPTER 17 I C BUS 17.4 Registers C00 and I C01 are controlled by the following registers. • IIC control registers 0, 1 (IICC0, IICC1) • IIC status registers 0, 1 (IICS0, IICS1) • IIC flag registers 0, 1 (IICF0, IICF1) •...
Page 537 V850ES/JF3-L CAPTER 17 I C BUS (1/4) After reset: 00H Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) IICEn Specification of I...
Page 538 V850ES/JF3-L CAPTER 17 I C BUS (2/4) Note SPIEn Enable/disable generation of interrupt request when stop condition is detected Disabled Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) • Cleared by instruction • Set by instruction •...
Page 539 V850ES/JF3-L CAPTER 17 I C BUS (3/4) STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCLn line is high level and then the start condition is generated.
Page 540 V850ES/JF3-L CAPTER 17 I C BUS (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n pin goes to high level.
Page 541 V850ES/JF3-L CAPTER 17 I C BUS (2) IIC status registers 0, 1 (IICS0, IICS1) The IICSn register indicates the status of I C0n (n = 0, 1). These registers are read-only, in 8-bit or 1-bit units. However, the IICSn register can only be read when the IICCn.STTn bit is 1 or during the wait period.
Page 542 V850ES/JF3-L CAPTER 17 I C BUS (2/3) COIn Matching address detection Addresses do not match. Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) • When a start condition is detected • When the received address matches the local •...
Page 543 V850ES/JF3-L CAPTER 17 I C BUS (3/3) STDn Start condition detection Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STDn bit = 0) Condition for setting (STDn bit = 1) •...
Page 544 V850ES/JF3-L CAPTER 17 I C BUS (3) IIC flag registers 0, 1 (IICF0, IICF1) The IICFn register sets the I C0n operation mode and indicates the I C bus status. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read-only.
Page 545 V850ES/JF3-L CAPTER 17 I C BUS Note After reset: 00H Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH <7> <6> <1> <0> IICFn STCFn IICBSYn STCENn IICRSVn (n = 0, 1) STCFn STTn bit clear Start condition issued Start condition cannot be issued, STTn bit cleared...
Page 546 V850ES/JF3-L CAPTER 17 I C BUS (4) IIC clock select registers 0, 1 (IICCL0, IICCL1) The IICCLn register sets the transfer clock for I C0n. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only.
Page 547 V850ES/JF3-L CAPTER 17 I C BUS (5) IIC function expansion registers 0, 1 (IICX0, IICX1) The IICXn register sets I C0n function expansion (valid only in the high-speed mode). These registers can be read or written in 8-bit or 1-bit units.
Page 548 V850ES/JF3-L CAPTER 17 I C BUS Table 17-2. Clock Settings (1/2) IICX0 IICCL0 Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 2.50 MHz ≤ f ≤...
Page 549 V850ES/JF3-L CAPTER 17 I C BUS Table 17-2. Clock Settings (2/2) IICX1 IICCL1 Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLX1 SMC1 CL11 CL10 2.50 MHz ≤ f ≤...
Page 550 V850ES/JF3-L CAPTER 17 I C BUS (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKSm register controls the I C0n division clock (n = 0, 1). These registers control the I C00 division clock via the OCKS0 register and the I C01 division clock via the OCKS1 register.
Page 551 V850ES/JF3-L CAPTER 17 I C BUS (9) Slave address registers 0, 1 (SVA0, SVA1) The SVAn register holds the I C bus’s slave address. These registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. However, rewriting this register is prohibited when the IICSn.STDn bit = 1 (start condition detection).
Page 552: I C Bus Mode Functions
V850ES/JF3-L CAPTER 17 I C BUS 17.5 I C Bus Mode Functions 17.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0, 1). SCL0n ....This pin is used for serial clock input and output.
Page 553: I C Bus Definitions And Control Methods
1). When a start condition is detected, the IICSn.STDn bit is set (1) (n = 0, 1). Caution When the IICCn.IICEn bit of the V850ES/JF3-L is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line.
Page 554: Addresses
V850ES/JF3-L CAPTER 17 I C BUS 17.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 555: Transfer Direction Specification
V850ES/JF3-L CAPTER 17 I C BUS 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 556: Ack
V850ES/JF3-L CAPTER 17 I C BUS 17.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues.
Page 557: Stop Condition
V850ES/JF3-L CAPTER 17 I C BUS 17.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition (n = 0, A stop condition is generated when the master device outputs to the slave device when serial transfer has been completed.
Page 558: Wait State
V850ES/JF3-L CAPTER 17 I C BUS 17.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1).
Page 559 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-12. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master after output of ninth clock.
Page 560: Wait State Cancellation Method
V850ES/JF3-L CAPTER 17 I C BUS 17.6.7 Wait state cancellation method In the case of I C0n, wait state can be canceled normally in the following ways (n = 0, 1). • By writing data to the IICn register • By setting the IICCn.WRELn bit to 1 (wait state cancellation) •...
Page 561: I C Interrupt Request Signals (Intiicn)
V850ES/JF3-L CAPTER 17 I C BUS 17.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing (n = 0, 1).
Page 562 V850ES/JF3-L CAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0...
Page 563 V850ES/JF3-L CAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5...
Page 564: Slave Device Operation (When Receiving Slave Address Data (Address Match))
V850ES/JF3-L CAPTER 17 I C BUS 17.7.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4...
Page 565 V850ES/JF3-L CAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5...
Page 566 V850ES/JF3-L CAPTER 17 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5...
Page 567 V850ES/JF3-L CAPTER 17 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0...
Page 568: Slave Device Operation (When Receiving Extension Code)
V850ES/JF3-L CAPTER 17 I C BUS 17.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4...
Page 569 V850ES/JF3-L CAPTER 17 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5...
Page 570 V850ES/JF3-L CAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5...
Page 571 V850ES/JF3-L CAPTER 17 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0...
Page 572: Operation Without Communication
V850ES/JF3-L CAPTER 17 I C BUS 17.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1 Δ 1: IICSn register = 00000001B Remarks 1. Δ: Generated only when SPIEn bit = 1 2.
Page 573 V850ES/JF3-L CAPTER 17 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing)
Page 574: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
V850ES/JF3-L CAPTER 17 I C BUS 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 Δ2 1: IICSn register = 01000110B (Example: When IICSn.ALDn bit is read during interrupt servicing) Δ...
Page 575 V850ES/JF3-L CAPTER 17 I C BUS (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ3 1: IICSn register = 10001110B 2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 576 V850ES/JF3-L CAPTER 17 I C BUS (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 Δ3 1: IICSn register = 1000X110B 2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 577 V850ES/JF3-L CAPTER 17 I C BUS (5) When arbitration loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn Δ2 1: IICSn register = 1000X110B Δ 2: IICSn register = 01000001B Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1...
Page 578 V850ES/JF3-L CAPTER 17 I C BUS (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIMn bit = 0 IICCn.STTn bit = 1 ↓ AD6 to AD0 D7 to D0...
Page 579 V850ES/JF3-L CAPTER 17 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ↓ AD6 to AD0 D7 to D0 Δ4...
Page 580 V850ES/JF3-L CAPTER 17 I C BUS (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIMn bit = 0 IICCn.SPTn bit = 1 ↓ AD6 to AD0 D7 to D0...
Page 581: Interrupt Request Signal (Intiicn) Generation Timing And Wait Control
V850ES/JF3-L CAPTER 17 I C BUS 17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below (n = 0, 1).
Page 582 V850ES/JF3-L CAPTER 17 I C BUS (4) Wait cancellation method The four wait cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • By start condition setting (IICCn.STTn bit = 1) Note •...
Page 583: Address Match Detection Method
V850ES/JF3-L CAPTER 17 I C BUS 17.9 Address Match Detection Method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1).
Page 584: Arbitration
V850ES/JF3-L CAPTER 17 I C BUS 17.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs.
Page 585: Wakeup Function
V850ES/JF3-L CAPTER 17 I C BUS Table 17-5. Status During Arbitration and Interrupt Request Signal Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 Transmitting address transmission At falling edge of eighth or ninth clock following byte transfer...
Page 586: Communication Reservation
V850ES/JF3-L CAPTER 17 I C BUS 17.14 Communication Reservation 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used.
Page 587 V850ES/JF3-L CAPTER 17 I C BUS Table 17-6. Wait Periods Clock Selection CLXn SMCn CLn1 CLn0 Wait Period (when OCKSm = 18H set) 26 clocks /2 (when OCKSm = 10H set) 52 clocks /3 (when OCKSm = 11H set) 78 clocks...
Page 588 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-14. Communication Reservation Timing STTn Write to Program processing IICn Set SPDn Communication Hardware processing reservation and INTIICn STDn SCL0n SDA0n Generated by master with bus access Remark n = 0, 1 STTn:...
Page 589 V850ES/JF3-L CAPTER 17 I C BUS The communication reservation flowchart is illustrated below. Figure 17-16. Communication Reservation Flowchart SET1 STTn Sets STTn bit (communication reservation). Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM).
Page 590: When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
V850ES/JF3-L CAPTER 17 I C BUS 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used •...
Page 591: Cautions
(3) When the IICCn.IICEn bit of the V850ES/JF3-L is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.
Page 592: Communication Operations
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the V850ES/JF3-L loses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication.
Page 593: Master Operation In Single Master System
V850ES/JF3-L CAPTER 17 I C BUS 17.16.1 Master operation in single master system Figure 17-17. Master Operation in Single Master System START Note Initialize I C bus Refer to Table 4-15 Settings When Port Pins Are Used for Alternate Functions...
Page 594 V850ES/JF3-L CAPTER 17 I C BUS 17.16.2 Master operation in multimaster system Figure 17-18. Master Operation in Multimaster System (1/3) START Refer to Table 4-15 Settings When Port Pins Are Used for Alternate Functions Set ports to set the I C mode before this function is used.
Page 595 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-18. Master Operation in Multimaster System (2/3) Communication reservation enabled Communication start preparation STTn = 1 (start condition generation) Securing wait time by software Wait (refer to Table 17-6) MSTSn = 1? INTIICn...
Page 596 INTIICn interrupt occurrence to confirm the arbitration result. 3. When using the V850ES/JF3-L as the slave in the multimaster system, confirm the status using the IICSn and IICFn registers for each INTIICn interrupt occurrence to determine the next processing.
Page 597: Slave Operation
V850ES/JF3-L CAPTER 17 I C BUS 17.16.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 598 V850ES/JF3-L CAPTER 17 I C BUS For reception, receive the required number of data and do not return ACK for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition.
Page 599 V850ES/JF3-L CAPTER 17 I C BUS The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are executed.
Page 600: Timing Of Data Communication
V850ES/JF3-L CAPTER 17 I C BUS 17.17 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 601 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-22. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn...
Page 602 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-22. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IICn data IICn data IICn ACKDn STDn...
Page 603 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-22. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn data IICn address ACKDn...
Page 604 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-23. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn...
Page 605 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-23. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (2/3) (b) Data Processing by master device ← ← IICn IICn FFH Note IICn...
Page 606 V850ES/JF3-L CAPTER 17 I C BUS Figure 17-23. Example of Slave to Master Communication (When 8-Clock → 9-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (3/3) (c) Stop condition Processing by master device ← IICn address ←...
Page 607: Chapter 18 Dma Function (Dma Controller)
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) The V850ES/JF3-L includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory).
Page 608: Configuration
V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.2 Configuration On-chip Internal RAM peripheral I/O Internal bus On-chip peripheral I/O bus DMA source address Data Address register n (DSAnH/DSAnL) control control DMA destination address register n (DDAnH/DDAnL) DMA transfer count Count...
Page 609: Registers
V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3).
Page 610 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3).
Page 611 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (3) DMA transfer count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer.
Page 612 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3).
Page 613 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are write- only.
Page 614 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O.
Page 615 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Table 18-1. DMA Start Factors IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source DMA request by interrupt disabled INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTTQ0OV INTTQ0CC0 INTTQ0CC1 INTTQ0CC2 INTTQ0CC3 INTTP0OV INTTP0CC0...
Page 616: Transfer Targets
V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.4 Transfer Targets Table 18-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled). Table 18-2. Relationship Between Transfer Targets Transfer Destination Internal ROM On-Chip Internal RAM External Memory Peripheral I/O ×...
Page 617: Transfer Types
V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.6 Transfer Types As a transfer type, the 2-cycle transfer is supported. In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination.
Page 618: Dma Channel Priorities
V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The priorities are checked for every transfer cycle.
Page 619: Dma Transfer Start Factors
V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started.
Page 620: Dma Abort Factors
0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt controller (INTC) (n = 0 to 3). The V850ES/JF3-L does not output a terminal count signal to an external device. Therefore, confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
Page 621 Figure 18-1. Priority of DMA (1) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation Read Write Read Write Read DMA transfer processing processing for transfer for transfer for transfer Idle Idle DMA2...
Page 622 Figure 18-2. Priority of DMA (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation Read Read Write Write Read DMA transfer processing for transfer processing for transfer for transfer Idle Idle DMA0...
Page 623 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Figure 18-3. Period in Which DMA Transfer Request Is Ignored (1) System clock DMAn transfer Note 1 request DFn bit Note 2 Note 2 Note 2 CPU processing DMA0 processing CPU processing Mode of processing...
Page 624 Figure 18-4. Period in Which DMA Transfer Request Is Ignored (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation DMA transfer Read Write Read Write Read processing processing for transfer for transfer for transfer...
Page 625: Cautions
V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.13 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, see 3.4.8 (1) (a) System wait control...
Page 626 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized.
Page 627 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O).
Page 628 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (8) Bus arbitration for CPU Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU.
Page 629 V850ES/JF3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (12) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00),...
Page 630: Chapter 19 Interrupt/Exception Processing Function
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/JF3-L is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 49 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 631 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (1/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − Reset Interrupt RESET RESET pin input RESET 0000H 00000000H Undefined Reset input by internal source −...
Page 632 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (2/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register Maskable Interrupt INTTP5OV TMP5 overflow TMP5 0250H 00000250H nextPC TP5OVIC INTTP5CC0 TMP5 capture 0/compare 0 match...
Page 633 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing is started. Note, however, that the restored PC when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextPC (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished).
Page 634: Non-Maskable Interrupts
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals.
Page 635 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2) (b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing Non-maskable Non-maskable interrupt request signal generated during non-maskable interrupt servicing interrupt being INTWDT2 serviced • NMI request generated during NMI servicing •...
Page 636: Operation
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW.
Page 637: Restore
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 638: Np Flag
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) From INTWDT2 signal Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2) by using the RETI instruction is disabled. Execute the following software reset processing. Figure 19-4. Software Reset Processing INTWDT2 occurs.
Page 639: Maskable Interrupts
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JF3-L has 55 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
Page 640 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-5. Maskable Interrupt Servicing INT input INTC acknowledged xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt...
Page 641: Restore
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 642: Priorities Of Maskable Interrupts
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 643 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b...
Page 644 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i...
Page 645 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-8. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 646: Interrupt Control Register (Xxicn)
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units.
Page 647 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2. Interrupt Control Register (xxICn) (1/2) Address Register <7> <6> FFFFF110H LVIIC LVIIF LVIMK LVIPR2 LVIPR1 LVIPR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2...
Page 648: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2. Interrupt Control Register (xxICn) (2/2) Address Register <7> <6> FFFFF170H DMAIC0 DMAIF0 DMAMK0 DMAPR02 DMAPR01 DMAPR00 FFFFF172H DMAIC1 DMAIF1 DMAMK1 DMAPR12 DMAPR11 DMAPR10 FFFFF174H DMAIC2 DMAIF2 DMAMK2 DMAPR22 DMAPR21 DMAPR20 FFFFF176H DMAIC3...
Page 649 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: FFFFH Address: IMR3 FFFFF106H, IMR3L FFFFF106H, IMR3H FFFFF107H Note IMR3 (IMR3H IMR3L WTMK WTIMK KRMK DMAMK3 DMAMK2 DMAMK1 DMAMK0 After reset: FFFFH Address: IMR2 FFFFF104H, IMR2L FFFFF104H, IMR2H FFFFF105H UA2RMK/ Note IMR2 (IMR2H...
Page 650: In-Service Priority Register (Ispr)
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced.
Page 651: Id Flag
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.7 ID flag This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW. Reset sets this flag to 00000020H.
Page 652: Software Exception
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 19.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 653: Restore
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.2 Restore Restoration from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address.
Page 654: Ep Flag
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H NP EP ID SAT CY OV Exception processing status Exception processing not in progress.
Page 655: Exception Trap
19.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/JF3-L, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 19.5.1 Illegal opcode An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B.
Page 656 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-11. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restoration Restoration from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 657: Debug Trap
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. (1) Operation Upon occurrence of a debug trap, the CPU performs the following processing.
Page 658 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW.
Page 659: External Interrupt Request Input Pins (Nmi And Intp0 To Intp7)
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) 19.6.1 Noise elimination (1) Eliminating noise on NMI pin The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer.
Page 660 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0) The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6.
Page 661 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt falling, rising edge specification register 3 (INTF3, INTR3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP7).
Page 662 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H) The INTF9H and INTR9H registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP4 to INTP6).
Page 663 V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Noise elimination control register (NFC) Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using the NFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among...
Page 664: Interrupt Acknowledge Time Of Cpu
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt.
Page 665: Periods In Which Interrupts Are Not Acknowledged By Cpu
V850ES/JF3-L CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
Page 666: Chapter 20 Key Interrupt Function
V850ES/JF3-L CHAPTER 20 KEY INTERRUPT FUNCTION CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register.
Page 667: Register
V850ES/JF3-L CHAPTER 20 KEY INTERRUPT FUNCTION 20.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units.
Page 668: Chapter 21 Standby Function
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION CHAPTER 21 STANDBY FUNCTION 21.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 21-1.
Page 669 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Figure 21-1. Status Transition Reset Internal oscillation clock operation Sub-IDLE mode operates, WDT overflow PLL operates) Oscillation stabilization wait Normal operation mode Subclock operation mode Clock through mode operates, (PLL operates) PLL operates) HALT mode...
Page 670: Registers
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. This register is a special register that can be written only by the special sequence combinations (see 3.4.7 Special registers).
Page 671 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units.
Page 672 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register.
Page 673 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION (4) Regulator protection register (REGPR) The REGPR register is used to protect the regulator output voltage level control register 0 (REGOVL0) so that illegal data is not written to REGOVL0. Data cannot be written to the REGOVL0 register unless enabling data (C9H) is written to the REGPR register.
Page 674 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION (5) Regulator output voltage level control register 0 (REGOVL0) This register is used to select the low-voltage STOP mode, low-voltage subclock operation mode, or low-voltage sub-IDLE mode. The power consumption can be reduced by lowering the output voltage of the regulator.
Page 675: Halt Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.3 HALT Mode 21.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 676 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. Table 21-3. Operating Status in HALT Mode Setting of HALT Mode Operating Status Item When Subclock Is Not Used...
Page 677: Idle1 Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.4 IDLE1 Mode 21.4.1 Setting and operation status The IDLE1 mode is set by clearing the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops.
Page 678 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Table 21-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed.
Page 679: Idle2 Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.5 IDLE2 Mode 21.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other on-chip peripheral functions stops.
Page 680 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Table 21-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address after securing the prescribed setup time.
Page 681: Securing Setup Time When Releasing Idle2 Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the flash memory after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after the IDLE2 mode is set.
Page 682: Stop Mode/Low-Voltage Stop Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.6 STOP Mode/Low-Voltage STOP Mode 21.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode. The low-voltage STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 after setting the REGOVL0 register to 01H in normal operation mode.
Page 683 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Be sure to observe the above sequence. Note, however, that step <7> may be performed at any time as long as it is done after step <6>. (The setting in step <7> may be made without problem, even after the low-voltage STOP mode has been released.) Cautions 1, Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode/low-voltage STOP mode.
Page 684 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Table 21-8. Operating Status in STOP Mode Setting of STOP Mode Operating Status Item When Subclock Is Not Used When Subclock Is Used Operable Main clock oscillator Stops oscillation − Subclock oscillator Oscillaties Internal oscillator...
Page 685 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Table 21-9. Operating Status in Low-Voltage STOP Mode Setting of Low-Voltage Operating Status STOP Mode When Subclock Is Not Used When Subclock Is Used Item Operable Main clock oscillator Stops oscillation − Subclock oscillator Oscillates...
Page 686: Releasing Stop Mode/Low-Voltage Stop Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.6.2 Releasing STOP mode/low-voltage STOP mode The STOP mode and low-voltage STOP mode are released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the STOP mode and low-voltage STOP mode, or reset signal (reset by RESET pin input, WDT2RES signal, or low-voltage detector (LVI)).
Page 687: Re-Setting After Release Of Low-Voltage Stop Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.6.3 Re-setting after release of low-voltage STOP mode (1) If low-voltage STOP mode is released by interrupt The status after the low-voltage STOP mode has been released is as follows. • Regulator: Automatically returns to the normal level.
Page 688: Securing Oscillation Stabilization Time When Releasing Stop Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.6.4 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set.
Page 689: Subclock Operation Mode/Low-Voltage Subclock Operation Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.7 Subclock Operation Mode/Low-Voltage Subclock Operation Mode 21.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. The low-voltage subclock operation mode is set by setting the REGOVL0 register to 02H in the subclock operation mode.
Page 690 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION (1) Procedure for setting “subclock operation mode” → “low-voltage subclock operation mode” Make the following settings in the subclock operation mode. <1> Stop the main clock and PLL. <2> Stop the functions that are specified to be stopped in Table 21-14 Operating Status in Low-Voltage Sub- IDLE Mode.
Page 691 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Table 21-11. Operating Status in Subclock Operation Mode Setting of Subclock Operation Mode Operating Status Item When Main Clock Is Oscillating When Main Clock Is Stopped Operable Subclock oscillator Oscillates Internal oscillator Oscillation enabled Note...
Page 692 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Table 21-12. Operating Status in Low-Voltage Subclock Operation Mode Setting of Low-Voltage Operating Status Subclock Operation Main Clock Is Stopped (Must Be Stopped) Mode Item Operable Subclock oscillator Oscillates Internal oscillator Oscillation enabled Note Stops operation...
Page 693: Releasing Subclock Operation Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.7.2 Releasing subclock operation mode The subclock operation mode is released by a reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)) when the CK3 bit is set to 0.
Page 694: Sub-Idle Mode/Low-Voltage Sub-Idle Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode 21.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode. The low-voltage sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 after setting the REGOVL0 register to 02H in the subclock operation...
Page 695 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Be sure to observe the above sequence. For the setting of the subclock operation mode, see 21.7.1 Setting and operation status. Cautions 1. Following the store instruction to the PSC register for setting the sub-IDLE mode/low-voltage sub- IDLE mode, insert the five or more NOP instructions.
Page 696 V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION Table 21-14. Operating Status in Low-Voltage Sub-IDLE Mode Setting of Low-Voltage Operating Status Sub-IDLE Mode Main Clock Is Stopped (Must Be Stopped) Item Operable Subclock oscillator Oscillates Internal oscillator Oscillation enabled Note Stops operation Stops operation...
Page 697: Releasing Sub-Idle Mode/Low-Voltage Sub-Idle Mode
V850ES/JF3-L CHAPTER 21 STANDBY FUNCTION 21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode The sub-IDLE mode/low-voltage sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-IDLE mode/low-voltage sub-IDLE mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)).
Page 698: Chapter 22 Reset Functions
V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS CHAPTER 22 RESET FUNCTIONS 22.1 Overview The following reset functions are available. (1) Four kinds of reset sources • External reset input via the RESET pin • Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES) •...
Page 699: Registers To Check Reset Source
CHAPTER 22 RESET FUNCTIONS 22.2 Registers to Check Reset Source The V850ES/JF3-L has four kinds of reset sources. After a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (RESF).
Page 700: Operation
V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS 22.3 Operation 22.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released.
Page 701 V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS Figure 22-2. Timing of Reset Operation by RESET Pin Input Initialized to f /8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation...
Page 702 V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS Figure 22-3. Timing of Power-on Reset Operation Initialized to f /8 operation RESET Analog delay Internal system reset signal Oscillation stabilization time count Must be on-chip regulator stabilization Overflow of timer for oscillation stabilization Note...
Page 703: Reset Operation By Watchdog Timer 2
V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS 22.3.2 Reset operation by watchdog timer 2 When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status.
Page 704 V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS Figure 22-4. Timing of Reset Operation by WDT2RES Signal Generation Initialized to f /8 operation WDT2RES Analog delay Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflow R01UH0017EJ0400 Rev.4.00 Page 688 of 816...
Page 705: Reset Operation By Low-Voltage Detector
V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS 22.3.3 Reset operation by low-voltage detector If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status.
Page 706: Operation After Reset Release
V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS 22.3.4 Operation after reset release After the reset is released, the main clock starts oscillation and oscillation stabilization time (differs depending on the option byte setting. For details, see CHAPTER 27 OPTION BYTE). Is secured, and the CPU starts program execution.
Page 707: Reset Function Operation Flow
V850ES/JF3-L CHAPTER 22 RESET FUNCTIONS 22.3.5 Reset function operation flow Start (reset source generated) Note 1 Set RESF register → Reset occurs reset release Internal oscillation and main clock oscillation start, WDT2 count up starts (reset mode) Main clock oscillation stabilization...
Page 708: Cautions
When executing the power-on reset operation, the supply voltage must be within the guaranteed operating range when the reset status is released. The usable range of the supply voltage of the V850ES/JF3-L differs depending on the internal operating frequency (2.2 to 2.7 V @5 MHz (MAX.) or 2.7 to 3.6 V @20 MHz (MAX.)). Therefore, observe the following points.
Page 709: Chapter 23 Clock Monitor
V850ES/JF3-L CHAPTER 23 CLOCK MONITOR CHAPTER 23 CLOCK MONITOR 23.1 Functions The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset.
Page 710: Register
V850ES/JF3-L CHAPTER 23 CLOCK MONITOR 23.3 Register The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.7 Special registers).
Page 711: Operation
V850ES/JF3-L CHAPTER 23 CLOCK MONITOR 23.4 Operation This section explains the functions of the clock monitor. The start and stop conditions are as follows. <Start condition> Enabling operation by setting the CLM.CLME bit to 1 <Stop conditions> • While oscillation stabilization time is being counted after STOP mode is released •...
Page 712 V850ES/JF3-L CHAPTER 23 CLOCK MONITOR (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in Figure 23-2.
Page 713 V850ES/JF3-L CHAPTER 23 CLOCK MONITOR (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is automatically started.
Page 714: Chapter 24 Low-Voltage Detector (Lvi)
V850ES/JF3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.1 Functions The low-voltage detector (LVI) has the following functions. • If the interrupt occurrence at low-voltage detection is selected, the low-voltage detector compares the supply voltage ) and the detected voltage (V ), and generates an internal interrupt signal when the supply voltage drops or rises across the detected voltage.
Page 715: Registers
V850ES/JF3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.3 Registers The low-voltage detector is controlled by the following registers. • Low voltage detection register (LVIM) • Low voltage detection level select register (LVIS) (1) Low voltage detection register (LVIM) The LVIM register is a special register. This can be written only in the special combination of the sequences (see 3.4.7 Special registers).
Page 716 V850ES/JF3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) (2) Low voltage detection level select register (LVIS) The LVIS register is used to select the level of low voltage to be detected. This register can be read or written in 8-bit units. After reset: Note...
Page 717: Operation
V850ES/JF3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4 Operation Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 24.4.1 To use for internal reset signal <To start operation>...
Page 718: To Use For Interrupt
V850ES/JF3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4.2 To use for interrupt <To start operation> <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS.LVIS0 bit. <3> Set the LVIM.LVION bit to 1 (to enable operation).
Page 719: Chapter 25 Crc Function
V850ES/JF3-L CHAPTER 25 CRC FUNCTION CHAPTER 25 CRC FUNCTION 25.1 Functions • CRC operation circuit for detection of data block errors • Generation of 16-bit CRC code using a CRC-CCITT (X + 1) generation polynomial for blocks of data of any length in 8-bit units •...
Page 720: Registers
V850ES/JF3-L CHAPTER 25 CRC FUNCTION 25.3 Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H...
Page 721: Operation
V850ES/JF3-L CHAPTER 25 CRC FUNCTION 25.4 Operation An example of the CRC operation circuit is shown below. Figure 25-2. CRC Operation Circuit Operation Example (LSB First) (1) Setting of CRCIN = 01H (2) CRCD register read 1189H CRC code is stored The code when 01H is sent LSB first is (1000 0000).
Page 722: Usage Method
V850ES/JF3-L CHAPTER 25 CRC FUNCTION 25.5 Usage Method How to use the CRC logic circuit is described below. Figure 25-3. CRC Operation Flow Start Write of 0000H to CRCD register Input data exists? CRCD register read CRCIN register write [Basic usage method] <1>...
Page 723 V850ES/JF3-L CHAPTER 25 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB-first as an example.
Page 724: Chapter 26 Regulator
CHAPTER 26 REGULATOR CHAPTER 26 REGULATOR 26.1 Outline The V850ES/JF3-L includes a regulator to reduce power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffers).
Page 725: Operation
CHAPTER 26 REGULATOR 26.2 Operation The regulator of the V850ES/JF3-L always operates in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, subclock operation mode, sub-IDLE mode, or during reset). The output voltage of the regulator can be lowered in the STOP mode, subclock operation mode, and sub-IDLE mode to reduce the power consumption.
Page 726: Chapter 27 Option Byte
When writing a program to the V850ES/JF3-L, be sure to set the option data in the program at address 000007AH. The data in this area cannot be rewritten during program execution.
Page 727 V850ES/JF3-L CHAPTER 27 OPTION BYTE The following shows program examples when the CA850 is used. [Program example] #-------------------------------------------------------------- # OPTION_BYTES #-------------------------------------------------------------- .section "OPTION_BYTES" .byte 0b00000001 -- 0x7a .byte 0b00000000 -- 0x7b .byte 0b00000000 -- 0x7c .byte 0b00000000 -- 0x7d .byte 0b00000000 -- 0x7e .byte 0b00000000 -- 0x7f...
Page 728: Chapter 28 Flash Memory
PD70F3736: 256 KB flash memory Flash memory versions offer the following advantages for development environments and mass production applications. For altering software after the V850ES/JF3-L is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models.
Page 729: Memory Configuration
CHAPTER 28 FLASH MEMORY 28.2 Memory Configuration The V850ES/JF3-L internal flash memory area is divided into 64 or 128 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory located at the addresses of blocks 0 to 15 is replaced by the physical memory located at the addresses of blocks 16 to 31.
Page 730: Functional Outline
CHAPTER 28 FLASH MEMORY 28.3 Functional Outline The internal flash memory of the V850ES/JF3-L can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/JF3-L has already been mounted on the target system or not (off- board/on-board programming).
Page 731 V850ES/JF3-L CHAPTER 28 FLASH MEMORY Table 28-2. Basic Functions Support ( √ : Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming √ √ Blank check The erasure status of the entire memory is checked. √ × Note...
Page 732 V850ES/JF3-L CHAPTER 28 FLASH MEMORY Table 28-4. Security Setting Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (√: Executable, ×: Not Executable, −: Not Supported) On-Board/ Self Programming On-Board/ Self Off-Board Programming Off-Board Programming Programming Chip erase command: ×...
Page 733: Rewriting By Dedicated Flash Programmer
28.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/JF3-L is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series).
Page 734: Communication Mode
V850ES/JF3-L CHAPTER 28 FLASH MEMORY 28.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/JF3-L is performed by serial communication using the UARTA0 or CSIB0 interface of the V850ES/JF3-L. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 28-3. Communication with Dedicated Flash Programmer (UARTA0)
Page 735 The dedicated flash programmer outputs the transfer clock, and the V850ES/JF3-L operates as a slave. When the PG-FP5 is used as the dedicated flash programmer, it generates the following signals to the V850ES/JF3-L. For details, refer to the PG-FP5 User’s Manual (U18865E).
Page 736 V850ES/JF3-L CHAPTER 28 FLASH MEMORY Table 28-6. Wiring of V850ES/JF3-L Flash Writing Adapters (FA-80GK-GAK-B, FA-80GC-GAD-B) Flash Programmer (FG-FP5) Name of FA CSIB0 + HS Used CSIB0 Used UARTA0 Used Connection Pin Board Pin Signal Name Pin Function Pin Name Pin No.
Page 737 V850ES/JF3-L CHAPTER 28 FLASH MEMORY Figure 28-6. Wiring Example of V850ES/JF3-L Flash Writing Adapter (FA-80GK-GAK-B, FA-80GC-GAD-B) (In CSIB0 + HS Mode) (1/2) 60 Note 1 V850ES/JF3-L Connect this pin to GND. Connect this pin to VDD. Note 3 Note 2 μ...
Page 738 V850ES/JF3-L CHAPTER 28 FLASH MEMORY Figure 28-6. Wiring Example of V850ES/JF3-L Flash Writing Adapter (FA-80GA-GAK-B, FA-80GC-GAD-B) (In CSIB0 + HS Mode) (2/2) Notes 1. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor.
Page 739: Flash Memory Control
V850ES/JF3-L CHAPTER 28 FLASH MEMORY 28.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 28-7. Procedure for Manipulating Flash Memory Start Switch to flash memory programming mode Supplies FLMD0 pulse Select communication system Manipulate flash memory End? R01UH0017EJ0400 Rev.4.00...
Page 740: Selection Of Communication Mode
28.4.4 Selection of communication mode In the V850ES/JF3-L, the communication mode is selected by inputting pulses (11 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 741: Communication Commands
Dedicated flash programmer V850ES/JF3-L The following shows the commands for flash memory control in the V850ES/JF3-L. All of these commands are issued from the dedicated flash programmer, and the V850ES/JF3-L performs the processing corresponding to the commands. Table 28-7. Flash Memory Control Commands...
Page 742: Pin Connection
V850ES/JF3-L CHAPTER 28 FLASH MEMORY 28.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode.
Page 743 V850ES/JF3-L CHAPTER 28 FLASH MEMORY Table 28-8. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released FLMD0 FLMD1 Operation Mode Don’t care Normal operation mode Flash memory programming mode Setting prohibited (3) Serial interface pin The following shows the pins used by each serial interface.
Page 744 V850ES/JF3-L Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/JF3-L outputs affects the other device, isolate the signal on the other device side. V850ES/JF3-L Dedicated flash programmer connection pin...
Page 745 V850ES/JF3-L CHAPTER 28 FLASH MEMORY (4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 746: Rewriting By Self Programming
28.5.1 Overview The V850ES/JF3-L supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user...
Page 747: Features
(1) Secure self programming (boot swap function) The V850ES/JF3-L supports a boot swap function that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. By writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 to 15.
Page 748: Standard Self Programming Flow
V850ES/JF3-L CHAPTER 28 FLASH MEMORY 28.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 28-17. Standard Self Programming Flow Flash memory manipulation Flash environment initialization processing • Disable accessing flash area •...
Page 749: Flash Functions
V850ES/JF3-L CHAPTER 28 FLASH MEMORY 28.5.4 Flash functions Table 28-10. Flash Function List Function Name Outline Support √ FlashInit Self-programming library initialization √ FlashEnv Flash environment start/end √ FlashFLMDCheck FLMD pin check √ FlashStatusCheck Hardware processing execution status check √...
Page 750: Internal Resources Used
V850ES/JF3-L CHAPTER 28 FLASH MEMORY 28.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 28-11. Internal Resources Used Resource Name...
Page 751: Chapter 29 On-Chip Debug Function
The V850ES/JF3-L on-chip debug function can be implemented by the following two methods. • Using the DCU (debug control unit) On-chip debug function is implemented by the on-chip DCU in the V850ES/JF3-L, with using the DRST, DCK, DMS, DDI, and DDO pins as the debug interface pins.
Page 752: Debugging With Dcu
V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1 Debugging with DCU Programs can be debugged using the debug interface pins (DRST, DCK, DMS, DDI, and DDO) to connect the on-chip debug emulator (MINICUBE). 29.1.1 Connection circuit example Figure 29-1. Circuit Connection Example When Debug Interface Pins Are Used for Communication Interface...
Page 753 V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION (2) DCK This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from MINICUBE. In the on-chip debug unit, the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling edge.
Page 754: Maskable Functions
CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1.3 Maskable functions Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JF3-L functions are listed below. Table 29-2. Maskable Functions Maskable Functions with ID850QB...
Page 755 V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION Note After reset: 01H Address: FFFFF9FCH < > OCDM OCDM0 OCDM0 Operation mode Selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the P05/INTP2/DRST pin.
Page 756: Operation
V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0.
Page 757: Cautions
V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1.6 Cautions (1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN (program execution), the break function may malfunction. (2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal is input from a pin.
Page 758: Debugging Without Using Dcu
1 kΩ RESET signal Reset circuit Notes 1. Connect TXDA0/SOB0 (transmit side) of the V850ES/JF3-L to RXD/SI (receive side) of the target connector, and TXD/SO (transmit side) of the target connector to RXDA0/SIB0 (receive side) of the V850ES/JF3-L. 2. This pin may be used to supply a clock from MINICUBE2 during flash memory programming. For details, refer to CHAPTER 28 FLASH MEMORY.
Page 759 Pin No. SI/RXD Input Pin to receive commands and data from P41/SOB0 P30/TXDA0 V850ES/JF3-L SO/TXD Output Pin to transmit commands and data to V850ES/JF3-L P40/SIB0 P31/RXDA0 − Note Output Clock output pin for 3-wire serial communication P42/SCKB0 Not needed −...
Page 760: Maskable Functions
CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.2.2 Maskable functions Only reset signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JF3-L functions are listed below. Table 29-4. Maskable Functions Maskable Functions with ID850QB Corresponding V850ES/JF3-L Functions −...
Page 761 V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION Figure 29-4. Memory Spaces Where Debug Monitor Programs Are Allocated Internal ROM Internal RAM 00FFFFFH 3FFEFFFH (16 bytes) 3FFEFF0H Access-prohibited area Internal RAM area (2 KB) Note 1 Note 3 Access-prohibited area CSI/UART receive...
Page 762 V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION (3) Reset vector A reset vector includes the jump instruction for the debug monitor program. [How to secure areas] It is not necessary to secure this area intentionally. When downloading a program, however, the debugger rewrites the reset vector in accordance with the following cases.
Page 763 To avoid problems that may occur during the debugger startup, however, it is recommended to secure this area in advance, using the compiler. The following shows examples for securing the area, using the Renesas Electronics compiler CA850. Add the assemble source file and link directive code, as shown below.
Page 764 V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION (5) Securement of communication serial interface UARTA0 or CSIB0 is used for communication between MINICUBE2 and the target system. The settings related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur.
Page 765 V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION • Port registers when UARTA0 is used When UARTA0 is used, port registers are set to make the TXDA0 and RXDA0 pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.)
Page 766: Cautions
V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.2.4 Cautions (1) Handling of device that was used for debugging Do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed. Moreover, do not embed the debug monitor program into mass-produced products.
Page 767: Rom Security Function
29.3 ROM Security Function 29.3.1 Security ID The flash memory versions of the V850ES/JF3-L perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator.
Page 768: Setting
V850ES/JF3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.3.2 Setting The following shows how to set the ID code as shown in Table 29-5. When the ID code is set as shown in Table 29-5, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4”...
Page 769: Chapter 30 Electrical Specifications
V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS CHAPTER 30 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +4.6 Supply voltage = EV = AV = AV REF0 REF1 −0.5 to +4.6 = EV = AV...
Page 770 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low P02 to P06, P30 to P35, P38, P39, Per pin P40 to P42, P50 to P55, P90, P91, Total of all pins...
Page 771 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Capacitance (T = 25°C, V = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit I/O capacitance = 1 MHz Unmeasured pins returned to 0 V Operating Conditions = −40 to +85°C, V...
Page 772 = 2.7 to 3.6 V Note 6 in PLL mode Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JF3-L so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics.
Page 773 The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/JF3-L so that the internal operating conditions are within the specifications of the DC and AC characteristics. = −20 to +80°C) (ii) Murata Mfg.
Page 774 The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/JF3-L so that the internal operating conditions are within the specifications of the DC and AC characteristics. R01UH0017EJ0400 Rev.4.00 Page 758 of 816...
Page 775 Oscillation Note 2 stabilization time Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JF3-L so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics. 2. Time required from when V reaches the oscillation voltage range (2.2 V (MIN.)) to when the crystal resonator...
Page 776 The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/JF3-L so that the internal operating conditions are within the specifications of the DC and AC characteristics. = −40 to +85°C) (ii) Citizen Miyota Co., Ltd.: Crystal resonator (T...
Page 777 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS PLL Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input frequency Output frequency μ Lock time After V reaches 2.7 V (MIN.)
Page 778 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (1/3) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high RESET, FLMD0, P97 to P99, P913 to 0.8EV...
Page 779 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (2/3) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit − 1.0 Output voltage, high...
Page 780 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (3/3) REF0 REF1 Note 1 Note 2 Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 3...
Page 781 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Data Retention Characteristics In STOP mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage...
Page 782 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points (V , AV , EV REF0 Measurement points AC Test Output Measurement Points Measurement points Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 783 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS CLKOUT Output Timing = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN.
Page 784 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Bus Timing (1) In multiplexed bus mode (a) Read/write cycle (CLKOUT asynchronous) = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V = EV = AV = 0 V, C...
Page 785 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode CLKOUT (output) A16, A17 (output) <9> Hi-Z AD0 to AD15 (I/O) Address Data <6> <7> <12> ASTB (output) <17> <14> <29> <8> <13> <11> <10> <15> RD (output) <16>...
Page 786 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode CLKOUT (output) A16, 17 (output) <30> AD0 to AD15 (I/O) Address Data <6> <7> ASTB (output) <17> <18> <14> <11> <19> <20> WR0, WR1 (output) <16> <25>...
Page 787 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (b) Read/write cycle (CLKOUT synchronous): In multiplexed bus mode = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V = EV = AV = 0 V, C = 50 pF)
Page 788 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode CLKOUT (output) <31> A16, A17 (output) <37> <42> AD0 to AD15 (I/O) Address Data <33> <33> <41> ASTB (output) WR0, WR1 (output) <34> <34> WAIT (input) <38>...
Page 789 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (2) Bus hold (a) CLKOUT asynchronous = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V = EV = AV = 0 V, C = 50 pF) REF0...
Page 790 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (b) CLKOUT synchronous = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN.
Page 791 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Power On/Power Off/Reset Timing = −40 to +85°C, V = 2.2 to 3.6 V, V = EV = AV = 0 V, C = 50 pF) VREF0 VREF1 Parameter Symbol Conditions MIN. MAX. Unit ↑ → V ↑...
Page 792 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS Key Return Timing = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V = EV = AV = 0 V, C = 50 pF) REF1 Parameter Symbol Conditions MIN.
Page 793 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS CSIB Timing (1) Master mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN. MAX. Unit 2.7 V ≤...
Page 794 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS C Bus Mode = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V = EV = AV = 0 V) REF0 REF1 Parameter Symbol Normal Mode High-Speed Mode Unit MIN.
Page 795 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS C Bus Mode <108> <109> SCL0n (I/O) <112> <110> <114> <113> <111> <115> <107> <116> <107> SDA0n (I/O) <106> <113> <114> Stop Start Restart Stop condition condition condition condition Remark n = 0, 1 A/D Converter = −40 to +85°C, V...
Page 796 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS D/A Converter = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution ±1.2 Overall error R = 2 MΩ...
Page 797 Supply voltage <R> Number of rewrites Used for updating programs When Retained 1,000 times using flash memory programmer and Renesas Electronics self programming 15 years library Used for updating data When using Retained 10,000 times Renesas Electronics EEPROM emulation library (usable ROM size:...
Page 798 V850ES/JF3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (3) Programming characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Chip erase time = 20 MHz (batch processing) Write time per 256 bytes = 20 MHz Block internal verify time = 20 MHz Block blank check time...
Page 799: Chapter 31 Package Drawings
V850ES/JF3-L CHAPTER 31 PACKAGE DRAWINGS CHAPTER 31 PACKAGE DRAWINGS 80-PIN PLASTIC LQFP (14x14) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 14.00±0.20 14.00±0.20 17.20±0.20 17.20±0.20 1.70 MAX. 0.125±0.075 1.40±0.05 0.25 +0.08 0.30 −0.04 0.125 +0.075 −0.025 0.80 0.886±0.15 1.60±0.20 3° +5°...
Page 800 V850ES/JF3-L CHAPTER 31 PACKAGE DRAWINGS 80-PIN PLASTIC LQFP (FINE PITCH) (12x12) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 12.00±0.20 12.00±0.20 14.00±0.20 14.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 +0.07 0.20 −0.03 0.125 +0.075 −0.025 0.50 0.60±0.15 1.00±0.20 3° +5° θ...
Page 801: Chapter 32 Recommended Soldering Conditions
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. The V850ES/JF3-L is lead-free products. 2. For soldering methods and conditions other than those recommended above, please contact an Renesas Electronics sales representative. R01UH0017EJ0400 Rev.4.00...
Page 802: Appendix A Development Tools
V850ES/JF3-L APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/JF3-L. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 803 V850ES/JF3-L APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Software package Language processing software Debugging software • Integrated debugger • C compiler package • System simulator • Device file Control software • Project manager Embedded software Note 1 • Real-time OS (Windows only) •...
Page 804: Software Package
V850ES/JF3-L APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) commonly used with V850 microcontrollers are included Software package for V850 this package. microcontrollers μ Part number: S××××SP850 Remark ×××× in the part number differs depending on the host machine and OS used.
Page 805: Debugging Tools (Hardware)
V850ES/JF3-L APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) ® A.4.1 When using IECUBE QB-V850ESSX2 The system configuration when connecting the QB-V850ESSX2 to the host machine (PC-9821 series, PC/AT compatible) is shown below. Even if optional products are not prepared, connection is possible.
Page 806 (S type: QB-80GC-TC-01S (GC package), QB-80GK-TC-01S (GK package), T type: QB-80GC-NQ-01T (GC package), QB-80GK-NQ-01T(GK package)) <14> Target system Notes 1. Download the device file from the Renesas Electronics website. http://www2.renesas.com/micro/ja/ods/index.html 2. Under development 3. Supplied with the device depending on the ordering number.
Page 807 The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using the V850ES/JF3-L. It supports the integrated debugger ID850QB. This emulator should be used in combination with a power supply unit and emulation probe. Use the USB interface cable to connect this emulator to the host machine.
Page 808: When Using Minicube Qb-V850Mini
8830E-026-170S (supplied with MINICUBE) Note 2 KEL connector 8830E-026-170L (sold separately) Notes 1. Download the device file from the Renesas Electronics website. http://www2.renesas.com/micro/ja/ods/index.html 2. Product of KEL Corporation Remark The numbers in the angular brackets correspond to the numbers in Figure A-3.
Page 809: When Using Minicube2 Qb-Mini2
MINICUBE. The cable length is approximately 2 m. <4> MINICUBE2 This on-chip debug emulator serves to debug hardware and software when On-chip debug emulator developing application systems using the V850ES/JF3-L. It supports integrated debugger ID850QB. <5> 16-pin target cable Cable to connect MINICUBE2 and the target system.
Page 810: Debugging Tools (Software)
V850ES/JF3-L APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) ID850QB This debugger supports the in-circuit emulators for V850 microcontrollers. The Integrated debugger ID850QB is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
Page 811: Embedded Software
V850ES/JF3-L APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software μ RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to ITRON 3.0 specifications. Real-time OS A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than the RX850.
Page 812: Flash Memory Writing Tools
V850ES/JF3-L APPENDIX A DEVELOPMENT TOOLS A.7 Flash Memory Writing Tools Flashpro IV Flash programmer dedicated to microcontrollers with on-chip flash memory. (part number: PG-FP4) Flashpro V (part number: PG-FP5) Flash programmer QB-MINI2 (MINICUBE2) On-chip debug emulator with programming function. FA-80GC-GAD-B Flash memory writing adapter used connected to the Flashpro IV and FlashproV, etc.
Page 813: Appendix B Register Index
V850ES/JF3-L APPENDIX B REGISTER INDEX APPENDIX B REGISTER INDEX (1/9) Symbol Name Unit Page ADA0CR0 A/D conversion result register 0 ADA0CR0H A/D conversion result register 0H ADA0CR1 A/D conversion result register 1 ADA0CR1H A/D conversion result register 1H ADA0CR2 A/D conversion result register 2...
Page 814 V850ES/JF3-L APPENDIX B REGISTER INDEX (2/9) Symbol Name Unit Page CB1STR CSIB1 status register CB1TIC Interrupt control register INTC CB1TX CSIB1 transmit data register CB1TXL CSIB1 transmit data register L CB2CTL0 CSIB2 control register 0 CB2CTL1 CSIB2 control register 1...
Page 815 V850ES/JF3-L APPENDIX B REGISTER INDEX (3/9) Symbol Name Unit Page DDA3L DMA destination address register 3L DMAC DMAIC0 Interrupt control register INTC DMAIC1 Interrupt control register INTC DMAIC2 Interrupt control register INTC DMAIC3 Interrupt control register INTC DSA0H DMA source address register 0H...
Page 816 V850ES/JF3-L APPENDIX B REGISTER INDEX (4/9) Symbol Name Unit Page IMR2L Interrupt mask register 2L INTC IMR3 Interrupt mask register 3 INTC IMR3H Interrupt mask register 3H INTC IMR3L Interrupt mask register 3L INTC INTF0 External interrupt falling edge specification register 0...
Page 817 V850ES/JF3-L APPENDIX B REGISTER INDEX (5/9) Symbol Name Unit Page Port 4 function register Port Port 5 function register Port Port 9 function register Port PF9H Port 9 function register H Port PF9L Port 9 function register L Port PFC0...
Page 818 V850ES/JF3-L APPENDIX B REGISTER INDEX (6/9) Symbol Name Unit Page PMC5 Port 5 mode control register Port PMC9 Port 9 mode control register Port PMC9H Port 9 mode control register H Port PMC9L Port 9 mode control register L Port...
Page 819 V850ES/JF3-L APPENDIX B REGISTER INDEX (7/9) Symbol Name Unit Page TP0CCR1 TMP0 capture/compare register 1 Timer TP0CNT TMP0 counter read buffer register Timer TP0CTL0 TMP0 control register 0 Timer TP0CTL1 TMP0 control register 1 Timer TP0IOC0 TMP0 I/O control register 0...
Page 820 V850ES/JF3-L APPENDIX B REGISTER INDEX (8/9) Symbol Name Unit Page TQ0CCIC0 Interrupt control register INTC TQ0CCIC1 Interrupt control register INTC TQ0CCIC2 Interrupt control register INTC TQ0CCIC3 Interrupt control register INTC TQ0CCR0 TMQ0 capture/compare register 0 Timer TQ0CCR1 TMQ0 capture/compare register 1...
Page 821 V850ES/JF3-L APPENDIX B REGISTER INDEX (9/9) Symbol Name Unit Page WDTM2 Watchdog timer mode register 2 WTIC Interrupt control register INTC WTIIC Interrupt control register INTC Watch timer operation mode register R01UH0017EJ0400 Rev.4.00 Page 805 of 816 Sep 30, 2010...
Page 822: Appendix C Instruction Set List
V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST APPENDIX C INSTRUCTION SET LIST C.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions.
Page 823 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length.
Page 824 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Code Condition Formula...
Page 825: Instruction Set (In Alphabetical Order)
V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV × × × × reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1] × × × ×...
Page 826 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2)
Page 827 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 × × × × ×...
Page 828 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] × × imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16)
Page 829 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1]...
Page 830 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2]...
Page 831 V850ES/JF3-L APPENDIX C INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions.
Page 832: Appendix D Revision History
V850ES/JF3-L APPENDIX D REVISION HISTORY APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition Page Description p. 454 Modification of Caution in 15.6.10 Receive data noise filter p. 454 Modification of Figure 15-13 Timing of RXDAn Signal Judged as Noise p.
Page 833 V850ES/JF3-L User’s Manual: Hardware Publication Date: Rev.4.00 Sep 30, 2010 Published by: Renesas Electronics Corporation...
Page 834 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
Page 835 V850ES/JF3-L R01UH0017EJ0400...

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