Renesas V850ES/JE3-E User Manual
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Renesas V850ES/JE3-E User Manual

Renesas V850ES/JE3-E User Manual

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V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E
32
RENESAS MCU
V850ES/Jx3-E Microcontrollers
V850ES/JE3-E
μPD70F3826
μPD70F3827
μPD70F3828
μPD70F3829
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
V850ES/JF3-E
μPD70F3830
μPD70F3831
μPD70F3832
μPD70F3833
V850ES/JG3-E
μPD70F3834
μPD70F3835
μPD70F3836
μPD70F3837
Rev.1.00 Jun, 2012

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Summary of Contents for Renesas V850ES/JE3-E

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.

  • Page 4: Index

    It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E → Read this manual according to the CONTENTS.
  • Page 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
  • Page 6 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E Hardware User’s...
  • Page 7 Silicon Storage Technology, Inc. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America.

  • Page 8: Table Of Contents

    CONTENTS CHAPTER 1 INTRODUCTION......................... 21 General ............................21 Features ............................ 25 Application Fields ........................27 Ordering Information ....................... 27 Pin Configuration (Top View)....................28 Function Block Configuration....................33 1.6.1 Internal block diagram........................33 1.6.2 Internal units ...........................36 CHAPTER 2 PIN FUNCTIONS ....................... 39 List of Pin Functions........................
  • Page 9 4.3.8 Port DL............................152 Port Register Settings When Alternate Function Is Used..........154 Cautions ..........................163 4.5.1 Cautions on setting port pins......................163 4.5.2 Cautions on bit manipulation instruction for port n register (Pn)............166 4.5.3 Cautions on on-chip debug pins....................167 4.5.4 Cautions on P54/INTP11/DRST pin....................167 4.5.5 Cautions on P51 pin when power is turned on................167 4.5.6 Hysteresis characteristics ......................167 CHAPTER 5 CLOCK GENERATION FUNCTION ................
  • Page 10 Overview ..........................302 Functions ..........................302 Configuration.......................... 303 7.3.1 Pin configuration ...........................305 7.3.2 Register configuration ........................306 Registers ..........................307 Operation ..........................324 7.5.1 Interval timer mode (TAB1MD2 to TAB1MD0 bits = 000) .............325 7.5.2 External event count mode (TAB1MD2 to TAB1MD0 bits = 001)..........334 7.5.3 External trigger pulse output mode (TAB1MD2 to TAB1MD0 bits = 010) ........343 7.5.4 One-shot pulse output mode (TAB1MD2 to TAB1MD0 bits = 011) ..........356 7.5.5 PWM output mode (TAB1MD2 to TAB1MD0 bits = 100) ..............365...
  • Page 11 CHAPTER 10 MOTOR CONTROL FUNCTION .................. 550 10.1 Functional Overview ......................550 10.2 Configuration.......................... 551 10.3 Control Registers ........................555 10.4 Operation ..........................565 10.4.1 System outline ..........................565 10.4.2 Dead-time control (generation of negative-phase wave signal).............570 10.4.3 Interrupt culling function ........................576 10.4.4 Operation to rewrite register with transfer function................584 10.4.5 TAA4 tuning operation for A/D conversion start trigger signal output..........602 10.4.6 A/D conversion start trigger output function ..................605...
  • Page 12 14.5 Operation ..........................668 14.5.1 Basic operation ..........................668 14.5.2 Conversion operation timing ......................669 14.5.3 Trigger mode..........................670 14.5.4 Operation mode ..........................672 14.5.5 Power-fail compare mode ......................676 14.6 Cautions ..........................681 14.7 How to Read A/D Converter Characteristics Table ............685 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ..........689 15.1 Features ..........................
  • Page 13 16.6.4 Single transfer mode (slave mode, transmission mode) ...............753 16.6.5 Single transfer mode (slave mode, reception mode)..............755 16.6.6 Single transfer mode (slave mode, transmission/reception mode)..........757 16.6.7 Continuous transfer mode (master mode, transmission mode).............759 16.6.8 Continuous transfer mode (master mode, reception mode) ............761 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) ........764 16.6.10 Continuous transfer mode (slave mode, transmission mode) ..........768...
  • Page 14 17.12 Arbitration ..........................840 17.13 Wakeup Function ........................841 17.14 Communication Reservation ....................842 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)......842 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) .......846 17.15 Cautions ..........................847 17.16 Communication Operations ....................
  • Page 15 18.9.1 Message reception........................954 18.9.2 Reading reception data .........................955 18.9.3 Receive history list function......................956 18.9.4 Mask function..........................958 18.9.5 Multi buffer receive block function....................960 18.9.6 Remote frame reception........................961 18.10 Message Transmission......................962 18.10.1 Message transmission......................962 18.10.2 Transmit history list function.....................964 18.10.3 Automatic block transmission (ABT) ..................966 18.10.4 Transmission abort process .....................968 18.10.5...
  • Page 16 19.6.4 EPC control registers ........................1051 19.6.5 Data hold registers........................1103 19.6.6 EPC request data registers ......................1126 19.6.7 Bridge register..........................1141 19.6.8 DMA register ..........................1145 19.6.9 Peripheral control registers ......................1149 19.7 STALL Handshake or No Handshake................. 1153 19.8 Register Values in Specific Status ..................1154 19.9 FW Processing ........................
  • Page 17 22.6.1 Noise elimination.........................1426 22.6.2 Edge detection ..........................1426 22.7 Interrupt Acknowledge Time of CPU.................. 1433 22.8 Periods in Which Interrupts Are Not Acknowledged by CPU ......... 1434 22.9 Cautions ..........................1434 CHAPTER 23 KEY INTERRUPT FUNCTION (V850ES/JE3-E and V850ES/JG3-E) ...... 1435 Index-10...
  • Page 18 23.1 Function ..........................1435 23.2 Register ..........................1436 23.3 Cautions ..........................1436 CHAPTER 24 STANDBY FUNCTION ....................1437 24.1 Overview ..........................1437 24.2 Registers ..........................1439 24.3 HALT Mode ........................... 1442 24.3.1 Setting and operation status .......................1442 24.3.2 Releasing HALT mode ........................1442 24.4 IDLE1 Mode...........................
  • Page 19 27.3 Registers ..........................1476 27.4 Operation ..........................1478 27.4.1 To use for internal reset signal....................1478 27.4.2 To use for interrupt........................1479 27.5 RAM Retention Voltage Detection Operation..............1480 CHAPTER 28 CRC FUNCTION......................1481 28.1 Functions ..........................1481 28.2 Configuration........................1481 28.3 Registers ..........................1482 28.4 Operation ..........................
  • Page 20 31.2.4 Cautions............................1538 31.3 ROM Security Function ....................... 1539 31.3.1 Security ID ..........................1539 31.3.2 Setting............................1540 CHAPTER 32 ELECTRICAL SPECIFICATIONS ................1542 32.1 Absolute Maximum Ratings ....................1542 32.2 Capacitance .......................... 1544 32.3 Operating Conditions ......................1544 32.4 Oscillator Characteristics....................1545 32.4.1 Main clock oscillator characteristics ....................1545 32.4.2 Subclock oscillator characteristics ....................1546 32.4.3 PLL characteristics........................1547 32.4.4 Internal oscillator characteristics ....................1547...

  • Page 21: Chapter 1 Introduction

    V850ES/JF3-E, and V850ES/JG3-E feature multiply instructions realized by a hardware multiplier, saturated operation instructions, and bit manipulation instructions. Table 1-1 lists the products of the V850ES/JE3-E, Table 1-2 lists the products of the V850ES/JF3-E, and Table 1-3 lists the products of the V850ES/JG3-E.
  • Page 22 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JE3-E Product List Generic Name V850ES/JE3-E μ μ μ μ Part Number PD70F3826 PD70F3827 PD70F3828 PD70F3829 Internal Flash memory 64 KB 128 KB 256 KB 256 KB memory Internal RAM 16 KB...
  • Page 23 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION Table 1-2. V850ES/JF3-E Product List Generic Name V850ES/JF3-E μ μ μ μ Part Number PD70F3830 PD70F3831 PD70F3832 PD70F3833 Internal Flash memory 64 KB 128 KB 256 KB 256 KB memory Internal RAM 16 KB...
  • Page 24 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION Table 1-3. V850ES/JG3-E Product List Generic Name V850ES/JG3-E μ μ μ μ Part Number PD70F3834 PD70F3835 PD70F3836 PD70F3837 Internal Flash memory 64 KB 128 KB 256 KB 256 KB memory Internal RAM 16 KB...

  • Page 25: Features

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION Features Minimum instruction execution time: 20.0 ns (main clock (f ) = 50 MHz: V = 2.85 to 3.6 V) μ 30.5 s (subclock (f ) = 32.768 kHz) 32 bits × 32 registers General-purpose registers: Signed multiplication (16 ×...
  • Page 26 Internal oscillation clock: 220 kHz (TYP.) Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode 64-pin plastic LQFP (fine pitch) (10 × 10) (V850ES/JE3-E) Package: 64-pin plastic WQFN (9 × 9) (V850ES/JE3-E) (Under planning) 80-pin plastic WQFN (fine pitch) (12 × 12) (V850ES/JF3-E) (Under planning) 100-pin plastic WQFN (fine pitch) (14 ×...

  • Page 27: Application Fields

    256 KB μ 100-pin plastic LQFP (fine pitch) (14 × 14) PD70F3837GK-GAK-AX 256 KB μ Note 121-pin plastic FBGA (8 × 8) PD70F3837F1-CAH-A Note Under planning. Remark The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E are lead-free products. R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 28: Pin Configuration (Top View)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION Pin Configuration (Top View) • V850ES/JE3-E 64-pin plastic LQFP (fine pitch) (10 × 10) μ μ PD70F3826GB-GAT-AX PD70F3827GB-GAT-AX μ μ PD70F3828GB-GAT-AX PD70F3829GB-GAT-AX P1MDIO REF0 P1MDC P1COL P02/NMI P1CRS P20/INTP01 Note2 REGC Note1 FLMD0 Note2...
  • Page 29 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION • V850ES/JE3-E 64-pin plastic WQFN (9 × 9) μ μ PD70F3826GB-6B4-AX PD70F3827GB-6B4-AX μ μ PD70F3828GB-6B4-AX PD70F3829GB-6B4-AX P1MDIO REF0 exposed die pad P1MDC P1COL P02/NMI P1CRS P20/INTP01 Note2 REGC Note1 FLMD0 Note2 REGC P1RXCLK RESET...
  • Page 30 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION • V850ES/JF3-E 80-pin plastic LQFP (fine pitch) (12 × 12) μ μ PD70F3830GK-GAT-AX PD70F3831GK-GAT-AX μ μ PD70F3832GK-GAT-AX PD70F3833GK-GAT-AX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61...
  • Page 31 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION • V850ES/JG3-E 100-pin plastic LQFP (fine pitch) (14 × 14) μ μ PD70F3834GC-UEU-AX PD70F3835GC-UEU-AX μ μ PD70F3836GC-UEU-AX PD70F3837GC-UEU-AX P93/TOAB1B2/TRGAB1/KR3/INTP14 REF0 P92/TOAB1T2/TOAB12/TIAB12/KR2/INTP13 P02/NMI P91/TOAB1B1/TIAB10/KR1/TOAB10 P03/INTP00/ADTRG/EXCLK P90/TOAB1T1/TOAB11/TIAB11/KR0/INTP12 P20/INTP01 P1MDIO P1MDC P21/RTCDIV/RTCCL P22/RTC1HZ/INTP02 P1COL P1CRS Note2 REGC...
  • Page 32 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION Pin names ADTRG: A/D trigger input Real-time output port RTP00 to RTP05: ANI0 to ANI9: Analog input RXDC0 to RXDC3: Receive data ASCKC0: Asynchronous serial clock SCKF0 to SCKF4 Serial clock Analog reference voltage...

  • Page 33: Function Block Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram • V850ES/JE3-E Ethernet Timer/counter function Note1 Note2 controller 16-bit timer/ function event counter AB: EXCLK 1 ch 32-bit barrel Multiplier 16 × 16 → 32 shifter DataRAM...
  • Page 34 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION • V850ES/JF3-E Ethernet Timer/counter function Note1 Note2 controller TIAB10 to TIAB13, EVTAB1, TRGAB1, 16-bit timer/ function TOAB1OFF event counter AB: EXCLK 1 ch TOAB10 to TOAB13 32-bit barrel Multiplier TOAB1T1 to TOAB1T3, 16 × 16 → 32...
  • Page 35 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION • V850ES/JG3-E Ethernet Timer/counter function Note1 Note2 controller TIAB10 to TIAB13, EVTAB1, TRGAB1, 16-bit timer/ function TOAB1OFF event counter AB: EXCLK 1 ch TOAB10 to TOAB13 32-bit barrel Multiplier TOAB1T1 to TOAB1T3, 16 × 16 → 32...

  • Page 36: Internal Units

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
  • Page 37 Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E include eight kinds of serial interfaces (asynchronous serial interface C (UARTC), 3-wire variable-length serial interface F (CSIF), an I C bus interface (I...
  • Page 38 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 1 INTRODUCTION (16) CRC function A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data is provided on-chip. (17) DCU (debug control unit) An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided.

  • Page 39: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS List of Pin Functions The names and functions of the pins of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E are described below. There are three types of pin I/O buffer power supplies: AV , EV , and UV .
  • Page 40 JE3E JF3E JG3E Port 0 (Refer to 4. 3. 1) 2-bit I/O port (V850ES/JG3-E) − − INTP00/ADTRG/EXCLK 1-bit I/O port (V850ES/JE3-E, V850ES/JF3-E) Input/output can be specified in 1-bit units. Port 2 (Refer to 4. 3. 2) INTP01 7-bit I/O port (V850ES/JG3-E) −...
  • Page 41 − − − PDL0 Port DL (Refer to 4. 3. 8) 11-bit I/O port (V850ES/JG3-E) − − − PDL1 1-bit I/O port (V850ES/JE3-E, V850ES/JF3-E) − − − PDL2 Input/output can be specified in 1-bit units. − − − PDL3 −...
  • Page 42 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (2) Non-port Pins (1/6) Pin Name Pin No. Function Alternate Function JE3E JF3E JG3E − − ADTRG Input External trigger input for A/D converter P03/INTP00/EXCLK ANI0 Input Analog voltage input for A/D converter...
  • Page 43 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (2/6) Pin Name Pin No. Function Alternate Function JE3E JF3E JG3E − − INTP00 Input External interrupt request input P03/ADTRG/EXCLK (maskable, analog noise elimination) INTP01 Analog noise elimination or digital noise − −...
  • Page 44 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (3/6) Pin Name Pin No. Function Alternate Function JE3E JF3E JG3E − P1COL Input Conflict detection input for Ethernet − P1CRS Input Carrier detection input for Ethernet − P1MDC Output Serial transfer clock output −...
  • Page 45 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (4/6) Pin Name Pin No. Function Alternate Function JE3E JF3E JG3E SCKF0 Serial clock I/O (CSIF0 to CSIF4) P42/TIAA40/TOAA40/RTP02 − SCKF1 P25/TIAA30/TOAA30 SCKF2 P32/ASCKC0/TIAA10/TOAA10 − − SCKF3 P915 − − SCKF4 P35/TIAA21/TOAA21/TOAA1OFF/INTP06 −...
  • Page 46 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (5/6) Pin Name Pin No. Function Alternate Function JE3E JF3E JG3E TIAA40 Input External event count input/capture trigger P42/SCKF0/TOAA40/RTP02 input/external trigger input (TAA4) − − TIAA41 Input Capture trigger input (TAA4) P45/TOAA41/RTP05 −...
  • Page 47 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (6/6) Pin Name Pin No. Function Alternate Function JE3E JF3E JG3E TXDC0 Output Serial transmit data output (UARTC0 to P30/SIF2/TIAA00/TOAA00 UARTC3) − TXDC1 P23/SIF1/SDA00/INTP03 N-ch open-drain output selectable Note TXDC2 P36/SDA02/CTXD0 TXDC3 P40/SIF0/SDA01/RTP00 −...

  • Page 48: Pin States

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various operation modes are described below. Table 2-2. Pin Operation Status in Each Operation Mode Note 2 Note 2 Pin Name When Power Is...

  • Page 49: Pin I/O Circuit Types, I/O Buffer Power Supplies And Connection Of Unused Pins

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/3) Pin Name Alternate Function Pin number I/O Circuit Type Recommended Connection JE3E JF3E JG3E 10-D Input: Independently connect to EV or V via a resistor.
  • Page 50 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Alternate Function Pin number I/O Circuit Type Recommended Connection JE3E JF3E JG3E ANI0 11-G Input: Independently connect to or AV via a resistor. REF0 ANI1 Output: Leave open. ANI2 ANI3...
  • Page 51 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Alternate Function Pin number I/O Circuit Type Recommended Connection JE3E JF3E JG3E − P1COL Independently connect to EV or V via a resistor. − P1CRS − P1MDC − P1MDIO 5-AG −...
  • Page 52 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 10-D Type 2 Data P-ch IN/OUT Open drain N-ch Output disable Note Schmitt-triggered input with hysteresis characteristics Input enable Type 5 Type 10-N Data Data P-ch P-ch...

  • Page 53: Cautions

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 2 PIN FUNCTIONS Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P51/INTP08/DDO pin R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 54: Chapter 3 Cpu Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. Features Minimum instruction execution time: 20 ns (operating with main clock (f ) of 50 MHz: V = 2.85 to 3.6 V)

  • Page 55: Cpu Register Set

    CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E can be classified into two types: general- purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual.

  • Page 56: Program Register Set

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable.

  • Page 57: System Register Set

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below.
  • Page 58 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
  • Page 59 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
  • Page 60 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
  • Page 61 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
  • Page 62 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.

  • Page 63: Operation Modes

    In this mode, the internal flash memory can be programmed by using a flash programmer. (3) On-chip debug mode The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E are provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications.

  • Page 64: Address Space

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space For instruction addressing, up to a combined total of 1 MB of internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.

  • Page 65: Wraparound Of Cpu Address Space

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.

  • Page 66: Memory Map

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION 3.4.3 Memory map The areas shown below are reserved in the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E. Figure 3-2. Data Memory Map (Physical Addresses) 03FFFFFFH 03FFFFFFH On-chip peripheral I/O area (4 KB) 03FFF000H (80 KB)
  • Page 67 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION Figure 3-3. Memory Map of USB function/Ethernet 0 2 F F F F F F H Access-prohibited area 0 0 2 F 0 0 0 4 H 0 0 2 F 0 0 0 3 H...
  • Page 68 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION Figure 3-4. Program Memory Map 0 3 F F F F F F H Use prohibited (program fetch prohibited area) 0 3 F F F 0 0 0 H 0 3 F F E F F F H...

  • Page 69: Areas

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION 3.4.4 Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (64 KB) 64 KB are allocated to addresses 00000000H to 000FFFFH in the following products.
  • Page 70 (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E include a data-only RAM in addition to the internal RAM. The RAM capacity of V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E is as follows.
  • Page 71 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (a) Internal RAM (16 KB) An internal RAM area of 16 KB is allocated to addresses 03FFB000H to 03FFEFFFH in the following products. Accessing addresses 03FF0000H to 03FFAFFFH is prohibited. μ • PD70F3826, 70F3830, 70F3834 Figure 3-8.
  • Page 72 F F F F 0 0 0 0 H (3) Data-only RAM (16 KB) A data-only RAM area of 16 KB is allocated to addresses 00280000H to 00283FFFH in the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E. Accessing addresses 3FF0000H to 03FF2FFFH is prohibited.
  • Page 73 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (4) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-12. On-Chip Peripheral I/O Area Physical address space Logical address space 0 3 F F F F F F H...

  • Page 74: Recommended Use Of Address Space

    Recommended use of address space The architecture of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
  • Page 75 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer.
  • Page 76 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION Figure 3-13. Recommended Memory Map Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H...

  • Page 77: Peripheral I/O Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION 3.4.6 Peripheral I/O registers (1/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note 1 FFFFF004H Port DL register 0000H √ √ Note 1 FFFFF004H Port DL register L PDLL √...
  • Page 78 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (2/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF100H Interrupt mask register 0 IMR0 FFFFH √ √ FFFFF100H Interrupt mask register 0L IMR0L √ √ FFFFF101H Interrupt mask register 0H IMR0H √...
  • Page 79 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (3/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF130H Interrupt control register PIC15 √ √ FFFFF132H Interrupt control register PIC16 √ √ FFFFF134H Interrupt control register PIC17 √ √...
  • Page 80 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (4/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF196H Interrupt control register CF0RIC/IICIC1 /UC3RIC √ √ FFFFF198H Interrupt control register CF0TIC/UC3TIC √ √ FFFFF19AH Interrupt control register CF1RIC/IICIC0 /UC1RIC √...
  • Page 81 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (5/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF1FAH In-service priority register ISPR √ FFFFF1FCH Command register PRCMD Undefined √ √ FFFFF1FEH Power save control register √ √ FFFFF200H...
  • Page 82 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (6/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ Note FFFFF400H Port 0 register √ √ Note FFFFF404H Port 2 register √ √ Note FFFFF406H Port 3 register √ Note...
  • Page 83 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (7/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF560H TAB1 control register 0 TAB1CTL0 √ √ FFFFF561H TAB1 control register 1 TAB1CTL1 √ √ FFFFF562H TAB1 I/O control register 0 TAB1IOC0 √...
  • Page 84 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (8/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF630H TAA0 control register 0 TAA0CTL0 √ √ FFFFF631H TAA0 control register 1 TAA0CTL1 √ √ FFFFF632H TAA0 I/O control register 0 TAA0IOC0 √...
  • Page 85 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (9/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF666H TAA3 capture/compare register 0 TAA3CCR0 0000H √ FFFFF668H TAA3 capture/compare register 1 TAA3CCR1 0000H √ FFFFF66AH TAA3 counter read buffer register...
  • Page 86 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (10/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF828H Processor clock control register √ √ FFFFF82CH PLL control register PLLCTL √ √ FFFFF82EH CPU operation clock status register CCLS √...
  • Page 87 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (11/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFFA2AH UARTC2 option control register 1 UC2OPT1 √ √ FFFFFA30H UARTC3 control register 0 UC3CTL0 √ FFFFFA31H UARTC3 control register 1 UC3CTL1 √...
  • Page 88 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (12/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFC12H External interrupt falling edge specification register 9 INTF9 0000H √ √ FFFFFC12H External interrupt falling edge specification register 9L INTF9L √...
  • Page 89 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (13/13) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFD24H CSIF2 receive data register CF2RX 0000H √ FFFFFD24H CSIF2 receive data register L CF2RXL √ FFFFFD26H CSIF2 transmit data register CF2TX 0000H √...

  • Page 90: Programmable Peripheral I/O Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION 3.4.7 Programmable peripheral I/O registers The BPC register is used to select the programmable peripheral I/O register area. The BPC register is valid only in the 70F3829, 70F3833, and 70F3837. (1) Peripheral I/O area select control register (BPC) This register can be read or written in 16-bit units.

  • Page 91: Special Registers

    Special registers Special registers are registers that are protected from being written with illegal data due to a program loop. The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E have the following eight special registers. • Power save control register (PSC) • Clock control register (CKC) •...
  • Page 92 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register.
  • Page 93 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
  • Page 94 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units.

  • Page 95: Cautions

    3.4.9 Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
  • Page 96 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
  • Page 97 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (2/2) Peripheral Function Register Name Access C00 to I IICS0 to IICS2 Read CRCD Write Note CAN controller C0GMABT, Read/Write + 1) / (2 + j) (MIN.) CANMOD Note (m = 0 to 31, a = 1 to 4) C0GMABTD, (2 ×...
  • Page 98 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 3 CPU FUNCTION (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...

  • Page 99: Chapter 4 Port Functions

    Basic Port Configuration The V850ES/JE3-E features a total of 26 I/O ports consisting of ports 0, 2 to 5, 7, and DL. The V850ES/JF3-E features a total of 42 I/O ports consisting of ports 0, 2 to 5, 7, 9, and DL.
  • Page 100 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS Figure 4-1. Port Configuration Diagram (V850ES/JE3-E) Port0 Port5 Port2 Port7 Port3 PDL5 PortDL Port4 Figure 4-2. Port Configuration Diagram (V850ES/JF3-E) Port0 Port5 Port2 Port6 Port3 Port9 P912 P913 PDL5 PortDL Port4 Figure 4-3. Port Configuration Diagram (V850ES/JG3-E)

  • Page 101: Port Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-4. Port Configuration (V850ES/JE3-E) Item Configuration Control register Port n mode register (PMn: n = 0, 2 to 5, 7, DL) Port n mode control register (PMCn: n = 0, 2 to 5, DL)
  • Page 102 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
  • Page 103 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
  • Page 104 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
  • Page 105 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1- bit units.
  • Page 106 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-4. Setting of Each Register and Pin Function Port mode Output mode “0” PMn register Input mode “1” Alternate function (when two alternate functions are available) “0”...

  • Page 107: Port 0

    CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 1-bit (V850ES/JE3-E and V850ES/JF3-E)/2-bit (V850ES/JG3-E) port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-8. Port 0 Alternate-Function Pins Pin Name Pin No.
  • Page 108 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) (a) V850ES/JE3-E and V850ES/JF3-E After reset: FFH R/W Address:FFFFF420H PM02 PM02 I/O mode control Output mode. Input mode. (b) V850ES/JG3-E After reset: FFH R/W Address:FFFFF420H PM03 PM02...
  • Page 109 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) (a) V850ES/JE3-E and V850ES/JF3-E After reset: FFH R/W Address:FFFFF440H PMC0 PMC02 PMC02 Specification of P02 pin operation mode I/O port NMI Input (b) V850ES/JG3-E After reset: 00H...
  • Page 110 Specification of P03 pin alternate function INTP00 input ADTRG input EXCLK input Setting prohibited (7) Port 0 function register (PF0) (a) V850ES/JE3-E and V850ES/JF3-E After reset: 00H R/W Address:FFFFFC60H PF02 PF02 Control of normal output or N-ch open-drain output Normal output...

  • Page 111: Port 2

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 2 Port 2 is a 1-bit (V850ES/JE3-E)/5-bit (V850ES/JF3-E)/7-bit (V850ES/JG3-E) port for which I/O settings can be controlled in 1-bit units. Port 2 includes the following alternate-function pins. Table 4-9. Port 2 Alternate-Function Pins Pin Name Pin No.
  • Page 112 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (1) Port 2 register (P2) (a) V850ES/JE3-E After reset: 00H (output latch) R/W Address: FFFFF404H Output data control (In output mode) Output 0. Output 1. (b) V850ES/JF3-E After reset: 00H (output latch) R/W Address: FFFFF404H Output data control (In output mode)(n=0,3 to 6) Output 0.
  • Page 113 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port 2 mode register (PM2) (a) V850ES/JE3-E After reset:FFH R/W Address: FFFFF424H PM20 PM20 I/O mode control Output mode Input mode (b) V850ES/JF3-E After reset:FFH R/W Address: FFFFF424H PM26 PM25 PM24 PM23...
  • Page 114 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (3) Port 2 mode control register (PMC2) (1/2) (a) V850ES/JE3-E After reset:00H R/W Address: FFFFF444H PMC2 PMC20 PMC20 Specification of P20 pin operation mode I/O port INTP01 input (b) V850ES/JF3-E After reset:00H R/W Address: FFFFF444H...
  • Page 115 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2/2) (c) V850ES/JG3-E After reset:00H R/W Address: FFFFF444H PMC2 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 PMC26 Specification of P26 pin operation mode I/O port TIAA31 input/TOAA31 input/INTP05 input PMC25 Specification of P25 pin operation mode...
  • Page 116 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (4) Port 2 function control register (PFC2) (V850ES/JF3-E, V850ES/JG3-E only) (a) V850ES/JF3-E After reset:00H R/W Address: FFFFF464H PFC2 PFC26 PFC25 PFC24 PFC23 (b) V850ES/JG3-E After reset:00H R/W Address: FFFFF464H PFC2 PFC26 PFC25 PFC24...
  • Page 117 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (6) Port 2 alternate function specifications PFCE26 PFC26 Specification of P26 pin alternate function (V850ES/JF3-E,V850ES/JG3-E only) TIAB31 input TOAB31 output INTP05 input Setting prohibited PFCE25 PFC25 Specification of P25 pin alternate function (V850ES/JF3-E,V850ES/JG3-E only)
  • Page 118 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (7) Port 2 function register (PF2) (a) V850ES/JE3-E After reset:00H R/W Address: FFFFFC64H PF20 PF20 Control of normal output or N-ch open-drain output Normal output N-ch open-drain output (b) V850ES/JF3-E After reset:00H R/W Address: FFFFFC64H...

  • Page 119: Port 3

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is a 5-bit (V850ES/JE3-E)/6-bit (V850ES/JF3-E)/8-bit (V850ES/JG3-E) port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-10. Port 3 Alternate-Function Pins Pin Name Pin No.
  • Page 120 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) (a) V850ES/JE3-E After reset:00H (output latch) R/W Address: FFFFF406H Output data control(in output mode) (n=0 to 2,6,7) Output 0. Output 1. (b) V850ES/JF3-E After reset:00H (output latch) R/W Address: FFFFF406H Output data control(in output mode) (n = 0 to 2,5 to 7) Output 0.
  • Page 121 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port 3 mode register (PM3) (a) V850ES/JE3-E After reset:FFH R/W Address: FFFFF426H PM37 PM36 PM32 PM31 PM30 PM3n I/O mode control (n = 0 to 2, 6,7) Output mode. Input mode (b) V850ES/JF3-E...
  • Page 122 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) (1/3) (a) V850ES/JE3-E After reset:00H R/W Address: FFFFF446H PMC3 PMC37 PMC36 PMC32 PMC31 PMC30 PMC37 Specification of P37pin operation mode I/O port Note RDXDC2 input/SCL02 I/O/CRXD0 input...
  • Page 123 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2/3) (b) V850ES/JF3-E After reset:00H R/W Address: FFFFF446 PMC3 PMC37 PMC36 PMC35 PMC32 PMC31 PMC30 PMC37 Specification of P37 pin operation mode I/O port Note RXDC2 input/SCL02 I/O/CRXD0 input PMC36 Specification of P36 pin operation mode...
  • Page 124 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (3/3) (c) V850ES/JG3-E After reset:00H R/W Address: FFFFF446H PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC37 Specification of P37 pin operation mode I/O port Note RXDC2 input/SCL02 I/O/CRXD0 input PMC36 Specification of P36 pin operation mode...
  • Page 125 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) (a) V850ES/JE3-E After reset:00H R/W Address: FFFFF446H PFC37 PFC36 PFC32 PFC31 PFC30 PFC3 (b) V850ES/JF3-E After reset:00H R/W Address: FFFFF446H PFC37 PFC36 PFC35 PFC32 PFC31 PFC30...
  • Page 126 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (5) Port 3 function control expansion register (PFCE3) (a) V850ES/JE3-E After reset:00H R/W Address: FFFFF706H Note Note PFCE3 PFCE32 PFCE31 PFCE30 PFCE37 PFCE36 μ Note PD70F3829 only (b) V850ES/JF3-E After reset:00H R/W Address: FFFFF706H...
  • Page 127 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS PFCE35 PFC35 Specification of P35 pin alternate function (V850ES/JF3-E, V850ES/JG3-E only) Note 1 SCKF4 I/O TIAA21 input TOAA21 output Note 2 TOAA1OFF input/INTP06 input Notes 1. V850ES/JG3-E only. V850ES/JF3-E is setting prohibited. 2. TOAA1OFF and INTP09 are alternate functions. When using the pin as the TOAA1OFF pin, disable INTP09 pin edge detection, which is the alternate function.
  • Page 128 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) (a) V850ES/JE3-E After reset:00H R/W Address: FFFFFC66H PF37 PF36 PF32 PF31 PF30 PF3n Control of normal output or N-ch open-drain output(n = 0 to 2,6,7) Normal output (CMOS output)

  • Page 129: Port 4

    CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit (V850ES/JE3-E and V850ES/JF3-E) and 6-bit (V850ES/JG3-E) port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-11 Port 4 Alternate-Function Pins Pin Name Pin No.
  • Page 130 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (1) Port 4 register (P4) (a) V850ES/JE3-E and V850ES/JF3-E After reset: 00H(output latch) R/W Address:FFFFF408H Output data control (In output mode) (n = 0 to 2) Output 0. Output 1. (b) V850ES/JG3-E After reset: 00H(output latch) R/W Address:FFFFF408H Output data control (In output mode) (n = 0 to 5) Output 0.
  • Page 131 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port 4 mode register (PM4) (a) V850ES/JE3-E and V850ES/JF3-E After reset: 00H(output latch) R/W Address:FFFFF428H PM42 PM41 PM40 PM4n I/O mode control (n = 0 to 2) Output mode Input mode (b) V850ES/JG3-E...
  • Page 132 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) (a) V850ES/JE3-E and V850ES/JF3-E After reset:00H R/W Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 Specification of P42 pin operation mode I/O port SCKF0 I/O/TIAA40 input/TOAA40 output/RTP02 output...
  • Page 133 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (4) Port 4 function control register (PFC4) (a) V850ES/JE3-E and V850ES/JF3-E After reset:00H R/W Address: FFFFF468H PFC4 PFC42 PFC41 PFC40 (b) V850ES/JG3-E After reset:00H R/W Address: FFFFF468H PFC4 PFC45 PFC42 PFC41 PFC40 Remark For details of alternate-function specification, see 4.3.4 (6) Port 4 alternate function...
  • Page 134 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (6) Port 4 alternate function specifications PFCE45 PFC45 Specification of P45 pin alternate function (V850ES/JG3-E only) Setting prohibited TIAA41 input TOAA41 output RTP05 output PFCE44 Specification of P44 pin alternate function (V850ES/JG3-E only)
  • Page 135 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (7) Port 4 function register (PF4) After reset:00H R/W Address: FFFFFC68H PF41 PF40 PF4n Control of normal output or N-ch open-drain output (n = 0,1) Normal output (CMOS output) N-ch open-drain output R01UH0232EJ0100 Rev. 1.00...

  • Page 136: Port 5

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 5-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-12. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name...
  • Page 137 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port 5 mode register (PM5) After reset: FFH R/W Address:FFFFF42AH PM54 PM53 PM52 PM51 PM50 PM5n I/O mode control (n= 0 to 4) Output mode. Intput mode. (3) Port 5 mode control register (PMC5)
  • Page 138 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (4) Port 5 function register (PF5) After reset: 00H R/W Address:FFFFFC6AH PF54 PF53 PF52 PF51 PF50 PF5n Control of normal output or N-ch open-drain output (n = 0 to 4) Normal output (CMOS output) N-ch open-drain output R01UH0232EJ0100 Rev.

  • Page 139: Port 7

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 7 Port 7 is a 10-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-13. Port 7 Alternate-Function Pins Pin Name Pin No.
  • Page 140 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L) After reset:FFH R/W Address: PM7L FFFFF42EH, PM7H FFFFF42FH PM7H PM79 PM78 PM7L PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70...

  • Page 141: Port 9 (V850Es/Jf3-E, V850Es/Jg3-E)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 9 (V850ES/JF3-E, V850ES/JG3-E) Port 9 is a 11-bit (V850ES/JF3-E)/ 13-bit (V850ES/JG3-E) port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-14. Port 9 Alternate-Function Pins Pin No.
  • Page 142 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) (a) V850ES/JF3-E After reset: 0000H (output latch) R/W Address: P9F FFFF412H, P9L FFFF412H, P9H FFFF413H P9 (P9H) P913 P912 (P9L) Output data control (In output mode) (n = 0 to 8,12,13) Output 0.
  • Page 143 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port 9 mode register (PM9) (a) V850ES/JF3-E After reset: FFFFH R/W Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H PM9 (PM9H) PM913 PM912 PM98 (PM9L) PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90...
  • Page 144 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) (1/4) (a) V850ES/JF3-E (1/2) After reset:0000H R/W Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H PMC9 (PMC9H) PMC913 PMC912 PMC98 PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91...
  • Page 145 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2/4) (a) V850ES/JF3-E (2/2) PMC95 Specification of P95 pin operation mode I/O port TOAB1B3 output/EVTAB1 input/KR5 input/INTP16 input PMC94 Specification of P94 pin operation mode I/O port TOAB1T3 output/TOAB13 output/TIAB13 input/KR4 input/INTP15 input...
  • Page 146 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (3/4) (b) V850ES/JG3-E (1/2) After reset:0000H R/W Address: PM9 FFFFF452H, PM9L FFFFF452H, PM9H FFFFF453H PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC98 PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 (PMC9L) PMC915 Specification of P915 pin operation mode...
  • Page 147 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (4/4) (b) V850ES/JG3-E (2/2) PMC97 Specification of P97 pin operation mode I/O port TENC00 input/TIT01 input/KR7 input/TOT01 output PMC96 Specification of P96 pin operation mode I/O port TECR0 input/TIT00 input/KR06 input/TOT00 output PMC95...
  • Page 148 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) After reset:0000H R/W Address: PFC9 FFFFF472H, PFC9 FFFFF472H, PFC9H FFFFF473H PFC9 (PFC9H) PFC98 (PFC9L) PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90 Remarks 1. For details of alternate function specification, see 4.3.7 (6) Port 9 alternate function specifications.
  • Page 149 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS Port 9 alternate function specifications PFCE914 Specification of P914 pin alternate function SOF3 output INTP20 input PFCE913 Specification of P913 pin alternate function Note SIF3 input INTP19 input Note V850ES/JG3-E only. V850ES/JF3-E is setting prohibited.
  • Page 150 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS PFCE94 PFC94 Specification of P94 pin alternate function TOAB1T3 output/TOAB13 output TIAB13 input/KR4 input INTP15 input Setting prohibited Caution KR4 and TIAB13 are alternate functions. When using the pin for the TIAB13 function, disable key return detection of KR4, which is the alternate function (set the KRM.KRM4 bit to 0).
  • Page 151 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (7) Port 9 function register (PF9) (a) V850ES/JF3-E After reset : 0000H R/W Address: PF9 FFFFFC72H PFC9L FFFFFC72H, PFC9H FFFFFC73H PF9 (PF9H) PF913 PF912 PF98 PF97 PF96 PF95 PF94 PF93 PF92 PF91 PF90...

  • Page 152: Port Dl

    CHAPTER 4 PORT FUNCTIONS 4.3.8 Port DL Port DL is a 1-bit (V850ES/JE3-E and V850ES/JF3E) 16-bit(V850ES/JG3-E) port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-15. Port DL Alternate-Function Pins Pin Name Pin No.
  • Page 153 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (1) Port DL register L (PDLL) / Port DL register (PDL) (a) V850ES/JE3-E and V850ES/JF3-E After reset: 00H(output latch) R/W Address:FFFFF004H PDLL PDL5 PDL5 Output data control (In output mode) Output 0. Output 1.

  • Page 154: Port Register Settings When Alternate Function Is Used

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS (2) Port DL mode register (PMDL) (a) V850ES/JE3-E and V850ES/JF3-E After reset: FFH R/W Address:FFFFF024H PMDL5 PMDLL PMDL5 I/O mode control Output mode. Input mode. (b) V850ES/JG3-E After reset: FFFFH R/W Address: PMDL FFFFF024H,...
  • Page 155 Table 4-16. Using Port Pin as Alternate-Function Pin (1/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
  • Page 156 Table 4-16. Using Port Pin as Alternate-Function Pin (2/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name TXDC0...
  • Page 157 Table 4-16. Using Port Pin as Alternate-Function Pin (3/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Note 1 SCKF4...
  • Page 158 Table 4-16. Using Port Pin as Alternate-Function Pin (4/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name SCKF0...
  • Page 159 Table 4-16. Using Port Pin as Alternate-Function Pin (5/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
  • Page 160 Table 4-16. Using Port Pin as Alternate-Function Pin (6/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Note 1...
  • Page 161 Table 4-16. Using Port Pin as Alternate-Function Pin (7/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Note 1...
  • Page 162 Table 4-16. Using Port Pin as Alternate-Function Pin (8/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...

  • Page 163: Cautions

    4.5.1 Cautions on setting port pins (1) In the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E, the general-purpose port functions share pins with several peripheral function I/O pins. Switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode) by setting the PMCn register. Note the following cautions with regards to this register setting sequence.
  • Page 164 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS The setting procedure that may cause malfunction on switching from the P41 pin to the SCL01 pin is shown below. Setting Procedure Setting Contents Pin State Pin Level <1> Initial value Port mode (input)
  • Page 165 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS Figure 4-5. Example of Switching from P02 to NMI (Incorrect) 0 → 1 PMC0 PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode Rising NMI interrupt occurrence edge detector P02/NMI PMC02 bit = 0: Low level ↓...

  • Page 166: Cautions On Bit Manipulation Instruction For Port N Register (Pn)

    Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E.

  • Page 167: Cautions On On-Chip Debug Pins

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 4 PORT FUNCTIONS 4.5.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P54/INTP11/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used.

  • Page 168: Chapter 5 Clock Generation Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION CHAPTER 5 CLOCK GENERATION FUNCTION Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode = 3.0 to 6.25 MHz (f = 3.0 to 6.25 MHz) • In PLL mode = 3.0 to 6.25 MHz (×8: f...

  • Page 169: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION Configuration Figure 5-1. Clock Generator FRC bit Subclock RTC clock, oscillator WDT clock Prescaler 3 RTC clock IDLE CLS, CK3 control MFRC PLLON bits IDLE mode CK2 to CK0 bits Main clock...
  • Page 170 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (f • In clock-through mode = 3.0 to 6.25 MHz • In PLL mode = 3.0 to 6.25 MHz (×8) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (f...

  • Page 171: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units.
  • Page 172 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION After reset: 03H Address: FFFFF828H < > < > < > Note MFRC Use of subclock on-chip feedback resistor Used Not used Main clock oscillator control Oscillation enabled Oscillation stopped • Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop.
  • Page 173 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started.
  • Page 174 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses.
  • Page 175 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units.

  • Page 176: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION Operation 5.4.1 Operation of each clock The following table shows the operation status of each clock. Table 5-1. Operation Status of Each Clock Register Setting and PCC Register Operation Status CLS Bit = 1,...

  • Page 177: Pll Function

    5.5.1 Overview In the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E, an operating clock that is 8 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions.
  • Page 178 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.8 Special registers). The CKC register controls the internal system clock in the PLL mode.
  • Page 179 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status.

  • Page 180: Usage

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 5 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units.

  • Page 181: Chapter 6 16-Bit Timer/Event Counter Aa (Taa)

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Timer AA (TAA) is 16-bit timer/event counter. The V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E have TAA0 to TAA5. Overview An overview of TAAn is shown below. • Clock selection: 8 ways •...

  • Page 182: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Configuration TAAn includes the following hardware. Table 6-1. Configuration of TAAn Item Configuration Registers 16-bit counter TAAn capture/compare registers 0, 1 (TAAnCCR0, TAAnCCR1) TAAn counter read buffer register (TAAnCNT) CCR0, CCR1 buffer registers...
  • Page 183 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TAAnCNT register. When the TAAnCTL0.TAAnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TAAnCNT register is read at this time, 0000H is read.

  • Page 184: Pin Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.3.1 Pin configuration The timer inputs and outputs that configure TAAn are shared with the following ports. The port functions must be set when using each pin (see Table 4-16 Using Port Pin as Alternate-Function Pin).

  • Page 185: Register Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.3.2 Register configuration The register and bit configurations of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E differ depending on the products. Register configurations of each product are shown below. (1) V850ES/JE3-E Channel...
  • Page 186 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) V850ES/JF3-E Channel Register Name Bit Position TAA0 TAA0CTL0 TAA0CE TAA0CKS2 TAA0CKS1 TAA0CKS0 TAA0CTL1 TAA0SYE TAA0EST TAA0EEE TAA0SYM TAA0MD2 TAA0MD1 TAA0MD0 TAA0IOC0 TAA0OL1 TAA0OE1 TAA0OL0 TAA0OE0 TAA0IOC1 TAA0IS3 TAA0IS2 TAA0IS1...
  • Page 187 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) V850ES/JG3-E Channel Register Name Bit Position TAA0 TAA0CTL0 TAA0CE TAA0CKS2 TAA0CKS1 TAA0CKS0 TAA0CTL1 TAA0SYE TAA0EST TAA0EEE TAA0SYM TAA0MD2 TAA0MD1 TAA0MD0 TAA0IOC0 TAA0OL1 TAA0OE1 TAA0OL0 TAA0OE0 TAA0IOC1 TAA0IS3 TAA0IS2 TAA0IS1...

  • Page 188: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Registers The registers that control TAAn are as follows. • TAAn control register 0 (TAAnCTL0) • TAAn control register 1 (TAAnCTL1) • TAAn I/O control register 0 (TAAnIOC0) • TAAn I/O control register 1 (TAAnIOC1) •...
  • Page 189 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) TAAn control register 0 (TAAnCTL0) The TAAnCTL0 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units.
  • Page 190 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) TAAn control register 1 (TAAnCTL1) The TAAnCTL1 register is an 8-bit register that controls the operation of TAAn. This register can be read or written in 8-bit or 1-bit units.
  • Page 191 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2/2) TAAmEEE Count clock selection (m = 0 to 4) Disables operation with external event count input. (Performs counting with the count clock selected by the TAAmCTL0.TAAmCK0 to TAAmCK2 bits.) Enables operation with external event count input.
  • Page 192 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (3) TAAn I/O control register 0 (TAAnIOC0) The TAAnIOC0 register is an 8-bit register that controls the timer output (TOAAn0, TOAAn1 pins). This register can be read or written in 8-bit or 1-bit units.
  • Page 193 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (4) TAAn I/O control register 1 (TAAnIOC1) The TAAnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIAAn0, TIAAn1 pins). This register can be read or written in 8-bit or 1-bit units.
  • Page 194 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (5) TAAn I/O control register 2 (TAAnIOC2) The TAAnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIAAn0 pin) and external trigger input signal (TIAAn0 pin).
  • Page 195 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (6) TAAn I/O control register 4 (TAAnIOC4) The TAAnIOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units.
  • Page 196 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (7) TAAn option register 0 (TAAnOPT0) The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units.
  • Page 197 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (8) TAAn option register 1 (TAAnOPT1) The TAAnOPT1 register is an 8-bit register that controls the 32-bit capture function realized by a cascade connection. Rewriting this register is prohibited while the timer is operating (TAAnCTL0.TAAnCE = 1).
  • Page 198 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (9) TAAn capture/compare register 0 (TAAnCCR0) The TAAnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS0 bit.
  • Page 199 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (a) Function as compare register The TAAnCCR0 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16- bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAAnCC0) is generated.
  • Page 200 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (10) TAAn capture/compare register 1 (TAAnCCR1) The TAAnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TAAnOPT0.TAAnCCS1 bit.
  • Page 201 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (a) Function as compare register The TAAnCCR1 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1. The set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16- bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated.
  • Page 202 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (11) TAAn counter read buffer register (TAAnCNT) The TAAnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TAAnCTL0.TAAnCE bit = 1, the count value of the 16-bit timer can be read.
  • Page 203 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (12) Noise elimination control register (TANFCn) Digital noise elimination can be selected for the TIAAn0 and TIAAn1 pins. The noise elimination setting is selected using the TANFCn register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f and f /4.
  • Page 204 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) A timing example of noise elimination performed by the timer AA input pin digital filter is shown Figure 6-2. Figure 6-2. Example of Digital Noise Elimination Timing Noise elimination clock...

  • Page 205: Operation

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Operation The modes realized by the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E, differ depending on the channels. The following tables show the executable functions of each channel. Table 6-5. Executable Channels for TAAn Functions (V850ES/JE3-E)
  • Page 206 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Table 6-7. Executable Channels for TAAn Functions (V850ES/JG3-E) Operation Mode TAA0 TAA1 TAA2 TAA3 TAA4 Interval timer mode Enable Enable Enable Enable Enable External event count mode Enable Enable Enable...
  • Page 207 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Anytime write and batch write With TAAn, the TAAnCCR0 and TAAnCCR1 registers can be rewritten during timer operation (TAAnCTL0.TAAnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode.
  • Page 208 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-4. Example of Anytime Write Timing (Interval Timer Mode of TAA0) TAA0CE bit = 1 FFFFH 16-bit counter 0000H TAA0CCR0 register CCR0 buffer register 0000H TAA0CCR1 register CCR1 buffer register...
  • Page 209 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Batch write In this mode, data is transferred all at once from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
  • Page 210 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-5. Example of Basic Batch Write Operation Flowchart (PWM Output Mode of TAA0) START Initial settings • Set values to TAA0CCRm register • Enable timer operation (TAA0CE bit = 1) →...
  • Page 211 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-6. Timing of Batch Write (Interval Timer Mode of TAA0) TAA0CE bit = 1 FFFFH 16-bit counter 0000H TAA0CCR0 register CCR0 buffer register 0000H Note 1 Note 1 Same value write...

  • Page 212: Interval Timer Mode (Taanmd2 To Taanmd0 Bits = 000)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.1 Interval timer mode (TAAnMD2 to TAAnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated at any interval if the TAAnCTL0.TAAnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAAn0 pin.
  • Page 213 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOAAn0 pin is inverted. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register.
  • Page 214 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-9. Register Settings for Interval Timer Mode Operation (2/2) (c) TAAn I/O control register 0 (TAAnIOC0) TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0 TAAnIOC0 0: Disables TOAAn0 pin output 1: Enables TOAAn0 pin output...
  • Page 215 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Interval timer mode operation flow Figure 6-10. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register TOAAn0 pin output INTTAAnCC0 signal <1> <2>...
  • Page 216 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Interval timer mode operation timing (a) Operation if TAAnCCR0 register is set to 0000H If the TAAnCCR0 register is set to 0000H, the INTTAAnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOAAn0 pin is inverted.
  • Page 217 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Operation if TAAnCCR0 register is set to FFFFH If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTAAnCC0 signal is generated and the output of the TOAAn0 pin is inverted.
  • Page 218 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Notes on rewriting TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
  • Page 219 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Operation of TAAnCCR1 register Figure 6-11. Configuration of TAAnCCR1 Register TAAnCCR1 register Output CCR1 buffer register TOAAn1 pin controller Match signal INTTAAnCC1 signal Clear Count clock Output 16-bit counter...
  • Page 220 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is less than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is generated once per cycle. At the same time, the output of the TOAAn1 pin is inverted.
  • Page 221 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the count value of the 16-bit counter does not match the value of the TAAnCCR1 register.

  • Page 222: External Event Count Mode (Taanmd2 To Taanmd0 Bits = 001)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.2 External event count mode (TAAnMD2 to TAAnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TAAnCTL0.TAAnCE bit is set to 1, and an interrupt request signal (INTTAAnCC0) is generated each time the specified...
  • Page 223 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register.
  • Page 224 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-16. Register Setting for Operation in External Event Count Mode (2/2) (e) TAAn counter read buffer register (TAAnCNT) The count value of the 16-bit counter can be read by reading the TAAnCNT register.
  • Page 225 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) External event count mode operation flow Figure 6-17. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register INTTAAnCC0 signal <1> <2>...
  • Page 226 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TAAnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation of the count clock to be enabled by the external event count input (TAAnCTL1.TAAnMD2 to...
  • Page 227 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Notes on rewriting the TAAnCCR0 register To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
  • Page 228 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Operation of TAAnCCR1 register Figure 6-18. Configuration of TAAnCCR1 Register TAAnCCR1 register CCR1 buffer register Match signal INTTAAnCC1 signal Clear Edge TIAAn0 pin 16-bit counter detector Match signal INTTAAnCC0 signal...
  • Page 229 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the INTTAAnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TAAnCCR1 register do not match.

  • Page 230: External Trigger Pulse Output Mode (Taanmd2 To Taanmd0 Bits = 010)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.3 External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1.
  • Page 231 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-22. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TAAnCE bit External trigger input (TIAAn0 pin input) TAAnCCR0 register INTTAAnCC0 signal TOAAn0 pin output (only when software...
  • Page 232 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-23. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCTL0 Select count clock 0: Stops counting 1: Enables counting...
  • Page 233 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 Select valid edge of external trigger input (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register.
  • Page 234 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in external trigger pulse output mode Figure 6-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TAAnCE bit External trigger input...
  • Page 235 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TAAnCCR0, TAAnCCR1 register setting change flow Only writing of the TAAnCCR1 START register must be performed when the set duty factor is changed.
  • Page 236 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last.
  • Page 237 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) In order to transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TAAnCCR0 register and then set the active level width to the TAAnCCR1 register.
  • Page 238 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically.
  • Page 239 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Conflict between trigger detection and match with TAAnCCR1 register If the trigger is detected immediately after the INTTAAnCC1 signal is generated, the 16-bit counter is cleared to 0000H at the same time, the output signal of the TOAAn1 pin is asserted, and the counter continues counting.
  • Page 240 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Conflict between trigger detection and match with TAAnCCR0 register If the trigger is detected immediately after the INTTAAnCC0 signal is generated, the 16-bit counter is cleared to 0000H again and continues counting up. Therefore, the active period of the TOAAn1 pin is extended by the time from generation of the INTTAAnCC0 signal to trigger detection.
  • Page 241 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (e) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the external trigger pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register.

  • Page 242: One-Shot Pulse Output Mode (Taanmd2 To Taanmd0 Bits = 011)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.4 One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is set to 1.
  • Page 243 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-26. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TAAnCE bit External trigger input (TIAAn0 pin input) TAAnCCR0 register INTTAAnCC0 signal TOAAn0 pin output (only when software...
  • Page 244 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-27. Register Setting for Operation in One-Shot Pulse Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCTL0 Select count clock 0: Stops counting 1: Enables counting...
  • Page 245 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-27. Register Setting for Operation in One-Shot Pulse Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 Select valid edge of external trigger input (e) TAAn counter read buffer register (TAAnCNT) The value of the 16-bit counter can be read by reading the TAAnCNT register.
  • Page 246 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in one-shot pulse output mode Figure 6-28. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TAAnCE bit External trigger input (TIAAn0 pin input)
  • Page 247 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TAAnCCRm register To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change the set value.
  • Page 248 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Generation timing of compare match interrupt request signal (INTTAAnCC1) The generation timing of the INTTAAnCC1 signal in the one-shot pulse output mode is different from other INTTAAnCC1 signals; the INTTAAnCC1 signal in the one-shot pulse output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register.

  • Page 249: Pwm Output Mode (Taanmd2 To Taanmd0 Bits = 100)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.5 PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOAAn1 pin when the TAAnCTL0.TAAnCE bit is set to 1.
  • Page 250 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-30. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register CCR0 buffer register INTTAAnCC0 signal TOAAn0 pin output TAAnCCR1 register CCR1 buffer register INTTAAnCC1 signal...
  • Page 251 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-31. Setting of Registers in PWM Output Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCTL0 Note 1 Select count clock 0: Stops counting 1: Enables counting...
  • Page 252 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-31. Setting of Registers in PWM Output Mode (2/2) (d) TAAn I/O control register 2 (TAAnIOC2) TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0 TAAnIOC2 Select valid edge of external event count input.
  • Page 253 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in PWM output mode Figure 6-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TAAnCE bit TAAnCCR0 register CCR0 buffer register INTTAAnCC0 signal...
  • Page 254 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-32. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TAAnCCR0, TAAnCCR1 register setting change flow Only writing of the TAAnCCR1 START register must be performed when only the set duty factor is changed.
  • Page 255 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last. Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC1 signal is detected.
  • Page 256 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is FFFFH, the INTTAAnCC1 signal is generated periodically.
  • Page 257 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Generation timing of compare match interrupt request signal (INTTAAnCC1) The timing of generation of the INTTAAnCC1 signal in the PWM output mode differs from the timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the PWM output mode is generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register.

  • Page 258: Free-Running Timer Mode (Taanmd2 To Taanmd0 Bits = 101)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.6 Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. At this time, the TAAnCCRm register can be used as a compare register or a capture register, depending on the setting of the TAAnOPT0.TAAnCCS0 and TAAnOPT0.TAAnCCS1 bits.
  • Page 259 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0 and TOAAn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TAAnCCRm register, a compare match interrupt request signal (INTTAAnCCm) is generated, and the output signal of the TOAAnm pin is inverted.
  • Page 260 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and a capture interrupt request signal (INTTAAnCCm) is generated.
  • Page 261 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-36. Register Setting in Free-Running Timer Mode (1/2) (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCTL0 Note Select count clock 0: Stops counting 1: Enables counting Note The setting is invalid when the TAAnCTL1.TAAnEEE bit = 1...
  • Page 262 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-36. Register Setting in Free-Running Timer Mode (2/2) (d) TAAn I/O control register 1 (TAAnIOC1) TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0 TAAnIOC1 Select valid edge of TIAAn0 pin input Select valid edge...
  • Page 263 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 6-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter...
  • Page 264 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TAAnCTL0 register is performed before setting the (TAAnCKS0 to TAAnCKS2 bits), TAAnCE bit to 1.
  • Page 265 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) When using capture/compare register as capture register Figure 6-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input TAAnCCR0 register...
  • Page 266 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TAAnCTL0 register is performed before setting the (TAAnCKS0 to TAAnCKS2 bits), TAAnCE bit to 1.
  • Page 267 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in free-running timer mode (a) Interval operation with TAAnCCRm register used as compare register When 16-bit timer/event counter AA is used as an interval timer with the TAAnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTAAnCCm signal has been detected.
  • Page 268 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (b) Pulse width measurement with TAAnCCRm used as capture register When pulse width measurement is performed with the TAAnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTAAnCCm signal has been detected and for calculating the interval.
  • Page 269 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
  • Page 270 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit Note TAAnOVF0 flag TIAAn0 pin input TAAnCCR0 register Note...
  • Page 271 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TAAnCE bit INTTAAnOV signal TAAnOVF bit Note TAAnOVF0 flag TIAAn0 pin input TAAnCCR0 register...
  • Page 272 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next.
  • Page 273 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TAAnCE bit TIAAnm pin input TAAnCCRm register INTTAAnOV signal TAAnOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
  • Page 274 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.

  • Page 275: Pulse Width Measurement Mode (Taanmd2 To Taanmd0 Bits = 110)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.7 Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to 1. Each time the valid edge input to the TIAAnm pin has been detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and the 16-bit counter is cleared to 0000H.
  • Page 276 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAAnCE bit TIAAnm pin input 0000H TAAnCCRm register INTTAAnCCm signal INTTAAnOV signal Cleared to 0 by TAAnOVF bit...
  • Page 277 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-41. Register Setting in Pulse Width Measurement Mode (a) TAAn control register 0 (TAAnCTL0) TAAnCE TAAnCKS2 TAAnCKS1 TAAnCKS0 TAAnCTL0 Select count clock 0: Stops counting 1: Enables counting (b) TAAn control register 1 (TAAnCTL1)
  • Page 278 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Operation flow in pulse width measurement mode Figure 6-42. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAAnCE bit TIAAn0 pin input 0000H 0000H TAAnCCR0 register INTTAAnCC0 signal <1>...
  • Page 279 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register.

  • Page 280: Timer Output Operations

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.5.8 Timer output operations The following table shows the operations and output levels of the TOAAn0 and TOAAn1 pins. Table 6-8. Timer Output Control in Each Mode Operation Mode TOAAn1 Pin...

  • Page 281: Timer-Tuned Operation Function

    Timer AA and timer AB have a timer-tuned operation function. The timer-tuned operation function is used to tune the internal timers of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E, so that the number of capture or compare registers of the slave timer (the number of timer outputs and the number of compare match interrupts of the slave timer) can be added to the master timer.
  • Page 282 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Table 6-11 show the timer modes that can be used in the tuned-operation mode and Table 6-12 shows the differences of the timer output functions between individual operation and tuned operation (√: Settable, ×: Not settable).

  • Page 283: Free-Running Timer Mode (During Timer-Tuned Operation)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.6.1 Free-running timer mode (during timer-tuned operation) This section explains the free-running timer mode of the timer-tuned operation. For the combination of timer-tuned operations, see Table 6-10. In this section, an example of timer-tuned operation using TAA1 and TAA0 is shown.
  • Page 284 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (1) Settings in free-running timer mode (compare function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] •...
  • Page 285 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-44. Example of Timing in Free-Running Mode (Compare Function) FFFFH TAA1 16-bit counter 0000H TAA1CE TAA1CCR0 TAA1CCR1 TAA0CCR0 TAA0CCR1 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0 INTTAA0CC1 INTTAA1OV TAA1OVF TAA1OVF write clear (0)
  • Page 286 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (2) Settings in free-running timer mode (capture function) [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled) [Initial settings of master timer (TAA1)] •...
  • Page 287 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-45. Example of Timing in Free-Running Mode (Capture Function) FFFFH TAA1 16-bit counter 0000H TAA1CE TIAA10 TIAA11 TIAA00 TIAA01 TAA1CCR0 0000 TAA1CCR1 0000 TAA0CCR0 0000 TAA0CCR1 0000 INTTAA1CC0 INTTAA1CC1...
  • Page 288 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) (3) Settings in free-running timer mode (capture/compare used together) An example of using TAA0 as a capture register and TAA1 as a compare register is shown below. [Initial settings] Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled) Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
  • Page 289 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-46. Example of Timing in Free-Running Mode (Capture/Compare Used Together) FFFFH TAA1 16-bit counter 0000H TAA1CE TIAA10 TIAA11 TAA1CCR0 0000 TAA1CCR1 0000 TAA0CCR0 0000 TAA0CCR1 0000 INTTAA1CC0 INTTAA1CC1 INTTAA0CC0...

  • Page 290: Pwm Output Mode (During Timer-Tuned Operation)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.6.2 PWM output mode (during timer-tuned operation) This section explains the PWM output mode of timer-tuned operation. For combinations of timer-tuned operations, see Table 6-10. This section presents an example of a timer-tuned operation with TAB1 and TAA4.
  • Page 291 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) [Batch write] In the PWM output mode, the next batch write is enabled by writing the TAB1CCR1 register of the master timer (TAB1). After all the compare registers that must be rewritten have been rewritten, therefore, the TAB1CCR1 register of the master timer (TAB1) must be written.

  • Page 292: Simultaneous-Start Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Simultaneous-Start Function Timer AA and timer AB have a timer-tuned operation function. By using the simultaneous-start function, a timer operation in which the operation start timing and count up timing of the master timer and slave timer are synchronized can be performed.

  • Page 293: Pwm Output Mode (Simultaneous-Start Operation)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.7.1 PWM output mode (simultaneous-start operation) In this section, the operation of the simultaneous-start function is shown, where TAA1 is used as the master timer and TAA0 is used as the slave timer.
  • Page 294 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-49. Timing Example of Simultaneous-Start Function (TAA1: Master, TAA0: Slave) FFFFH TAA1 16 -bit counter 0000H FFFFH TAA0 16 -bit counter 0000H TAA1CE bit TAA1CCR0 register TAA1CCR1 register INTTAA1CC0 interrupt...

  • Page 295: Cascade Connection

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Cascade Connection This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer. For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as capture registers (TAA0CCSn = 1).
  • Page 296 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) The operation of each pin and signal when TAA1 and TAA0 are connected in cascade is shown below. Table 6-12. Status in Cascade Connection Name Higher/Lower Function Operation TIAA10 pin input...
  • Page 297 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (1/2) FFFFFFFFH 1a1b 0e0f 1c1d 0g0h 32-bit counter 0a0b 1e1f 0c0d 00000000H Operation enable bit ( TAA1CE) TIAA10 input...
  • Page 298 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (2/2) <2> Capture 1 read flow <1> Count operation start flow START INTTAA0CCR1 generated? Register initial setting Perform initial setting...
  • Page 299 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Figure 6-52. Example of Basic Timing When TAA1 and TAA0 Are Connected in Cascade FFFFFFFFH 1a1b 0e0f 1c1d 0g0h 32-bit counter 0a0b 0i0j 1e1f 0c0d 1g1h 00000000H Operation enable bit...

  • Page 300: Selector Function

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) Selector Function In the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E, the alternate-function pins of ports or peripheral I/O (TAA1, TAA0, UARTC0, UARTC1 or CAN0) signals can be selected as the capture trigger input of TAA1 and TAA0.

  • Page 301: Cautions

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA) 6.10 Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TAAnCCR0 and TAAnCCR1 registers if the capture trigger is input immediately after the TAAnCE bit is set to 1.

  • Page 302: Chapter 7 16-Bit Timer/Event Counter Ab (Tab)

    CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer AB (TAB) is a 16-bit timer/event counter. The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E have TAB1. Overview An outline of TAB1 is shown below. • Clock selection: 8 ways •...

  • Page 303: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Configuration TAB1 includes the following hardware. Table 7-1. Configuration of TAB1 Item Configuration Registers 16-bit counter TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) TAB1 counter read buffer register (TAB1CNT)
  • Page 304 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TAB1CNT register. When the TAB1CTL0.TAB1CE bit = 0, the value of the 16-bit counter is FFFFH. If the TAB1CNT register is read at this time, 0000H is read.

  • Page 305: Pin Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (7) Output controller This circuit controls the output of the TOAB10 to TOAB13 pins. The output controller is controlled by the TAB1IOC0 register. (8) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock.

  • Page 306: Register Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.3.2 Register configuration The register and bit configurations of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E differ depending on the products. Register configurations of each product are shown below. (1) V850ES/JE3-E Channel...

  • Page 307: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Registers The registers that control TAB1 are as follows. • TAB1 control register 0 (TAB1CTL0) • TAB1 control register 1 (TAB1CTL1) • TAB1 I/O control register 0 (TAB1IOC0) • TAB1 I/O control register 1 (TAB1IOC1) •...
  • Page 308 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) TAB1 control register 0 (TAB1CTL0) The TAB1CTL0 register is an 8-bit register that controls the operation of TAB1. This register can be read or written in 8-bit or 1-bit units.
  • Page 309 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) TAB1 control register 1 (TAB1CTL1) The TAB1CTL1 register is an 8-bit register that controls the operation of TAB1. This register can be read or written in 8-bit or 1-bit units.
  • Page 310 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (3) TAB1 I/O control register 0 (TAB1IOC0) The TAB1IOC0 register is an 8-bit register that controls the timer output (TOAB10 to TOAB13 pins). This register can be read or written in 8-bit or 1-bit units.
  • Page 311 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (4) TAB1 I/O control register 1 (TAB1IOC1) The TAB1IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIAB10 to TIAB13 pins). This register can be read or written in 8-bit or 1-bit units.
  • Page 312 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (5) TAB1 I/O control register 2 (TAB1IOC2) The TAB1IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (EVTAB1 pin) and external trigger input signal (TRGAB1 pin).
  • Page 313 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (6) TAB1 I/O control register 4 (TAB1IOC4) The TAB1IOC4 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units.
  • Page 314 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (7) TAB1 option register 0 (TAB1OPT0) The TAB1OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units.
  • Page 315 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (8) TAB1 capture/compare register 0 (TAB1CCR0) The TAB1CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS0 bit.
  • Page 316 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR0 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR0 register is transferred to the CCR0 buffer register. When the value of the 16- bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTAB1CC0) is generated.
  • Page 317 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (9) TAB1 capture/compare register 1 (TAB1CCR1) The TAB1CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS1 bit.
  • Page 318 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR1 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR1 register is transferred to the CCR1 buffer register. When the value of the 16- bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTAB1CC1) is generated.
  • Page 319 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (10) TAB1 capture/compare register 2 (TAB1CCR2) The TAB1CCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS2 bit.
  • Page 320 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR2 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR2 register is transferred to the CCR2 buffer register. When the value of the 16- bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTAB1CC2) is generated.
  • Page 321 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (11) TAB1 capture/compare register 3 (TAB1CCR3) The TAB1CCR3 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, according to the setting of the TAB1OPT0.TAB1CCS3 bit.
  • Page 322 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (a) Function as compare register The TAB1CCR3 register can be rewritten even when the TAB1CTL0.TAB1CE bit = 1. The set value of the TAB1CCR3 register is transferred to the CCR3 buffer register. When the value of the 16- bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTAB1CC3) is generated.
  • Page 323 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (12) TAB1 counter read buffer register (TAB1CNT) The TAB1CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TAB1CTL0.TAB1CE bit = 1, the count value of the 16-bit timer can be read.

  • Page 324: Operation

    CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Operation The modes realized by the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E, differ depending on the products. The following table shows the executable operation modes of each product Table 7-7. Executable Modes of Each Product...

  • Page 325: Interval Timer Mode (Tab1Md2 To Tab1Md0 Bits = 000)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.1 Interval timer mode (TAB1MD2 to TAB1MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTAB1CC0) is generated at the specified interval if the TAB1CTL0.TAB1CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAB10 pin.
  • Page 326 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOAB10 pin is inverted. Additionally, the set value of the TAB1CCR0 register is transferred to the CCR0 buffer register.
  • Page 327 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 TAB1IOC0 0: Disable TOAB10 pin output...
  • Page 328 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Interval timer mode operation flow Figure 7-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TAB1CE bit TAB1CCR0 register TOAB10 pin output INTTAB1CC0 signal <1> <2>...
  • Page 329 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Interval timer mode operation timing (a) Operation if TAB1CCR0 register is set to 0000H If the TAB1CCR0 register is set to 0000H, the INTTAB1CC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOAB10 pin is inverted.
  • Page 330 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Notes on rewriting TAB1CCR0 register To change the value of the TAB1CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAB1CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
  • Page 331 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Operation of TAB1CCR1 to TAB1CCR3 registers Figure 7-6. Configuration of TAB1CCR1 to TAB1CCR3 Registers TAB1CCR1 register CCR1 buffer Output TOAB11 pin register controller Match signal INTTAB1CC1 signal TAB1CCR2 register...
  • Page 332 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TAB1CCRk register is less than the set value of the TAB1CCR0 register, the INTTAB1CCk signal is generated once per cycle. At the same time, the output of the TOAB1k pin is inverted.
  • Page 333 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TAB1CCRk register is greater than the set value of the TAB1CCR0 register, the count value of the 16-bit counter does not match the value of the TAB1CCRk register.

  • Page 334: External Event Count Mode (Tab1Md2 To Tab1Md0 Bits = 001)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.2 External event count mode (TAB1MD2 to TAB1MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TAB1CTL0.TAB1CE bit is set to 1, and an interrupt request signal (INTTAB1CC0) is generated each time the specified...
  • Page 335 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of the external event count input is detected. Additionally, the set value of the TAB1CCR0 register is transferred to the CCR0 buffer register.
  • Page 336 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TAB1 counter read buffer register (TAB1CNT) The count value of the 16-bit counter can be read by reading the TAB1CNT register.
  • Page 337 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) External event count mode operation flow Figure 7-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TAB1CE bit TAB1CCR0 register INTTAB1CC0 signal <1> <2>...
  • Page 338 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TAB1CCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TAB1CTL1.TAB1MD2 to...
  • Page 339 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Notes on rewriting the TAB1CCR0 register To change the value of the TAB1CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TAB1CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
  • Page 340 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Operation of TAB1CCR1 to TAB1CCR3 registers Figure 7-13. Configuration of TAB1CCR1 to TAB1CCR3 Registers TAB1CCR1 register CCR1 buffer register Match signal INTTAB1CC1 signal TAB1CCR2 register CCR2 buffer register Match signal...
  • Page 341 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TAB1CCRk register is smaller than the set value of the TAB1CCR0 register, the INTTAB1CCk signal is generated once per cycle. Remark k = 1 to 3 ≥...
  • Page 342 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) If the set value of the TAB1CCRk register is greater than the set value of the TAB1CCR0 register, the INTTAB1CCk signal is not generated because the count value of the 16-bit counter and the value of the TAB1CCRk register do not match.

  • Page 343: External Trigger Pulse Output Mode (Tab1Md2 To Tab1Md0 Bits = 010)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.3 External trigger pulse output mode (TAB1MD2 to TAB1MD0 bits = 010) In the external trigger pulse output mode, TAB1 waits for a trigger when the TAB1CTL0.TAB1CE bit is set to 1. When the valid edge of the external trigger input signal is detected, TAB1 starts counting, and outputs a PWM waveform from the TOAB11 to TOAB13 pins.
  • Page 344 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-17. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TAB1CE External trigger input (TRGAB1 pin input) TAB1CCR0 register INTTAB1CC0 signal TOAB10 pin output (only when software...
  • Page 345 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) TAB1 waits for a trigger when the TAB1CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOAB1k pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted.
  • Page 346 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TAB1 control register 1 (TAB1CTL1) TAB1EST TAB1MD2 TAB1MD1 TAB1MD0 TAB1SYE TAB1EEE TAB1CTL1 0, 1, 0: External trigger pulse...
  • Page 347 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TAB1 I/O control register 2 (TAB1IOC2) TAB1ETS1 TAB1ETS0 TAB1EES1 TAB1EES0 TAB1IOC2 Select valid edge of external trigger input...
  • Page 348 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in external trigger pulse output mode Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TAB1CE bit External trigger input...
  • Page 349 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TAB1CCR1 to TAB1CCR3 register setting change flow Writing the TAB1CCR1 START Setting of TAB1CCR2,...
  • Page 350 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAB1CCR1 register last.
  • Page 351 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) To transfer data from the TAB1CCRm register to the CCRm buffer register, the TAB1CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TAB1CCR0 register, set the active level width to the TAB1CCR2 and TAB1CCR3 registers, and then set the active level to the TAB1CCR1 register.
  • Page 352 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAB1CCRk register to 0000H. If the set value of the TAB1CCR0 register is FFFFH, the INTTAB1CCk signal is generated periodically.
  • Page 353 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTAB1CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOAB1k pin is asserted, and the counter continues counting.
  • Page 354 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTAB1CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOAB1k pin is extended by time from generation of the INTTAB1CC0 signal to trigger detection.
  • Page 355 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (e) Generation timing of compare match interrupt request signal (INTTAB1CCk) The timing of generation of the INTTAB1CCk signal in the external trigger pulse output mode differs from the timing of other INTTAB1CCk signals; the INTTAB1CCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.

  • Page 356: One-Shot Pulse Output Mode (Tab1Md2 To Tab1Md0 Bits = 011)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.4 One-shot pulse output mode (TAB1MD2 to TAB1MD0 bits = 011) In the one-shot pulse output mode, TAB1 waits for a trigger when the TAB1CTL0.TAB1CE bit is set to 1. When the valid edge of the external trigger input is detected, TAB1 starts counting, and outputs a one-shot pulse from the TOAB11 to TOAB13 pins.
  • Page 357 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TAB1CE bit External trigger input (TRGAB1 pin input) TAB1CCR0 register INTTAB1CC0 signal TOAB10 pin output (only when software...
  • Page 358 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, TAB1 waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAB1k pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger.
  • Page 359 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/3) (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 Note Note TAB1IOC0...
  • Page 360 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3) (f) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) If D is set to the TAB1CCR0 register and D to the TAB1CCRk register, the active level width and output delay period of the one-shot pulse are as follows.
  • Page 361 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in one-shot pulse output mode Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TAB1CE bit External trigger input (TRGAB1 pin input)
  • Page 362 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <1> Count operation start flow <2> TAB1CCR0 to TAB1CCR3 register setting change flow As rewriting the TAB1CCRm register START...
  • Page 363 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in one-shot pulse output mode (a) Notes on rewriting TAB1CCRm register To change the set value of the TAB1CCRm register to a smaller value, stop counting once, and then change the set value.
  • Page 364 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Generation timing of compare match interrupt request signal (INTTAB1CCk) The generation timing of the INTTAB1CCk signal in the one-shot pulse output mode is different from other INTTAB1CCk signals; the INTTAB1CCk signal is generated when the count value of the 16-bit counter matches the value of the TAB1CCRk register.

  • Page 365: Pwm Output Mode (Tab1Md2 To Tab1Md0 Bits = 100)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.5 PWM output mode (TAB1MD2 to TAB1MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOAB11 to TOAB13 pins when the TAB1CTL0.TAB1CE bit is set to 1.
  • Page 366 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-25. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TAB1CE bit TAB1CCR0 register INTTAB1CC0 signal TOAB10 pin output TAB1CCR1 register INTTAB1CC1 signal TOAB11 pin output Active Active...
  • Page 367 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOAB1k pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
  • Page 368 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-26. Setting of Registers in PWM Output Mode (2/3) (c) TAB1 I/O control register 0 (TAB1IOC0) TAB1OL3 TAB1OE3 TAB1OL2 TAB1OE2 TAB1OL1 TAB1OE1 TAB1OL0 TAB1OE0 Note Note TAB1IOC0 0: Disable TOAB10 pin output...
  • Page 369 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-26. Register Setting in PWM Output Mode (3/3) (f) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) If D is set to the TAB1CCR0 register and D to the TAB1CCRk register, the cycle and active level of the PWM waveform are as follows.
  • Page 370 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in PWM output mode Figure 7-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TAB1CE bit TAB1CCR0 register CCR0 buffer register INTTAB1CC0 signal...
  • Page 371 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TAB1CCR1 to TAB1CCR3 register setting change flow Writing the TAB1CCR1 register START Setting of TAB1CCR2,...
  • Page 372 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TAB1CCR1 register last. Rewrite the TAB1CCRk register after writing the TAB1CCR1 register after the INTTAB1CC1 signal is detected.
  • Page 373 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) To transfer data from the TAB1CCRm register to the CCRm buffer register, the TAB1CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TAB1CCR0 register, set the active level width to the TAB1CCR2 and TAB1CCR3 registers, and then set the active level width to the TAB1CCR1 register.
  • Page 374 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TAB1CCRk register to 0000H. If the set value of the TAB1CCR0 register is FFFFH, the INTTAB1CCk signal is generated periodically.
  • Page 375 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Generation timing of compare match interrupt request signal (INTTAB1CCk) The timing of generation of the INTTAB1CCk signal in the PWM output mode differs from the timing of other INTTAB1CCk signals; the INTTAB1CCk signal is generated when the count value of the 16-bit counter matches the value of the TAB1CCRk register.

  • Page 376: Free-Running Timer Mode (Tab1Md2 To Tab1Md0 Bits = 101)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.6 Free-running timer mode (TAB1MD2 to TAB1MD0 bits = 101) In the free-running timer mode, TAB1 starts counting when the TAB1CTL0.TAB1CE bit is set to 1. At this time, the TAB1CCRm register can be used as a compare register or a capture register, according to the setting of the TAB1OPT0.TAB1CCS0 and TAB1OPT0.TAB1CCS1 bits.
  • Page 377 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, TAB1 starts counting, and the output signals of the TOAB10 to TOAB13 pins are inverted. When the count value of the 16-bit counter subsequently matches the set value of the TAB1CCRm register, a compare match interrupt request signal (INTTAB1CCm) is generated, and the output signal of the TOAB1m pin is inverted.
  • Page 378 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When the TAB1CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TAB1m pin is detected, the count value of the 16-bit counter is stored in the TAB1CCRm register, and a capture interrupt request signal (INTTAB1CCm) is generated.
  • Page 379 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-31. Register Setting in Free-Running Timer Mode (1/3) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CKS2 TAB1CKS1 TAB1CKS0 TAB1CTL0 Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TAB1CTL1.TAB1EEE bit = 1...
  • Page 380 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-31. Register Setting in Free-Running Timer Mode (2/3) (d) TAB1 I/O control register 1 (TAB1IOC1) TAB1IS7 TAB1IS6 TAB1IS5 TAB1IS4 TAB1IS3 TAB1IS2 TAB1IS1 TAB1IS0 TAB1IOC1 Select valid edge of TIAB10 pin input...
  • Page 381 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-31. Register Setting in Free-Running Timer Mode (3/3) (h) TAB1 capture/compare registers 0 to 3 (TAB1CCR0 to TAB1CCR3) These registers function as capture registers or compare registers according to the setting of the TAB1OPT0.TAB1CCSm bit.
  • Page 382 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter...
  • Page 383 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting The initial setting of these registers TAB1CTL0 register is performed before setting the (TAB1CKS0 to TAB1CKS2 bits), TAB1CE bit to 1.
  • Page 384 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) When using capture/compare register as capture register Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TAB1CE bit TIAB10 pin input TAB1CCR0 register...
  • Page 385 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting The initial setting of these registers TAB1CTL0 register is performed before setting the (TAB1CKS0 to TAB1CKS2 bits), TAB1CE bit to 1.
  • Page 386 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When TAB1 is used as an interval timer with the TAB1CCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTAB1CCm signal has been detected.
  • Page 387 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When performing an interval operation in the free-running timer mode, four intervals can be set with one channel. To perform the interval operation, the value of the corresponding TAB1CCRm register must be re-set in the interrupt servicing that is executed when the INTTAB1CCm signal is detected.
  • Page 388 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TAB1CCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTAB1CCm signal has been detected and for calculating an interval.
  • Page 389 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TAB1CCRm register in synchronization with the INTTAB1CCm signal, and calculating the difference between the value read this time and the previously read value.
  • Page 390 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two or more capture registers are used. First, an example of incorrect processing is shown below.
  • Page 391 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TAB1CE bit INTTAB1OV signal TAB1OVF bit Note TAB1OVF0 flag TIAB10 pin input TAB1CCR0 register Note...
  • Page 392 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TAB1CE bit INTTAB1OV signal TAB1OVF bit Note TAB1OVF0 flag TIAB10 pin input TAB1CCR0 register...
  • Page 393 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next.
  • Page 394 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TAB1CE bit TIAB1m pin input TAB1CCRm register INTTAB1OV signal TAB1OVF bit Note Overflow counter 2H 0H 1 cycle of 16-bit counter Pulse width <1>...
  • Page 395 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAB1OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAB1OPT0 register. To accurately detect an overflow, read the TAB1OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.

  • Page 396: Pulse Width Measurement Mode (Tab1Md2 To Tab1Md0 Bits = 110)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.7 Pulse width measurement mode (TAB1MD2 to TAB1MD0 bits = 110) In the pulse width measurement mode, TAB1 starts counting when the TAB1CTL0.TAB1CE bit is set to 1. Each time the valid edge input to the TAB1m pin has been detected, the count value of the 16-bit counter is stored in the TAB1CCRm register, and the 16-bit counter is cleared to 0000H.
  • Page 397 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAB1CE bit TIAB1m pin input 0000H TAB1CCRm register INTTAB1CCm signal INTTAB1OV signal Cleared to 0 by TAB1OVF bit...
  • Page 398 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TAB1 control register 0 (TAB1CTL0) TAB1CE TAB1CKS2 TAB1CKS1 TAB1CKS0 TAB1CTL0 Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TAB1EEE bit = 1.
  • Page 399 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TAB1 option register 0 (TAB1OPT0) TAB1OVF TAB1CCS3 TAB1CCS2 TAB1CCS1 TAB1CCS0 TAB1OPT0 Overflow flag (f) TAB1 counter read buffer register (TAB1CNT) The value of the 16-bit counter can be read by reading the TAB1CNT register.
  • Page 400 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (1) Operation flow in pulse width measurement mode Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TAB1CE bit TIAB10 pin input 0000H 0000H TAB1CCR0 register INTTAB1CC0 signal <1>...
  • Page 401 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TAB1OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TAB1OPT0 register.

  • Page 402: Triangular Wave Pwm Mode (Tab1Md2 To Tab1Md0 Bits = 111)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.8 Triangular wave PWM mode (TAB1MD2 to TAB1MD0 bits = 111) In the triangular wave PWM mode, TAB1 capture/compare register k (TAB1CCRk) is used to set the duty factor, and TAB1 capture/compare register 0 (TAB1CCR0) is used to set the cycle.
  • Page 403 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Figure 7-38. Timing of Basic Operation in Triangular Wave PWM Mode (TAB1OE0 = 1, TAB1OE1 = 1, TAB1OE2 = 1, TAB1OE3 = 1, TAB1OL0 = 0, TAB1OL1 = 0, TAB1OL2 = 0, TAB1OL3 = 0)

  • Page 404: Timer Output Operations

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) 7.5.9 Timer output operations The following table shows the operations and output levels of the TOAB10 to TOAB13 pins. Table 7-8. Timer Output Control in Each Mode Operation Mode TOAB10 Pin...

  • Page 405: Timer-Tuned Operation Function/Simultaneous-Start Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Timer-Tuned Operation Function/Simultaneous-Start Function Timer AA and timer AB have a timer-tuned operation function/simultaneous-start function. The timers that can be synchronized are listed in Table 7-8. Table 7-8. Timer-Tuned Operation Mode...

  • Page 406: Cautions

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TAB1CCR0, TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers if the capture trigger is input immediately after the TAB1CE bit is set to 1.

  • Page 407: Chapter 8 16-Bit Timer/Event Counter T (Tmt)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Timer T (TMT) is a 16-bit timer/event counter. An encoder count function and other functions are added to timer AA (TAA). However, TMT does not have a function to operate with an external event count input when it operates in the interval timer mode.

  • Page 408: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Configuration TMT0 includes the following hardware. Table 8-1. Configuration of TMT0 Item Configuration 16-bit counter × 1 Registers TMT0 capture/compare registers 0, 1 (TT0CCR0, TT0CCR1) TMT0 counter read buffer register (TT0CNT)
  • Page 409 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-1. Block Diagram of TMT0 Internal bus TT0CNT TT0TCW Counter INTTT0OV 16-bit counter control Clear TOT00 /128 TOT01 Edge detection/ TECR0 CCR0 Noise eliminator buffer Note TENC00 Edge detection/...
  • Page 410 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TT0CNT register. When the TT0CTL0.TT0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TT0CNT register is read at this time, 0000H is read.

  • Page 411: Pin Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.3.1 Pin configuration The timer inputs and outputs that configure TMT0 are shared with the following ports. The port functions must be set when using each pin (see Table 4-16 Using Port Pin as Alternate-Function Pin).

  • Page 412: Register Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.3.2 Register configuration The register and bit configurations of the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E differ depending on the product. Register configurations of each product are shown below. (1) V850ES/JE3-E Channel...

  • Page 413: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Registers (1) TMT0 control register 0 (TT0CTL0) The TT0CTL0 register is an 8-bit register that controls the operation of TMT0. This register can be read or written in 8-bit or 1-bit units.
  • Page 414 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) TMT0 control register 1 (TT0CTL1) The TT0CTL1 register is an 8-bit register that controls the TMT0 operation. This register can be read or written in 8-bit or 1-bit units.
  • Page 415 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Cautions 1. The TT0EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored.
  • Page 416 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (3) TMT0 control register 2 (TT0CTL2) The TT0CTL2 register is an 8-bit register that controls the encoder count function operation. The TT0CTL2 register is valid only in the encoder compare mode.
  • Page 417 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) TT0UDS1 TT0UDS0 Up/down count selection When valid edge of TENC00 input is detected Counts down when TENC01 = high level. Counts up when TENC01 = low level. Counts up when valid edge of TENC00 input is detected.
  • Page 418 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (4) TMT0 I/O control register 0 (TT0IOC0) The TT0IOC0 register is an 8-bit register that controls the timer output (TOT00, TOT01 pins). This register can be read or written in 8-bit or 1-bit units.
  • Page 419 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) After reset: 00H Address: FFFFF603H <2> <0> TT0OL1 TT0OE1 TT0OL0 TT0OE0 TT0IOC0 Note TT0OL1 TOT01 pin output level setting TOT01 pin starts output at high level. TOT01 pin starts output at low level.
  • Page 420 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (5) TMT0 I/O control register 1 (TT0IOC1) The TT0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIT00, TIT01 pins). This register can be read or written in 8-bit or 1-bit units.
  • Page 421 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (6) TMT0 I/O control register 2 (TT0IOC2) The TT0IOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (TENC00 pin) and external trigger input signal.
  • Page 422 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (7) TMT0 I/O control register 3 (TT0IOC3) The TT0IOC3 register is an 8-bit register that controls the encoder clear function operation. The TT0IOC3 register is valid only in the encoder compare mode.
  • Page 423 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) TT0ECS1 TT0ECS0 Valid edge setting of encoder clear signal (TECR0 pin) Detects no edge (clearing encoder is invalid). Detects rising edge. Detects falling edge. Detects both edges. TT0EIS1 TT0EIS0 Valid edge setting of encoder input signals (TENC00, TENC01 pins) Detects no edge (inputting encoder is invalid).
  • Page 424 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (8) TMT0 option register 0 (TT0OPT0) The TT0OPT0 register is an 8-bit register that sets the capture/compare operation and detects overflows. This register can be read or written in 8-bit or 1-bit units.
  • Page 425 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (9) TMT0 option register 1 (TT0OPT1) The TT0OPT1 register is an 8-bit register that detects overflows, underflows, and count-up/down operations of the encoder count function. The TT0OPT1 register is valid only in the encoder compare mode.
  • Page 426 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) TT0EOF Overflow detection flag for TMT0 encoder function Set (1) Overflow occurs. Reset (0) Cleared by writing 0 to the TT0EOF bit or when the TT0CTL0.TT0CE bit = 0 •...
  • Page 427 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (10) TMT0 capture/compare register 0 (TT0CCR0) The TT0CCR0 register is a 16-bit register that can be used as a capture register or compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS0 bit.
  • Page 428 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (a) Function as compare register The TT0CCR0 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0) is generated.
  • Page 429 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (11) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is a 16-bit register that can be used as a capture register or compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TT0OPT0.TT0CCS1 bit.
  • Page 430 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (a) Function as compare register The TT0CCR1 register can be rewritten even when the TT0CTL0.TT0CE bit = 1. The set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC01) is generated.
  • Page 431 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (12) TMT0 counter write register (TT0TCW) The TT0TCW register is used to set the initial value of the 16-bit counter. The TT0TCW register is valid only in the encoder compare mode.
  • Page 432 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (14) Noise elimination control register (TTNFC) Digital noise elimination can be selected for the TIT00, TIT01, TENC00, TENC01, and TECR0 pins. The noise elimination settings are performed using the TTNFC register.
  • Page 433 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) A timing example of noise elimination performed by the timer T input pin digital filter is shown Figure 8-2. Figure 8-2. Example of Digital Noise Elimination Timing Noise elimination clock...

  • Page 434: Timer Output Operations

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Timer Output Operations The following table shows the operations and output levels of the TOT00 and TOT01 pins. Table 8-5. Timer Output Control in Each Mode Operation Mode TOT01 Pin...

  • Page 435: Operation

    CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Operation The modes realized by the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E, differ depending on the products. The following table shows the executable operation modes of each product Table 8-7. Executable Mode for Each Product...
  • Page 436 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Basic counter operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. (a) Count start operation •...
  • Page 437 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Count value hold operation The value of the 16-bit counter is held by the TT0CTL2.TT0ECC bit in the encoder compare mode. The value of the 16-bit counter is reset to FFFFH when the TT0ECC bit = 0 and TT0CTL0.TT0CE bit = 0. When the TT0CE bit is next set to 1, the set value of the TT0TCW register is transferred to the 16-bit counter and a count operation is performed.
  • Page 438 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Anytime write and batch write The TT0CCR0 and TT0CCR1 registers in TMT0 can be rewritten during timer operation (TT0CTL0.TT0CE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode.
  • Page 439 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-4. Timing of Anytime Write TT0CE bit = 1 FFFFH 16-bit counter 0000H TT0CCR0 register CCR0 buffer register 0000H TT0CCR1 register CCR1 buffer register 0000H INTTT0CC0 signal INTTT0CC1 signal Remarks 1.
  • Page 440 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Batch write In this mode, data is transferred all at once from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
  • Page 441 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-5. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TT0CCRn register • Timer operation enable (TT0CE bit = 1) → Transfer values of TT0CCRn...
  • Page 442 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-6. Timing of Batch Write TT0CE bit = 1 FFFFH 16-bit counter 0000H TT0CCR0 register CCR0 buffer register 0000H Note 1 Note 1 Same value write TT0CCR1 register Note 2...

  • Page 443: Interval Timer Mode (Tt0Md3 To Tt0Md0 Bits = 0000)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.1 Interval timer mode (TT0MD3 to TT0MD0 bits = 0000) In the interval timer mode, an interrupt request signal (INTTT0CC0) is generated at the interval set by the TT0CCR0 register if the TT0CTL0.TT0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOT00 pin.
  • Page 444 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOT00 pin is inverted. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register.
  • Page 445 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-9. Register Setting for Interval Timer Mode Operation (2/2) (d) TMT0 counter read buffer register (TT0CNT) By reading the TT0CNT register, the count value of the 16-bit counter can be read.
  • Page 446 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Interval timer mode operation flow Figure 8-10. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register TOT00 pin output INTTT0CC0 signal <1> <2>...
  • Page 447 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Interval timer mode operation timing (a) Operation if TT0CCR0 register is set to 0000H If the TT0CCR0 register is set to 0000H, the INTTT0CC0 signal is generated at each count clock, and the output of the TOT00 pin is inverted.
  • Page 448 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Operation if TT0CCR0 register is set to FFFFH If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTT0CC0 signal is generated and the output of the TOT00 pin is inverted.
  • Page 449 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value.
  • Page 450 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Operation of TT0CCR1 register Figure 8-11. Configuration of TT0CCR1 Register TT0CCR1 register Output CCR1 buffer register TOT01 pin controller Match signal INTTT0CC1 signal Clear Count clock Output 16-bit counter...
  • Page 451 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CCR1 register is set to the same value as the TT0CCR0 register, the INTTT0CC0 signal is generated at the same timing as the INTTT0CC1 signal and the TOT01 pin output is inverted. In other words, a square wave can be output from the TOT01 pin.
  • Page 452 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the count value of the 16-bit counter does not match the value of the TT0CCR1 register. Consequently, the INTTT0CC1 signal is not generated, nor is the output of the TOT01 pin changed.

  • Page 453: External Event Count Mode (Tt0Md3 To Tt0Md0 Bits = 0001)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.2 External event count mode (TT0MD3 to TT0MD0 bits = 0001) In the external event count mode, the valid edge of the external event count input (TENC00) is counted when the TT0CTL0.TT0CE bit is set to 1, and an interrupt request signal (INTTT0CC0) is generated each time the number of edges...
  • Page 454 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-15. Basic Timing in External Event Count Mode FFFFH 16-bit counter − 1 16-bit counter 0000 0001 0000H External event count input TT0CE bit (TENC00 pin input) TT0CCR0 register...
  • Page 455 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TT0CCR0 register is transferred to the CCR0 buffer register.
  • Page 456 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-16. Register Setting for Operation in External Event Count Mode (2/2) (f) TMT0 capture/compare register 1 (TT0CCR1) The TT0CCR1 register is not used in the external event count mode. However, the set value of the TT0CCR1 register is transferred to the CCR1 buffer register.
  • Page 457 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) External event count mode operation flow Figure 8-17. Software Processing Flow in External Event Count Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register INTTT0CC0 signal <1> <2> <1> Count operation start flow...
  • Page 458 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in external event count mode (a) Operation if TT0CCR0 register is set to 0000H When the TT0CCR0 register is set to 0000H, the 16-bit counter is repeatedly cleared to 0000H and generates the INTTT0CC0 signal each time it has detected the valid edge of the external event count signal and its value has matched that of the CCR0 buffer register.
  • Page 459 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Operation with TT0CCR0 set to FFFFH and TT0CCR1 register to 0000H When the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time it has detected the valid edge of the external event count signal.
  • Page 460 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Notes on rewriting TT0CCR0 register If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting once and then change the set value.
  • Page 461 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (e) Operation of TT0CCR1 register Figure 8-18. Configuration of TT0CCR1 Register TT0CCR1 register CCR1 buffer register Match signal INTTT0CC1 signal Clear TENC00 pin Edge (external event 16-bit counter Note detector...
  • Page 462 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the INTTT0CC1 signal is not generated because the count value of the 16-bit counter and the value of the TT0CCR1 register do not match.

  • Page 463: External Trigger Pulse Output Mode (Tt0Md3 To Tt0Md0 Bits = 0010)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.3 External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010) In the external trigger pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1.
  • Page 464 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-22. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TT0CE bit External trigger input (TENC00 pin input) TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register...
  • Page 465 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-23. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CKS2 TT0CKS1 TT0CKS0 TT0CTL0 Select count clock 0: Stops counting 1: Enables counting...
  • Page 466 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-23. Setting of Registers in External Trigger Pulse Output Mode (2/2) (e) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register.
  • Page 467 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in external trigger pulse output mode Figure 8-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TT0CE bit External trigger input...
  • Page 468 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TT0CCR0, TT0CCR1 register setting change flow Writing of the TT0CCR1 register START must be performed when only the set duty factor is changed.
  • Page 469 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last.
  • Page 470 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) In order to transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TT0CCR0 register and then set the active level width to the TT0CCR1 register.
  • Page 471 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
  • Page 472 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced.
  • Page 473 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the INTTT0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the TOT01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
  • Page 474 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTT0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up again from that point. Therefore, the active period of the TOT01 pin is extended by the time from generation of the INTTT0CC0 signal to trigger detection.
  • Page 475 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (e) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generating the INTTT0CC1 signal in the external trigger pulse output mode differs from the timing of generating INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register.

  • Page 476: One-Shot Pulse Output Mode (Tt0Md3 To Tt0Md0 Bits = 0011)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.4 One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011) In the one-shot pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set to 1.
  • Page 477 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-26. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TT0CE bit External trigger input (TENC00 pin input) TT0CCR0 register INTTT0CC0 signal TOT00 pin output TT0CCR1 register...
  • Page 478 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-27. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CKS2 TT0CKS1 TT0CKS0 TT0CTL0 Note Select count clock 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1.
  • Page 479 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-27. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 Select valid edge of external Note trigger input (TENC00 pin) Note Set the valid edge selection of the unused alternate external input signals to “No edge...
  • Page 480 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in one-shot pulse output mode Figure 8-28. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TT0CE bit External trigger input (TENC00 pin input)
  • Page 481 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TT0CCRn register If the value of the TT0CCRn register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
  • Page 482 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Generation timing of compare match interrupt request signal (INTTT0CC1) The generation timing of the INTTT0CC1 signal in the one-shot pulse output mode is different from INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register.

  • Page 483: Pwm Output Mode (Tt0Md3 To Tt0Md0 Bits = 0100)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.5 PWM output mode (TT0MD3 to TT0MD0 bits = 0100) In the PWM output mode, a PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1.
  • Page 484 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-30. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register INTTT0CC1 signal...
  • Page 485 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-31. Setting of Registers in PWM Output Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CKS2 TT0CKS1 TT0CKS0 TT0CTL0 Note Select count clock 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1.
  • Page 486 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-31. Register Setting in PWM Output Mode (2/2) (d) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 Select valid edge of external event count input (TENC00 pin).
  • Page 487 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in PWM output mode Figure 8-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal...
  • Page 488 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-32. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TT0CCR0, TT0CCR1 register setting change flow (duty only) Only writing of the TT0CCR1 START...
  • Page 489 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TT0CCR1 register last. Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC1 signal is detected.
  • Page 490 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
  • Page 491 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Generation timing of compare match interrupt request signal (INTTT0CC1) The timing of generation of the INTTT0CC1 signal in the PWM output mode differs from the timing of INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TT0CCR1 register.

  • Page 492: Free-Running Timer Mode (Tt0Md3 To Tt0Md0 Bits = 0101)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.6 Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101) In the free-running timer mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. At this time, the TT0CCR0 and TT0CCR1 registers can be used as compare registers or capture registers, depending on the setting of the TT0OPT0.TT0CCS0 and TT0OPT0.TT0CCS1 bits.
  • Page 493 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) • Compare operation When the TT0CE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOT0n pin is inverted. When the count value of the 16-bit counter later matches the set value of the TT0CCRn register, a compare match interrupt request signal (INTTT0CCn) is generated, and the output signal of the TOT0n pin is inverted.
  • Page 494 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) • Capture operation When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and a capture interrupt request signal (INTTT0CCn) is generated.
  • Page 495 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-36. Register Setting in Free-Running Timer Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CKS2 TT0CKS1 TT0CKS0 TT0CTL0 Note Select count clock 0: Stops counting 1: Enables counting Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1...
  • Page 496 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-36. Register Setting in Free-Running Timer Mode (2/2) (e) TMT0 I/O control register 2 (TT0IOC2) TT0EES1 TT0EES0 TT0ETS1 TT0ETS0 TT0IOC2 Select valid edge of external event count input (TENC00 pin)
  • Page 497 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter...
  • Page 498 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TT0CTL0 register is performed before setting the (TT0CKS0 to TT0CKS2 bits) TT0CE bit to 1.
  • Page 499 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) When using capture/compare register as capture register Figure 8-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input TT0CCR0 register...
  • Page 500 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TT0CTL0 register is performed before setting the (TT0CKS0 to TT0CKS2 bits) TT0CE bit to 1.
  • Page 501 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter T is used as an interval timer with the TT0CCRn register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTT0CCn signal has been detected.
  • Page 502 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TT0CCRn register used as a capture register, software processing is necessary for reading the capture register each time the INTTT0CCn signal has been detected and for calculating an interval.
  • Page 503 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
  • Page 504 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TT0CE bit INTTT0OV signal TT0OVF bit Note TT0OVF0 flag TIT00 pin input TT0CCR0 register Note...
  • Page 505 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TT0CE bit INTTT0OV signal TT0OVF bit Note TT0OVF0 flag TIT00 pin input TT0CCR0 register...
  • Page 506 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next.
  • Page 507 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TT0CE bit TIT0n pin input TT0CCRn register INTTT0OV signal TT0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...

  • Page 508: Pulse Width Measurement Mode (Tt0Md3 To Tt0Md0 Bits = 0110)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.7 Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110) In the pulse width measurement mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. Each time the valid edge input to the TIT0n pin has been detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and the 16-bit counter is cleared to 0000H.
  • Page 509 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TT0CE bit TIT0n pin input 0000H TT0CCRn register INTTT0CCn signal INTTT0OV signal Cleared to 0 by CLR instruction...
  • Page 510 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-41. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMT0 control register 0 (TT0CTL0) TT0CE TT0CKS2 TT0CKS1 TT0CKS0 TT0CTL0 Note Select count clock 0: Stops counting 1: Enables counting Note Setting is invalid when the TT0CTL1.TT0EEE bit = 1.
  • Page 511 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-41. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMT0 option register 0 (TT0OPT0) TT0CCS1 TT0CCS0 TT0OVF TT0OPT0 Overflow flag (f) TMT0 counter read buffer register (TT0CNT) The value of the 16-bit counter can be read by reading the TT0CNT register.
  • Page 512 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (1) Operation flow in pulse width measurement mode Figure 8-42. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TT0CE bit TIT00 pin input 0000H 0000H TT0CCR0 register INTTT0CC0 signal <1>...
  • Page 513 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF bit when it is 1.

  • Page 514: Triangular-Wave Pwm Output Mode (Tt0Md3 To Tt0Md0 Bits = 0111)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.8 Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111) In the triangular-wave PWM output mode, a triangular-wave PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1.
  • Page 515 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-44. Basic Timing in Triangular-Wave PWM Output Mode FFFFH 16-bit counter 0000H TT0CE bit TT0CCR0 register CCR0 buffer register INTTT0CC0 signal TOT00 pin output TT0CCR1 register CCR1 buffer register...

  • Page 516: Encoder Count Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.9 Encoder count function The encoder count function includes an encoder compare mode (see 8.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)). Mode TT0CCR0 Register TT0CCR1 Register Encoder compare mode...
  • Page 517 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (5) Controlling bits of TT0CTL2 register The setting of the TT0CTL2 register in the encoder compare mode is shown below. Table 8-9. Setting of TT0CTL2 Register Mode TT0UDS1, TT0ECM1 Bit...
  • Page 518 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Detailed explanation of each bit <1> TT0UDS1 and TT0UDS0 bits: Count-up/-down selection Whether the 16-bit counter is counting up or down is identified by the phase input from the TENC00 or TENC01 pin and depending on the settings of the TT0UDS1 and TT0UDS0 bits.
  • Page 519 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) • When TT0UDS1 and TT0UDS0 bits = 01 TENC00 Pin TENC01 Pin Count Operation Low level Rising edge Count down Falling edge Both edges High level Rising edge Falling edge...
  • Page 520 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) • When TT0UDS1 and TT0UDS0 bits = 10 TENC00 Pin TENC01 Pin Count Operation Low level Falling edge Counter does not perform count operation but holds value immediately before. Rising edge...
  • Page 521 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) • When TT0UDS1 and TT0UDS0 bits = 11 TENC00 Pin TENC01 Pin Count Operation Low level Falling edge Count down Rising edge Low level High level Rising edge Falling edge...
  • Page 522 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) <2> TT0ECM1 and TT0ECM0 bits: Timer/counter clear function upon match of the compare register The 16-bit counter performs its count operation in accordance with the set value of the TT0ECM1 and TT0ECM0 bits when the count value of the counter matches the value of the CCRn buffer register.
  • Page 523 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) <3> TT0LDE bit: Transfer function of the set value of the TT0CCR0 register to the 16-bit counter when the counter underflows When the TT0LDE bit = 1, the set value of the TT0CCR0 register can be transferred to the 16-bit counter when the counter underflows.
  • Page 524 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-52. Operation Timing (Count Operation in Range from 0000H to Set Value of TT0CCR0 Register) Peripheral clock Count timing signal H = down counting TT0ESF bit − 0002H 0001H...
  • Page 525 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin) The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are selected by the TT0IOC3.TT0SCE bit.
  • Page 526 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Clearing method <2>: By detecting clear level condition of the TENC00, TENC01, and TECR0 pins (TT0SCE bit = 1) When the TT0SCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECR0, TENC00, or TENC01 pin specified by the TT0ZCL, TT0BCL, and TT0ACL bits is detected.
  • Page 527 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (1/3) (i) If inputting the high level to the TECR0 pin lags behind inputting the low level to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up.
  • Page 528 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (2/3) (ii) If the high level is input to the TECR0 pin at the same time as the low level is input to the TECN01 pin while the counter is counting up, the counter is cleared without counting up.
  • Page 529 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (3/3) (iv) If the high level is input to the TECR0 pin later than the low level is input to the TENC01 pin while the counter is counting up, the counter is cleared after it counts up.
  • Page 530 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (7) Notes on using encoder count function (a) If compare match interrupt is not generated immediately after operation is started If a value which is the same as that of the TT0TCW register is set to the TT0CCR0 or TT0CCR1 register and the counter operation is started when the TT0CTL2.TT0ECC bit = 0, and if the count value (TT0TCW) of the...
  • Page 531 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) If overflow does not occur immediately after start of operation If the count operation is resumed when the TT0CTL2.TT0ECC bit = 1, the 16-bit counter does not overflow if its count value that has been held is FFFFH and if the next count operation is counting up.

  • Page 532: Encoder Compare Mode (Tt0Md3 To Tt0Md0 Bits = 1000)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) 8.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000) In the encoder compare mode, the encoder is controlled by using both the TT0CCR0 and TT0CCR1 registers as compare registers and the input pins for encoder count function (TENC00, TENC01, and TECR0).
  • Page 533 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) Figure 8-56. Encoder Compare Mode Operation Processing Valid edge of TENC00, TENC01 detected? Count down Which count operation? Count up TT0ECM0 = 1? TT0ECM1 = 1? (TT0CTL2) (TT0CTL2) Count value matches...
  • Page 534 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (2) Encoder compare mode operation timing (a) Basic timing 1 [Register setting conditions] • TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 01 The 16-bit counter is cleared to 0000H when its count value matches the value of the CCR0 buffer register.
  • Page 535 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the counter and the 16-bit counter starts operating.
  • Page 536 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (b) Basic timing 2 [Register setting condition] • TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 00 The 16-bit counter is not cleared even when its count value matches the value of the CCRn buffer register (a = 0, 1).
  • Page 537 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating.
  • Page 538 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) (c) Basic timing 3 [Register setting condition] • TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 11 The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR0 buffer register.
  • Page 539 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT) When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is transferred to the 16-bit counter and the counter starts operating.

  • Page 540: Chapter 9 16-Bit Interval Timer M (Tmm)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E have four TMM channels (TMMn). Overview TMMn has the following features. • Interval function • 8 clocks selectable •...

  • Page 541: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Configuration TMMn includes the following hardware. Table 9-1. Configuration of TMMn Item Configuration Timer register 16-bit counter Register TMMn compare register 0 (TMnCMP0) Control register TMMn control register 0 (TMnCTL0) Figure 9-1.
  • Page 542 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) 16-bit counter This is a 16-bit counter that counts the internal clock. The 16-bit counter cannot be read or written. (2) TMMn compare register 0 (TMnCMP0) The TMnCMP0 register is a 16-bit compare register.

  • Page 543: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Registers (1) TMMn control register (TMnCTL0) The TMnCTL0 register is an 8-bit register that controls the TMMn operation. This register can be read or written in 8-bit or 1-bit units.
  • Page 544 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) After reset: 00H Address: TM0CTL0 FFFFFA80H, TM1CTL0 FFFFFA90H, TM2CTL0 FFFFFAA0H, TM3CTL0 FFFFFAB0H <7> TMnCTL0 TMnCE TMnCKS2 TMnCKS1 TMnCKS0 (n = 0 to 3) TMnCE Internal clock operation enable/disable specification TMMn operation disabled (16-bit counter reset asynchronously).

  • Page 545: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Operation Caution Do not set the TMnCMP0 register to FFFFH. 9.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTMnEQ0) is generated at the specified interval if the TMnCTL0.TMnCE bit is set to 1.
  • Page 546 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) When the TMnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting.
  • Page 547 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TMnCE bit TMnCMP0 register INTTMnEQ0 signal <1> <2> <1> Count operation start flow...
  • Page 548 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TMnCMP0 register to FFFFH. (a) Operation if TMnCMP0 register is set to 0000H If the TMnCMP0 register is set to 0000H, the INTTMnEQ0 signal is generated at each count clock.

  • Page 549: Cautions

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.4.2 Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TMnCTL0.TMnCE bit is set to 1, depending on the count clock selected.

  • Page 550: Chapter 10 Motor Control Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.1 Functional Overview Timer AB1 (TAB1) and the TAB1 option (TAB1OP0) can be used as an inverter function that controls a motor. It performs a tuning operation with timer AA4 (TAA4) and A/D conversion of the A/D converter can be started when the value of TAB1 matches the value of TAA4.

  • Page 551: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.2 Configuration The motor control function consists of the following hardware. Item Configuration Timer register Dead-time counters Compare register TAB1 dead-time compare register (TAB1DTC register) Control registers TAB1 option register 1 (TAB1OPT1)
  • Page 552 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-1. Block Diagram of Motor Control TOAB10 TAB1 TOAB1T1 TMQ option • Carrier • 3-phase PWM • 6-phase PWM TOAB1B1 generation generation with dead time from 3-phase PWM TOAB1T2 TAA4 •...
  • Page 553 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-2. TAB1 Option Internal bus TOAB10 TABnDTC High-impedance (10-bit dead-time value) output controller TAB1 Channel 1 Positive Level TOAB1T1 phase control TOAB10 Clear Edge Dead-time counter 1 Active setting...
  • Page 554 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (1) TAB1 dead-time compare register (TAB1DTC) The TAB1DTC register is a 10-bit compare register that specifies the dead-time value. Rewriting this register is prohibited when the TAB1CTL0.TAB1CE bit = 1.

  • Page 555: Control Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.3 Control Registers (1) TAB1 option register 1 (TAB1OPT1) The TAB1OPT1 register is an 8-bit register that controls the interrupt request signal generated by the timer AB1 option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1.
  • Page 556 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (2) TAB1 option register 2 (TAB1OPT2) The TAB1OPT2 register is an 8-bit register that controls the timer AB1 option function. This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. However, rewriting the TAB1DTM bit is prohibited when the TAB1CE bit is 1.
  • Page 557 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (2/2) TAB1ATM3 TAB1ATM3 mode selection Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting up. Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while dead-time counter is counting down.
  • Page 558 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (3) TAB1 I/O control register 3 (TAB1IOC3) The TAB1IOC3 register is an 8-bit register that controls the output of the timer AB1 option function. To output from the TOAB1Tm pin, set the TAB1IOC0.TAB1OEm bit to 1 and then set the TAB1IOC3 register.
  • Page 559 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (a) Output from TOAB1Tm and TOAB1Bm pins The TOAB1Tm pin output is controlled by the TAB1IOC0.TAB1OLm and TAB1IOC0.TAB1OEm bits. The TOAB1Bm pin output is controlled by the TAB1IOC3.TAB1OLBm and TAB1IOC3.TAB1OEBm bits.
  • Page 560 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Table 10-1. TOAB1Tm Pin Output TAB1OLm Bit TAB1OEm Bit TAB1CE Bit TOAB1Tm Pin Output Low-level output Low-level output TOAB1Tm positive-phase output High-level output High-level output TOAB1Tm negative-phase output Remark m = 1 to 3 Table 10-2.
  • Page 561 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (1/2) After reset: 00H Address: HZA0CTL0 FFFFF590H, HZA0CTL1 FFFFF591H <7> <6> <3> <2> <0> HZA0CTLn HZA0DCEn HZA0DCMn HZA0DCNn HZA0DCPn HZA0DCTn HZA0DCCn HZA0DCFn (n = 0, 1) High-impedance output control HZA0DCEn Disable high-impedance output control operation.
  • Page 562 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (2/2) High-impedance output trigger bit HZA0DCTn No operation Pins are made to go into a high-impedance state by software and the HZA0DCFn bit is set to 1. • If an edge indicating abnormality is input to the external pin (which is detected according to the setting of the HZA0DCNn and HZA0DCPn bits), the HZA0DCTn bit is invalid even if it is set to 1.
  • Page 563 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-4. High-Impedance Output Controller Configuration INTP16 Edge detection Edge detection INTP09 TOAA1OFF/ Analog HZA0CTL1 INTP09 filter Note TAA1 TOAA11 TOAB1OFF/ Analog HZA0CTL0 INTP16 filter TOAB1B1 TMQOP Main Clock monitor...
  • Page 564 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (a) Setting procedure (i) Setting of high-impedance control operation <1> Set the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits. <2> Set the HZA0DCEn bit to 1 (enable high-impedance control). (ii) Changing setting after enabling high-impedance control operation <1>...

  • Page 565: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.4 Operation 10.4.1 System outline (1) Outline of 6-phase PWM output The 6-phase PWM output mode is used to generate a 6-phase PWM output wave, by using the timer AB1 (TAB1) and the TAB1 option (TAB1OP0) in combination.
  • Page 566 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-5. Outline of 6-Phase PWM Output Mode A/D trigger 16-bit counter Up/down selection generator INTTAB1OV signal INTTAB1OV_BASE (valley interrupt) Interrupt 0001H culling circuit INTTAB1CC0 signal (crest interrupt) TOAB10 pin...
  • Page 567 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-6. Timing Chart of 6-Phase PWM Output Mode M + 1 M + 1 16-bit counter 0000H TAB1CCR0 (carrier data) register TAB1CCR1 (phase U data) register TAB1CCR2 (phase V data)
  • Page 568 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (2) Interrupt requests Two types of interrupt requests are available: the INTTAB1CC0 (crest interrupt) signal and INTTAB1OV (valley interrupt) signal. The INTTAB1CC0 and INTTAB1OV signals can be culled by using the TAB1OPT1 register.
  • Page 569 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-7. Interrupt and Up/Down Flag M + 1 M + 1 16-bit counter 0000H TAB1CCR0 M (carrier data) register TAB1CCR1 i (phase U data) register TAB1CCR2 j (phase V data)

  • Page 570: Dead-Time Control (Generation Of Negative-Phase Wave Signal)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.4.2 Dead-time control (generation of negative-phase wave signal) (1) Dead-time control mechanism In the 6-phase PWM output mode, compare registers 1 to 3 (TAB1CCR1, TAB1CCR2, and TAB1CCR3) are used to set the duty factor, and compare register 0 (TAB1CCR0) is used to set the cycle.
  • Page 571 CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (2) PWM output of 0%/100% The V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E are capable of 0% wave output and 100% wave output for PWM output. A low level is continuously output from the TOAB1Tm pin as the 0% wave output. A high level is continuously output from the TOAB1Tm pin as the 100% wave output.
  • Page 572 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-10. 100% PWM Output Waveform (With Dead Time) 16-bit counter TAB1CCR0 register TAB1CCR1 0000H 0000H register CCR1 0000H 0000H 0000H buffer register <1> <2> <3> <4> TOAB1T1 pin output...
  • Page 573 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-11. PWM Output Waveform from 0% to 100% and from 100% to 0% (With Dead Time) 16-bit counter TAB1CCR0 register TAB1CCR1 0000H M + 1 0000H M + 1...
  • Page 574 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-12. PWM Output Waveform with Dead Time (2) (a) 0% output (TAB1CCRm register = M + 1, TAB1CCR0 register = M, TAB1DTC register = a) 16-bit counter 0000H TOAB1m signal...
  • Page 575 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (4) Automatic dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1) The dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the TAB1OPT2.TAB1DTM bit to 1.

  • Page 576: Interrupt Culling Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (5) Dead-time control in case of incorrect setting Usually, the TOAB1m (internal signal) output of TAB1 changes only once during dead-time counting, only in the vicinity of 0% and 100% output. This section shows an example where the TAB1CCR0 register (carrier cycle) and TAB1DTC register (dead-time value) are incorrectly set.
  • Page 577 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) • The TAB1OPT1.TAB1ICE bit is used to enable output of the INTTAB1CC0 interrupt and the number of times the interrupt is to be culled. • The TAB1OPT1.TAB1IOE bit is used to enable output of the INTTAB1OV interrupt and the number of times the interrupt is to be culled.
  • Page 578 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (1) Interrupt culling operation Figure 10-15. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Crest/Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled)
  • Page 579 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-16. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0, TAB1OPT2.TAB1RDE Bit = 1 (Crest Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled)
  • Page 580 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-17. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT2.TAB1RDE Bit = 1 (Valley Interrupt Output) 16-bit counter TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled)
  • Page 581 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (2) To alternately output crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV) To alternately output the crest and valley interrupts, set both the TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits to 1. Figure 10-18. Crest/Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control)
  • Page 582 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (3) To output only crest interrupt (INTTAB1CC0) Set the TAB1OPT1.TAB1ICE bit to 1 and clear the TAB1OPT1.TAB1IOE bit to 0. Figure 10-19. Crest Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control)
  • Page 583 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (4) To output only valley interrupt (INTTAB1OV) Clear the TAB1OPT1.TAB1ICE bit to 0 and set the TAB1IOE bit to 1. Figure 10-20. Valley Interrupt Output (a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control)

  • Page 584: Operation To Rewrite Register With Transfer Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.4.4 Operation to rewrite register with transfer function The following seven registers are provided with a transfer function and are used to control a motor. Each of the registers has a buffer register.
  • Page 585 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (1) Anytime rewrite mode This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The setting of the TAB1OPT2.TAB1RDE bit is ignored. In this mode, the value written to each register with a transfer function is immediately transferred to an internal buffer register and compared with the value of the counter.
  • Page 586 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (b) Rewriting TAB1CCRm register Figure 10-24 shows the timing of rewriting before the value of the 16-bit counter matches the value of the TAB1CCRm register (<1> in Figure 10-23), and Figure 10-25 shows the timing of rewriting after the value of the 16-bit counter matches the value of the TAB1CCRm register (<2>...
  • Page 587 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-24. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting Before Match Occurs) If the TAB1CCRm register is rewritten before its value matches the value of the 16-bit counter, the register value will match the value of the 16-bit counter after the register has been rewritten.
  • Page 588 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-25. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting After Match Occurs) 16-bit counter TAB1CCRm register CCRm buffer register TOAB1Tm <3> <1> pin output INTTAB1CCm <2> signal <1> Matching of the count value of the 16-bit counter and the value of the TAB1CCRm register as a result of rewriting the register is ignored after a match signal has been generated, and the PWM output does not change.
  • Page 589 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (2) Batch rewrite mode (transfer mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0.
  • Page 590 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-26. Basic Operation in Batch Mode 16-bit counter (TAB1) Transfer <Q2> timing TAB1CCR0 <Q3> register CCR0 buffer register TAB1CCR1 <Q3> <Q1>&<P1> register CCR1 buffer register <Q3> TAB1CCR2 register CCR2 buffer...
  • Page 591 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (b) Rewriting TAB1CCR0 register When rewriting the TAB1CCR0 register in the batch rewrite mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16-bit counter value and TAB1CCR0 register value) or at the valley (match between the 16-bit counter value and 0001H).
  • Page 592 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) The transfer timing in Figure 10-28 is at the point where the crest timing occurs. While the 16-bit counter is counting down, the cycle changes and an asymmetrical triangular wave is output. Because the cycle changes, rewrite the duty factor (voltage data value).
  • Page 593 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-29. Example of Rewriting TAB1CCR0 Register (During Counting Down) M + 1 16-bit N + 1 counter Transfer timing TAB1CCR0 register CCR0 buffer 0000H register TAB1CCR1 register CCR1 buffer...
  • Page 594 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (c) Rewriting TAB1CCRm register Figure 10-30. Example of Rewriting TAB1CCRm Register 16-bit counter Transfer timing TAB1CCRm register CCRm buffer 0000H register TOAB1Tm register INTTAB1CCm signal <1> <2> <1> <2> Rewriting during period <1> (rewriting during counting up) Because the TAB1CCRm register value is transferred at the transfer timing of the crest (match between the 16-bit counter value and TAB1CCRm register value), an asymmetrical triangular wave is output.
  • Page 595 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (3) Intermittent batch rewrite mode (transfer culling mode) This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1. In this mode, the values written to each compare register are transferred to the internal buffer register all at once after the culled transfer timing and compared with the counter value.
  • Page 596 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-31. Basic Operation in Intermittent Batch Rewrite Mode 16-bit counter (TAB1) Transfer <Q2> <Q4> <Q4> timing TAB1CCR0 <Q3> register CCR0 buffer register TAB1CCR1 <Q3> <Q1>&<P1> register CCR1 buffer register <Q3>...
  • Page 597 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (b) Rewriting TAB1CCR0 register When rewriting the TAB1CCR0 register in the intermittent batch mode, the output waveform differs depending on where the occurrence of the crest or valley interrupt is specified by the interrupt culling setting. The following figure illustrates the change of the output waveform when interrupts are culled.
  • Page 598 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-33. Rewriting TAB1CCR0 Register (When Valley Interrupt Is Set) M + 1 M + 1 16-bit N + 1 counter Transfer timing TAB1CCR0 register CCR0 buffer 0000H register TAB1CCR1...
  • Page 599 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (c) Rewriting TAB1CCR1 to TAB1CCR3 registers • Transfer at crest when crest interrupt is set Because the register is transferred at the transfer timing of the crest interrupt, an asymmetrical triangular wave is output.
  • Page 600 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) • Transfer at valley when valley interrupt is set Because the register is transferred at the transfer timing of the valley interrupt, a symmetrical triangular wave is output. Figure 10-35. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00001)
  • Page 601 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (4) Rewriting TAB1OPT0.TAB1CMS bit The TAB1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten during timer operation (when TAB1CTL0.TAB1CE bit = 1). However, the operation and caution illustrated in Figure 10-36 are necessary.

  • Page 602: Taa4 Tuning Operation For A/D Conversion Start Trigger Signal Output

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.4.5 TAA4 tuning operation for A/D conversion start trigger signal output This section explains the tuning operation of TAA4 and TAB1 in the 6-phase PWM output mode. In the 6-phase PWM output mode, the tuning operation is performed with TAB1 serving as the master and TAA4 as a slave.
  • Page 603 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (e) Set the TAA4CE bit to 1 and set the TAB1CE bit to 1 immediately after that to start the 6-phase PWM output operation Rewriting the TAB1CTL0, TAB1CTL1, TAB1IOC1, TAB1IOC2, TAA4CTL0, and TAA4CTL1 registers is prohibited during operation.
  • Page 604 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-37. TAA4 During Tuning Operation M + 1 M + 1 16-bit counter of TAB1 TAB1CCR0 M (carrier data) register TAB1CCR1 i (phase U data) register j (phase V data)

  • Page 605: A/D Conversion Start Trigger Output Function

    CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) 10.4.6 A/D conversion start trigger output function The V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E have a function to select four trigger sources (INTTAB1OV, INTTAB1CC0, INTTAA4CC0, INTTAA4CC1) to generate the A/D conversion start trigger signal (TABTADT0).
  • Page 606 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Cautions 1. The A/D conversion start trigger signal output that is set by the TAB1AT2 and TAB1AT3 bits can be used only when TAA4 is performing a tuning operation as the slave timer of TAB1. If TAB1 and TAA4 are not performing a tuning operation, or if a mode other than the 6-phase PWM output mode is used, the output cannot be guaranteed.
  • Page 607 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-38. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00000: Without Interrupt Culling) 16-bit counter...
  • Page 608 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) Figure 10-39. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output (TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1, TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00010: With Interrupt Culling) (1) 16-bit...
  • Page 609 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 10 MOTOR CONTROL FUNCTION (V850ES/JF3-E, V850ES/JG3-E) (1) Operation under boundary condition (operation when 16-bit counter matches INTTAA4CC0 signal) Table 10-3. Operation When TAB1CCR0 Register = M, TAB1AT2 Bit = 1, TAB1ATM2 Bit = 0 (Counting Up Period Selected)

  • Page 610: Chapter 11 Real-Time Counter

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER CHAPTER 11 REAL-TIME COUNTER 11.1 Functions The real-time counter (RTC) has the following features. • Counting up to 99 years using year, month, day-of-week, day, hour, minute, and second sub-counters provided • Year, month, day-of-week, day, hour, minute, and second counter display using BCD codes Note 1 •...

  • Page 611: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.2 Configuration The real-time counter includes the following hardware. Table 11-1. Configuration of Real-Time Counter Item Configuration Control registers Real-time counter control register 0 (RC1CC0) Real-time counter control register 1 (RC1CC1) Real-time counter control register 2 (RC1CC2)
  • Page 612 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER Figure 11-1. Block Diagram of Real-Time Counter CLOE1 RTC1HZ Note2 Minute Hour Day-of-week alarm alarm alarm INTRTC1 INTRTC0 Count clock = 32.768 kHz 1 minute 1 hour 1 month 1 day BRG Note1...

  • Page 613: Pin Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.2.1 Pin configuration The RTC outputs included in the real-time counter are alternatively used as shown in Table 11-2. The port function must be set when using each pin (see Table 4-17 Settings When Pins Are Used for Alternate Functions).

  • Page 614: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.3 Registers The real-time counter is controlled by the following 18 registers. (1) Real-time counter control register 0 (RC1CC0) The RC1CC0 register selects the real-time counter input clock. This register can be read or written in 8-bit or 1-bit units.
  • Page 615 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER After reset: 00H Address: FFFFFADEH Note Note RC1CC1 RTCE CLOE1 CLOE0 AMPM RTCE Control of operation of each counter Stops counter operation. Enables counter operation. Note CLOE1 RTC1HZ pin output control Disables RTC1HZ pin output (1 Hz)
  • Page 616 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (3) Real-time counter control register 2 (RC1CC2) The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters. This register can be read or written in 8-bit or 1-bit units.
  • Page 617 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (4) Real-time counter control register 3 (RC1CC3) The RC1CC3 register is an 8-bit register that controls the interval interrupt function and RTCDIV pin. This register can be read or written in 8-bit or 1-bit units.
  • Page 618 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (5) Sub-count register (RC1SUBC) The RC1SUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes a value of 0000H to 7FFFH and counts one second with a clock of 32.768 kHz.
  • Page 619 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (7) Minute count register (RC1MIN) The RC1MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows.
  • Page 620 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER Table 11-3 shows the relationship among the AMPM bit setting value, RC1HOUR register value, and time. Table 11-3. Time Digit Display 12-Hour Display (AMPM Bit = 0) 24-Hour Display (AMPM Bit = 1)
  • Page 621 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (9) Day count register (RC1DAY) The RC1DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows.
  • Page 622 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (11) Day-of-week count register (RC1WEEK) The RC1WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the day-of-week count value. It counts up in synchronization with the day counter.
  • Page 623 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (11) Month count register (RC1MONTH) The RC1MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows.
  • Page 624 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (13) Watch error correction register (RC1SUBU) The RC1SUBU register is an 8-bit register that can be used to correct the watch with high accuracy when the watch is early or late, by changing the value (reference value: 7FFFH) overflowing from the sub-count register (RSUBC) to the second counter register.
  • Page 625 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (14) Alarm minute setting register (RC1ALM) The RC1ALM register is an 8-bit register that is used to set minutes of alarm. This register can be read or written in 8-bit units. Reset sets this register to 00H.
  • Page 626 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (16) Alarm day-of-week setting register (RC1ALW) The RC1ALW register is an 8-bit register that is used to set the day-of-week of the alarm. This register can be read or written in 8-bit units.
  • Page 627 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (a) Alarm interrupt setting examples (RC1ALM, RC1ALH, and RC1ALW setting examples) Tables 11-4 and 11-5 show setting examples if Sunday is RC1WEEK = 00, Monday is RC1WEEK = 01, Tuesday is RC1WEEK = 02, ···, and Saturday is RC1WEEK = 06.
  • Page 628 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (18) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H...

  • Page 629: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4 Operation 11.4.1 Initial settings The initial settings are set when operating the watch function and performing a fixed-cycle interrupt operation. Figure 11-2. Initial Setting Procedure Start Stops counter operation. RC1CC0.RC1PWR bit = 0 Setting RC1CKS Selects real-time counter (RTC) operation clock.

  • Page 630: Rewriting Each Counter During Real-Time Counter Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4.2 Rewriting each counter during real-time counter operation Set as follows when rewriting each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1). Figure 11-3. Rewriting Each Counter During Real-time Counter Operation...

  • Page 631: Reading Each Counter During Real-Time Counter Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4.3 Reading each counter during real-time counter operation Set as follows when reading each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1, RTCE = 1). Figure 11-4. Reading Each Counter During Real-time Counter Operation...

  • Page 632: Changing Intrtc0 Interrupt Setting During Real-Time Counter Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4.4 Changing INTRTC0 interrupt setting during real-time counter operation If the setting of the INTRTC0 interrupt (fixed-cycle interrupt) signal is changed while the real-time counter clock operates (PC1PWR = 1, RTCE =1), the INTRCT0 interrupt waveform may include whiskers and unintended signals may be output.

  • Page 633: Changing Intrtc1 Interrupt Setting During Real-Time Counter Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4.5 Changing INTRTC1 interrupt setting during real-time counter operation If the setting of the INTRTC1 interrupt (alarm interrupt) signal is changed while the real-time counter operates (RC1PWR = 1, RTCE = 1), the INTRCT1 interrupt waveform may include whiskers and unintended signals may be output.

  • Page 634: Initial Intrtc2 Interrupt Settings

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4.6 Initial INTRTC2 interrupt settings Set as follows to set the INTRTC1 interrupt (interval interrupt). Figure 11-7. INTRTC2 Interrupt Setting Start RC1CC0.RC1PWR bit = 1 Enables counter operation. Setting RC1CC3.ICT2 to <1> Selects INTRTC2 (interval) interrupt interval.

  • Page 635: Changing Intrtc2 Interrupt Setting During Real-Time Counter Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4.7 Changing INTRTC2 interrupt setting during real-time counter operation If the setting of the INTRTC2 interrupt (interval interrupt) is changed while the real-time counter clock operates (PC1PWR = 1, RTCE = 1), the INTRCT2 interrupt waveform may include whiskers and unintended signals may be output.

  • Page 636: Initializing Real-Time Counter

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER 11.4.8 Initializing real-time counter The procedure for initializing the real-time counter is shown below. Figure 11-9. Initializing Real-Time Counter Start Setting RTCnMK bit Masks interrupt signal (INTRTCn) RTCDIV interrupt disable processing RC1CC3.CLOE2 bit = 0 RTC1HZ interrupt disable processing RC1CC1.CLOE1 bit = 0...

  • Page 637: Watch Error Correction Example Of Real-Time Counter

    11.4.9 Watch error correction example of real-time counter The watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E. Deviation, here, refers to steady-state deviation, which is deviation in the frequency when the resonator is designed.
  • Page 638 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER As shown in Figure 11-10, the watch can be accurately counted by incrementing the RC1SUBC count value, if a positive error faster than 32.768 kHz occurs at the resonator. Similarly, if a negative error slower than 32.768 kHz occurs at the resonator, the watch can be accurately counted by decrementing the RC1SUBC count value.
  • Page 639 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER (3) DEV bit The DEV bit determines when the setting by the F6 to F0 bits is enabled. The value set by the F6 to F0 bits is reflected upon the next timing, but not to the RC1SUBC count value every time.
  • Page 640 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 11 REAL-TIME COUNTER Table 11-7. Range of Frequencies That Can Be Corrected When DEV Bit = 0 F5 to F0 RC1SUBC Correction Value Frequency of Connected Clock (Including Steady-State Deviation) − 000000 No correction − 000001...

  • Page 641: Chapter 12 Functions Of Watchdog Timer 2

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.1 Functions Watchdog timer 2 has the following functions. • Default-start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) →...

  • Page 642: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 12-1. Block Diagram of Watchdog Timer 2 to f to f INTWDT2 Clock to f Output 16-bit...

  • Page 643: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release.
  • Page 644 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 Table 12-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.) 41.0 ms 18.6 ms 10.2 ms 81.9 ms 37.2 ms...

  • Page 645: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register. The WDTE register can be read or written in 8-bit units.

  • Page 646: Chapter 13 Real-Time Output Function (Rto)

    Because signals without jitter can be output by using RTO, it is suitable for controlling a stepper motor. One 3-bit real-time output port channel is provided in the V850ES/JE3-E and V850ES/JF3-E and one 6-bit real-time output port channel is provided in the V850ES/JG3-E.

  • Page 647: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.2 Configuration The block diagram of RTO is shown below. Figure 13-1. Block Diagram of RTO Real-time output Real-time output buffer register 0H RTP04 to latch 0H (RTBH0) RTP05 Real-time output...
  • Page 648 RTBH05 RTBH04 Note V850ES/JG3-E only Cautions 1. Be sure to set the RTBL0.RTBL03 bit 0 for V850ES/JE3-E and V850ES/JF3-E. Be sure to set the RTBH0.RTBH05, and RTBH0.RTB04 bits 0 for V850ES/JG3-E. 2. Accessing the RTBL0 and RTBH0 registers is prohibited in the following statuses.

  • Page 649: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.3 Registers RTO is controlled using the following two registers. • Real-time output port mode register 0 (RTPM0) • Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units.
  • Page 650 2. The INTTAA0CC0 signal is output for 1 clock of the count clock selected by TAA0. Caution Set the RTPEG0, BYTE0, and EXTR0 bits only when the RTPOE0 bit = 0. Table 13-3. Operation Modes and Output Triggers of Real-Time Output Port (V850ES/JE3-E and V850ES/JF3-E) EXTR0...

  • Page 651: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits).

  • Page 652: Usage

    After setting the PFC5.PFC5m bit and PFCE5.PFCE5m bit to the RTO pin, set the PMC5.PMC45 bit to 1 (m = 0 to 2: V850ES/JE3-E and V850ES/JF3-E, m = 0 to 5: V850ES/JG3-E). • Specify the real-time output port mode or port mode in 1-bit units.

  • Page 653: Chapter 14 A/D Converter

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER CHAPTER 14 A/D CONVERTER 14.1 Overview The A/D converter consists of that converts analog input to digital values, and of 10 channels (ANI0 to ANI9 pins). The A/D converter has the following features.

  • Page 654: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.3 Configuration The block diagram of the A/D converter is shown below. Figure 14-1. Block Diagram of A/D Converter REF0 ANI0 Sample & hold circuit ADA0CE bit ANI1 ANI2 Voltage comparator & Compare voltage...
  • Page 655 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) The SAR compares the voltage value of the analog input signal with the output voltage of the compare voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB).
  • Page 656 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AV and AV and generates a voltage for REF0 comparison with the analog input signal. (13) ANI0 to ANI9 pins These are analog input pins for the 10 A/D converter channels and are used to input analog signals to be converted into digital signals.

  • Page 657: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used.
  • Page 658 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (2/2) Trigger mode specification ADA0TMD Software trigger mode External trigger mode/timer trigger mode ADA0EF A/D converter status display A/D conversion stopped A/D conversion in progress Cautions 1. Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
  • Page 659 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this bit to 00H.
  • Page 660 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER Table 14-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) ADA0FR3 to A/D Conversion Time ADA0FR0 Stabilization Time + 50MHz 48 MHz 32 MHz 24 MHz Bits Conversion Time + Wait Time μ...
  • Page 661 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER Table 14-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0FR3 to A/D Conversion Time ADA0FR0 Conversion Time 50MHz 48 MHz 32 MHz 24 MHz Bits (+ Stabilization Time) μ...
  • Page 662 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
  • Page 663 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (4) Analog input channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units.
  • Page 664 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, the ADA0CRn register is used for 16-bit access and the ADA0CRnH register for 8-bit access.
  • Page 665 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANIn) and the A/D conversion result (ADA0CRn register) is as follows. × 1,024 + 0.5) SAR = INT ( REF0 = SAR × 64...
  • Page 666 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
  • Page 667 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.

  • Page 668: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.5 Operation 14.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.

  • Page 669: Conversion Operation Timing

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.5.2 Conversion operation timing Figure 14-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Second conversion Setup Sampling A/D conversion Wait Setup...

  • Page 670: Trigger Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.5.3 Trigger mode The timing of starting the conversion operation is specified by setting the trigger mode. The trigger mode includes the software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
  • Page 671 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI9) specified by the ADA0S register is started by the compare match interrupt request signal (INTTAA2CC0 or INTTAA2CC1) of the capture/compare register connected to the timer.

  • Page 672: Operation Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.5.4 Operation mode Four operation modes are available as the modes in which to set the ANIn pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits.
  • Page 673 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER Figure 14-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3...
  • Page 674 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (3) One-shot select mode In this mode, the voltage of one analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
  • Page 675 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER Figure 14-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4...

  • Page 676: Power-Fail Compare Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter).
  • Page 677 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
  • Page 678 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER Figure 14-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1...
  • Page 679 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
  • Page 680 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER Figure 14-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data ANI1 Data Data ANI2 ANI3 Data Data 1 Data 2...

  • Page 681: Cautions

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI9 pins Input the voltage within the specified range to the ANI0 to ANI9 pins.
  • Page 682 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
  • Page 683 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (7) AV REF0 (a) The AV pin is used as the power supply pin of the A/D converter and also supplies power to the alternate- REF0 function ports. In an application where a backup power supply is used, be sure to supply the same potential as to the AV pin as shown in Figure 14-15.
  • Page 684 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (10) Standby mode Because the A/D converter stops operating in the STOP mode, the conversion results are invalid, so power consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion results after the STOP mode is released are invalid.

  • Page 685: How To Read A/D Converter Characteristics Table

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER 14.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
  • Page 686 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
  • Page 687 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale − 3/2 LSB). Figure 14-19. Full-Scale Error...
  • Page 688 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 14 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.

  • Page 689: Chapter 15 Asynchronous Serial Interface C (Uartc)

    CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) In the V850ES/JE3-E, asynchronous serial interface C (UARTC) is provided with 3 channels, and in the V850ES/JF3-E and V850ES/JG3-E,UARTC is provided with 4 channels. 15.1 Features Transfer rate: 300 bps to 3.125 Mbps (using internal system clock of 24 MHz and dedicated baud rate generator)

  • Page 690: Configuration

    UCnOPT0 UCnCTL2 Internal bus Note UARTC0 only Remarks 1. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) 2. For the configuration of the baud rate generator, see Figure 15-18. UARTCn includes the following hardware.
  • Page 691 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (1) UARTCn control register 0 (UCnCTL0) The UCnCTL0 register is an 8-bit register used to specify the UARTCn operation. (2) UARTCn control register 1 (UCnCTL1) The UCnCTL1 register is an 8-bit register used to select the input clock for the UARTCn.

  • Page 692: Mode Switching Between Uartc And Other Serial Interfaces

    15.3 Mode Switching Between UARTC and Other Serial Interfaces 15.3.1 Mode switching between UARTC0 and CSIF2 In the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E, UARTC0 and CSIF2 share the same pin and therefore cannot be used simultaneously. Set UARTC0 in advance, using the PMC3, PFC3 and PFCE3 registers, before use.

  • Page 693: Mode Switching Between Uartc1, Csif1 And I 2 C00

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 15.3.2 Mode switching between UARTC1, CSIF1 and I In the V850ES/JF3-E and V850ES/JG3-E, UARTC1, CSIF1 and I C00 share the same pin, so these functions cannot be used simultaneously. Set UARTC1 in advance, using the PMC2, PFC2 and PFCE2 registers.

  • Page 694: C02, And Can0

    15.3.3 Mode switching between UARTC2, I C02, and CAN0 μ μ In the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E, UARTC2, I C02, and CAN0 ( PD70F3829, PD70F3833 and 70F3837 only) share the same pin and therefore cannot be used simultaneously. Set UARTC2 in advance, using the PMC3, PFC3, and PFCE3 registers, before use.

  • Page 695: Mode Switching Between Uartc3, Csif0, And I 2 C01

    CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 15.3.4 Mode switching between UARTC3, CSIF0, and I In the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E, UARTC3, CSIF0, and I C01 share the same pin and therefore cannot be used simultaneously. Set UARTC3 in advance, using the PMC4, PFC4, and PFCE4 registers, before use.

  • Page 696: Registers

    UCnRXE bit to 1 again. Otherwise, initialization may not be executed (for the base clock, see 15.7 (1) (a) Base clock). Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 697 This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the UCnRXE bit = 0. Remarks 1. For details of parity, see 15.6.9 Parity types and operations. 2. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) (2) UARTCn control register 1 (UCnCTL1) For details, see 15.7 (2) UARTCn control register 1 (UCnCTL1).
  • Page 698 • Set the UCnSTT bit after setting the UCnPWR bit = UCnTXE bit = 1. Caution Do not set the UCnSRT and UCnSTT bits (to 1) during SBF reception (UCnSRF bit = 1). Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 699 • The input level of the RXDCn pin can be inverted using the UCnRDL bit. • This register can be set when the UCnPWR bit = 0 or the UCnRXE bit = 0. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 700 • If transmitting or receiving in the LIN communication format, set the UCnEBE to 0. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) The following shows the relationship between the register setting value and the data format.
  • Page 701 Other than 00 Data Data Parity Stop Stop Remarks 1. Data: Data bit Stop: Stop bit Parity: Parity bit 2. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 702 • UCnCTL0.UCnPWR = 0 • UCnCTL0.UCnTXE = 0 UCnTSF bit • 0 write UCnPE, UCnFE, UCnOVE bits • UCnCTL0.UCnRXE = 0 Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 703 • The UCnOVE bit can be both read and written, but it can only be cleared by writing 0 to it. When 1 is written to this bit, the value is retained. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 704 (b) Character length 9-bit (UCnOPT1.UCnEBE = 1) After reset: 01FFH Address: UC0RX FFFFFA06H, UC1RX FFFFFA16H, UC2RX FFFFFA26H, UC3RX FFFFFA36H UCnRX Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 705 (b) Character length 9-bit (UCnOPT1.UCnEBE = 1) After reset: 01FFH Address: UC0TX FFFFFA08H, UC1TX FFFFFA18H, UC2TX FFFFFA28H, UC3TX FFFFFA38H UCnTX Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 706: Interrupt Request Signals

    If transmit data is transferred from the UCnTX register to the UARTCn transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 707: Operation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 15.6 Operation 15.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-10, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
  • Page 708 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) Figure 15-10. UARTC Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H...

  • Page 709: Sbf Transmission/Reception Format

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 15.6.2 SBF transmission/reception format The V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E have an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
  • Page 710 5. Check-sum field distinctions are made by software. UARTC is initialized following CSF reception, and the processing for setting the SBF reception mode again is performed by software. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 711: Sbf Transmission

    Transmission is suspended until the data to be transmitted next is written to the UCnTX register, or until the SBF transmission trigger (UCnSTT bit) is set. Figure 15-9. SBF Transmission Stop TXDCn INTUCnT interrupt Setting of UCnSTT bit Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 712: Sbf Reception

    (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) RXDCn 10.5 UCnSRF INTUCnR interrupt Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 713: Uart Transmission

    Write of the next transmit data to the UCnTX register is enabled after the INTUCnT signal is generated. Figure 15-11. UART Transmission TXDCn Start Parity Stop INTUCnT Remarks 1. LSB first 2. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 714: Continuous Transmission Procedure

    Figure 15-12. Continuous Transmission Processing Flow Start Register settings UCnTX write Occurrence of transmission interrupt? Required number of writes performed? Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 715 Data (n – 1) Data (n) Transmission Data (n – 1) Data (n) shift register INTUCnT UCnTSF UCnPWR or UCnTXE bit Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 716: Uart Reception

    INTUCnR is output following reception completion. Figure 15-14. UART Reception RXDCn Start Parity Stop INTUCnR UCnRX Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 717 (UCnRMK) of the interrupt control register (UCnRIC), clear (0) the UCnPWR bit or UCnRXE bit, and then clear the interrupt request flag (UCnRIF) of the UCnRIC register. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 718: Reception Errors

    Error processing Caution When an INTUCnR signal is generated, the UCnSTR register must be read to check for errors. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 719 Caution If a receive error interrupt occurs during continuous reception, read the contents of the UCnSTR register must be read before the next reception is completed, then perform error processing. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 720: Parity Types And Operations

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) 15.6.9 Parity types and operations Caution When using the LIN function, fix the UCnCTL0.UCnPS1 and UCnCTL0.UCnPS0 bits to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.

  • Page 721: Receive Data Noise Filter

    RXDCn Internal signal C Match LD_EN detector Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) Figure 15-17. Timing of RXDCn Signal Judged as Noise Base clock RXDCn (input) Internal signal A Internal signal B...

  • Page 722: Dedicated Baud Rate Generator

    UCnCTL2: UCnCKS3 to UCnCKS0 UCnBRS7 to UCnBRS0 Note Only UARTC0 is valid; setting UARTC1 to UARTC3 is prohibited. Remarks 1. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) 2. f Main clock frequency 3. f...
  • Page 723 Setting prohibited Note Only UARTC0 is valid; setting UARTC1 to UARTC3 is prohibited. Remarks 1. f : Main clock frequency 2. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 724 UCLK /254 UCLK /255 UCLK Remarks 1. f : Clock frequency selected by the UCnCTL1.UCnCKS3 to UCLK UCnCTL1.UCnCKS0 bits 2. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 725 2. The baud rate error during reception must satisfy the range indicated in (5) Allowable baud rate range during reception. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 726 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) To set the baud rate, perform the following calculation for setting the UCnCTL1 and UCnCTL2 registers (when using internal clock). <1> Set k to fxx/2/(2 × target baud rate) and m to 0.
  • Page 727 −4.00 2500000 0.00 Setting prohibited Setting prohibited 3000000 4.17 0.00 Remark f Main clock frequency ERR: Baud rate error (%) n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 728 FLmax Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) As shown in Figure 15-19, the receive data latch timing is determined by the counter set using the UCnCTL2 register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing.
  • Page 729 (k). The higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: Set value of UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits 3. n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 730 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (6) Transfer rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.

  • Page 731: Cautions

    However, the reception side initializes the timing by detecting the start bit, so the reception result is not affected. Remark n = 0, 2, 3 (V850ES/JE3-E) n = 0 to 3 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 732: Chapter 16 Clocked Serial Interface F (Csif)

    SIFn: Serial data input SCKFn: Serial clock I/O Transmission mode, reception mode, and transmission/reception mode specifiable Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 733: Configuration

    CCLK Main clock frequency Count clock of the baud rate generator BRGm n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) m = 1 (n = 0, 1) m = 2 (n = 2, 3)

  • Page 734: Mode Switching Between Csif And Other Serial Interfaces

    16.3.1 Switching between CSIF0, UARTC3, and I C01 mode In the V850ES/JE3-E V850ES/JF3-E and V850ES/JG3-E, CSIF0, UARTC3, and I C01 share the same pin, so these functions cannot be used simultaneously. Set CSIF0 in advance, using the PMC4, PFC4, and PFCE4 registers.

  • Page 735: Mode Switching Between Csif1, Uartc1, And I 2 C00

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.3.2 Mode switching between CSIF1, UARTC1, and I In the V850ES/JF3-E and V850ES/JG3-E, CSIF1, UARTC1, and I C00 share the same pin and therefore cannot be used simultaneously. Set UARTC1 and I C00 in advance, using the PMC2, PFC2 and PFCE2 registers, before use.

  • Page 736: Mode Switching Between Csif2 And Uartc0

    CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.3.3 Mode switching between CSIF2 and UARTC0 In the V850ES/JE3-E V850ES/JF3-E and V850ES/JG3-E, CSIF2 and UARTC0 share the same pin and therefore cannot be used simultaneously. Set CSIF2 and UARTC0 in advance, using the PMC3, PFC3, and PFCE3 registers, before use.

  • Page 737: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.4 Registers The following registers are used to control CSIFn. • CSIFn receive register (CFnRX) • CSIFn transmit register (CFnTX) • CSIFn control register 0 (CFnCTL0) • CSIFn control register 1 (CFnCTL1) •...
  • Page 738 CF2RX FFFFFD24H, CF3RX FFFFFD34H, CF4RX FFFFFD44H CFnRX Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) (2) CSIFn transmit data register (CFnTX) The CFnTX register is a 16-bit buffer register used to write the CSIFn transfer data.
  • Page 739 Caution To forcibly suspend transmission/reception, clear the CFnPWR bit to 0 instead of the CFnRXE and CFnTXE bits. At this time, the clock output is stopped. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 740 Note These bits can only be rewritten when the CFnPWR bit = 0. However, the CFnPWR can be set to 1 at the same time as these bits are rewritten. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 741 Caution Be sure to clear bits 3 and 2 to “0”. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 742 2. If n is 1 to 3, set the communication clock (f ) to 5 MHz or lower. CCLK Remarks 1. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) 2. When n = 0 or 1, m = 1...
  • Page 743 × × × 16 bits Remarks 1. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) 2. If the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the LSB of the CFnTX and CFnRX registers.
  • Page 744 Insertion of 0 (ii) Transfer bit length = 12 bits, LSB first SIFn SOFn Insertion of 0 Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 745 • Read this bit even if reading the reception data is not required. • The CFnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.

  • Page 746: Interrupt Request Signals

    CFnTX register and, as soon as writing to CFnTX has been enabled, the transmission enable interrupt request signal is generated. In the single transmission and single transmission/reception modes, the INTCFnT interrupt is not generated. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 747: Operation

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 748 INTCFnR signal is generated. (8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 749: Single Transfer Mode (Master Mode, Reception Mode)

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 750 (9) Read the CFnRX register. (10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 751: Single Transfer Mode (Master Mode, Transmission/Reception Mode)

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 752 (9) Read the CFnRX register. (10) To end transmission/reception, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 753: Single Transfer Mode (Slave Mode, Transmission Mode)

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 754 (8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.

  • Page 755: Single Transfer Mode (Slave Mode, Reception Mode)

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 756 (9) Read the CFnRX register. (10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 757: Single Transfer Mode (Slave Mode, Transmission/Reception Mode)

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 758 (9) Read the CFnRX register. (10) To end transmission/reception, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 759: Continuous Transfer Mode (Master Mode, Transmission Mode)

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 760 = 0 after checking that the CFnTSF bit = 0. Caution In continuous transmission mode, the reception completion interrupt request signal (INTCFnR) is not generated. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 761: Continuous Transfer Mode (Master Mode, Reception Mode)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (f ) = f /2 or f /3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =...
  • Page 762 Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 763 (13) To release the reception enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.

  • Page 764: Continuous Transfer Mode (Master Mode, Transmission/Reception Mode)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (f ) = f /2 or f /3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =...
  • Page 765 Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 766 (9) When a new transmit data is written to the CFnTX register before communication completion, the next communication is started following communication completion. (10) Read the CFnRX register. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 767 (15) To release the transmission/reception enable status, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.

  • Page 768: Continuous Transfer Mode (Slave Mode, Transmission Mode)

    Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 769 = 0 after checking that the CFnTSF bit = 0. Caution In continuous transmission mode, the reception completion interrupt request signal (INTCFnR) is not generated. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 770: Continuous Transfer Mode (Slave Mode, Reception Mode)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (f ) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer CCLK data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
  • Page 771 Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 772 (13) To release the reception enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.

  • Page 773: Continuous Transfer Mode (Slave Mode, Transmission/Reception Mode)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00), communication clock (f ) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer CCLK data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
  • Page 774 Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 775 CFnTX register is enabled, the INTCFnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CFnTX register. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 776 (15) To release the transmission/reception enable status, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.

  • Page 777: Reception Error

    (CFnSTR.CFnOVE) is set to 1. The receive data is overwritten. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 778: Clock Timing

    INTCFnR signal, the written data is not transferred because the CFnTSF bit is set to 1. Use the continuous transfer mode, not the single transfer mode, for such applications. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 779 INTCFnR signal, the written data is not transferred because the CFnTSF bit is set to 1. Use the continuous transfer mode, not the single transfer mode, for such applications. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 780: Output Pins

    Remarks 1. The output level of the SCKFn pin changes if any of the CFnCTL1.CFnCKP or CFnCKS2 to CFnCKS0 bits is rewritten. 2. n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) (2) SOFn pin When CSIFn operation is disabled (CFnPWR bit = 0), the SOFn pin output status is as follows.

  • Page 781: Baud Rate Generator

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) 16.8 Baud Rate Generator The BRG1 to BRG4 baud rate generators are connected to CSIF0 to CSIF4 as shown in the following block diagram. BRG1 BRG1 CSIF0 CSIF1 BRG2 BRG2...

  • Page 782: Baud Rate Generation

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 16 CLOCKED SERIAL INTERFACE F (CSIF) (2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3) The PRSCM1 to PRSCM4 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H.

  • Page 783: Cautions

    Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode is recommended especially when using DMA. Remark n = 0, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E) n = 0 to 4 (V850ES/JG3-E) R01UH0232EJ0100 Rev.

  • Page 784: Chapter 17 I C Bus

    Since SCL0n and SDA0n pins are used for N-ch open-drain outputs, I C0n requires pull-up resistors for the serial clock line and the serial data bus line. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 785: Configuration

    IIC flag register n register m (OCKSm) register n (IICCLn) register n (IICXn) (IICFn) Internal bus Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) m = 0, 1 R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 786 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 17 I C BUS A serial bus configuration example is shown below. Figure 17-2. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1...
  • Page 787 This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 788 However, the bus status cannot be detected immediately after operation, so set the bus status detector to the initial status by using the IICFn.STCENn bit. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 789: C Bus And Other Serial Interfaces

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 17 I C BUS 17.3 Mode Switching of I C Bus and Other Serial Interfaces 17.3.1 Mode switching between I C00, CSIF1, and UARTC1 In the V850ES/JF3-E and V850ES/JG3-E, I C00, CSIF1, and UARTC1 share the same pin and therefore cannot be used simultaneously.

  • Page 790: C01, Csif0, And Uartc3

    C BUS 17.3.2 Mode switching between I C01, CSIF0, and UARTC3 In the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E, I C01, CSIF0, and UARTC3 share the same pin and therefore cannot be used simultaneously. Switching among I C01, CSIF0, and UARTC3 must be set in advance, using the PMC4, PFC4, and PFCE4 registers.

  • Page 791: C02, Uartc2, And Can0

    C BUS 17.3.3 Mode switching between I C02, UARTC2, and CAN0 μ In the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E, I C02, UARTC2, and CAN0 ( PD70F3829, 70F3833, 70F3837 only) share the same pin and therefore cannot be used simultaneously. Switching among I C02, UARTC2, and CAN0 must be set in advance, using the PMC3, PFC3, and PFCE3 registers.

  • Page 792: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 17 I C BUS 17.4 Registers C0n is controlled by the following registers. • IIC control register n (IICCn) • IIC status register n (IICSn) • IIC flag register n (IICFn) • IIC clock select register n (IICCLn) •...
  • Page 793 Cn operation, immediately set the LRELn bit to 1 with a bit manipulation instruction. Remarks 1. The LRELn and WRELn bits are 0 when read after the data has been set. 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 794 • Cleared by instruction • Set by instruction • After reset Note This flag’s signal is invalid when the IICEn bit = 0. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 795 • When the IICEn bit = 0 (operation stop) • After reset Remarks 1. The STTn bit is 0 if it is read immediately after data setting. 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 796 TRCn bit is 1, the TRCn bit is cleared to 0 and the SDA0n line is set to high impedance. Remarks 1. The SPTn bit is 0 if it is read immediately after data setting. 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 797 Note This bit is also cleared when a bit manipulation instruction is executed for another bit in the IICSn register. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 798 Note The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when the WRELn bit is set to 1 and the wait state is canceled to 0 at the ninth clock by TRCn bit = 1. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 799 • When the IICEn bit changes from 1 to 0 (operation stop) • After reset Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 800 C0n is disabled (IICCn.IICEn bit = 0). After operation is enabled, IICFn can be read. Reset sets these registers to 00H. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 801 3. Write the IICRSVn bit only when operation is stopped (IICEn bit = 0). Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 802 Caution Be sure to clear bits 7 and 6 to “0”. Remarks 1. When the IICCn.IICEn bit = 0, 0 is read when reading the CLDn and DADn bits. 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev.
  • Page 803 After reset: 00H Address: IICX0 FFFFFD85H, IICX1 FFFFFD95H, IICX2 FFFFFDA5H < > IICXn CLXn Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) (6) I C0n transfer clock setting method The I C0n transfer clock frequency (f ) is calculated using the following expression.
  • Page 804 (OCKSm = 13H) fxx/120 40.00 MHz ≤ fxx ≤ 41.90 MHz 333.33 kHz to 349.17 kHz − − − − Other than above Setting prohibited Remarks 1. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) m = 0, 1 2. ×: don’t care R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 805 Selection of I Cn division clock Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) (8) IIC shift registers n (IICn) The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock.
  • Page 806 IICSn.STDn bit = 1 (start condition detection). Reset sets these registers to 00H. After reset: 00H Address: SVA0 FFFFFD83H, SVA1 FFFFFD93H, SVA2 FFFFFDA3H SVAn Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 807: I C Bus Mode Functions

    SCL0n SCL0n Clock output (Clock output) (Clock input) Clock input SDA0n SDA0n Data output Data output Data input Data input Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 808: I C Bus Definitions And Control Methods

    The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n pin’s low-level period can be extended and a wait state can be inserted (n = 0 to 2). Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 809: Start Condition

    = 1). When a start condition is detected, the IICSn.STDn bit is set (1). Caution When the IICCn.IICEn bit of the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E is set to 1 while other devices are communicating, the start condition may be detected depending on the status of the communication line.

  • Page 810: Addresses

    Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) An address is output when the slave address and the transfer direction described in 17.6.3 Transfer direction specification are written together to the IICn registers as eight bits of data.

  • Page 811: Transfer Direction Specification

    INTIICn Note The INTIICn signal is generated if a local address or extension code is received during slave device operation. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 812: Ack

    R/W ACK SDA0n Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) When the local address is received, ACK is automatically generated regardless of the value of the ACKEn bit. No ACK is generated if an address other than the local address is received (NACK).

  • Page 813: Stop Condition

    A stop condition is generated when serial transfer from the master device to the slave device has been completed. When the V850ES/JE3-E, V850ES/JF3-E, and V850ES/JG3-E is used as the slave device, it can detect the stop condition. Figure 17-12. Stop Condition...

  • Page 814: Wait State

    IICCn.WRELn bit is set to 1. IICn SCL0n ACKEn Transfer lines Wait state Wait state from master from slave SCL0n SDA0n Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 815 SDA0n Generate according to previously set ACKEn bit value Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) A wait state may be automatically generated depending on the setting of the IICCn.WTIMn bit. Normally, the receiving side cancels the wait state when the IICCn.WRELn bit is set to 1 or when FFH is written to the IICn register and the transmitting side cancels the wait state when data is written to the IICn register.

  • Page 816: Wait State Cancellation Method

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 17 I C BUS 17.6.7 Wait state cancellation method In the case of I C0n, a wait state can be canceled normally in the following ways. • By writing data to the IICn register • By setting the IICCn.WRELn bit to 1 (wait state cancellation) •...

  • Page 817: I C Interrupt Request Signals (Intiicn)

    Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 SPTn bit = 1 ↓...
  • Page 818 Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 STTn bit = 1 SPTn bit = 1 ↓...
  • Page 819 Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 SPTn bit = 1 ↓...

  • Page 820: Slave Device Operation (When Receiving Slave Address Data (Address Match))

    Remarks 1. : Always generated Δ: Generated only when IICCn.SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 AD6 to AD0 D7 to D0 D7 to D0 Δ4...
  • Page 821 : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 (after restart, address match) AD6 to AD0...
  • Page 822 : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 (after restart, extension code reception) AD6 to AD0...
  • Page 823 : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 (after restart, address mismatch (= not extension code))

  • Page 824: Slave Device Operation (When Receiving Extension Code)

    Remarks 1. : Always generated Δ: Generated only when IICCn.SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 AD6 to AD0 D7 to D0 D7 to D0 Δ5...
  • Page 825 : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 (after restart, address match) AD6 to AD0...
  • Page 826 : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 (after restart, extension code reception) AD6 to AD0...

  • Page 827: Operation Without Communication

    : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 (after restart, address mismatch (= not extension code))

  • Page 828: Arbitration Loss Operation (Operation As Slave After Arbitration Loss)

    Remarks 1. : Always generated Δ: Generated only when IICCn.SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 AD6 to AD0 D7 to D0 D7 to D0 Δ4...
  • Page 829 Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 AD6 to AD0 D7 to D0 D7 to D0 Δ5...

  • Page 830: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)

    Remarks 1. : Always generated Δ: Generated only when IICCn.SPIEn bit = 1 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) (2) When arbitration loss occurs during transmission of extension code AD6 to AD0...
  • Page 831 Δ 3: IICSn register = 00000001B Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 AD6 to AD0...
  • Page 832 : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. Dn = D6 to D0 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> Extension code AD6 to AD0...
  • Page 833 Δ 2: IICSn register = 01000001B Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 834 Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 IICCn.STTn bit = 1 ↓...
  • Page 835 Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 STTn bit = 1 ↓...
  • Page 836 Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) <2> When WTIMn bit = 1 IICCn.SPTn bit = 1 ↓...

  • Page 837: Interrupt Request Signal (Intiicn) Generation Timing And Wait Control

    Remarks 1. The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) (1) During address transmission/reception •...
  • Page 838 When an 8-clock wait has been selected (WTIMn bit = 0), whether or not ACK has been generated must be determined prior to wait cancellation. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) (5) Stop condition detection The INTIICn signal is generated when a stop condition is detected.

  • Page 839: Address Match Detection Method

    Remarks 1. For the expansion codes other than the above, see I C bus specifications issued by NXP. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 840: Arbitration

    Figure 17-14. Arbitration Timing Example Master 1 Hi-Z SCL0n Hi-Z SDA0n Master 1 loses arbitration Master 2 SCL0n SDA0n Transfer lines SCL0n SDA0n Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 841: Wakeup Function

    However, when a stop condition is detected, the IICCn.SPIEn bit is set regardless of the wakeup function, and this determines whether INTIICn signal is enabled or disabled. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 842: Communication Reservation

    The wait periods, which should be set via software, are listed in Table 17-6. These wait periods can be set by the SMCn, CLn1, and CLn0 bits of the IICCLn register and the IICXn.CLXn bit. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 843 × /10 (OCKSm = 13H) 100 clocks Remarks 1. m = 0, 1 n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) 2. × = don’t care The communication reservation timing is shown below. R01UH0232EJ0100 Rev. 1.00...
  • Page 844 INTIICn STDn SCL0n SDA0n Generated by master with bus access Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) STTn: Bit of IICCn register STDn: Bit of IICSn register SPDn: Bit of IICSn register Communication reservations are accepted via the following timing.
  • Page 845 IICn register write operation Note The communication reservation operation executes a write to the IICn register when a stop condition interrupt request occurs. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 846: When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)

    × 30 clocks × 40 clocks × 50 clocks 10 clocks Remarks 1. ×: don’t care 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) m = 0, 1 R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...

  • Page 847: Cautions

    (3) When the IICCn.IICEn bit of the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E is set to 1 while other devices are communicating, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.

  • Page 848: Communication Operations

    The actual communication is performed in the communication processing, and includes arbitration with other masters data as well as transmission/reception with the slave. (3) Slave operation An example of when the V850ES/JE3-E, V850ES/JF3-E, or V850ES/JG3-E is used as the slave of the I C0n bus is shown below.

  • Page 849: Master Operation In Single Master System

    Remarks 1. For the transmission and reception formats, comply with the specifications of the communicating product. 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) m = 0, 1 R01UH0232EJ0100 Rev. 1.00...

  • Page 850: Master Operation In Multimaster System

    I C0n bus (SCL0n, SDA0n pins = high level) by referring to the specifications of the communicating product. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) m = 0, 1 R01UH0232EJ0100 Rev. 1.00...
  • Page 851 STCFn = 0? INTIICn interrupt occurred? Waiting for bus release EXCn = 1 or COIn =1? Stop condition detection Slave operation Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 852 Remarks 1. For the transmission and reception formats, comply with the specifications of the communicating product. 2. When using the V850ES/JE3-E, V850ES/JF3-E, or V850ES/JG3-E as the master in a multimaster system, read the IICSn.MSTSn bit for each INTIICn interrupt occurrence to confirm the arbitration result.

  • Page 853: Slave Operation

    (3) Communication direction flag This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 854 After that, the master device generates the stop condition or restart condition. This causes exit from communications. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 855 Clear ready flag Clear ready flag ACKDn = 1? Clear communication mode flag WRELn = 1 Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) m = 0, 1 R01UH0232EJ0100 Rev. 1.00 Jun 19, 2012...
  • Page 856 Remarks 1. <1> to <3> above correspond to <1> to <3> in Figure 17-23 Slave Operation Flowchart (2). 2. n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) Figure 17-22. Slave Operation Flowchart (2) INTIICn occurred <1>...

  • Page 857: Timing Of Data Communication

    Data input via the SDA0n pin is captured by the IICn register at the rising edge of the SCL0n pin. The data communication timing is shown below. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 858 Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn. 2. To cancel the slave wait state, write FFH to IICn or set WRELn. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 859 Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn. 2. To cancel the slave wait state, write FFH to IICn or set WRELn. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 860 Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn. 2. To cancel the slave wait state, write FFH to IICn or set WRELn. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 861 Notes 1. To cancel the master wait state, write FFH to IICn or set WRELn. 2. Cancel the wait during a slave transmission by writing to IICn, not by setting WRELn. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 862 Notes 1. To cancel the master wait state, write FFH to IICn or set WRELn. 2. Cancel the wait during a slave transmission by writing to IICn, not by setting WRELn. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...
  • Page 863 2. Cancel the wait during a slave transmission by writing to IICn, not by setting WRELn. 3. When the wait during a slave transmission is canceled by setting WRELn, TRCn is cleared. Remark n = 1, 2 (V850ES/JE3-E) n = 0 to 2 (V850ES/JF3-E and V850ES/JG3-E) R01UH0232EJ0100 Rev. 1.00...

  • Page 864: Chapter 18 Can Controller

    The V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E feature an on-chip 1-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E products with an on-chip CAN controller are as follows. μ...

  • Page 865: Overview Of Functions

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.1.2 Overview of functions Table 18-1 presents an overview of the CAN controller functions. Table 18-1. Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz)

  • Page 866: Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.1.3 Configuration The CAN controller is composed of the following four blocks. (1) Internal bus interface This functional block provides an internal bus interface and means of transmitting and receiving signals between the CAN module and the host CPU.

  • Page 867: Can Protocol

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications.

  • Page 868: Frame Types

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 18-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame...
  • Page 869 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 18-4. Remote Frame Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field...
  • Page 870 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 18-6. Arbitration Field (in Standard Format Mode) Arbitration field (Control field) Identifier (r1) ID28 ....ID18...
  • Page 871 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER <3> Control field The control field sets “DLC” as the number of data bytes in the data field (DLC = 0 to 8). Figure 18-8. Control Field (Arbitration field) Control field (Data field)
  • Page 872 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 18-9. Data Field (Control field)
  • Page 873 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER <6> ACK field The ACK field is used to acknowledge normal reception. Figure 18-11. ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Remark D: Dominant = 0 R: Recessive = 1 •...
  • Page 874 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. • The bus state differs depending on the error status.
  • Page 875 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER • Operation in error status Table 18-6. Operation in Error Status Error Status Operation A node in this status can transmit immediately after a 3-bit intermission. Error active A node in this status can transmit 8 bits after the intermission.

  • Page 876: Error Frame

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.2.4 Error frame An error frame is output by a node that has detected an error. Figure 18-15. Error Frame Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits...

  • Page 877: Overload Frame

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node has not completed the reception operation Note • If a dominant level is detected at the first two bits during intermission •...

  • Page 878: Functions

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.3 Functions 18.3.1 Determining bus priority (1) When a node starts transmission: • During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission: •...

  • Page 879: Can Sleep Mode/Can Stop Mode Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.3.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function puts the CAN controller in waiting mode to achieve low power consumption. The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode by bus operation (the CAN stop mode is controlled by CPU access).
  • Page 880 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification. • Error active • Error passive • Bus-off These types of error states are classified by the values of the C0ERC.TEC7 to C0ERC.TEC0 bits (transmission error counter bits) and the C0ERC.REC6 to C0ERC.REC0 bits (reception error counter bits) as...
  • Page 881 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-13. Types of Error States Type Operation Value of Error Indication of C0INFO Operation Specific to Error State Counter Register • Outputs an active error flag (6 consecutive dominant- Error active Transmission...
  • Page 882 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter counts up immediately after error detection. Table 18-14. Error Counter...
  • Page 883 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (5) Recovery from bus-off state When the CAN module is in the bus-off state, the transmission pins (CTXD0) cut off from the CAN bus always output the recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
  • Page 884 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-17. Recovery from Bus-off State Through Normal Recovery Sequence TEC > FFH »bus-off« »bus-off-recovery-sequence« »error-active« »error-passive« BOFF bit in C0INFO register <1> <2> OPMODE[2:0] in C0CTRL ≠ 00H ≠ 00H register (written by user) <3>...
  • Page 885 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (6) Initializing CAN module error counter register (C0ERC) in initialization mode If it is necessary to initialize the C0ERC and C0INFO registers for debugging or evaluating a program, they can be initialized to the default value by setting the C0CTRL.CCERC bit in the initialization mode. When initialization has been completed, the CCERC bit is automatically cleared to 0.

  • Page 886: Baud Rate Control Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer base clock (f ) that is the CAN module system clock (f ) divided by 1 to 256 (see 18.6 (12)
  • Page 887 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Remark The CAN protocol specification defines the segments constituting the data bit time as shown in Figure 18-19. Figure 18-19. Configuration of Data Bit Time Defined by CAN Specification Data bit time (DBT)
  • Page 888 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (3) Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
  • Page 889 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). • The phase error of the edge is given by the relative position of the detected edge and sync segment.

  • Page 890: Connection With Target System

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.4 Connection with Target System The microcontroller with on-chip CAN controller has to be connected to the CAN bus using an external transceiver. Figure 18-22. Connection to CAN Bus CTXD0 Microcontroller CANL with on-chip...

  • Page 891: Internal Registers Of Can Controller

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.5 Internal Registers of CAN Controller 18.5.1 CAN controller configuration Table 18-15. List of CAN Controller Registers Item Register Name CAN global registers CAN0 global control register (C0GMCTRL) CAN0 global clock selection register (C0GMCS)

  • Page 892: Register Access Type

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.5.2 Register access type Table 18-16. Register Access Types (1/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC000H CAN0 global control register C0GMCTRL 0000H √...
  • Page 893 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (2/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC100H CAN0 message data byte 01 register 00 C0MDATA0100 Undefined √...
  • Page 894 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (3/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC140H CAN0 message data byte 01 register 02 C0MDATA0102 Undefined √...
  • Page 895 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (4/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC180H CAN0 message data byte 01 register 04 C0MDATA0104 Undefined √...
  • Page 896 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (5/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC1C0H CAN0 message data byte 01 register 06 C0MDATA0106 Undefined √...
  • Page 897 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (6/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC200H CAN0 message data byte 01 register 08 C0MDATA0108 Undefined √...
  • Page 898 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (7/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC240H CAN0 message data byte 01 register 10 C0MDATA0110 Undefined √...
  • Page 899 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (8/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC280H CAN0 message data byte 01 register 12 C0MDATA0112 Undefined √...
  • Page 900 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (9/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC2C0H CAN0 message data byte 01 register 14 C0MDATA0114 Undefined √...
  • Page 901 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (10/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC300H CAN0 message data byte 01 register 16 C0MDATA0116 Undefined √...
  • Page 902 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (11/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC340H CAN0 message data byte 01 register 18 C0MDATA0118 Undefined √...
  • Page 903 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (12/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC380H CAN0 message data byte 01 register 20 C0MDATA0120 Undefined √...
  • Page 904 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (13/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC3C0H CAN0 message data byte 01 register 22 C0MDATA0122 Undefined √...
  • Page 905 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (14/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC400H CAN0 message data byte 01 register 24 C0MDATA0124 Undefined √...
  • Page 906 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (15/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC440H CAN0 message data byte 01 register 26 C0MDATA0126 Undefined √...
  • Page 907 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (16/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC480H CAN0 message data byte 01 register 28 C0MDATA0128 Undefined √...
  • Page 908 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-16. Register Access Types (17/17) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ 03FEC4C0H CAN0 message data byte 01 register 30 C0MDATA0130 Undefined √...

  • Page 909: Register Bit Configuration

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.5.3 Register bit configuration Table 18-17. CAN Global Register Bit Configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FEC000H C0GMCTRL (W) Clear GOM...
  • Page 910 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-18. CAN Module Register Bit Configuration (1/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FEC040H C0MASK1L CMID7 to CMID0 03FEC041H CMID15 to CMID8...
  • Page 911 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-18. CAN Module Register Bit Configuration (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FEC05AH C0BRP TQPRS7 to TQPRS0 03FEC05CH C0BTR...
  • Page 912 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-19. Message Buffer Register Bit Configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FECxx0H C0MDATA01m Message data (byte 0) 03FECxx1H Message data (byte 1)

  • Page 913: Registers

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.6 Registers Caution Accessing the CAN controller registers is prohibited in the following statuses. For details, refer to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. • When the CPU operates with the subclock and the main clock oscillation is stopped •...
  • Page 914 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (1) CAN0 global control register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module. (1/2) After reset: 0000H Address: 03FEC000H (a) Read MBON C0GMCTRL EFSD (b) Write C0GMCTRL...
  • Page 915 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) EFSD Bit enabling forced shut down Forced shut down by GOM bit = 0 disabled. Forced shut down by GOM bit = 0 enabled. Caution To request forced shut down, clear the GOM bit to 0 immediately after the EFSD bit has been set to 1.
  • Page 916 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2) CAN0 global clock selection register (C0GMCS) The C0GMCS register is used to select the CAN module system clock. After reset: 0FH Address: 03FEC002H C0GMCS CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP0...
  • Page 917 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (3) CAN0 global automatic block transmission control register (C0GMABT) The C0GMABT register is used to control the automatic block transmission (ABT) operation. (1/2) After reset: 0000H Address: 03FEC006H (a) Read C0GMABT ABTCLR ABTTRG...
  • Page 918 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) (b) Write Set ABTCLR Automatic block transmission engine clear request bit The automatic block transmission engine is in idle status or under operation. Request to clear the automatic block transmission engine. After the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1.
  • Page 919 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (4) CAN0 global automatic block transmission delay register (C0GMABTD) The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT.
  • Page 920 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (5) CAN0 module mask control register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers are used to extend the number of receivable messages in the same message buffer by masking part of the identifier (ID) of a message and invalidating the ID comparison of the masked part.
  • Page 921 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) • CAN0 module mask 3 register (C0MASK3L, C0MASK3H) After reset: Undefined Address: C0MASK3L 03FEC048H, C0MASK3H 03FEC04AH C0MASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1...
  • Page 922 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (6) CAN0 module control register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module. (1/4) After reset: 0000H Address: 03FEC050H (a) Read RSTAT TSTAT C0CTRL CCERC VALID...
  • Page 923 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/4) CCERC Error counter clear bit The C0ERC and C0INFO registers are not cleared in the initialization mode. The C0ERC and C0INFO registers are cleared in the initialization mode. Remarks 1. The CCERC bit is used to clear the C0ERC and C0INFO registers for re-initialization or forced recovery from the bus-off status.
  • Page 924 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (3/4) PSMODE1 PSMODE0 Power save mode No power save mode is selected. CAN sleep mode Setting prohibited CAN stop mode Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored.
  • Page 925 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (4/4) Set PSMODE0 Clear PSMODE0 Setting of PSMODE0 bit PSMODE0 bit is cleared to 0. PSMODE bit is set to 1. Other than above PSMODE0 bit is not changed. Set PSMODE1 Clear PSMODE1 Setting of PSMODE1 bit PSMODE1 bit is cleared to 0.
  • Page 926 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (7) CAN0 module last error information register (C0LEC) The C0LEC register provides the error information of the CAN protocol. After reset: 00H Address: 03FEC052H C0LEC LEC2 LEC1 LEC0 LEC2 LEC1 LEC0 Last CAN protocol error information...
  • Page 927 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (8) CAN0 module information register (C0INFO) The C0INFO register indicates the status of the CAN module. After reset: 00H Address: 03FEC053H C0INFO BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off status bit Not bus-off status (transmit error counter ≤ 255). (The value of the transmit counter is less than 256.) Bus-off status (transmit error counter >...
  • Page 928 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (9) CAN0 module error counter register (C0ERC) The C0ERC register indicates the count value of the transmission/reception error counter. After reset: 0000H Address: 03FEC054H C0ERC REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0...
  • Page 929 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (10) CAN0 module interrupt enable register (C0IE) The C0IE register is used to enable or disable the interrupts of the CAN module. (1/2) After reset: 0000H Address: 03FEC056H (a) Read C0IE CIE5 CIE4...
  • Page 930 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) (b) Write Set CIE5 Clear CIE5 Setting of CIE5 bit CIE5 bit is cleared to 0. CIE5 bit is set to 1. Other than above CIE5 bit is not changed. Set CIE4...
  • Page 931 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (11) CAN0 module interrupt status register (C0INTS) The C0INTS register indicates the interrupt status of the CAN module. After reset: 0000H Address: 03FEC058H (a) Read C0INTS CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 (b) Write...
  • Page 932 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (12) CAN0 module bit rate prescaler register (C0BRP) The C0BRP register is used to select the CAN protocol layer base clock (f ). The communication baud rate is set to the C0BTR register.
  • Page 933 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (13) CAN0 module bit rate register (C0BTR) The C0BTR register is used to control the data bit time of the communication baud rate. Figure 18-24. Data Bit Time Data bit time (DBT) Sync segment...
  • Page 934 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER After reset: 370FH Address: 03FEC05CH C0BTR SJW1 SJW0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 SJW1 SJW0 Length of synchronization jump width 4TQ (default value) TSEG22 TSEG21 TSEG20 Length of time segment 2...
  • Page 935 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (14) CAN0 module last in-pointer register (C0LIPT) The C0LIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored. After reset: Undefined Address: 03FEC05EH...
  • Page 936 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (15) CAN0 module receive history list register (C0RGPT) The C0RGPT register is used to read the receive history list. (1/2) After reset: xx02H Address: 03FEC060H (a) Read RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2...
  • Page 937 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) (b) Write Clear ROVF Setting of ROVF bit ROVF bit is not changed. ROVF bit is cleared to 0. (16) CAN0 module last out-pointer register (C0LOPT) The C0LOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
  • Page 938 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (17) CAN0 module transmit history list register (C0TGPT) The C0TGPT register is used to read the transmit history list. (1/2) After reset: xx02H Address: 03FEC064H (a) Read TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2...
  • Page 939 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) (b) Write Clear TOVF Setting of TOVF bit TOVF bit is not changed. TOVF bit is cleared to 0. (18) CAN0 module time stamp register (C0TS) The C0TS register is used to control the time stamp function.
  • Page 940 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) (a) Read TSLOCK Time stamp lock function enable bit Time stamp lock function stopped. The TSOUT signal toggles each time the selected time stamp capture event occurs. Time stamp lock function enabled.
  • Page 941 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (19) CAN0 message data byte register (C0MDATAxm, C0MDATAym) (x = 0 to 7, y = 01, 23, 45, 67) The C0MDATAxm register is used to store the data of a transmit/receive message, and can be accessed in 8-bit unit.
  • Page 942 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) C0MDATA45m MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 C0MDATA4m MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 C0MDATA5m MDATA5 MDATA5 MDATA5 MDATA5 MDATA5...
  • Page 943 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (20) CAN0 message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB Address: See Table 18-16.
  • Page 944 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (21) CAN0 message configuration register m (C0MCONFm) The C0MCONFm register is used to specify the type of the message buffer and to set a mask. (1/2) After reset: Undefined Address: See Table 18-16.
  • Page 945 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/2) Message buffer assignment bit Message buffer not used. Message buffer used. Caution Be sure to set bits 2 and 1 to “0”. (22) CAN0 message ID register m (C0MIDLm, C0MIDHm) The C0MIDLm and C0MIDHm registers are used to set an identifier (ID).
  • Page 946 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (23) CAN0 message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. (1/3) After reset: 00x000000 Address: See Table 18-16. 000xx000B (a) Read C0MCTRLm (b) Write...
  • Page 947 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2/3) Message buffer transmission request bit No message frame transmitting request that is pending or being transmitted is in the message buffer. The message buffer is holding transmission of a message frame pending or is transmitting a message frame.
  • Page 948 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (3/3) Set TRQ Clear TRQ Setting of TRQ bit TRQ bit is cleared to 0. TRQ bit is set to 1. Other than above TRQ bit is not changed. Caution Even if the TRQ bit is set (1), transmission may not be immediately executed depending on the situation such as when a message is received from another node or when a message is transmitted from the message buffer.

  • Page 949: Bit Set/Clear Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.7 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
  • Page 950 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-26. Bit Status After Bit Setting/Clearing Operations Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Clear 7 Clear 6 Clear 5 Clear 4 Clear 3 Clear 2 Clear 1 Clear 0...

  • Page 951: Can Controller Initialization

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.8 CAN Controller Initialization 18.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the C0GMCS.CCP0 to C0GMCS.CCP3 bits by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.

  • Page 952: Transition From Initialization Mode To Operation Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-27. Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefinition Redefinition completed Execute transmission? Wait for 1 bit of CAN data. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 Cautions 1.

  • Page 953: Resetting Error Counter C0Erc Of Can Module

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-28. Transition to Operation Modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H OPMODE[2:0] = 00H and CAN bus is busy. and CAN bus is busy.

  • Page 954: Message Reception

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.9 Message Reception 18.9.1 Message reception All buffers satisfying the following conditions are searched in all the message buffer areas in all the operation modes in order to store newly receive messages. •...

  • Page 955: Reading Reception Data

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.9.2 Reading reception data If it is necessary to consistently read data from the CAN message buffer by software, follow the recommended procedures shown in Figures 18-49 and 18-50. While receiving a message, the CAN module sets the C0MCTRLm.DN bit two times, at the beginning of the processing to store data in the message buffer and at the end of this storing processing.

  • Page 956: Receive History List Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding C0LIPT register and the receive history list get pointer (RGPT) with the corresponding C0RGPT register.
  • Page 957 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without the RHL being read by the host processor, a complete sequence of receptions can not be recovered.

  • Page 958: Mask Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.9.4 Mask function For some message buffers that are used for reception, whether one of four global reception masks is applied can be selected. Load resulting from comparing message identifiers is reduced by masking some bits, and, as a result, some different identifiers can be received in a buffer.
  • Page 959 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER <3> Mask setting for CAN module 1 (mask 1) (Example) (Using CAN1 address mask 1 registers L and H (C1MASK1L and C1MASK1H)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18...

  • Page 960: Multi Buffer Receive Block Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.

  • Page 961: Remote Frame Reception

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions.

  • Page 962: Message Transmission

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.10 Message Transmission 18.10.1 Message transmission In all the operation modes, if the C0MCTRLm.TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched.
  • Page 963 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER After the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the TRQ bit set to 1 in advance) is transmitted.

  • Page 964: Transmit History List Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer in which each data frame or remote frame was received and stored. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding C0LOPT register, and the transmit history list get pointer (TGPT) with the corresponding C0TGPT register.
  • Page 965 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-32. Transmit History List Transmit history list (THL) Transmit history list (THL) Event: Message buffer 4 - CPU confirms Tx completion Message buffer 3 of message buffer 6, 9, and 2. Last out-...

  • Page 966: Automatic Block Transmission (Abt)

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).
  • Page 967 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Cautions 1. To resume the normal operation mode with ABT from the message buffer 0, set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed.

  • Page 968: Transmission Abort Process

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.10.4 Transmission abort process Remark m = 00 to 31 (1) Transmission abort process other than in normal operation mode with automatic block transmission (ABT) The user can clear the C0MCTRLm.TRQ bit to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful.

  • Page 969: Remote Frame Transmission

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.10.5 Remote frame transmission Remote frames can be transmitted only from transmit message buffers. Set whether a data frame or remote frame is transmitted via the C0MCONFm.RTR bit. Setting (1) the RTR bit sets remote frame transmission.

  • Page 970: Power Saving Modes

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.11 Power Saving Modes 18.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
  • Page 971 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER (2) Status in CAN sleep mode The CAN module is in one of the following states after it enters the CAN sleep mode. • The internal operating clock is stopped and the power consumption is minimized.

  • Page 972: Can Stop Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.11.2 CAN stop mode The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.

  • Page 973: Example Of Using Power Saving Modes

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.

  • Page 974: Interrupt Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.

  • Page 975: Diagnosis Functions And Special Operational Modes

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods.

  • Page 976: Single-Shot Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER In the receive-only mode, no message frames can be transmitted from the CAN module to the CAN bus. Transmit requests issued for message buffers defined as transmit message buffers are held pending. In the receive-only mode, the CAN transmission pin (CTXD0) in the CAN module is fixed to the recessive level.

  • Page 977: Self-Test Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back.

  • Page 978: Transmission/Reception Operation In Each Operation Mode

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.13.4 Transmission/reception operation in each operation mode Table 18-21 shows the transmission/reception operation in each operation mode. Table 18-21. Overview of Transmission/Reception Operation in Each Operation Mode Operation Mode Data Frame/ Error Frame/...

  • Page 979: Time Stamp Function

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have different frequencies).
  • Page 980 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Caution The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer.

  • Page 981: Baud Rate Settings

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.15 Baud Rate Settings 18.15.1 Bit rate setting conditions Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows. (a) 5TQ ≤ SPT (sampling point) ≤ 17 TQ SPT = TSEG1 + 1TQ (b) 8 TQ ≤...
  • Page 982 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-22. Settable Bit Rate Combinations (1/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) DBT Length SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2...
  • Page 983 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-22. Settable Bit Rate Combinations (2/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) DBT Length SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2...
  • Page 984 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-22. Settable Bit Rate Combinations (3/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit: %) DBT Length SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2...

  • Page 985: Representative Examples Of Baud Rate Settings

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.15.2 Representative examples of baud rate settings Tables 18-23 and 18-24 show representative examples of baud rate settings. Table 18-23. Representative Examples of Baud Rate Settings (f = 8 MHz) (1/2) CANMOD Set Baud...
  • Page 986 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-23. Representative Examples of Baud Rate Settings (f = 8 MHz) (2/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Sampling Rate Value Ratio of Register Set...
  • Page 987 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-24. Representative Examples of Baud Rate Settings (f = 16 MHz) (1/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Sampling Rate Value Ratio of Register Set...
  • Page 988 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Table 18-24. Representative Examples of Baud Rate Settings (f = 16 MHz) (2/2) CANMOD Set Baud Division C0BRP Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Sampling Rate Value Ratio of Register Set...

  • Page 989: Operation Of Can Controller

    V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER 18.16 Operation of CAN Controller The processing procedure shown below is recommended to operate the CAN controller. Develop your program by referring to this recommended processing procedure. Remark m = 00 to 31 Figure 18-36.
  • Page 990 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-37. Re-initialization START Clear OPMODE. INIT mode? C0BRP register, Initialize message C0BTR register. buffers. C0IE register. C0ERC and C0INFO register clear? C0MASK register. Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register.
  • Page 991 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-38. Message Buffer Initialization START RDY bit = 1? Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? C0MCONFm register. C0MIDHm register, C0MIDLm register.
  • Page 992 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-39 shows the processing for a receive message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 001B to 101B). Figure 18-39. Message Buffer Redefinition START START Clear VALID bit. C0CTRLCLEAR_VALID =1 RDY = 1? Clear RDY bit.
  • Page 993 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-40 shows the processing for a transmit message buffer during transmission (MT2 to MT0 bits of C0MCONFm register = 000B). Figure 18-40. Message Buffer Redefinition during Transmission START START Transmit abort process Transmit abort process Clear RDY bit.
  • Page 994 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-41 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 18-41. Message Transmit Processing START TRQ bit = 0? Clear RDY bit. Set RDY bit = 0...
  • Page 995 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-42 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 18-42. ABT Message Transmit Processing START START ABTTRG bit = 0? ABTTRG = 0? Clear RDY bit...
  • Page 996 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-43. Transmission via Interrupt (Using C0LOPT Register) Start Transmit completion interrupt servicing Read C0LOPT register. Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0?
  • Page 997 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-44. Transmission via Interrupt (Using C0TGPT Register) START Transmit completion interrupt servicing Read C0TGPT register. TOVF bit = 1? Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0...
  • Page 998 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-45. Transmission via Software Polling START CINTS0 bit = 1? Clear CINTS0 bit. Clear CINTS0 bit = 1 Read C0TGPT register. TOVF bit = 1? Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit.
  • Page 999 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-46. Transmission Abort Processing (Other Than in Normal Operation Mode with ABT) START Clear TRQ bit. Set TRQ bit = 0 Clear TRQ bit = 1 Wait for a period of 11 CAN...
  • Page 1000 V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E CHAPTER 18 CAN CONTROLLER Figure 18-47. Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) START Clear ABTTRG bit. SET_ABTTRG bit = 0 CLEAR_ABTTRG bit = 1 ABTTRG bit = 0? Clear TRQ bit.

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