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Renesas V850ES/JE3-L User Manual

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V850ES/JC3-L, V850ES/JE3-L

32

RENESAS MCU

V850ES/Jx3-L Microcontrollers

V850ES/JC3-L

μPD70F3797

μPD70F3798

μPD70F3799

μPD70F3800

μPD70F3801

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

μPD70F3802

μPD70F3803

μPD70F3804

μPD70F3838

μPD70F3839

User's Manual: Hardware

V850ES/JE3-L

μPD70F3805

μPD70F3806

μPD70F3807

μPD70F3808

μPD70F3840

Rev.0.01

— Preliminary —

Jul, 2010

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Summary of Contents for Renesas V850ES/JE3-L

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 Readers This manual is intended for users who wish to understand the functions of the V850ES/JC3-L, V850ES/JE3-L and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JC3-L, V850ES/JE3-L shown in the Organization below.
Page 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 6 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JC3-L, V850ES/JE3-L Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/JC3-L, V850ES/JE3-L Hardware User’s Manual...
Page 7 Silicon Storage Technology, Inc. IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in the United States of America.
Page 8: Table Of Contents
4.1.1 V850ES/JC3-L (40-pin) ........................89 4.1.2 V850ES/JC3-L (48-pin) ........................89 4.1.3 V850ES/JE3-L ..........................89 Basic Port Configuration......................90 4.2.1 V850ES/JC3-L (40-pin) ........................90 4.2.2 V850ES/JC3-L (48-pin) ........................91 4.2.3 V850ES/JE3-L ..........................92 Port Configuration ........................93 4.3.1 Port 0 ..............................99 4.3.2 Port 1 (V850ES/JC3-L (48-pin), V850ES/JE3-L)................105...
Page 9 6.4.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) ..............267 6.4.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) ............276 6.4.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)..........292 6.4.8 Timer output operations ........................296 Selector (V850ES/JE3-L only) ....................297 Cautions ..........................298...
Page 10 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)..............299 Functions ..........................299 Configuration.......................... 300 7.2.1 Pins used by TMQ0 ........................302 7.2.2 Interrupts............................302 Registers ..........................303 Operations ..........................318 7.4.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) ..............325 7.4.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) .............336 7.4.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .........347 7.4.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) ...........362 7.4.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) ..............372...
Page 11 13.5.4 Operation mode ..........................492 13.5.5 Power-fail compare mode ......................498 13.6 Cautions ..........................505 13.7 How to Read A/D Converter Characteristics Table ............510 CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) ........514 14.1 Functions ..........................514 14.2 Configuration.......................... 515 14.3 Registers ..........................516 14.4 Operation ..........................
Page 12 15.6.1 Data format ...........................535 15.6.2 UART transmission ........................537 15.6.3 Continuous transmission procedure....................538 15.6.4 UART reception ..........................540 15.6.5 Reception errors ...........................542 15.6.6 Parity types and operations......................544 15.6.7 LIN transmission/reception format ....................545 15.6.8 SBF transmission..........................547 15.6.9 SBF reception ..........................548 15.6.10 Receive data noise filter ......................549 15.7 Dedicated Baud Rate Generator...................
Page 13 17.5.1 Pin configuration ...........................636 17.6 I C Bus Definitions and Control Methods ................637 17.6.1 Start condition ..........................637 17.6.2 Addresses .............................638 17.6.3 Transfer direction specification .....................639 17.6.4 ACK ..............................640 17.6.5 Stop condition ..........................641 17.6.6 Wait state............................642 17.6.7 Wait state cancellation method .....................644 17.7 I C Interrupt Request Signals (INTIICn)................
Page 14 19.2.3 NP flag ............................720 19.3 Maskable Interrupts ....................... 721 19.3.1 Operation ............................721 19.3.2 Restoration............................723 19.3.3 Priorities of maskable interrupts....................724 19.3.4 Interrupt control register (xxICn) ....................728 19.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) ................730 19.3.6 In-service priority register (ISPR) ....................732 19.3.7 ID flag ............................733 19.3.8 Watchdog timer mode register 2 (WDTM2)...................733 19.4 Software Exception........................
Page 15 21.7.1 Setting and operation status ......................776 21.7.2 Releasing subclock operation mode .....................780 21.7.3 Releasing low-voltage subclock operation mode ................780 21.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode ..............781 21.8.1 Setting and operation status ......................781 21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode ...............784 CHAPTER 22 RESET FUNCTION......................785 22.1 Overview ..........................
Page 16 28.3 Functional Outline........................821 28.4 Rewriting by Dedicated Flash Memory Programmer ............824 28.4.1 Programming environment......................824 28.4.2 Communication mode ........................825 28.4.3 Flash memory control ........................827 28.4.4 Selection of communication mode ....................828 28.4.5 Communication commands......................829 28.4.6 Pin connection in on-board programming ..................830 28.5 Rewriting by Self Programming....................
Page 17 31.8.7 A/D converter ..........................897 31.8.8 D/A converter ..........................898 31.8.9 LVI circuit characteristics ......................898 31.9 Flash Memory Programming Characteristics ..............899 CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target)........901 32.1 Absolute Maximum Ratings ....................901 32.2 Capacitance ..........................902 32.3 Operating Conditions ......................903 32.4 Oscillator Characteristics......................
Page 18 32.6 DC Characteristics ......................... 907 32.6.1 Pin characteristics.........................907 32.6.2 Supply current characteristics .......................909 32.6.3 Data retention characteristics (in STOP mode)................910 32.7 AC Characteristics ......................... 911 32.7.1 Measurement conditions .......................911 32.7.2 Power on/power off/reset timing....................912 32.8 Peripheral Function Characteristics ..................913 32.8.1 Interrupt timing ..........................913 32.8.2 Key return timing...........................913 32.8.3 Timer timing ..........................913...
Page 19: Chapter 1 Introduction
RENESAS MCU Jul 23, 2010 CHAPTER 1 INTRODUCTION The V850ES/JC3-L and V850ES/JE3-L are one of the products in the Renesas Electronics V850 single-chip microcontroller series designed for low-power operation for real-time control applications. General The V850ES/JC3-L and V850ES/JE3-L are 32-bit single-chip microcontrollers that include the V850ES CPU core and peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter.
Page 20 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JC3-L Product List (1/2) Generic Name V850ES/JC3-L μ μ μ μ μ Part Number PD70F3797 PD70F3798 PD70F3799 PD70F3800 PD70F3838...
Page 21 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JC3-L Product List (2/2) Generic Name V850ES/JC3-L μ μ μ μ μ Part Number PD70F3801 PD70F3802 PD70F3803 PD70F3804 PD70F3839...
Page 22 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JE3-L Product List Generic Name V850ES/JE3-L μ μ μ μ μ Part Number PD70F3805 PD70F3806 PD70F3807 PD70F3808 PD70F3840 Internal...
Page 23: Features
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Features Minimum instruction execution time: 50 ns (operating on main clock (f ) of 20 MHz: V = 2.7 to 3.6 V)
Page 24 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Timer function: 16-bit interval timer M (TMM): 1 channel Note 16-bit timer/event counter P (TMP): 6 channels 16-bit timer/event counter Q (TMQ): 1 channel...
Page 25: Application Fields
64-pin plastic LQFP (fine pitch) (10 × 10) PD70F3808GB-GAH-AX 128 KB μ 64-pin plastic LQFP (fine pitch) (10 × 10) PD70F3840GB-GAH-AX 256 KB Remark The V850ES/JE3-L is a lead-free product. R01UH0018EJ0001 Rev. 0.01 Page 25 of 958 Jul 23, 2010...
Page 26: Pin Configuration (Top View)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Pin Configuration (Top View) • V850ES/JC3-L 40-pin plastic WQFN (6 × 6) μ μ μ PD70F3797K8-4B4-AX PD70F3798K8-4B4-AX PD70F3799K8-4B4-AX μ μ PD70F3800K8-4B4-AX...
Page 27 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION • V850ES/JC3-L 48-pin plastic WQFN (7 × 7) μ μ μ PD70F3801K8-5B4-AX PD70F3802K8-5B4-AX PD70F3803K8-5B4-AX μ μ PD70F3804K8-5B4-AX PD70F3839K8-5B4-AX P99/SCKB1 REF0 exposed die pad...
Page 28 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION • V850ES/JC3-L 48-pin plastic LQFP (fine pitch) (7 × 7) μ μ μ PD70F3801GA-GAM-AX PD70F3802GA-GAM-AX PD70F3803GA-GAM-AX μ μ PD70F3804GA-GAM-AX PD70F3839GA-GAM-AX P99/SCKB1...
Page 29 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION • V850ES/JE3-L 64-pin plastic LQFP (fine pitch) (10 × 10) μ μ μ PD70F3805GB-GAH-AX PD70F3806GB-GAH-AX PD70F3807GB-GAH-AX μ μ PD70F3808GB-GAH-AX PD70F3840GB-GAH-AX P99/SCKB1...
Page 30 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Pin functions ADTRG: A/D trigger input RESET: Reset ANI0 to ANI9: Analog input RTC1HZ, Real-time Counter Clock Output ANO0: Analog output...
Page 31: Function Block Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram (1) V850ES/JC3-L (40-pin) Timer/counter function Note1 Note2 TIP20, TIP50, 16-bit timer/ TIP21, TIP51 event counter P:...
Page 32 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION (2) V850ES/JC3-L (48-pin) Timer/counter function Note1 Note2 TIP00, TIP20, TIP50, 16-bit timer/ TIP21, TIP51 event counter P: TOP00, TOP20, TOP50, 6 ch...
Page 33 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION (3) V850ES/JE3-L Timer/counter function Note1 Note2 TIP00 to TIP20, TIP40, TIP50, 16-bit timer/ TIP00 to TIP51 event counter P: TOP00 to TOP20, TOP40, TOP50,...
Page 34: Internal Units
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing.
Page 35 Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (12) Serial interface The V850ES/JC3-L, V850ES/JE3-L include three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire variable-length serial interface B (CSIB), and an I C bus interface (I (13) A/D converter This 10-bit A/D converter includes 10/6/5 analog input pins.
Page 36 8-bit I/O Serial interface, key interrupt input, timer I/O, external interrupt − 1-bit I/O − 1-bit I/O Table 1-4. Port Functions (V850ES/JE3-L) Port Alternate Function 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset, real-time counter output 1-bit I/O...
Page 37: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTION CHAPTER 2 PIN FUNCTIONS List of Pin Functions The functions of the pins in the V850ES/JC3-L, V850ES/JE3-L are described below. There are 2 or 3 types of pin I/O buffer power supplies: AV , AV , and EV .
Page 38 5 V tolerant. − − INTP3 − Port 1 (refer to 4.3.2) ANO0 1-bit I/O port (V850ES/JC3-L: 48-pin, V850ES/JE3-L only). Input/output can be specified in 1-bit units. − Port 3 (refer to 4.3.3) TXDA0/SOB4 2-bit I/O port (V850ES/JC3-L : 40-pin) −...
Page 39 (40) (48) Port 7 (refer to 4.3.6) ANI0 5-bit I/O port (V850ES/JC3-L : 40-pin) ANI1 6-bit I/O port (V850ES/JC3-L : 48-pin) ANI2 10-bit I/O port (V850ES/JE3-L) ANI3 Input/output can be specified in 1-bit units. ANI4 − ANI5 − − ANI6 −...
Page 40 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION (2) Non-port functions (1/5) Function Description Pin No. Alternate Function JC3L JC3L JE3L (40) (48) ADTRG Input A/D converter external trigger input. 5 V tolerant.
Page 41 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION (2/5) Function Description Pin No. Alternate Function JC3L JC3L JE3L (40) (48) INTP0 Input External interrupt request input P03/ADTRG/RTC1HZ (maskable, analog noise elimination).
Page 42 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION (3/5) Function Description Pin No. Alternate Function JC3L JC3L JE3L (40) (48) − RXDA0 Input Serial receive data input (UARTA0 to UARTA2) P31/INTP7/SIB4 5 V tolerant.
Page 43 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION (4/5) Function Description Pin No. Alternate Function JC3L JC3L JE3L (40) (48) − P32/ASCKA0/SCKB4/TOP00 TIP00 Input External event count input/capture trigger input/external trigger input (TMP0).
Page 44 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION (5/5) Function Description Pin No. Alternate Function JC3L JC3L JE3L (40) (48) TOQ00 Output Timer output (TMQ0) P53/SIB2/KR3/TIQ00/RTP03/DDO N-ch open-drain output selectable.
Page 45: Pin States
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes...
Page 46: Pin I/O Circuit Types, I/O Buffer Power Supplies, And Connection Of Unused Pins
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins (1/2) Alternate Function Pin No. I/O Circuit...
Page 47 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION (2/2) Alternate Function Pin No. Recommended Connection of Unused Pin Circuit JC3L JC3L JE3L Type (40) (48) P70 to P74...
Page 48 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION Figure 2-1. Pin I/O Circuits Type 2 Type 10-N Data P-ch IN/OUT IN/OUT Open drain N-ch Output disable Schmitt-triggered input with hysteresis characteristics...
Page 49: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 2 PIN FUNCTION Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P10/ANO0 pin •...
Page 50: Chapter 3 Cpu Function
V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JC3-L and V850ES/JE3-L are based on RISC architecture and executes almost all instructions in one clock cycle by using a 5-stage pipeline. Features Variable length instructions (16 bits/32 bits)
Page 51: Cpu Register Set
CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/JC3-L and V850ES/JE3-L can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual.
Page 52: Program Register Set
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available.
Page 53: System Register Set
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below.
Page 54 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs.
Page 55 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
Page 56 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU.
Page 57 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
Page 58 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.
Page 59: Operation Modes
Data can be erased and written from/to the flash memory by using a user application program. For details, see CHAPTER 28 FLASH MEMORY. (4) On-chip debug mode The V850ES/JC3-L, V850ES/JE3-L is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications. For details, see CHAPTER 29 ON-CHIP DEBUG FUNCTION.
Page 60: Address Space
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB.
Page 61: Memory Map
V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION 3.4.2 Memory map The areas shown below are reserved in the V850ES/JC3-L, V850ES/JE3-L. Figure 3-2. Data Memory Map (Physical Addresses) F F F F F F F F H Image 63 F C 0 0 0 0 0 0 H...
Page 62 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 0 3 F F F F F F H Use prohibited (program fetch prohibited area)
Page 63: Areas
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION 3.4.3 Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (16 KB) 16 KB are allocated to addresses 00000000H to 00003FFFH in the following versions.
Page 64 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (c) Internal ROM (64 KB) 64 KB are allocated to addresses 00000000H to 0000FFFFH in the following versions. Accessing addresses 00010000H to 000FFFFFH is prohibited.
Page 65 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (e) Internal ROM (256 KB) 256 KB are allocated to addresses 00000000H to 0003FFFFH in the following versions. Accessing addresses 00040000H to 000FFFFFH is prohibited.
Page 66 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (b) Internal RAM (16 KB) 16 KB are allocated to addresses 03FFB000H to 03FFEFFFH in the following versions. Accessing addresses 03FF0000H to 03FFAFFFH is prohibited.
Page 67 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB allocated to physical addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Page 68: Wraparound Of Data Space
Recommended use of address space The architecture of the V850ES/JC3-L, V850ES/JE3-L requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
Page 69 CHAPTER 3 CPU FUNCTION (2) Data space With the V850ES/JC3-L, V850ES/JE3-L, it seems that there are sixty-four 64 MB (26-bit address) physical address spaces on the 4 GB (32-bit address) CPU address space. Therefore, the most significant bit (bit 25) of a 26-bit address of these 64 MB spaces is sign-extended to 32 bits and allocated as an address.
Page 70 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16.
Page 71 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION μ Figure 3-12. Recommended Memory Map ( PD70F3840) Program space Data space F F F F F F F F H...
Page 72: Peripheral I/O Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION 3.4.6 Peripheral I/O registers (1/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note FFFFF004H Port DL register 0000H √...
Page 73 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (2/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF102H Interrupt mask register 1 IMR1 FFFFH √ √...
Page 74 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (3/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF1 Interrupt control register (INTCB0R/INTIIC1) CB0RIC/IICIC1 √ √...
Page 75 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (4/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF218H A/D conversion result register 4 ADA0CR4 Undefined √...
Page 76 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (5/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF422H Port 1 mode register √ FFFFF426H Port 3 mode register FFFFH √...
Page 77 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (6/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF590H TMP0 control register 0 TP0CTL0 √ √...
Page 78 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (7/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF5D6H TMP4 capture/compare register 0 TP4CCR0 0000H √ FFFFF5D8H...
Page 79 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (8/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF870H Clock monitor mode register √ √ FFFFF888H...
Page 80 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (9/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFFADDH RTC control register 0 RC1CC0 √ √...
Page 81 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (10/10) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFD26H CSIB2 transmit data register CB2TX 0000H √ FFFFFD26H...
Page 82: Special Registers
Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JC3-L and V850ES/JE3-L have the following seven special registers. • Power save control register (PSC) • Clock control register (CKC) •...
Page 83 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation.
Page 84 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1).
Page 85 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register.
Page 86: Registers To Be Set First
CHAPTER 3 CPU FUNCTION 3.4.8 Registers to be set first Be sure to set the following registers first when using the V850ES/JC3-L, V850ES/JE3-L. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
Page 87: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION 3.4.9 Cautions (1) Accessing special on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
Page 88 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 3 CPU FUNCTION (2) Conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1>...
Page 89: Chapter 4 Port Functions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS Features 4.1.1 V850ES/JC3-L (40-pin) I/O port pins: 27 • N-ch open-drain output selectable: 20 (5 V tolerant: 17) Input/output specifiable in 1-bit units 4.1.2...
Page 90: Basic Port Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Basic Port Configuration 4.2.1 V850ES/JC3-L (40-pin) The V850ES/JC3-L (40-pin) features a total of 27 I/O port pins organized as ports 0, 3 to 5, 7, 9, CM, and DL. The port configuration is shown below.
Page 91: V850Es/Jc3-L (48-Pin)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS 4.2.2 V850ES/JC3-L (48-pin) The V850ES/JC3-L (48-pin) features a total of 34 I/O port pins organized as ports 0, 1, 3 to 5, 7, 9, CM, and DL. The port configuration is shown below.
Page 92: V850Es/Je3-L
CHAPTER 4 PORT FUNCTIONS 4.2.3 V850ES/JE3-L The V850ES/JE3-L features a total of 50 I/O port pins organized as ports 0, 1, 3 to 5, 7, 9, CM, and DL. The port configuration is shown below. Figure 4-3. Port Configuration (V850ES/JE3-L)
Page 93: Port Configuration
Port n function control expansion register (PFCEn: n = 0, 3, 5, 9 ) Port n function register (PFn: n = 0, 3 to 5, 9) Port pins I/O: 34 Table 4-6. Port Configuration (V850ES/JE3-L) Item Configuration Control registers Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CM, DL)
Page 94 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (1) Port n register (Pn) Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is made up of a port latch that retains the output data and a circuit that reads the pin status.
Page 95 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) PMn specifies the input mode or output mode of the port. Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units.
Page 96 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate functions.
Page 97 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) PFn is a register that specifies normal output (CMOS output) or N-ch open-drain output.
Page 98 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-4. Setting of Each Register and Pin Function Port mode Output mode “0”...
Page 99: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 5-bit port (V850ES/JE3-L) or a 3-bit port (V850ES/JC3-L (40-pin), V850ES/JC3-L (48-pin)) for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-8. Port 0 Alternate-Function Pins Pin No.
Page 100 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (1) Port 0 register (P0) (a) V850ES/JC3-L (40-pin), V850ES/JC3-L (48-pin) After reset: 00H (output latch) Address: FFFFF400H Output data control (in output mode) (n = 2, 3, 5)
Page 101 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) (a) V850ES/JC3-L (40-pin), V850ES/JC3-L (48-pin) After reset: FFH Address: FFFFF420H PM05 PM03 PM02 PM0n...
Page 102 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) (a) V850ES/JC3-L (40-pin), V850ES/JC3-L (48-pin) After reset: 00H Address: FFFFF440H PMC0 PMC05 PMC03...
Page 103 Port 0 alternate function specifications. (6) Port 0 alternate function specifications Note Note Note PFCE04 PFC04 Specification of P04 pin alternate function INTP1 input RTCDIV output RTCCL output Setting prohibited Note V850ES/JE3-L only R01UH0018EJ0001 Rev.0.01 Page 103 of 958 Jul 23, 2010...
Page 104 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS PFCE03 PFC03 Specification of P03 pin alternate function INTP0 input ADTRG input Setting prohibited RTC1HZ output (7) Port 0 function register (PF0)
Page 105: Port 1 (V850Es/Jc3-L (48-Pin), V850Es/Je3-L)
V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 (V850ES/JC3-L (48-pin), V850ES/JE3-L) Port 1 is a 1-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pin. Table 4-9. Port 1 Alternate-Function Pins Pin No.
Page 106: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is a 8-bit port (V850ES/JE3-L) or a 5-bit port (V850ES/JC3-L (48-pin)), a 2-bit port (V850ES/JC3-L (40-pin)) for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins.
Page 107 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) (a) V850ES/JC3-L (40-pin) After reset: 0000H (output latch) Address: FFFFF406H Output data control (in output mode) (n = 0, 1)
Page 108 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2) Port 3 mode register (PM3) (a) V850ES/JC3-L (40-pin) After reset: FFFFH Address: FFFFF426H PM3L PM31 PM30 PM3n I/O mode control (n = 0, 1)
Page 109 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) (1/2) (a) V850ES/JC3-L (40-pin) After reset: 0000H Address: FFFFF446H PMC3L PMC31 PMC30 PMC31...
Page 110 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2/2) (c) V850ES/JE3-L After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H PMC3 (PMC3H) PMC39 PMC38 (PMC3L) PMC35 PMC34...
Page 111 3. To read/write bits 8 to 15 of the PFC3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC3H register. (5) Port 3 function control expansion register L (PFCE3L) (V850ES/JC3-L (48-pin), V850ES/JE3-L) After reset: 00H...
Page 112 Notes1. V850ES/JC3-L (48-pin), V850/JE3-L only 2. V850ES/JE3-L only 3. INTP7 and RXDA0 are alternate functions. When using the pin for RXDA0, disable edge detection for INTP7 (clear the INTF3.INTF31 bit and the INTR3.INTR31 bit to 0). When using the pin for INTP7, stop UARTA0 reception (clear the UA0CTL0.UA0RXE bit to 0).
Page 113 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) (a) V850ES/JC3-L (40-pin) After reset: 0000H Address: FFFFFC66H PF3L PF31 PF30 PF3n Specification of normal output (CMOS output) or N-ch open-drain output (n = 0, 1)
Page 114: Port 4
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins.
Page 115 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 Specification of pin operation...
Page 116: Port 5
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins.
Page 117 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2) Port 5 mode register (PM5) After reset: FFH Address: FFFFF42AH PM55 PM54 PM53 PM52 PM51 PM50 PM5n I/O mode control (n = 0 to 5)
Page 118 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) After reset: 00H Address: FFFFF46AH PFC5 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50 Remark For details of alternate function specification, see 4.3.5 (6)
Page 119 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS PFCE52 PFC52 Specification of P52 pin alternate function Setting prohibited Note TIQ03 input/KR2 input TOQ03 input RTP02 output PFCE51 PFC51...
Page 120 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (7) Port 5 function register (PF5) After reset: 00H Address: FFFFFC6AH PF55 PF54 PF53 PF52 PF51 PF50 PF5n Specification of normal output (CMOS output) or N-ch open-drain output (n = 0 to 5)
Page 121: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 7 Port 7 is a 10-bit port (V850ES/JE3-L) or a 6-bit port (V850ES/JC3-L (48-pin)), a 5-bit port (V850ES/JC3-L (40-pin)) for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins.
Page 122 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (1) Port 7 register H, port 7 register L (P7H, P7L) (a) V850ES/JC3-L (40-pin) After reset: 00H (output latch) Address: FFFFF40EH...
Page 123 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L) (a) V850ES/JC3-L (40-pin) After reset: FFH Address: FFFFF42EH...
Page 124: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 9 Port 9 is a 15-bit port (V850ES/JE3-L) or a 6-bit port (V850ES/JC3-L (48-pin)), a 5-bit port (V850ES/JC3-L (40-pin)) for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins.
Page 125 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) (a) V850ES/JC3-L (40-pin) After reset: 0000H (output latch) Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H...
Page 126 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2) Port 9 mode register (PM9) (a) V850ES/JC3-L (40-pin) After reset: FFFFH Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H PM9 (PM9H)
Page 127 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) (1/4) (a) V850ES/JC3-L (40-pin) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H...
Page 128 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (2/4) (b) V850ES/JC3-L (48-pin) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H PMC9 (PMC9H) PMC915 PMC914 PMC99 PMC98...
Page 129 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (3/4) (c) V850ES/JE3-L (1/2) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910...
Page 130 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (4/4) (c) V850ES/JE3-L (2/2) PMC97 Specification of pin operation I/O port (P97) SIB1 input/TIP20 input/TOP20 output PMC96 Specification of pin operation...
Page 131 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 and PFCE9 registers to 0000H.
Page 132 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (5) Port 9 function control expansion register (PFCE9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 and PFCE9 registers to 0000H.
Page 133 Specification of P98 pin alternate function Setting prohibited SOB1 output PFCE97 PFC97 Specification of P97 pin alternate function Setting prohibited Note2 SIB1 input TIP20 input TOP20 output Notes 1. V850ES/JE3-L only 2. V850ES/JC3-L (48-pin), V850ES/JE3-L only R01UH0018EJ0001 Rev.0.01 Page 133 of 958 Jul 23, 2010...
Page 134 TXDA1 output SDA02 I/O Notes1. V850ES/JE3-L only 2. The RXDA1 and KR7 functions cannot be used at the same time. When using the pin for RXDA1, do not use the KR7 function. When using the pin for KR7, do not use the RXDA1 function. (It is recommended to set the PFC91 bit to 1 and clear the PFCE91 bit to 0.)
Page 135 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (7) Port 9 function register (PF9) (a) V850ES/JC3-L (40-pin) After reset: 0000H Address: PF9 FFFFFC72H, PF9L FFFFFC72H, PF9H FFFFFC73H PF9 (PF9H)
Page 136: Port Cm
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS 4.3.8 Port CM Port CM is a 1-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins.
Page 137: Port Dl
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS 4.3.9 Port DL Port DL is a 1-bit port for which I/O settings can be controlled in 1-bit units. Table 4-14. Port DL Alternate-Function Pins Pin No.
Page 138 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) Address: PDL FFFFF004H, PDLL FFFFF004H (PDLL) PDL5 PDL5 Output data control (in output mode)
Page 139: Block Diagrams
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Block Diagrams Figure 4-5. Block Diagram of Type A-1 PMmn PORT Address P-ch A/D input signal N-ch R01UH0018EJ0001 Rev.0.01 Page 139 of 958...
Page 140 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type A-2 PMmn PORT Address P-ch D/A output signal N-ch R01UH0018EJ0001 Rev.0.01 Page 140 of 958...
Page 141 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type C-1 PFmn PMmn PORT P-ch N-ch Address R01UH0018EJ0001 Rev.0.01 Page 141 of 958 Jul 23, 2010...
Page 142 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type E-3 PFmn Output enable signal when alternate function is used PMCmn PMmn Output signal when...
Page 143 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type G-1 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch...
Page 144 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type G-3 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when...
Page 145 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type G-6 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used P-ch PORT...
Page 146 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type G-12 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when...
Page 147 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type G-13 PFmn PMCmn PMmn Output signal when alternate function is used P-ch PORT N-ch Address R01UH0018EJ0001 Rev.0.01...
Page 148 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type G-14 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used P-ch PORT...
Page 149 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type G-15 PFmn Output enable signal when alternate function is used PFCmn PMCmn PMmn Output signal...
Page 150 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type G-16 PFmn PFCmn PMCmn PMmn PORT P-ch N-ch Note Address Input signal when alternate function is used Note There are no hysteresis characteristics in port mode.
Page 151 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type L-1 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch...
Page 152 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type N-2 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn Output signal when...
Page 153 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type N-3 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT...
Page 154 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type N-4 PFmn INTR INTRmn Note 1 INTF INTFmn Note 1 PMCmn PMmn PORT P-ch...
Page 155 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type N-5 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT...
Page 156 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type U-1 PFmn Output enable signal whenalternate PFCE function is used PFCEmn PFCmn PMCmn PMmn...
Page 157 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of Type U-5 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used...
Page 158 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type U-6 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used...
Page 159 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type U-7 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used...
Page 160 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type U-8 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used...
Page 161 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of Type U-9 PFmn OCDM0 OCDM0 Output enable signal when alternate function is used PFCE PFCEmn...
Page 162 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of Type U-15 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn...
Page 163 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of Type U-18 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used...
Page 164 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of Type U-19 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used...
Page 165 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of Type U-20 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used...
Page 166 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of Type U-21 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used...
Page 167 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-33. Block Diagram of Type U-22 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used...
Page 168 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of Type U-23 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used...
Page 169 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of Type U-24 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn...
Page 170 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-36. Block Diagram of Type AA-1 PFmn External reset signal OCDM0 OCDM0 INTR Note 1 INTRmn INTF Note 1...
Page 171: Port Register Settings When Alternate Function Is Used
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used Table 4-17 shows the port register settings when each port pin is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin.
Page 172 Table 4-17. Settings When Pins Are Used for Alternate Functions (1/5) Function Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Name (Registers) Pn Register PMn Register PMCn Register PFCEn Register PFCn Register Name −...
Page 173 Table 4-17. Settings When Pins Are Used for Alternate Functions (2/5) Function Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of Name PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name...
Page 174 Table 4-17. Settings When Pins Are Used for Alternate Functions (3/5) Function Alternate Function Other Bits PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Pnx Bit of Name (Registers) Pn Register PMn Register PMCn Register PFCEn Register PFCn Register Name Input...
Page 175 Table 4-17. Settings When Pins Are Used for Alternate Functions (4/5) Function Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of Name PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name...
Page 176 Table 4-17. Settings When Pins Are Used for Alternate Functions (5/5) Function Alternate Function Other Bits PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Pnx Bit of Name PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name...
Page 177: Cautions
4.6.1 Cautions on setting port pins (1) In the V850ES/JC3-L and V850ES/JE3-L, general-purpose port pins are shared with several peripheral I/O functions. To switch between using a pin as a general-purpose port pin (port mode) and as a peripheral function I/O pin (alternate-function mode), use the PMCn register.
Page 178 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS The setting order that may cause a malfunction when switching from the P41 pin function to the SCL01 pin function is shown below.
Page 179 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS Figure 4-37. Example of Switching from P02 to NMI (Incorrect) 0 → 1 PMC0 PMC0m bit = 0: Port mode...
Page 180: Cautions On Bit Manipulation Instruction For Port N Register (Pn)
Explanation: When writing to and reading from the Pn register of a port whose PMnm bit is 1, the output latch is written and the pin status is read. A bit manipulation instruction is executed in the following order in the V850ES/JC3-L, V850ES/JE3-L. <1> The Pn register is read in 8-bit units.
Page 181: Cautions On On-Chip Debug Pins
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 4 PORT FUNCTIONS 4.6.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used.
Page 182: Chapter 5 Clock Generator
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR Overview The clock generator generates the clock signals that are input to the CPU and peripherals. The clock generator includes a PLL circuit, which enables the clock frequency to be multiplied by four.
Page 183: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR Configuration Figure 5-1. Clock Generator FRC bit Timer M clock Subclock RTC/Watch timer clock, oscillator Watchdog timer 2 clock /2-f...
Page 184 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (1) Main clock oscillator The main clock oscillator uses a ceramic/crystal resonator connected to X1 and X2 pins to oscillate the following frequencies (f •...
Page 185: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.7 Special registers).
Page 186 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (2/2) Cautions 1. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Page 187 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (a) Example of changing main clock operation to subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits.
Page 188 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (b) Example of changing subclock operation to main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by program and wait until the oscillation stabilization time of the main clock has elapsed.
Page 189 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (2) Internal oscillator mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator.
Page 190: Operations
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR Operations 5.4.1 Operation of each clock The following table shows the operation status of each clock. Table 5-1. Operation Status of Each Clock...
Page 191: Pll Function
5.5.1 Overview In the V850ES/JC3-L, V850ES/JE3-L, an operating clock that is the oscillation frequency multiplied by 4 by the PLL function or an unmultiplied clock (clock-through mode) can be selected as the operating clock of the CPU and on-chip peripheral functions.
Page 192 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.7 Special registers).
Page 193 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (3) Lock register (LOCKR) The PLL locks the phase at a given frequency after the power is turned on or immediately after the STOP mode is canceled.
Page 194 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1.
Page 195: Usage
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR 5.5.3 Usage (1) When PLL is used • After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
Page 196: How To Connect A Resonator
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR How to Connect a Resonator 5.6.1 Main clock oscillator The signal input to the main clock oscillator is oscillated by a ceramic or crystal resonator connected to the X1 and X2 pins.
Page 197 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR Caution 1. When using the main clock or subclock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-2 and 5-3 to avoid an adverse effect from wiring capacitance.
Page 198 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 5 CLOCK GENERATOR Figure 5-4. Examples of Incorrect Resonator Connections (2/2) (c) The wiring is routed near a signal line (d) A current with a higher potential than that of the through which a high fluctuating current flows.
Page 199: Chapter 6 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/JC3-L, V850ES/JE3-L have six timer/event counter channels, TMP0 to TMP5. Overview TMPn has the following features. (1) Interval timer TMPn generates an interrupt at a preset interval and can output a square wave.
Page 200: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Configuration TMPn includes the following hardware. Table 6-1. Configuration of TMPn Item Configuration Registers 16-bit counter TMPn counter read buffer register (TPnCNT)
Page 201 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This is a 16-bit counter that counts internal clocks and external events. This counter can be read by using the TPnCNT register.
Page 202: Pins Used By Tmpn
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (10) Output controller This circuit controls the output of the TOPn0 and TOPn1 pins. The output controller is controlled by the TPnIOC0 register.
Page 203: Register Configuraiton
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.2.2 Register configuraiton For the V850ES/JC3-L and V850ES/JE3-L, the registers and their bit assignment differ for each product. The register configuration for each product is shown in the following tables (1) V850ES/JC3-L (40-pin)
Page 204 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) V850ES/JC3-L (48-pin) Channel Register name Bit position TMP0 TP0CTL0 TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL1 TP0EST TP0EEE...
Page 205 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) V850ES/JE3-L Channel Register name Bit position TMP0 TP0CTL0 TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL1 TP0EST TP0EEE TP0MD2...
Page 206: Interrupts
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.2.3 Interrupts The following three types of interrupt signals are used by TMPn: (1) INTTPnCC0 This signal is generated when the value of the 16-bit counter matches the value of the CCR0 buffer register, or when a capture signal is input from the TIPn0 pin.
Page 207: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Registers The registers that control TMPn are as follows. • TMPn control register 0 (TPnCTL0) • TMPn control register 1 (TPnCTL1) •...
Page 208 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn.
Page 209 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of TMPn.
Page 210 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the operation of timer output (TOPn0, TOPn1 pins).
Page 211 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins).
Page 212 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin).
Page 213 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and indicate the detection of an overflow.
Page 214 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register can be used as a capture register or a compare register depending on the mode.
Page 215 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1.
Page 216 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register can be used as a capture register or a compare register depending on the mode.
Page 217 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1.
Page 218 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register from which the count value of the 16-bit counter can be read.
Page 219: Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Operations For the V850ES/JC3-L, V850ES/JE3-L, the modes that can be enabled depend on each channel. The following table shows the modes that can be enabled for each channel. Table 6-5. TMPn Modes and Channels That Can Use These Modes (V850ES/JC3-L (40-pin))
Page 220 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Table 6-7. TMPn Modes and Channels That Can Use These Modes (V850ES/JE3-L) TMP0 TMP1 TMP2 TMP3 TMP4...
Page 221 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Basic counter operation The basic operation of the 16-bit counter is described below. For more details, see the descriptions of each operating mode.
Page 222 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Anytime write and batch write The TPnCCR0 and TPnCCR1 registers can be written even while TMPn is operating (that is, while the TPnCTL0.TPnCE bit is 1), but the way the CCR0 and CCR1 buffer registers are written differs depending on the...
Page 223 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-3. Anytime Write Timing TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register...
Page 224 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Batch write This writing method is used to transfer data from the TPnCCR0 and TPnCCR1 registers to the CCR0 and CCR1 buffer registers all at once while TMPn is operating.
Page 225 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-4. Flowchart Showing Basic Batch Write Operation START Initial settings • Set value to TPnCCRa register •...
Page 226 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-5. Batch Write Timing TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register...
Page 227: Interval Timer Mode (Tpnmd2 To Tpnmd0 Bits = 000)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.4.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, setting the TPnCTL0.TPnCE bit to 1 generates an interrupt request signal (INTTPnCC0) at a specified interval.
Page 228 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts incrementing.
Page 229 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-8. Register Settings in Interval Timer Mode (2/2) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1...
Page 230 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operations in interval timer mode Figure 6-9. Timing and Processing of Operations in Interval Timer Mode...
Page 231 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Using interval timer mode (a) Operation when TPnCCR0 register is set to 0000H When the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated each count clock cycle from the second clock cycle, and the output of the TOPn0 pin is inverted.
Page 232 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation when TPnCCR0 register is set to FFFFH When the TPnCCR0 register is set to FFFFH, the 16-bit counter increments up to FFFFH and is reset to 0000H in synchronization with the next increment timing.
Page 233 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register When rewriting the value of the TPnCCR0 register to a smaller value, stop counting first and then change the set value.
Page 234 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register The TPnCCR1 register is configured as follows in the interval timer mode.
Page 235 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the value of the TPnCCR1 register is less than or equal to the value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle.
Page 236 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the value of the TPnCCR1 register is greater than the value of the TPnCCR0 register, the value of the 16-bit counter will not match the value of the TPnCCR1 register.
Page 237 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) Operation of interval timer based on input of external event count (a) Operation When the 16-bit counter is incrementing based on the valid edge of the external count input (TIPn0 pin) in the interval timer mode, one external event count valid edge must be input immediately after the TPnCE bit changes from 0 to 1 to start the counter incrementing after the 16-bit counter is cleared from FFFFH to 0000H.
Page 238: External Event Count Mode (Tpnmd2 To Tpnmd0 Bits = 001)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.4.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number...
Page 239 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-18. Basic Timing of Operations in External Event Count Mode FFFFH 16-bit counter − 1 16-bit counter...
Page 240 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) An example of the register settings when the external event count mode is used is shown in the figure below.
Page 241 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-19. Register Settings in External Event Count Mode (2/2) (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading this register.
Page 242 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operations in external event count mode Figure 6-20. Timing and Processing of Operations in External Event Count Mode...
Page 243 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Using external event count mode (a) Operation when TPnCCR0 register is set to FFFFH When the TPnCCR0 register is set to FFFFH, the 16-bit counter increments up to FFFFH upon detection of the valid edge of the external event count signal and is reset to 0000H in synchronization with the next increment timing.
Page 244 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting TPnCCR0 register When rewriting the value of the TPnCCR0 register to a smaller value, stop counting first and then change the set value.
Page 245 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPnCCR1 register The TPnCCR1 register is configured as follows in the external event count mode.
Page 246 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the value of the TPnCCR1 register is greater than the value of the TPnCCR0 register, the value of the 16-bit counter will not match the value of the TPnCCR1 register and the INTTPnCC1 signal will not be generated.
Page 247: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 010)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.4.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, when the TPnCTL0.TPnCE bit is set to 1, TMPn waits for a trigger, which is the valid edge of the external trigger input signal, and starts incrementing when this trigger is detected.
Page 248 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-27. Basic Timing of Operations in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit...
Page 249 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-28. Register Settings in External Trigger Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0)
Page 250 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-28. Register Settings in External Trigger Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2)
Page 251 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operations in external trigger pulse output mode Figure 6-29. Timing and Processing of Operations in External Trigger Pulse Output Mode (1/2)
Page 252 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-29. Timing and Processing of Operations in External Trigger Pulse Output Mode (2/2) <1> Starting counting <3>...
Page 253 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Using external trigger pulse output mode How to change the PWM waveform in the external trigger pulse output mode is described below.
Page 254 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPnCCRa register to the CCRa buffer register, the TPnCCR1 register must be written.
Page 255 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Outputting a 0% or 100% PWM waveform To output a 0% waveform, clear the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically.
Page 256 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Detection of trigger immediately before or after INTTPnCC1 generation If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is set to the active level, and the counter continues incrementing.
Page 257 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Detection of trigger immediately before or after INTTPnCC0 generation If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues incrementing.
Page 258 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Timing of generating the compare match interrupt request signal (INTTPnCC1) In the external trigger pulse output mode, the INTTPnCC1 signal is generated when the value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 259: One-Shot Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 011)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) 6.4.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, when the TPnCTL0.TPnCE bit is set to 1, TMPn waits for a trigger, which is the valid edge of the external trigger input, and starts incrementing when this trigger is detected.
Page 260 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-39. Basic Timing of Operations in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit...
Page 261 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-40. Register Settings in One-Shot Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE...
Page 262 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-40. Register Settings in One-Shot Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2)
Page 263 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (1) Operations in one-shot pulse output mode Figure 6-41. Timing and Processing of Operations in One-Shot Pulse Output Mode...
Page 264 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (2) Using one-shot pulse mode (a) Rewriting the TPnCCRa register When rewriting the value of the TPnCCRa register to a smaller value, stop counting first and then change the set value.
Page 265 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-42. Rewriting TPnCCRa Register FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input)
Page 266 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (b) Timing of generating the compare match interrupt request signal (INTTPnCC1) In the one-shot pulse output mode, the INTTPnCC1 signal is generated when the value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 267: Pwm Output Mode (Tpnmd2 To Tpnmd0 Bits = 100)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) 6.4.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, when the TPnCTL0.TPnCE bit is set to 1, TMPn outputs a PWM waveform from the TOPn1 pin.
Page 268 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-45. Basic Timing of Operations in PWM Output Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register...
Page 269 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-46. Register Settings in PWM Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0...
Page 270 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-46. Register Settings in PWM Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1...
Page 271 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (1) Operations in PWM output mode Figure 6-47. Timing and Processing of Operations in PWM Output Mode (1/2)
Page 272 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-47. Timing and Processing of Operations in PWM Output Mode (2/2) <1> Starting counting <3> Changing the duty...
Page 273 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (2) Using PWM output mode (a) Changing the PWM waveform while the counter is incrementing To change the PWM waveform while the counter is incrementing, write to the TPnCCR1 register after changing the waveform setting.
Page 274 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (b) Outputting a 0% or 100% PWM waveform To output a 0% waveform, clear the TPnCCR1 register to 0000H.
Page 275 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) To output a 100% waveform, set the value of TPnCCR0 register + 1 to the TPnCCR1 register. If the value of the TPnCCR0 register is FFFFH, a 100% waveform cannot be output.
Page 276: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 Bits = 101)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) 6.4.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, TMPn starts incrementing when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRa register can be used as a compare register or a capture register, according to the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Page 277 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) • Compare operation When the TPnCE bit is set to 1, TMPn starts incrementing, and the output signals of the TOPn0 and TOPn1 pins are inverted.
Page 278 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) • Capture operation When the TPnCE bit is set to 1, the 16-bit counter starts incrementing. When it is detected that a valid edge as been input to the TIPna pin, the value of the 16-bit counter is stored in the TPnCCRa register, and a capture interrupt request signal (INTTPnCCa) is generated.
Page 279 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-55. Register Settings in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0...
Page 280 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-55. Register Settings in Free-Running Timer Mode (2/2) (d) TMPn I/O control register 1 (TPnIOC1) TPnIS3...
Page 281 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (1) Operations in free-running timer mode The following two operations occur in the free-running timer mode: • Capture operations •...
Page 282 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-56. Timing and Processing of Operations in Free-Running Timer Mode (Compare Function) (2/2) <1> Starting counting...
Page 283 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (b) Using a capture/compare register as a capture register Figure 6-57. Timing and Processing of Operations in Free-Running Timer Mode (Capture Function) (1/2)
Page 284 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-57. Timing and Processing of Operations in Free-Running Timer Mode (Capture Function) (2/2) <1> Starting counting...
Page 285 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (2) Using free-running timer mode (a) Interval operation using the TPnCCRa register as a compare register When TMPn is used as an interval timer with the TPnCCRa register used as a compare register, the comparison value at which the next interrupt request signal is generated each time the INTTPnCCa signal has been detected must be set by software.
Page 286 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (b) Pulse width measurement using the TPnCCRa register as a capture register When pulse width measurement is performed with the TPnCCRa register used as a capture register, each time the INTTPnCCa signal has been detected, the capture register must be read and the interval must be calculated by software.
Page 287 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (c) Processing an overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
Page 288 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-61. Example of Resolving Problem When Two Capture Registers Are Used By Using Overflow Interrupt FFFFH...
Page 289 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-62. Example of Resolving Problem When Two Capture Registers Are Used Without Using Overflow Interrupt FFFFH...
Page 290 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once between the first capture trigger and the next.
Page 291 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-64. Example of Using Software Processing to Resolve Problem When Capture Trigger Interval Is Long (When Using TIPn0)
Page 292: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 Bits = 110)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) 6.4.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, TMPn starts incrementing when the TPnCTL0.TPnCE bit is set to 1. Each time it is detected that a valid edge has been input to the TIPna pin, the value of the 16-bit counter is stored in the TPnCCRa register, and the 16-bit counter is cleared to 0000H.
Page 293 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-66. Basic Timing of Operations in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit...
Page 294 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Figure 6-67. Register Settings in Pulse Width Measurement Mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0...
Page 295 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (1) Operations in pulse width measurement mode Figure 6-68. Timing and Processing of Operations in Pulse Width Measurement Mode...
Page 296: Timer Output Operations
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) (2) Using pulse width measurement mode (a) Clearing the overflow flag (TPnOVF) The overflow flag (TPnOVF) can be cleared to 0 by reading the TPnOVF bit and, if its value is 1, either clearing the bit to 0 by using the CLR1 instruction or by writing 8-bit data (with bit 0 as 0) to the TPnOPT0 register.
Page 297: Selector (V850Es/Je3-L Only)
CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Selector (V850ES/JE3-L only) In the V850ES/JE3-L, the selector can be used to specify the capture trigger input for TMP as either a signal input to a port/timer alternate-function pin or peripheral I/O (TMP/UARTA) signal.
Page 298: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 6 16-BIT TIMER/EVEVT COUNTER P (TMP) Cautions (1) Capture operation When the capture operation is used and f /8, f /16, f /32, f...
Page 299: Chapter 7 16-Bit Timer/Event Counter Q (Tmq)
V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850ES/JC3-L, V850ES/JE3-L incorporate one TMQ timer/counter, TMQ0. Functions TMQ0 has the following features: (1) Interval timer TMQ0 generates an interrupt at a preset interval and can output a square wave.
Page 300: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Configuration TMQ0 includes the following hardware. Table 7-1. Configuration of TMQ0 Item Configuration Registers 16-bit counter TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
Page 301 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) 16-bit counter This is a 16-bit counter that counts internal clocks and external events. This counter can be read by using the TQ0CNT register.
Page 302: Pins Used By Tmq0
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) Output controller This circuit controls the output of the TOQ00 to TOQ03 pins. The output controller is controlled by the TQ0IOC0 register.
Page 303: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Registers The registers that control TMQ0 are as follows: • TMQ0 control register 0 (TQ0CTL0) • TMQ0 control register 1 (TQ0CTL1) •...
Page 304 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) TMQ0 control register 0 (TQ0CTL0) The TQ0CTL0 register is an 8-bit register that controls the operation of TMQ0.
Page 305 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) TMQ0 control register 1 (TQ0CTL1) The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0.
Page 306 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) TMQ0 I/O control register 0 (TQ0IOC0) The TQ0IOC0 register is an 8-bit register that controls the timer output (TOQ00 to TOQ03 pins).
Page 307 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the specification of the valid edge of the capture trigger input signals (TIQ00 to TIQ03 pins).
Page 308 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the specification of the valid edge of the external event count input signal (TIQ00 pin) and external trigger input signal (TIQ00 pin).
Page 309 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (6) TMQ0 option register 0 (TQ0OPT0) The TQ0OPT0 register is an 8-bit register that specifies the capture/compare operation and indicates the detection of an overflow.
Page 310 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQ0 capture/compare register 0 (TQ0CCR0) The TQ0CCR0 register can be used as a capture register or a compare register depending on the mode.
Page 311 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) The following table shows the functions of the capture/compare register in each operation mode, and how to write data to the compare register.
Page 312 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQ0 capture/compare register 1 (TQ0CCR1) The TQ0CCR1 register can be used as a capture register or a compare register depending on the mode.
Page 313 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) The following table shows the functions of the capture/compare register in each operation mode, and how to write data to the compare register.
Page 314 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQ0 capture/compare register 2 (TQ0CCR2) The TQ0CCR2 register can be used as a capture register or a compare register depending on the mode.
Page 315 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) The following table shows the functions of the capture/compare register in each operation mode, and how to write data to the compare register.
Page 316 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQ0 capture/compare register 3 (TQ0CCR3) The TQ0CCR3 register can be used as a capture register or a compare register depending on the mode.
Page 317 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) The following table shows the functions of the capture/compare register in each operation mode, and how to write data to the compare register.
Page 318: Operations
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Operations TMQ0 can execute the following operations: Table 7-7. TMQ0 Operating Modes Operating Mode TQ0CTL1.TQ0EST TIQ00 Pin...
Page 319 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Basic counter operation The basic operation of the 16-bit counter is described below. For more details, see the descriptions of each operating mode.
Page 320 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Anytime write and batch write The TQ0CCR0 to TQ0CCR3 registers can be written even while TMQ0 is operating (that is, while the TQ0CTL0.TQ0CE bit is 1), but the way the CCR0 to CCR3 buffer registers are written differs depending on the...
Page 321 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-3. Anytime Write Timing TQ0CE bit = 1 FFFFH 16-bit counter 0000H TQ0CCR0 register CCR0 buffer register...
Page 322 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Batch write This writing method is used to transfer data from the TQ0CCR0 to TQ0CCR3 registers to the CCR0 to CCR3 buffer registers all at once while TMQ0 is operating.
Page 323 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-4. Flowchart Showing Basic Batch Write Operation START Initial settings • Set value to TQ0CCRm register •...
Page 324 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-5. Batch Write Timing TQ0CE bit = 1 FFFFH 16-bit counter 0000H TQ0CCR0 register CCR0 buffer...
Page 325: Interval Timer Mode (Tq0Md2 To Tq0Md0 Bits = 000)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.4.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) In the interval timer mode, setting the TQ0CTL0.TQ0CE bit to 1 generates an interrupt request signal (INTTQ0CC0) at a specified interval.
Page 326 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts incrementing.
Page 327 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-8. Register Settings in Interval Timer Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3...
Page 328 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-8. Register Settings in Interval Timer Mode (3/3) (g) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3) Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode.
Page 329 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operations in interval timer mode Figure 7-9. Timing and Processing of Operations in Interval Timer Mode...
Page 330 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Using interval timer mode (a) Operation when TQ0CCR0 register is set to 0000H When the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated each count clock cycle from the second clock cycle, and the output of the TOQ00 pin is inverted.
Page 331 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Operation when TQ0CCR0 register is set to FFFFH When the TQ0CCR0 register is set to FFFFH, the 16-bit counter increments up to FFFFH and is reset to 0000H in synchronization with the next increment timing.
Page 332 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQ0CCR0 register When rewriting the value of the TQ0CCR0 register to a smaller value, stop counting first and then change the set value.
Page 333 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQ0CCR1 to TQ0CCR3 registers The TQ0CCR1 to TQ0CCR3 registers are configured as follows in the interval timer mode.
Page 334 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the value of the TQ0CCRk register is less than or equal to the value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle.
Page 335 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the value of the TQ0CCRk register is greater than the value of the TQ0CCR0 register, the value of the 16-bit counter will not match the value of the TQ0CCRk register.
Page 336: External Event Count Mode (Tq0Md2 To Tq0Md0 Bits = 001)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) Operation of interval timer based on input of external event count (a) Operation When the 16-bit counter is incrementing based on the valid edge of the external event count input (TIQ00 pin) in the interval timer mode, one external event count valid edge must be input immediately after the TQ0CE bit changes from 0 to 1 to start the counter incrementing after the 16-bit counter is cleared from FFFFH to 0000H.
Page 337 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. Remarks 1. For how to set the TIQ00 pin, see Table 7-2 Pins Used by TMQ0 and Table 4-17 Settings When Pins Are Used for Alternate Functions.
Page 338 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter increments each time the valid edge of the external event count input is detected, and the value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 339 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) An example of the register settings when the external event count mode is used is shown in the figure below.
Page 340 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-19. Register Settings in External Event Count Mode (2/2) (f) TMQ0 capture/compare register 0 (TQ0CCR0) When the TQ0CCR0 register is set to D...
Page 341 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operations in external event count mode Figure 7-20. Timing and Processing of Operations in External Event Count Mode...
Page 342 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Using external event count mode (a) Operation when TQ0CCR0 register is set to FFFFH When the TQ0CCR0 register is set to FFFFH, the 16-bit counter increments up to FFFFH upon detection of the valid edge of the external event count signal and is reset to 0000H in synchronization with the next increment timing.
Page 343 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting TQ0CCR0 register When rewriting the value of the TQ0CCR0 register to a smaller value, stop counting first and then change the set value.
Page 344 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers The TQ0CCR1 to TQ0CCR3 registers are configured as follows in the external event count mode.
Page 345 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the value of the TQ0CCRk register is less than or equal to the value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle.
Page 346 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the value of the TQ0CCRk register is greater than the value of the TQ0CCR0 register, the value of the 16-bit counter will not match the value of the TQ0CCRk register and the INTTQ0CCk signal will not be generated.
Page 347: External Trigger Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 010)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.4.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) In the external trigger pulse output mode, when the TQ0CTL0.TQ0CE bit is set to 1, TMQ0 waits for a trigger, which is the valid edge of the external trigger input signal, and starts incrementing when this trigger is detected.
Page 348 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-27. Basic Timing of Operations in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE...
Page 349 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, TMQ0 waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts incrementing, and outputs a PWM waveform from the TOQ0k pin.
Page 350 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-28. Register Settings in External Trigger Pulse Output Mode (2/3) (b) TMQ0 control register 1 (TQ0CTL1)
Page 351 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-28. Register Settings in External Trigger Pulse Output Mode (3/3) (d) TMQ0 I/O control register 2 (TQ0IOC2)
Page 352 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operations in external trigger pulse output mode Figure 7-29. Timing and Processing of Operations in External Trigger Pulse Output Mode (1/2)
Page 353 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-29. Timing and Processing of Operations in External Trigger Pulse Output Mode (2/2) <1> Starting counting <4>...
Page 354 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Using external trigger pulse output mode How to change the PWM waveform in the external trigger pulse output mode is described below.
Page 355 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-30. Changing PWM Waveform While Counter Is Incrementing FFFFH 16-bit counter 0000H TQ0CE bit External trigger input...
Page 356 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written.
Page 357 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Outputting a 0% or 100% PWM waveform To output a 0% waveform, clear the TQ0CCRk register to 0000H. Note that if the set value of the TQ0CCR0 register is FFFFH, the INTTQ0CCk signal is generated periodically.
Page 358 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) To output a 100% waveform, set the value of TQ0CCR0 register + 1 to the TQ0CCRk register.
Page 359 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Detection of trigger immediately before or after INTTQ0CCk generation If the trigger is detected immediately after the INTTQ0CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0k pin is set to the active level, and the counter continues incrementing.
Page 360 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Detection of trigger immediately before or after INTTQ0CC0 generation If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues incrementing.
Page 361 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Timing of generating the compare match interrupt request signal (INTTQ0CCk) In the external trigger pulse output mode, the INTTQ0CCk signal is generated when the value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 362: One-Shot Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 011)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) 7.4.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) In the one-shot pulse output mode, when the TQ0CTL0.TQ0CE bit is set to 1, TMQ0 waits for a trigger, which is the valid edge of the external trigger input, and starts incrementing when this trigger is detected.
Page 363 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-39. Basic Timing of Operations in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit...
Page 364 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, TMQ0 waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts incrementing, and outputs a one-shot pulse from the TOQ0k pin.
Page 365 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-40. Register Settings in One-Shot Pulse Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0)
Page 366 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-40. Register Settings in One-Shot Pulse Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
Page 367 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (1) Operations in one-shot pulse output mode Figure 7-41. Timing and Processing of Operations in One-Shot Pulse Output Mode (1/2)
Page 368 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-41. Timing and Processing of Operations in One-Shot Pulse Output Mode (2/2) <1> Starting counting <2> Changing the TQ0CCR0 to TQ0CCR3 register settings...
Page 369 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (2) Using one-shot pulse mode (a) Rewriting the TQ0CCRm register When rewriting the value of the TQ0CCRm register to a smaller value, stop counting first and then change the set value.
Page 370 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-42. Rewriting TQ0CCRm Register FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input)
Page 371 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (b) Timing of generating the compare match interrupt request signal (INTTQ0CCk) In the one-shot pulse output mode, the INTTQ0CCk signal is generated when the value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 372: Pwm Output Mode (Tq0Md2 To Tq0Md0 Bits = 100)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) 7.4.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) In the PWM output mode, when the TQ0CTL0.TQ0CE bit is set to 1, TMQ0 outputs a PWM waveform from the TOQ01 to TOQ03 pins.
Page 373 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-45. Basic Timing of Operations in PWM Output Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register...
Page 374 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts incrementing, and outputs a PWM waveform from the TOQ0k pin.
Page 375 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-46. Register Settings in PWM Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3...
Page 376 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-46. Register Settings in PWM Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
Page 377 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (1) Operations in PWM output mode Figure 7-47. Timing and Processing of Operations in PWM Output Mode (1/2)
Page 378 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-47. Timing and Processing of Operations in PWM Output Mode (2/2) <1> Starting counting <4> Changing the duty...
Page 379 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (2) Using PWM output mode (a) Changing the PWM waveform while the counter is incrementing To change the PWM waveform while the counter is incrementing, write to the TQ0CCR1 register after changing the waveform setting.
Page 380 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written.
Page 381 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (b) Outputting a 0% or 100% PWM waveform To output a 0% waveform, clear the TQ0CCRk register to 0000H.
Page 382 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (c) Timing of generating the compare match interrupt request signal (INTTQ0CCk) In the PWM output mode, the INTTQ0CCk signal is generated when the value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 383: Free-Running Timer Mode (Tq0Md2 To Tq0Md0 Bits = 101)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) 7.4.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) In the free-running timer mode, TMQ0 starts incrementing when the TQ0CTL0.TQ0CE bit is set to 1. At this time, the TQ0CCRm register can be used as a compare register or a capture register, according to the setting of the TQ0OPT0.TQ0CCS0 and TQ0OPT0.TQ0CCS1 bits.
Page 384 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-52. Configuration of TMQ0 in Free-Running Timer Mode TQ0CCR3 Output Note 2 TOQ03 pin output register...
Page 385 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) • Compare operation When the TQ0CE bit is set to 1, TMQ0 starts incrementing, and the output signals of the TOQ00 to TOQ03 pins are inverted.
Page 386 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) • Capture operation When the TQ0CE bit is set to 1, the 16-bit counter starts incrementing. When it is detected that a valid edge as been input to the TIQ0m pin, the value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal (INTTQ0CCm) is generated.
Page 387 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-55. Register Settings in Free-Running Timer Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0...
Page 388 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-55. Register Settings in Free-Running Timer Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL1...
Page 389 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-55. Register Settings in Free-Running Timer Mode (3/3) (e) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1...
Page 390 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (1) Operations in free-running timer mode The following two operations occur in the free-running timer mode: • Capture operations •...
Page 391 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-56. Timing and Processing of Operations in Free-Running Timer Mode (Compare Function) (2/2) <1> Starting counting...
Page 392 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (b) Using a capture/compare register as a capture register Figure 7-57. Timing and Processing of Operations in Free-Running Timer Mode (Capture Function) (1/2)
Page 393 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-57. Timing and Processing of Operations in Free-Running Timer Mode (Capture Function) (2/2) <1> Starting counting...
Page 394 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (2) Using free-running timer mode (a) Interval operation using the TQ0CCRm register as a compare register When TMQ0 is used as an interval timer with the TQ0CCRm register used as a compare register, the comparison value at which the next interrupt request signal is generated each time the INTTQ0CCm signal has been detected must be set by software.
Page 395 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, four intervals can be set for one channel.
Page 396 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (b) Pulse width measurement using the TQ0CCRm register as a capture register When pulse width measurement is performed with the TQ0CCRm register used as a capture register, each time the INTTQ0CCm signal has been detected, the capture register must be read and the interval must be calculated by software.
Page 397 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Four pulse widths can be measured in the free-running timer mode. When measuring a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRm register in synchronization with the INTTQ0CCm signal, and calculating the difference between that value and the previously read value.
Page 398 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (c) Processing an overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two or more capture registers are used. First, an example of incorrect processing is shown below.
Page 399 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-61. Example of Resolving Problem When Two or More Capture Registers Are Used by Using Overflow...
Page 400 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-62. Example of Resolving Problem When Two or More Capture Registers Are Used Without Using Overflow Interrupt...
Page 401 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once between the first capture trigger and the next.
Page 402 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-64. Example of Using Software Processing to Resolve Problem When Capture Trigger Interval Is Long (When Using TIQ0m)
Page 403: Pulse Width Measurement Mode (Tq0Md2 To Tq0Md0 Bits = 110)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) 7.4.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, TMQ0 starts incrementing when the TQ0CTL0.TQ0CE bit is set to 1. Each time it is detected that a valid edge has been input to the TIQ0m pin, the value of the 16-bit counter is stored in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H.
Page 404 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-66. Basic Timing of Operations in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit...
Page 405 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-67. Register Settings in Pulse Width Measurement Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE...
Page 406 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Figure 7-67. Register Settings in Pulse Width Measurement Mode (2/2) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading this register.
Page 407 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (1) Operations in pulse width measurement mode Figure 7-68. Timing and Processing of Operations in Pulse Width Measurement Mode...
Page 408: Timer Output Operations
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) (2) Using pulse width measurement mode (a) Clearing the overflow flag (TQ0OVF) The overflow flag (TQ0OVF) can be cleared to 0 by reading the TQ0OVF bit and, if its value is 1, either clearing the bit to 0 by using the CLR1 instruction or by writing 8-bit data (with bit 0 as “0”) to the TQ0OPT0 register.
Page 409: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 7 16-BIT TIMER/EVEVT COUNTER Q (TMQ) Cautions (1) Capture operation When the capture operation is used and f /8, f /16, f /32, f...
Page 410: Chapter 8 16-Bit Interval Timer M (Tmm)
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Timer M (TMM) is a 16-bit interval timer. The V850ES/JC3-L, V850ES/JE3-L incorporate one TMM timer, TMM0. Features TMM0 is a dedicated interval timer that generates interrupt requests at a specified interval based on the count clock...
Page 411: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Configuration TMM0 includes the following hardware. Table 8-1. Configuration of TMM0 Item Configuration Register 16-bit counter TMM0 compare register 0 (TM0CMP0) TMM0 control register 0 (TM0CTL0) Figure 8-1.
Page 412: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Registers (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the operation of TMM0.
Page 413 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (2) TMM0 compare register 0 (TM0CMP0) The TM0CMP0 register is a 16-bit compare register. This register can be read or written in 16-bit units.
Page 414: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Operation 8.4.1 Interval timer mode When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts incrementing.
Page 415 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) An example of the register settings when the interval timer mode is used is shown in the figure below.
Page 416 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (1) Operations in interval timer mode Figure 8-5. Timing and Processing of Operations in Interval Timer Mode...
Page 417 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (2) Using interval timer mode (a) Operation when TM0CMP0 register is set to 0000H When the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated for each count clock cycle.
Page 418: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) 8.4.2 Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1, depending on the count clock selected.
Page 419: Chapter 9 Watch Timer
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER CHAPTER 9 WATCH TIMER Functions The watch timer has the following functions. • Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock.
Page 420: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER Configuration The block diagram of the watch timer is shown below. Figure 9-1. Block Diagram of Watch Timer Internal bus...
Page 421 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER (1) Clock control This block controls supplying and stopping the operating clock (f ) when the watch timer operates on the main clock.
Page 422: Control Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER Control Registers The following registers are provided for the watch timer. • Prescaler mode register 0 (PRSM0) • Prescaler compare register 0 (PRSCM0) •...
Page 423 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units.
Page 424 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER (3) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 425 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER (2/2) WTM7 WTM3 WTM2 Selection of set time of watch flag (0.5 s: f (0.25 s: f μ (977 s: f μ...
Page 426: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER Operation 9.4.1 Watch timer operations The watch timer operates on the main clock or subclock (32.768 kHz) and generates an interrupt request signal (INTWT) at fixed, exact time intervals of 0.25 or 0.5 seconds.
Page 427: Interval Timer Operations
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER 9.4.2 Interval timer operations The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals determined by certain conditions.
Page 428 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER Figure 9-2. Timing of Watch Timer and Interval Timer Operations 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s)
Page 429: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 9 WATCH TIMER Cautions (1) Operation as watch timer The first watch timer interrupt request signal (INTWT) is not generated at the exact time specified using the WTM2 and WTM3 bits after operation is enabled (WTM.WTM1 and WTM.WTM0 bits = 11).
Page 430: Chapter 10 Real-Time Counter
• Pin output function of 1 Hz • Pin output function of 32.768 kHz (V850ES/JE3-L only) • Pin output function of 512 Hz or 16.384 kHz (V850ES/JE3-L only) • Watch error correction function • Subclock operation or main clock operation...
Page 431: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.2 Configuration The real-time counter includes the following hardware. Table 10-1. Configuration of Real-Time Counter Item Configuration Control registers Real-time counter control register 0 (RC1CC0)
Page 432 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER Figure 10-1. Block Diagram of Real-Time Counter CLOE1 RTC1HZ Minute Hour Day-of-week alarm alarm alarm INTRTC1 INTRTC0 Count clock = 32.768 kHz...
Page 433: Pin Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.2.1 Pin configuration The RTC outputs included in the real-time counter are alternatively used as shown in Table 10-2. The port function must be set when using each pin (see Table 4-17 Settings When Pins Are Used for Alternate Functions).
Page 434: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.3 Registers The real-time counter is controlled by the following 18 registers. (1) Real-time counter control register 0 (RC1CC0) The RC1CC0 register selects the real-time counter input clock.
Page 435 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER After reset: 00H Address: FFFFFADEH Note RC1CC1 RTCE CLOE1 CLOE0 AMPM RTCE Control of operation of each counter Stops counter operation.
Page 436 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (3) Real-time counter control register 2 (RC1CC2) The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters.
Page 437 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (4) Real-time counter control register 3 (RC1CC3) The RC1CC3 register is an 8-bit register that controls the interval interrupt function and RTCDIV pin.
Page 438 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (5) Sub-count register (RC1SUBC) The RC1SUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter.
Page 439 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (7) Minute count register (RC1MIN) The RC1MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes.
Page 440 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER Table 10-3 shows the relationship among the AMPM bit setting value, RC1HOUR register value, and time. Table 10-3. Time Digit Display...
Page 441 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (9) Day count register (RC1DAY) The RC1DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days.
Page 442 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (10) Day-of-week count register (RC1WEEK) The RC1WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the day-of-week count value.
Page 443 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (11) Month count register (RC1MONTH) The RC1MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months.
Page 444 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (13) Watch error correction register (RC1SUBU) The RC1SUBU register is an 8-bit register that can be used to correct the watch with high accuracy when the watch is early or late, by changing the value (reference value: 7FFFH) overflowing from the sub-count register (RSUBC) to the second counter register.
Page 445 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (14) Alarm minute setting register (RC1ALM) The RC1ALM register is an 8-bit register that is used to set minutes of alarm.
Page 446 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (16) Alarm day-of-week setting register (RC1ALW) The RC1ALW register is an 8-bit register that is used to set the day-of-week of the alarm.
Page 447 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER Table 10-5. Alarm Setting Example if AMPM = 1 (RC1HOUR Register 24-Hour Display) Register RC1ALW RC1ALH RC1ALM Alarm Setting Time...
Page 448 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (18) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units.
Page 449: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4 Operation 10.4.1 Initial settings The initial settings are set when operating the watch function and performing a fixed-cycle interrupt operation.
Page 450: Rewriting Each Counter During Real-Time Counter Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4.2 Rewriting each counter during real-time counter operation Set as follows when rewriting each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1).
Page 451: Reading Each Counter During Real-Time Counter Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4.3 Reading each counter during real-time counter operation Set as follows when reading each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, RC1YEAR) during real-time counter operation (RC1PWR = 1, RTCE = 1).
Page 452: Changing Intrtc0 Interrupt Setting During Real-Time Counter Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4.4 Changing INTRTC0 interrupt setting during real-time counter operation If the setting of the INTRTC0 interrupt (fixed-cycle interrupt) signal is changed while the real-time counter clock operates (PC1PWR = 1, RTCE =1), the INTRCT0 interrupt waveform may include whiskers and unintended signals may be output.
Page 453: Changing Intrtc1 Interrupt Setting During Real-Time Counter Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4.5 Changing INTRTC1 interrupt setting during real-time counter operation If the setting of the INTRTC1 interrupt (alarm interrupt) signal is changed while the real-time counter operates (RC1PWR = 1, RTCE = 1), the INTRCT1 interrupt waveform may include whiskers and unintended signals may be output.
Page 454: Initial Intrtc2 Interrupt Settings
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4.6 Initial INTRTC2 interrupt settings Set as follows to set the INTRTC1 interrupt (interval interrupt). Figure 10-7. INTRTC2 Interrupt Setting Start RC1CC0.RC1PWR bit = 1...
Page 455: Changing Intrtc2 Interrupt Setting During Real-Time Counter Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4.7 Changing INTRTC2 interrupt setting during real-time counter operation If the setting of the INTRTC2 interrupt (interval interrupt) is changed while the real-time counter clock operates (PC1PWR = 1, RTCE = 1), the INTRCT2 interrupt waveform may include whiskers and unintended signals may be output.
Page 456: Initializing Real-Time Counter
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER 10.4.8 Initializing real-time counter The procedure for initializing the real-time counter is shown below. Figure 10-9. Initializing Real-Time Counter Start...
Page 457: Watch Error Correction Example Of Real-Time Counter
10.4.9 Watch error correction example of real-time counter The watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the V850ES/JC3-L and V850ES/JE3-L. Deviation, here, refers to steady-state deviation, which is deviation in the frequency when the resonator is designed.
Page 458 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER As shown in Figure 10-10, the watch can be accurately counted by incrementing the RC1SUBC count value, if a positive error faster than 32.768 kHz occurs at the resonator. Similarly, if a negative error slower than 32.768 kHz occurs at the resonator, the watch can be accurately counted by decrementing the RC1SUBC count value.
Page 459 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER (3) DEV bit The DEV bit determines when the setting by the F6 to F0 bits is enabled. The value set by the F6 to F0 bits is reflected upon the next timing, but not to the RC1SUBC count value every time.
Page 460 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 10 REAL-TIME COUNTER Table 10-7. Range of Frequencies That Can Be Corrected When DEV Bit = 0 F5 to F0 RC1SUBC Correction Value...
Page 461: Chapter 11 Watchdog Timer 2
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 11 WATCHDOG TIMER 2 CHAPTER 11 WATCHDOG TIMER 2 11.1 Functions Watchdog timer 2 is the default-start watchdog timer and starts up automatically immediately after a reset ends.
Page 462: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 11 WATCHDOG TIMER 2 11.2 Configuration Watchdog timer 2 includes the following hardware. Table 11-1. Configuration of Watchdog Timer 2 Item Configuration Control registers...
Page 463: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 11 WATCHDOG TIMER 2 11.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
Page 464 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 11 WATCHDOG TIMER 2 Table 11-2. Loop Detection Time Interval of Watchdog Timer 2 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.)
Page 465: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 11 WATCHDOG TIMER 2 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting is restarted by writing “ACH” to the WDTE register.
Page 466: Chapter 12 Real-Time Output Function (Rto)
Because RTO can output signals without jitter, it is suitable for controlling a stepper motor. In the V850ES/JC3-L and V850ES/JE3-L, one 6-bit real-time output port channel is provided. The real-time output port can be set to the port mode or real-time output port mode in 1-bit units.
Page 467: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.2 Configuration RTO includes the following hardware. Table 12-1. Configuration of RTO Item Configuration Registers Real-time output buffer registers 0L, 0H (RTBL0, RTBH0)
Page 468 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold preset output data.
Page 469: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.3 Registers RTO is controlled using the following two registers. • Real-time output port mode register 0 (RTPM0) •...
Page 470 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port.
Page 471: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits).
Page 472: Usage
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. • Set the alternate-function pins of port 5 Set the PFC5.PFC5m bit and PFCE5.PFCE5m bit to 1, and then set the PMC5.PMC5m bit to 1 (m = 0 to 5).
Page 473: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Overview The A/D converter of the V850ES/JC3-L and V850ES/JE3-L have a resolution of 10 bits and converts an input analog signal into a digital value. The number of A/D converter in the V850ES/JC3-L and V850ES/JE3-L are shown below.
Page 474: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.3 Configuration The A/D converter includes the following hardware. Table 13-1. Configuration of A/D Converter Item Configuration Analog inputs m channels (ANIn pins)
Page 475 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (1) ANIn pins These are analog input pins for the m A/D converter channels and are used to input analog signals to be converted into digital signals.
Page 476 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (10) A/D converter mode register 2 (ADA0M2) This register specifies the hardware trigger mode. (11) A/D converter channel specification register (ADA0S) This register specifies the pin to which the analog voltage to be converted is input.
Page 477: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) •...
Page 478 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (2/2) ADA0ETS1 ADA0ETS0 Specification of external trigger (ADTRG pin) input valid edge No edge detection Falling edge detection Rising edge detection...
Page 479 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units.
Page 480 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Examples of the conversion time for each clock are shown below. Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
Page 481 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0 ADA0 ADA0 A/D Conversion Time Conversion Time...
Page 482 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units.
Page 483 Setting prohibited Setting prohibited Setting prohibited Notes 1. V850ES/JC3-L (48-pin), V850ES/JE3-L only. 2. V850ES/JE3-L only. Cautions 1. In the following modes, write data to the ADA0S register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable A/D conversion (ADA0CE bit = 1).
Page 484 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access.
Page 485 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANIn) and the A/D conversion result (ADA0CRn register) is as follows.
Page 486 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units.
Page 487 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units.
Page 488: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers.
Page 489: Conversion Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.5.2 Conversion timing Figure 13-3. Conversion Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit...
Page 490: Trigger Modes
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.5.3 Trigger modes The timing of starting conversion is specified by setting a trigger mode. The trigger modes include a software trigger mode and hardware trigger modes.
Page 491 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Caution When selecting the external trigger mode, set the high-speed conversion mode. Do not input a trigger during the stabilization time that is inserted once after A/D conversion is enabled (ADA0M0.ADA0CE bit = 1).
Page 492: Operation Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.5.4 Operation mode Four operation modes are available: continuous select mode, continuous scan mode, one-shot select mode, and one- shot scan mode.
Page 493 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-5. Example of Timing in Continuous Scan Mode (ADA0S Register = 03H) (1/2) (a) Timing example ANI0 Data Data...
Page 494 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-5. Example of Timing in Continuous Scan Mode (ADA0S Register = 03H) (2/2) (b) Relationship between analog input pins and A/D conversion result registers...
Page 495 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the voltage of the analog input pin specified by the ADA0S register is converted into a digital value only once.
Page 496 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-7. Example of Timing in One-Shot Scan Mode (ADA0S Register = 03H) (1/2) (a) Timing example ANI0 Data ANI1...
Page 497 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-7. Example of Timing in One-Shot Scan Mode (ADA0S Register = 03H) (2/2) (b) Relationship between analog input pins and A/D conversion result registers...
Page 498: Power-Fail Compare Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.5.5 Power-fail compare mode In this mode, whether the input analog signal voltage is the specified voltage or higher or whether it is lower than the specified voltage is judged, and if the condition specified by the ADA0PFC bit is satisfied, the A/D conversion end interrupt request signal (INTAD) is generated.
Page 499 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register.
Page 500 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-9. Example of Timing in Continuous Scan Mode (When Power-Fail Comparison Is Made: ADA0PFM.ADA0PFC bit = 0, ADA0S Register = 03H) (1/2)
Page 501 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-9. Example of Timing in Continuous Scan Mode (When Power-Fail Comparison Is Made: ADA0PFM.ADA0PFC bit = 0, ADA0S Register = 03H) (2/2)
Page 502 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register.
Page 503 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-11. Example of Timing in One-Shot Scan Mode (When Power-Fail Comparison Is Made: ADA0PFM.ADA0PFC bit = 0, ADA0S Register = 03H) (1/2)
Page 504 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER Figure 13-11. Example of Timing in One-Shot Scan Mode (When Power-Fail Comparison Is Made: ADA0PFM.ADA0PFC bit = 0, ADA0S Register = 03H) (2/2)
Page 505: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0.
Page 506 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (4) Alternate I/O The analog input pins (ANIn) function alternately as port pins. When selecting one of the ANIn pins to execute A/D conversion, do not execute an instruction to read an input port or write to an output port during conversion as the conversion resolution may drop.
Page 507 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (6) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 13-14. Internal Equivalent Circuit of ANIn Pin ANIn 14 kΩ...
Page 508 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (8) Reading ADA0CRn register When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written, the contents of the ADA0CRn register may be undefined.
Page 509 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (13) A/D conversion result hysteresis characteristics The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold capacitor and then performs A/D conversion.
Page 510: How To Read A/D Converter Characteristics Table
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, that is, the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 511 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization...
Page 512 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale −...
Page 513 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 13 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 514: Chapter 14 D/A Converter (V850Es/Jc3-L (48-Pin), V850Es/Je3-L)
CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) 14.1 Functions In the V850ES/JC3-L (48-pin), V850ES/JE3-L, one R-2R ladder type D/A converter channel is provided (DA0CS0). The D/A converter has the following functions. 8-bit resolution × 1 channel R-2R ladder method μ...
Page 515: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) 14.2 Configuration The D/A converter includes the following hardware. Table 14-1. D/A Converter Registers Used by Software...
Page 516: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) 14.3 Registers The registers that control the D/A converter are as follows. • D/A converter mode register (DA0M) •...
Page 517 Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) (2) D/A conversion value setting registers 0 (DA0CS0) The DA0CS0 register sets the analog voltage value output to the ANO0 pin.
Page 518: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CS0 register as the trigger.
Page 519: Cautions
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 14 D/A CONVERTER (V850ES/JC3-L (48-pin), V850ES/JE3-L) 14.4.3 Cautions Observe the following cautions when using the D/A converter. (1) Set the port pins to the input mode (PM10 bit = 1).
Page 520: Chapter 15 Asynchronous Serial Interface A (Uarta)
Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) The number of UARTA channels in the V850ES/JC3-L, V850ES/JE3-L are shown below. Product Name V850ESJC3-L (40-pin) V850ES/JC3-L (48-pin)
Page 521: Configuration
Selector to f Note ASCKA0 UAnCTL1 UAnCTL0 UAnSTR UAnOPT0 UAnCTL2 Internal bus Note UARTA0 only (V850ES/JC3-L (48-pin), V850ES/JE3-L only) Remark For the configuration of the baud rate generator, see Figure 15-17. R01UH0018EJ0001 Rev.0.01 Page 521 of 958 Jul 23, 2010...
Page 522 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the operation of UARTAn.
Page 523: Pin Functions Of Each Channel
15.2.1 Pin functions of each channel The RXDAn, TXDAn, and ASCKA0 pins used by UARTA in the V850ES/JC3-L, V850ES/JE3-L are used for other functions as shown in Table 15-2. To use these pins for UARTA, set the related registers as described in Table 4-17 Settings When Pins Are Used for Alternate Functions.
Page 524: Mode Switching Of Uarta And Other Serial Interfaces
15.3 Mode Switching of UARTA and Other Serial Interfaces 15.3.1 UARTA0 and CSIB4 mode switching In the V850ES/JC3-L (48-pin), V850ES/JE3-L), UARTA0 and CSIB4 share pins and therefore cannot be used simultaneously. To use the UARTA0 function, specify the UARTA0 mode in advance by using the PMC3, PFC3, and PFCE3 registers.
Page 525: Uarta1 And I C02 Mode Switching
15.3.2 UARTA1 and I C02 mode switching In the V850ES/JC3-L (48-pin), V850ES/JE3-L, UARTA1 and I C02 share pins and therefore cannot be used simultaneously. To use the UARTA1 function, specify the UARTA1 mode in advance by using the PMC9, PFC9, and PFCE9 registers.
Page 526: Uarta2 And I C00 Mode Switching
15.3.3 UARTA2 and I C00 mode switching In the V850ES/JC3-L (48-pin), V850ES/JE3-L, UARTA2 and I C00 share pins and therefore cannot be used simultaneously. To use the UARTA2 function, specify the UARTA2 mode in advance by using the PMC3 and PFC3 registers.
Page 527: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.4 Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation.
Page 528 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnDIR Data transfer order MSB first LSB first • This register can be rewritten only when the UAnPWR bit is 0 or the UAnTXE bit and the UAnRXE bit are 0.
Page 529 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register used to control SBF transmission/reception in the LIN communication format and the level of the transmission/reception signals for the UARTAn.
Page 530 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnSLS2 UAnSLS1 UAnSLS0 SBF transmit length selection 13-bit output (initial value) 14-bit output 15-bit output 16-bit output...
Page 531 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H <2> <1> <7> <0> UAnSTR UAnTSF UAnPE...
Page 532 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register.
Page 533 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (7) UARTAn transmit data register (UAnTX) The UAnTX register is an 8-bit register used to set transmit data.
Page 534: Interrupt Request Signals
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. • Reception complete interrupt request signal (INTUAnR) •...
Page 535: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6 Operation 15.6.1 Data format As shown in Figure 15-5, one frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 536 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-5. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H...
Page 537: Uart Transmission
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.2 UART transmission Transmission is enabled by setting the UAnCTL0.UAnPWR and UAnCTL0.UAnTXE bits to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 538: Continuous Transmission Procedure
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.3 Continuous transmission procedure Writing transmit data to the UAnTX register with transmission enabled triggers transmission. The data in the UAnTX register is transferred to the UARTAn transmit shift register, the transmission enable interrupt request signal (INTUAnT) is generated, and then shifting is started.
Page 539 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-8. Continuous Transmission Operation Timing (a) Transmission start TXDAn Start Data (1) Parity Stop Start Data (2)
Page 540: Uart Reception
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.4 UART reception First, enable reception by executing the following operations and monitor the RXDAn input to detect the start bit.
Page 541 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely.
Page 542: Reception Errors
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.5 Reception errors Three types of errors can occur during reception: parity errors, framing errors, and overrun errors. The data reception result error flag is set in the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output when an error occurs.
Page 543 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Table 15-5. Reception Error Causes Error Flag Reception Error Cause UAnPE Parity error The received parity bit does not match the setting.
Page 544: Parity Types And Operations
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.6 Parity types and operations The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 545: Lin Transmission/Reception Format
V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.7 LIN transmission/reception format The V850ES/JC3-L, V850ES/JE3-L have an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to reduce costs of automotive networks.
Page 546 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-12. LIN Reception Format Wake-up Sync Check signal break Sync DATA DATA frame field (SBF) field...
Page 547: Sbf Transmission
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.8 SBF transmission When the UAnCTL0.UAnPWR bit and UAnCTL0.UAnTXE bit are 1, the transmission enabled status is entered, and SBF transmission is started by setting the SBF transmission trigger (UAnOPT0.UAnSTT bit) to 1.
Page 548: Sbf Reception
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.9 SBF reception The reception enabled status is entered by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1.
Page 549: Receive Data Noise Filter
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.10 Receive data noise filter This filter samples signals received via the RXDAn pin using the base clock supplied by the dedicated baud rate generator.
Page 550: Dedicated Baud Rate Generator
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter block, and generates a serial clock during transmission and reception using UARTAn.
Page 551 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock.
Page 552 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn.
Page 553 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. UCLK Baud rate = [bps] 2 ×...
Page 554 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) To set the baud rate, perform the following calculation for setting the UAnCTL1 and UAnCTL2 registers (when using the internal clock).
Page 555 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below.
Page 556 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11)
Page 557 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Data frame length during continuous transmission In continuous transmission, the data frame length from the stop bit to the next start bit is 2 base clock cycles longer than usual.
Page 558: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.8 Cautions (1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped.
Page 559: Chapter 16 Clocked Serial Interface B (Csib)
Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) The number of CSIB channels in the V850ES/JC3-L, V850ES/JE3-L are shown below. Product Name V850ESJC3-L (40-pin) V850ES/JC3-L (48-pin)
Page 560: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.2 Configuration CSIBn includes the following hardware. Table 16-1. Configuration of CSIBn Item Configuration Registers CSIBn receive data register (CBnRX)
Page 561: Pin Functions Of Each Channel
16.2.1 Pin functions of each channel The SIBn, SOBn, and SCKBn pins used by CSIB in the V850ES/JC3-L, V850ES/JE3-L are used for other functions as shown in Table 16-2. To use these pins for CSIB, set the related registers as described in Table 4-17 Settings When Pins Are Used for Alternate Functions.
Page 562: Mode Switching Of Csib And Other Serial Interfaces
16.3.1 CSIB0 and I C01 mode switching In the V850ES/JC3-L and V850ES/JE3-L, CSIB0 and I C01 share pins and therefore cannot be used simultaneously. To use the CSIB0 function, specify the CSIB0 mode in advance by using the PMC4 and PFC4 registers.
Page 563: Csib4 And Uarta0 Mode Switching
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.3.2 CSIB4 and UARTA0 mode switching In the V850ES/JE3-L, CSIB4 and UARTA0 share pins and therefore cannot be used simultaneously. To use the CSIB4 function, specify the CSIB4 mode in advance by using the PMC3, PFC3, and PFCE3L registers.
Page 564: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.4 Registers The following registers are used to control CSIBn. • CSIBn receive data register (CBnRX) • CSIBn transmit data register (CBnTX) •...
Page 565 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (2) CSIBn transmit data register (CBnTX) The CBnTX register is a 16-bit buffer register used to write the CSIBn transfer data.
Page 566 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (3) CSIBn control register 0 (CBnCTL0) CBnCTL0 is an 8-bit register that controls CSIBn serial transfer. This register can be read or written in 8-bit or 1-bit units.
Page 567 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (2/3) Note CBnDIR Specification of transfer direction mode (MSB/LSB) MSB-first transfer LSB-first transfer Note CBnTMS Transfer mode specification...
Page 568 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (3/3) CBnSCE Specification of start transfer disable/enable Communication start trigger invalid Communication start trigger valid This bit enables or disables the communication start trigger in reception mode.
Page 569 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (4) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that is used to specify the CSIBn serial transfer operation mode.
Page 570 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (5) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that is used to specify the CSIBn serial transfer data length.
Page 571 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (a) Changing the transfer data length The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits.
Page 572 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (6) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only.
Page 573: Interrupt Request Signals
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.5 Interrupt Request Signals CSIBn can generate the following two interrupt request signals. • Reception complete interrupt request signal (INTCBnR) •...
Page 574: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6 Operation 16.6.1 Single transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),...
Page 575 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-6. Single Transfer Mode Operation Timing (Master Mode, Transmission Mode) CBnTSF bit INTCBnR signal SCKBn pin...
Page 576: Single Transfer Mode (Master Mode, Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),...
Page 577 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-8. Single Transfer Mode Operation Timing (Master Mode, Reception Mode) CBnTSF bit INTCBnR signal SCKBn pin...
Page 578: Single Transfer Mode (Master Mode, Transmission/Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),...
Page 579 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-10. Single Transfer Mode Operation Timing (Master Mode, Transmission/Reception Mode) CBnTSF bit INTCBnR signal SCKBn pin...
Page 580: Single Transfer Mode (Slave Mode, Transmission Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer...
Page 581 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-12. Single Transfer Mode Operation Timing (Slave Mode, Transmission Mode) CBnTSF bit INTCBnR signal SCKBn pin...
Page 582: Single Transfer Mode (Slave Mode, Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.5 Single transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer...
Page 583 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-13. Single Transfer Mode Operation (Slave Mode, Reception Mode) START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ←...
Page 584 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-14. Single Transfer Mode Operation Timing (Slave Mode, Reception Mode) CBnTSF bit INTCBnR signal SCKBn pin...
Page 585: Single Transfer Mode (Slave Mode, Transmission/Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer...
Page 586 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-16. Single Transfer Mode Operation Timing (Slave Mode, Transmission/Reception Mode) CBnTSF bit INTCBnR signal SCKBn pin...
Page 587: Continuous Transfer Mode (Master Mode, Transmission Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),...
Page 588 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-18. Continuous Transfer Mode Operation Timing (Master Mode, Transmission Mode) CBnTSF bit INTCBnT signal INTCBnR signal...
Page 589: Continuous Transfer Mode (Master Mode, Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),...
Page 590 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-19. Continuous Transfer Mode Operation (Master Mode, Reception Mode) START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ←...
Page 591 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-20. Continuous Transfer Mode Operation Timing (Master Mode, Reception Mode) CBnTSF bit INTCBnR signal CBnSCE bit...
Page 592: Continuous Transfer Mode (Master Mode, Transmission/Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00),...
Page 593 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-21. Continuous Transfer Mode Operation (Master Mode, Transmission/Reception Mode) START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ←...
Page 594 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-22. Continuous Transfer Mode Operation Timing (Master Mode, Transmission/Reception Mode) (1/2) CBnTSF bit INTCBnT signal INTCBnR signal...
Page 595 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-22. Continuous Transfer Mode Operation Timing (Master Mode, Transmission/Reception Mode) (2/2) (11) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated.
Page 596: Continuous Transfer Mode (Slave Mode, Transmission Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer...
Page 597 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-24. Continuous Transfer Mode Operation Timing (Slave Mode, Transmission Mode) CBnTSF bit INTCBnT signal SCKBn pin...
Page 598: Continuous Transfer Mode (Slave Mode, Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer...
Page 599 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-25. Continuous Transfer Mode Operation (Slave Mode, Reception Mode) START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ←...
Page 600 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-26. Continuous Transfer Mode Operation Timing (Slave Mode, Reception Mode) CBnTSF bit INTCBnR signal CBnSCE bit...
Page 601: Continuous Transfer Mode (Slave Mode, Transmission/Reception Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer...
Page 602 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-27. Continuous Transfer Mode Operation (Slave Mode, Transmission/Reception Mode) START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ←...
Page 603 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-28. Continuous Transfer Mode Operation Timing (Slave Mode, Transmission/Reception Mode) CBnTSF bit INTCBnT signal INTCBnR signal...
Page 604: Reception Errors
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.13 Reception errors When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the reception complete interrupt request signal (INTCBnR) is generated again if the next receive operation is completed before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag (CBnSTR.CBnOVE) is set to...
Page 605: Clock Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.6.14 Clock timing Figure 16-30. Clock Timing (1/2) (i) Communication type 1 (CBnCKP and CBnDAP bits = 00)
Page 606 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) Figure 16-30. Clock Timing (2/2) (iii) Communication type 2 (CBnCKP and CBnDAP bits = 01) SCKBn pin...
Page 607: Output Pins
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.7 Output Pins (1) SCKBn pin When CSIBn is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows.
Page 608: Baud Rate Generator
BRG3 Note1 BRG3 CSIB4 Notes 1. V850ES/JC3-L (48-pin), V850ES/JE3-L only 2. V850ES/JE3-L only (1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3) The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIBn. These registers can be read or written in 8-bit or 1-bit units.
Page 609: Baud Rate Generation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) (2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3) The PRSCM1 to PRSCM3 registers are 8-bit compare registers.
Page 610: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB) 16.9 Cautions When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer.
Page 611: Chapter 17 I C Bus
P91/SCL02 pins as the serial transmit/receive data I/O pins (SDA00 to SDA02) and serial clock I/O pins (SCL00 to SCL02), and set them to N-ch open-drain output. The number of I C channels in the V850ES/JC3-L, V850ES/JE3-L are shown below. Product Name V850ESJC3-L (40-pin)
Page 612: Mode Switching Of I
C Bus and Other Serial Interfaces 17.1.1 UARTA2 and I C00 mode switching In the V850ES/JC3-L and V850ES/JE3-L, UARTA2 and I C00 share pins and therefore cannot be used simultaneously. Set the operation mode to I C00 in advance, using the PMC3 and PFC3 registers.
Page 613: Csib0 And I 2 C01 Mode Switching
C BUS 17.1.2 CSIB0 and I C01 mode switching In the V850ES/JC3-L and V850ES/JE3-L, CSIB0 and I C01 share pins and therefore cannot be used simultaneously. Set the operation mode to I C01 in advance, using the PMC4 and PFC4 registers.
Page 614: Uarta1 And I 2 C02 Mode Switching
C BUS 17.1.3 UARTA1 and I C02 mode switching In the V850ES/JC3-L and V850ES/JE3-L, UARTA1 and I C02 share pins and therefore cannot be used simultaneously. Set the operation mode to I C02 in advance, using the PMC9, PFC9, and PFCE9 registers.
Page 615: Features
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.2 Features C0n have the following two modes. • Operation stopped mode • I C (Inter IC) bus mode (multimasters supported) (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption.
Page 616: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.3 Configuration The block diagram of the I C0n is shown below. Figure 17-4. Block Diagram of I Internal bus...
Page 617 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS A serial bus configuration example is shown below. Figure 17-5. Serial Bus Configuration Example Using I C Bus Master CPU1...
Page 618 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS C0n includes the following hardware. Table 17-1. Configuration of I Item Configuration Registers IIC shift register n (IICn) Slave address register n (SVAn)
Page 619 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers.
Page 620: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.4 Registers C0n is controlled by the following registers. • IIC control registers n (IICCn) • IIC status registers n (IICSn) •...
Page 621 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (1/4) After reset: 00H Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H <7> <6> <5> <4> <3> <2> <1> <0>...
Page 622 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (2/4) Note SPIEn Enable/disable generation of interrupt request when stop condition is detected Disabled Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) •...
Page 623 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (3/4) STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCLn line is high level and then the start condition is generated.
Page 624 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer).
Page 625 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (2) IIC status registers n (IICSn) The IICSn register indicates the status of I C0n. These registers are read-only, in 8-bit or 1-bit units. However, the IICSn register can only be read when the IICCn.STTn bit is 1 or during the wait period.
Page 626 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (2/3) COIn Matching address detection Addresses do not match. Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) •...
Page 627 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (3/3) STDn Start condition detection Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect...
Page 628 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (3) IIC flag registers n (IICFn) The IICFn register sets the I C0n operation mode and indicates the I C bus status.
Page 629 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Note After reset: 00H Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH, IICF2 FFFFFDAAH <7> <6> <1> <0> IICFn STCFn IICBSYn STCENn...
Page 630 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (4) IIC clock select registers n (IICCLn) The IICCLn register sets the transfer clock for I C0n. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only.
Page 631 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (5) IIC function expansion registers n (IICXn) The IICXn register sets I C0n function expansion (valid only in the high-speed mode).
Page 632 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Table 17-2. Clock Settings (1/2) IICX0 IICCL0 Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range...
Page 633 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Table 17-2. Clock Settings (2/2) IICXm IICCLm Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range...
Page 634 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKSm register controls the I C0n division clock (m = 0, 1).
Page 635 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (9) Slave address registers n (SVAn) The SVAn register holds the I C bus’s slave address. These registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. However, rewriting this register is prohibited when the IICSn.STDn bit = 1 (start condition detection).
Page 636: Pin Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows. SCL0n ....This pin is used for serial clock input and output.
Page 637: I C Bus Definitions And Control Methods
1). When a start condition is detected, the IICSn.STDn bit is set (1) . Caution When the IICCn.IICEn bit of the V850ES/JC3-L and V850ES/JE3-L are set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line.
Page 638: Addresses
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 639: Transfer Direction Specification
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 640: Ack
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives.
Page 641: Stop Condition
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition.
Page 642: Wait State
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state).
Page 643 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-13. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1)
Page 644: Wait State Cancellation Method
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.6.7 Wait state cancellation method In the case of I C0n, a wait state can be canceled normally in the following ways.
Page 645: I C Interrupt Request Signals (Intiicn)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing.
Page 646 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0...
Page 647 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓...
Page 648: Slave Device Operation (When Receiving Slave Address Data (Address Match))
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.7.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1>...
Page 649 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match)
Page 650 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception)
Page 651 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code))
Page 652: Slave Device Operation (When Receiving Extension Code)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0...
Page 653 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match)
Page 654 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception)
Page 655 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code))
Page 656: Operation Without Communication
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1...
Page 657 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0...
Page 658: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data...
Page 659 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ3...
Page 660 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch)
Page 661 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (5) When arbitration loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn Δ2 1: IICSn register = 1000X110B Δ...
Page 662 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1>...
Page 663 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ↓...
Page 664 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1>...
Page 665: Interrupt Request Signal (Intiicn) Generation Timing And Wait Control
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below.
Page 666 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS (4) Wait cancellation method The following four wait cancellation methods are available. • By setting the IICCn.WRELn bit to 1 •...
Page 667: Address Match Detection Method
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.9 Address Match Detection Method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
Page 668: Arbitration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is...
Page 669: Wakeup Function
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Table 17-5. Status During Arbitration and Interrupt Request Signal Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1...
Page 670: Communication Reservation
IICCn.LRELn bit was set to 1). If the IICCn.STTn bit is set to 1 while the bus is not used by the V850ES/JC3-L and V850ES/JE3-L, a start condition is automatically generated and a wait status is set after the bus is released (after a stop condition is detected).
Page 671 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Table 17-6. Wait Periods Clock Selection CLXn SMCn CLn1 CLn0 Wait Period (when OCKSm = 18H set) 26 clocks...
Page 672 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-15. Communication Reservation Timing STTn Write to Program processing IICn Set SPDn Communication Hardware processing reservation and INTIICn...
Page 673 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS The communication reservation flowchart is illustrated below. Figure 17-17. Communication Reservation Flowchart SET1 STTn Sets STTn bit (communication reservation).
Page 674: When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) If the IICCn.STTn bit is set when the bus is not being used by the V850ES/JC3-L and V850ES/JE3-L in a bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used by the V850ES/JC3-L and V850ES/JE3-L.
Page 675: Cautions
(3) When the IICCn.IICEn bit of the V850ES/JC3-L and V850ES/JE3-L is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line.
Page 676: Communication Operations
Next the following three operations are shown using flowcharts. (1) Master operation in single master system The flowchart when using the V850ES/JC3-L and V850ES/JE3-L as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
Page 677: Master Operation In Single Master System
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.16.1 Master operation in single master system Figure 17-18. Master Operation in Single Master System START Note Initialize I...
Page 678: Master Operation In Multimaster System
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.16.2 Master operation in multimaster system Figure 17-19. Master Operation in Multimaster System (1/3) START Refer to Table 4-17 Settings When Pins Are Used for Alternate Functions...
Page 679 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-19. Master Operation in Multimaster System (2/3) Communication reservation enabled Communication start preparation STTn = 1 (start condition generation)
Page 680 Remarks 1. Conform the transmission and reception formats to the specifications of the product involved in the communication. 2. When using the V850ES/JC3-L and V850ES/JE3-L as the master in a multimaster system, read the IICSn.MSTSn bit for each INTIICn interrupt occurrence to confirm the arbitration result.
Page 681: Slave Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.16.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 682 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS For reception, the required number of data items are received and ACK is not returned for the next data immediately after transfer is complete.
Page 683 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here).
Page 684: Timing Of Data Communication
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS 17.17 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner.
Page 685 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
Page 686 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
Page 687 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
Page 688 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-24. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master and 9-Clock Wait Is Selected for Slave) (1/3)
Page 689 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-24. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master and 9-Clock Wait Is Selected for Slave (2/3)
Page 690 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 17 I C BUS Figure 17-24. Example of Slave to Master Communication (When Wait Is Changed from 8 Clocks to 9 Clocks for Master and 9-Clock Wait Is Selected for Slave) (3/3)
Page 691: Chapter 18 Dma Function (Dma Controller)
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) The V850ES/JC3-L and V850ES/JE3-L include a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/Os, or between I/Os based on DMA requests issued by on- chip peripheral I/O (serial interfaces, timer/counters, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM).
Page 692: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.2 Configuration The block diagram of the DMAC is shown below. Figure 18-1. Block Diagram of DMAC On-chip...
Page 693 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) The DMAC includes the following hardware. Table 18-1. Configuration of DMAC Item Configuration Registers DMA source address registers 0 to 3 (DSA0 to DSA3)
Page 694: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3).
Page 695 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3).
Page 696 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (3) DMA transfer count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3).
Page 697 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3).
Page 698 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control DMA transfer for DMA channel n.
Page 699 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O.
Page 700 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Table 18-2. DMA Start Factors (1/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source JC3L(40) JC3L(48) JE3L DMA request by interrupt disabled INTP0 −...
Page 701 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Table 18-2. DMA Start Factors (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source JC3L(40) JC3L(48) JE3L INTCB2R INTCB2T −...
Page 702: Transfer Sources And Destinations
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.4 Transfer Sources and Destinations Table 18-3 shows the relationship between the transfer sources and destinations (√: Transfer enabled, ×: Transfer disabled).
Page 703: Transfer Types
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.6 Transfer Types Two-cycle transfer is supported as the transfer type. In two-cycle transfer, data is transferred in two cycles, a read cycle and a write cycle.
Page 704: Dma Channel Priorities
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 When the DMAC has released the bus, if another DMA transfer request that has a higher priority is issued, the one that has the higher priority always takes precedence.
Page 705: Time Related To Dma Transfer
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below.
Page 706: Dma Transfer Start Factors
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the DCHCn.STGn bit is set to 1 while the DCHCn.TCn bit is 0 and DCHCn.Enn bit is 1 (DMA transfer enabled),...
Page 707: End Of Dma Transfer
(INTC) (n = 0 to 3). The V850ES/JC3-L and V850ES/JE3-L do not output a terminal count signal to an external device. Therefore, confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
Page 708 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized.
Page 709 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (b) Repeatedly setting the INITn bit until transfer is forcibly terminated correctly <1> Before starting DMA, copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose register.
Page 710 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (8) Bus arbitration for CPU Because the DMA controller is a higher priority bus master than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU.
Page 711 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (12) Read values of DSAn and DDAn registers If the DSAn and DDAn registers are read during a DMA transfer, the values before and after the registers were updated might be read.
Page 712: Chapter 19 Interrupt Servicing/Exception Processing Function
V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION The V850ES/JC3-L and V850ES/JE3-L are provided with an interrupt controller dedicated to interrupt servicing (INTC) and can handle a total of 49/53/58 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 713 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (1/3) Type Default Name Trigger Generating Exception Handler Interrupt Control Priority Unit Code...
Page 714 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (2/3) Type Default Name Trigger Generating Exception Handler Interrupt Priority Unit Code Address...
Page 715 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (3/3) Type Default Name Trigger Generating Exception Handler Interrupt Control Priority Unit Code...
Page 716: Non-Maskable Interrupts
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged even when interrupts are disabled (DI) by the CPU. A non- maskable interrupt is not subject to priority control and takes precedence over all the other interrupt request signals.
Page 717 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Figure 19-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2) (b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing...
Page 718: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing and transfers control to the handler routine.
Page 719: Restoration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.2.2 Restoration (1) From NMI pin input Execution is returned from NMI servicing by using the RETI instruction.
Page 720: Np Flag
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION (2) From INTWDT2 signal Non-maskable interrupt servicing executed by INTWDT2 cannot be returned from by using the RETI instruction. To return from such servicing, execute the following software reset processing.
Page 721: Maskable Interrupts
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JC3-L and V850ES/JE3- L have 47/51/56 maskable interrupt sources.
Page 722 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Figure 19-5. Maskable Interrupt Servicing INT input INTC processing xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt...
Page 723: Restoration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.3.2 Restoration Execution is returned from maskable interrupt servicing by using the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC.
Page 724: Priorities Of Maskable Interrupts
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.3.3 Priorities of maskable interrupts The INTC can acknowledge an interrupt while servicing another. Interrupts that occur at the same time are serviced according to their priority order.
Page 725 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2)
Page 726 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2)
Page 727 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Figure 19-8. Example of Servicing Interrupt Requests Generated Simultaneously Main routine Interrupt request a (level 2) Note 1...
Page 728: Interrupt Control Register (Xxicn)
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.3.4 Interrupt control register (xxICn) An xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request.
Page 729 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Table 19-3. Interrupt Control Registers (xxICn) (1/2) Address Register <7> <6> FFFFF110H LVIIC LVIIF LVIMK LVIPR2 LVIPR1 LVIPR0...
Page 730: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Table 19-3. Interrupt Control Registers (xxICn) (2/2) Address Register <7> <6> Note1 FFFFF160H CB3TIC CB3TIF CB3TMK CB3TPR2 CB3TPR1...
Page 731 2. For the V850ES/JE3-L, 0 or 1 can be specified for this bit. For the V850ES/JC3-L, this bit must be set to 1. 3. For the V850ES/JE3-L and V850ES/JC3-L (48-pin), 0 or 1 can be specified for this bit. For the V850ES/JC3-L (40-pin), this bit must be set to 1.
Page 732: In-Service Priority Register (Ispr)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced.
Page 733: Id Flag
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.3.7 ID flag This flag stores information regarding enabling or disabling maskable interrupt request signals. The interrupt disable flag (ID) is assigned to the PSW.
Page 734: Software Exception
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.4 Software Exception A software exception occurs when the CPU executes the TRAP instruction, and can always be acknowledged.
Page 735: Restoration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.4.2 Restoration Execution is returned from software exception processing by the using RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC.
Page 736: Ep Flag
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.4.3 EP flag The EP flag is a status flag that indicates that exception processing is in progress. This flag is set when an exception occurs.
Page 737: Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/JC3-L and V850ES/JE3-L, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is used as an exception trap. 19.5.1 Illegal opcode An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B.
Page 738 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION Figure 19-11. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restoration Execution is returned from an exception trap by using the DBRET instruction.
Page 739 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.5.2 Debug trap A debug trap is an exception that occurs when the DBTRAP instruction is executed and can always be acknowledged.
Page 740 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION (2) Restoration Execution is returned from a debug trap by using the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC.
Page 741: Multiple Interrupt Servicing Control
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.6 Multiple Interrupt Servicing Control In multiple interrupt servicing control, the servicing of an interrupt is stopped if an interrupt request signal that has a higher priority level is generated.
Page 742: External Interrupt Request Input Pins (Nmi, Intp0 To Intp7)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.7 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) 19.7.1 Noise elimination (1) Noise elimination for NMI pin The NMI pin has an internal noise eliminator that uses analog delay (several 10 ns).
Page 743 INTP2 INTP1 INTP0 Note For the V850ES/JE3-L, 0 or 1 can be specified for this bit. For the V850ES/JC3-L, this bit must be cleared to 0. Remark For how to specify a valid edge, see Table 19-4. Table 19-4. Valid Edge Specification...
Page 744 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION (2) External interrupt falling, rising edge specification register 3 (INTF3, INTR3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP7).
Page 745 INTP6 INTP5 INTP4 Note For the V850ES/JE3-L, 0 or 1 can be specified for this bit. For the V850ES/JC3-L, this bit must be cleared to 0. Remark For how to specify a valid edge, see Table 19-6. Table 19-6. Valid Edge Specification...
Page 746 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION (4) Noise elimination control register (NFC) (V850ES/JE3-L only) Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are specified by using the NFC register.
Page 747 Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION An example of the timing of noise elimination performed by the timer T input pin digital filter is shown Figure 19-15.
Page 748: Interrupt Response Time Of Cpu
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.8 Interrupt Response Time of CPU Except for the following cases, the interrupt response time of the CPU is at least 4 clock cycles. To input interrupt request signals successively, input the next interrupt request signal at least 5 clock cycles after the preceding interrupt.
Page 749: Periods In Which Interrupts Are Not Acknowledged By Cpu
Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 19 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION 19.9 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (the interrupt is held pending).
Page 750: Chapter 20 Key Interrupt Function
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 20 KEY INTERRUPT FUNCTION CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register.
Page 751: Pin Functions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 20 KEY INTERRUPT FUNCTION 20.2 Pin Functions The key input pins that are used as key interrupts are also used for the other functions shown in Table 20-2. To use these pins as key interrupts, this function must be specified by setting the relevant registers (see Table 4-17 Settings When Pins Are Used for Alternate Functions).
Page 752: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 20 KEY INTERRUPT FUNCTION 20.4 Cautions (1) If a low level is input to any of the KR0 to KR7 pins, the INTKR signal is not generated even if the falling edge is input to another pin.
Page 753: Chapter 21 Standby Function
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION CHAPTER 21 STANDBY FUNCTION 21.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application.
Page 754 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Figure 21-1. Status Transition Reset Sub-IDLE mode operates, PLL operates) Oscillation Note stabilization wait Normal operation mode Subclock Clock through mode...
Page 755: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the standby mode.
Page 756 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation.
Page 757 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the setup time until the internal flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register.
Page 758 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION (4) Regulator protection register (REGPR) The REGPR register is used to protect the regulator output voltage level control register 0 (REGOVL0) so that illegal data is not written to REGOVL0.
Page 759 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION (5) Regulator output voltage level control register 0 (REGOVL0) This register is used to select the low-voltage STOP mode, low-voltage subclock operation mode, or low-voltage sub-IDLE mode.
Page 760: Halt Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.3 HALT Mode 21.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
Page 761 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-3. Operating Status in HALT Mode Setting of HALT Mode Operating Status Item When Subclock Is Not Used When Subclock Is Used...
Page 762: Idle1 Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.4 IDLE1 Mode 21.4.1 Setting and operation status The IDLE1 mode is set by clearing the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode.
Page 763: Releasing Idle1 Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.4.2 Releasing IDLE1 mode The IDLE1 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked...
Page 764 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-5. Operating Status in IDLE1 Mode Setting of IDLE1 Mode Operating Status Item When Subclock Is Not Used When Subclock Is Used...
Page 765: Idle2 Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.5 IDLE2 Mode 21.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode.
Page 766: Releasing Idle2 Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.5.2 Releasing IDLE2 mode The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked...
Page 767 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-7. Operating Status in IDLE2 Mode Setting of IDLE2 Mode Operating Status Item When Subclock Is Not Used When Subclock Is Used...
Page 768: Securing Setup Time When Releasing Idle2 Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.5.3 Securing setup time when releasing IDLE2 mode Setting the IDLE2 mode stops the operation of blocks other than the main clock oscillator, so the setup time specified by the OSTS register for the PLL or the flash memory is automatically secured after the IDLE2 mode is released.
Page 769: Stop Mode/Low-Voltage Stop Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.6 STOP Mode/Low-Voltage STOP Mode 21.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode.
Page 770 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION (1) Procedure for switching from normal mode to low-voltage STOP mode Specify the following settings in the normal operation mode (while the main clock is operating). In addition, set up the OSTS register as necessary.
Page 771 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-8. Operating Status in STOP Mode Setting of STOP Mode Operating Status Item When Subclock Is Not Used When Subclock Is Used...
Page 772 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-9. Operating Status in Low-Voltage STOP Mode Setting of Low-Voltage Operating Status STOP Mode When Subclock Is Not Used...
Page 773: Releasing Stop Mode/Low-Voltage Stop Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.6.2 Releasing STOP mode/low-voltage STOP mode The STOP mode/low-voltage STOP mode is released by a non-maskable interrupt request signal (NMI pin input,...
Page 774: Re-Setting After Release Of Low-Voltage Stop Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.6.3 Re-setting after release of low-voltage STOP mode (1) If low-voltage STOP mode is released by interrupt The status after the low-voltage STOP mode has been released is as follows.
Page 775: Securing Oscillation Stabilization Time When Releasing Stop Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.6.4 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set.
Page 776: Subclock Operation Mode/Low-Voltage Subclock Operation Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.7 Subclock Operation Mode/Low-Voltage Subclock Operation Mode 21.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. The low-voltage subclock operation mode is set by setting the REGOVL0 register to 02H in the subclock operation mode.
Page 777 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION (1) Procedure for switching from subclock operation mode to low-voltage subclock operation mode Make the following settings in the subclock operation mode.
Page 778 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-11. Operating Status in Subclock Operation Mode Setting of Subclock Operation Mode Operating Status Item When Main Clock Is Oscillating...
Page 779 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-12. Operating Status in Low-Voltage Subclock Operation Mode Setting of Low-Voltage Operating Status Subclock Operation Main Clock Is Stopped (Must Be Stopped)
Page 780: Releasing Subclock Operation Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.7.2 Releasing subclock operation mode The subclock operation mode is released by a reset signal (reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)) when the CK3 bit is set to 0.
Page 781: Sub-Idle Mode/Low-Voltage Sub-Idle Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode 21.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode.
Page 782 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Be sure to observe the above sequence. For the setting of the subclock operation mode, see 21.7.1 Setting and operation status.
Page 783 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION Table 21-14. Operating Status in Low-Voltage Sub-IDLE Mode Setting of Low-Voltage Operating Status Sub-IDLE Mode Main Clock Is Stopped (Must Be Stopped)
Page 784: Releasing Sub-Idle Mode/Low-Voltage Sub-Idle Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 21 STANDBY FUNCTION 21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode The sub-IDLE mode/low-voltage sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input,...
Page 785: Chapter 22 Reset Function
22.1 Overview The reset function is used to initialize the settings of the V850ES/JC3-L and V850ES/JE3-L functions. This function is used, for example, to stop operation at power-on until the supply voltage reaches the operation voltage level, or to initialize the settings of the V850ES/JC3-L and V850ES/JE3-L functions at any time.
Page 786: Configuration
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION 22.2 Configuration Figure 22-1. Block Diagram of Reset Function Internal bus Reset source flag register (RESF) WDT2RF CLMRF LVIRF WDT2 reset signal...
Page 787: Register To Check Reset Source
CHAPTER 22 RESET FUNCTION 22.3 Register to Check Reset Source The V850ES/JC3-L and V850ES/JE3-L have four reset sources. The source of the reset that occurred can be checked by using the reset source flag register (RESF) immediately after a reset ends.
Page 788: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION 22.4 Operation 22.4.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized.
Page 789 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION Figure 22-2. Timing of Reset Operation by RESET Pin Input Initialized to f RESET Analog delay Analog delay Analog delay...
Page 790 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION Figure 22-3. Timing of Power-on Reset Operation Initialized to f RESET Analog delay Internal system reset signal Oscillation stabilization time count...
Page 791: Reset Operation By Watchdog Timer 2
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION 22.4.2 Reset operation by watchdog timer 2 When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status.
Page 792 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION Figure 22-4. Timing of Reset Operation by WDT2RES Signal Generation Initialized to f WDT2RES Analog delay Internal system reset signal...
Page 793: Reset Operation By Low-Voltage Detector
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION 22.4.3 Reset operation by low-voltage detector If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status.
Page 794: Operation Immediately After Reset Ends
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION 22.4.4 Operation immediately after reset ends (1) Immediately after reset ends normally Immediately after a reset ends, the main clock starts oscillating, the oscillation stabilization time (which differs depending on the option byte;...
Page 795 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION (2) Emergency operation mode If an anomaly occurs in the main clock before the oscillation stabilization time is secured, WDT2 overflows before the CPU starts executing the program.
Page 796: Reset Function Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 22 RESET FUNCTION 22.4.5 Reset function operation Figure 22-7. Reset Function Operation Start (reset source generated) Note 1 Set RESF register → Reset occurs...
Page 797: Cautions
The usable range of the internal operating frequency of the V850ES/JC3-L and V850ES/JE3-L depend on the supply voltage (5 MHz (MAX.) @ 2.2 to 2.7 V or 20 MHz (MAX.) @ 2.7 to 3.6 V).
Page 798: Chapter 23 Clock Monitor
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 23 CLOCK MONITOR CHAPTER 23 CLOCK MONITOR 23.1 Functions The clock monitor monitors the main clock by using the internal oscillator clock and generates a reset request signal when oscillation of the main clock is stopped.
Page 799: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 23 CLOCK MONITOR 23.3 Registers The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register that can only be written in a combination of specific sequences (see 3.4.7...
Page 800: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 23 CLOCK MONITOR 23.4 Operation This section describes the clock monitor operation. The monitoring start and monitoring stop conditions are as follows. <Monitoring start condition >...
Page 801 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 23 CLOCK MONITOR (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit is 1, an internal reset signal is generated as shown in Figure 23-2.
Page 802 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 23 CLOCK MONITOR (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted.
Page 803: Chapter 24 Low-Voltage Detector (Lvi)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.1 Functions The low-voltage detector (LVI) has the following functions. • If interrupt occurrence at low-voltage detection is selected as the operation mode, the low-voltage detector compares...
Page 804: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.3 Registers The low-voltage detector is controlled by the following registers. • Low voltage detection register (LVIM) • Low voltage detection level select register (LVIS) (1) Low voltage detection register (LVIM) The LVIM register is a special register.
Page 805 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) (2) Low voltage detection level select register (LVIS) The LVIS register is used to select the level of voltage to be detected.
Page 806: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4 Operation Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated.
Page 807: To Use For Interrupt
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4.2 To use for interrupt <To start operation> <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS.LVIS0 bit.
Page 808: Chapter 25 Crc Function
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 25 CRC FUNCTION CHAPTER 25 CRC FUNCTION 25.1 Functions • Generation of CRC (Cyclic Redundancy Check) code for detecting errors in communication data •...
Page 809: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 25 CRC FUNCTION 25.3 Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units.
Page 810: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 25 CRC FUNCTION 25.4 Operation An example of the operation of the CRC circuit is shown below. Figure 25-2. CRC Circuit Operation Example (LSB First)
Page 811: Usage
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 25 CRC FUNCTION 25.5 Usage How to use the CRC logic circuit is described below. Figure 25-3. CRC Operation Start Write 0000H to CRCD register...
Page 812 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 25 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes.
Page 813: Chapter 26 Regulator
CHAPTER 26 REGULATOR CHAPTER 26 REGULATOR 26.1 Outline The V850ES/JC3-L and V850ES/JE3-L include a regulator to reduce power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffers).
Page 814 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 26 REGULATOR Figure 26-2. Regulator (V850ES/JC3-L (48-pin), V850ES/JE3-L) A/D converter I/O buffer REF0 D/A converter REF1 FLMD0 Flash Regulator memory REGC Internal digital circuits...
Page 815: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 26 REGULATOR 26.2 Operation The regulator connected to V always operates in all modes (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, subclock operation mode, sub-IDLE mode, or during reset).
Page 816: Chapter 27 Option Byte
After a reset ends, the oscillation stabilization time is secured, in accordance with these set values. When writing a program to the V850ES/JC3-L, V850ES/JE3-L, specify the option data at address 000007AH in the program, referring to 27.1 Program Example.
Page 817: Program Example
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 27 OPTION BYTE 27.1 Program Example The following shows program examples when the CA850 is used. #------------------------------------------------------------------------------ # OPTION_BYTES #------------------------------------------------------------------------------ .section "OPTION_BYTES" //Specifies the option byte at address 0000007A.// .byte 0b00000001 -- 0x7a...
Page 818: Chapter 28 Flash Memory
256 KB of flash memory Flash memory versions offer the following advantages for development environments and mass production applications. For altering software after the V850ES/JC3-L and V850ES/JE3-L are soldered onto the target system. For data adjustment when starting mass production.
Page 819: Memory Configuration
CHAPTER 28 FLASH MEMORY 28.2 Memory Configuration The V850ES/JC3-L, V850ES/JE3-L internal flash memory area is divided into 8 or 16 or 32 or 64 or 128 blocks and can be erased in block units. All the blocks can also be erased at once.
Page 820 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY Figure 28-1. Flash Memory Mapping (2/2) 003FFFFH Block 127 (2 KB) 003F800H 003F7FFH Block 126 (2 KB) 003F000H 003EFFFH 0020000H...
Page 821: Functional Outline
28.3 Functional Outline The internal flash memory of the V850ES/JC3-L, V850ES/JE3-L can be rewritten by using the rewrite function of the dedicated flash memory programmer, regardless of whether the V850ES/JC3-L, V850ES/JE3-L has already been mounted on the target system or not (off-board/on-board programming).
Page 822 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY Table 28-2. Basic Functions Support (√: Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming √ √ Blank check The erasure status of the entire memory is checked.
Page 823 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY Table 28-4. Security Settings Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (√: Executable, ×: Not Executable, −: Not Supported)
Page 824: Rewriting By Dedicated Flash Memory Programmer
For details, see the user’s manual of the dedicated flash memory programmer. UARTA0, CSIB0, or CSIB3 is used for the interface between the dedicated flash memory programmer and the V850ES/JC3-L, V850ES/JE3-L to perform writing, erasing, etc. A dedicated program adapter (FA series) is required for off-board writing.
Page 825: Communication Mode
V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY 28.4.2 Communication mode Communication between the dedicated flash memory programmer and the V850ES/JC3-L and V850ES/JE3-L are performed by serial communication using the UARTA0, CSIB0, or CSIB3 interfaces of the V850ES/JC3-L and V850ES/JE3-L. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 28-3.
Page 826 (3) CSIB0 + HS, CSIB3 + HS Serial clock: 2.4 kHz to 5 MHz (MSB first) The V850ES/JE3-L operates as a slave (V850ES/JC3-L does not use). Figure 28-5. Communication with Dedicated Flash Memory Programmer (CSIB0 + HS, CSIB3 + HS)
Page 827: Flash Memory Control
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY 28.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 28-6. Procedure for Manipulating Flash Memory...
Page 828: Selection Of Communication Mode
28.4.4 Selection of communication mode In the V850ES/JC3-L and V850ES/JE3-L, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash memory programmer.
Page 829: Communication Commands
V850ES/JC3-L, V850ES/JE3-L The following shows the commands for flash memory control in the V850ES/JC3-L and V850ES/JE3-L. All of these commands are issued from the dedicated flash memory programmer, and the V850ES/JC3-L and V850ES/JE3-L perform the processing corresponding to the commands.
Page 830: Pin Connection In On-Board Programming
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY 28.4.6 Pin connection in on-board programming When performing on-board writing, mount a connector on the target system to connect to the dedicated flash memory programmer.
Page 831 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY Table 28-8. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode Immediately After Reset Ends FLMD0 FLMD1 Operation Mode Don’t care...
Page 832 Dedicated flash memory programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/JC3-L and V850ES/JE3-L output affects the other device, isolate the signal on the other device side. V850ES/JC3-L, V850ES/JE3-L Dedicated flash memory...
Page 833 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY (4) RESET pin When the reset signals of the dedicated flash memory programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs.
Page 834: Rewriting By Self Programming
28.5.1 Overview The V850ES/JC3-L and V850ES/JE3-L support a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash...
Page 835: Features
(1) Secure self programming (boot swap function) The V850ES/JC3-L, V850ES/JE3-L supports a boot swap function that can be used to exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. By writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 to 15.
Page 836: Standard Self Programming Flow
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY 28.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. For details, see the Flash Memory Self-Programming Library User’s Manual (U17819E).
Page 837: Flash Functions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY 28.5.4 Flash functions Table 28-10. Flash Function List Function Name Outline Support √ FlashInit Self-programming library initialization √ FlashEnv Flash environment start/end √...
Page 838: Internal Resources Used
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 28 FLASH MEMORY 28.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming.
Page 839: Chapter 29 On-Chip Debug Function
On-chip debugging can be performed for the V850ES/JC3-L and V850ES/JE3-L by using the following two methods. • Using the DCU (debug control unit) On-chip debugging is performed by the on-chip DCU in the V850ES/JC3-L and V850ES/JE3-L, with the DRST, DCK, DMS, DDI, and DDO pins used as the debug interface pins.
Page 840 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION The following table shows the features of the two on-chip debugging methods. Table 29-1. Overview of On-Chip Debugging Debugging Using DCU Debugging Without Using DCU •...
Page 841: Debugging With Dcu
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1 Debugging with DCU By using the debug interface pins (DRST, DCK, DMS, DDI, and DDO) to connect the on-chip emulator (MINICUBE), programs can be debugged without using user resources other than these pins.
Page 842: Interface Signals
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1.2 Interface signals The interface signals are described below. (1) DRST This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously initializes the debug control unit.
Page 843: Mask Function
RESET pin, to make the DRST pin valid (initialization). 29.1.3 Mask function The reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked. The maskable signals in the integrated debugger (ID850QB) and the corresponding V850ES/JC3-L and V850ES/JE3-L functions are listed below. Table 29-2. Mask Functions...
Page 844: Registers
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1.4 Registers (1) On-chip debug mode register (OCDM) This register is used to specify whether a pin provided with an on-chip debug function is used as an on-chip debug pin or as an ordinary port/peripheral function pin.
Page 845: Operation
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0.
Page 846: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.1.6 Cautions (1) If a reset signal is input (from the target system or from an internal reset source) during program execution, the break function may malfunction.
Page 847: Debugging Without Using Dcu
RESET signal Reset circuit Notes 1. Connect TXDA0/SOB0/SOB3 (transmit side) of the V850ES/JC3-L and V850ES/JE3-L to RXD/SI (receive side) of the target connector, and TXD/SO (transmit side) of the target connector to RXDA0/SIB0/SIB3 (receive side) of the V850ES/JC3-L and V850ES/JE3-L.
Page 848 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION Table 29-3. Wiring Between V850ES/JC3-L and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) With CSIB0-HS With UARTA0 Signal Pin Function Pin Name Pin No.
Page 849 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION Table 29-4. Wiring Between V850ES/JE3-L and MINICUBE2 Pin Configuration of MINICUBE2 (QB-MINI2) With CSIB0-HS With CSIB3-HS With UARTA0 Signal...
Page 850: Mask Function
V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.2.2 Mask function Only reset signals can be masked. The maskable signals in the debugger (ID850QB) and the corresponding V850ES/JC3-L and V850ES/JE3-L functions are listed below. Table 29-5. Mask Functions Maskable Signals in ID850QB...
Page 851: Allocation Of User Resources
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.2.3 Allocation of user resources The user must prepare the following resources to perform communication between MINICUBE2 and the target device and implement each debug function.
Page 852 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION Figure 29-5. Memory Spaces Where Debug Monitor Programs Are Allocated Internal ROM Internal RAM 00FFFFFH 3FFEFFFH (16 bytes) Access-prohibited area...
Page 853 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION (3) Reset vector The reset vector includes the jump instruction for the debug monitor program. [How to secure the reset vector] It is not necessary to secure this area intentionally.
Page 854 To avoid problems that may occur during debugger startup, however, it is recommended to secure this area in advance, using the compiler. The following shows examples of securing the area, using the Renesas Electronics compiler CA850. Add the assemble source file and link directive code, as shown below.
Page 855 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION (5) Allocation of communication serial interface UARTA0, CSIB0, or CSIB3 is used for communication between MINICUBE2 and the target system. The settings related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur.
Page 856 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION • Port registers when UARTA0 is used When UARTA0 is used, port registers are set by the debug monitor program to make the TXDA0 and RXDA0 pins valid.
Page 857 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION • Port registers when CSIB3 is used When CSIB3 is used, port registers are set by the debug monitor program to make the SIB3, SOB3, SCKB3, and HS (PCM0) pins valid.
Page 858: Cautions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.2.4 Cautions (1) Handling of device that was used for debugging Do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed.
Page 859: Rom Security Function
29.3.1 Security ID The flash memory versions of the V850ES/JC3-L and V850ES/JE3-L perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on- chip debug emulator.
Page 860: Setting
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 29 ON-CHIP DEBUG FUNCTION 29.3.2 Setting The following shows how to set the ID code as shown in Table 29-6. When the ID code is set as shown in Table 29-6, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4”...
Page 861: Chapter 30 Electrical Specifications (V850Es/Jc3-L (40-Pin)) (Target)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2)
Page 862: Capacitance
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low P02, P03, P05, P30, P31, P40 to...
Page 863: Operating Conditions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.3 Operating Conditions = −40 to +85°C, V = EV = AV = EV = AV = 0 V)
Page 864: Oscillator Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.4 Oscillator Characteristics 30.4.1 Main clock oscillator characteristics (1) oscillator characteristics Main clock oscillator characteristics = −40 to +85°C, V...
Page 865: Subclock Oscillator Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) (2) External clock = −40 to +85°C, V = EV = AV = 2.7 to 3.6 V, V...
Page 866: Pll Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.4.3 PLL characteristics = −40 to +85°C, V = EV = AV = EV = AV = 0 V)
Page 867: Dc Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.6 DC Characteristics 30.6.1 Pin characteristics = −40 to +85°C, V = EV = AV = EV...
Page 868 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) = −40 to +85°C, V = EV = AV = EV = AV = 0 V) (2/2)
Page 869: Supply Current Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.6.2 Supply current characteristics = −40 to +85°C, V = EV = AV = EV = AV...
Page 870: Data Retention Characteristics (In Stop Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.6.3 Data retention characteristics (in STOP mode) = −40 to +85°C, V = EV = AV = EV...
Page 871: Ac Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.7 AC Characteristics 30.7.1 Measurement conditions (1) AC test input measurement points Measurement points (2) AC test output measurement points...
Page 872: Power On/Power Off/Reset Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.7.2 Power on/power off/reset timing = −40 to +85°C, V = EV = AV = 2.2 to 3.6 V, V...
Page 873: Peripheral Function Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.8 Peripheral Function Characteristics 30.8.1 Interrupt timing = −40 to +85°C, V = EV = AV = 2.2 to 3.6 V, V...
Page 874: Uart Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.8.4 UART timing = −40 to +85°C, V = EV = AV = EV = AV = 0 V, C...
Page 875 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) (2) Slave mode = −40 to +85°C, V = EV = AV = EV = AV = 0 V, C...
Page 876: C Bus Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.8.6 I C bus mode = −40 to +85°C, V = EV = AV = 2.2 to 3.6 V, V...
Page 877: A/D Converter
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) C Bus Timing <68> <69> SCL0n (I/O) <70> <74> <73> <71> <72> <75> <67> <76> <67> SDA0n (I/O) <66>...
Page 878: Lvi Circuit Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) 30.8.8 LVI circuit characteristics = −40 to +85°C, V = EV = AV = 2.2 to 3.6 V, V...
Page 879: Flash Memory Programming Characteristics
Renesas Electronics self programming 15 years library Used for updating data Retained 10,000 times When using Renesas Electronics EEPROM emulation library (usable ROM size: 12 KB 5 years of 6 consecutive blocks, or 6 KB of 3 consecutive blocks) −40 °C...
Page 880 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 30 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (40-pin)) (Target) (3) Programming characteristics = −40 to +85°C, V = EV = AV = 2.7 to 3.6 V, V...
Page 881: Chapter 31 Electrical Specifications (V850Es/Jc3-L (48-Pin)) (Target)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2)
Page 882: Capacitance
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low P02, P03, P05, P30 to P32, P38,...
Page 883: Operating Conditions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.3 Operating Conditions = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 884: Oscillator Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.4 Oscillator Characteristics 31.4.1 Main clock oscillator characteristics (1) oscillator characteristics Main clock oscillator characteristics = −40 to +85°C, V...
Page 885: Subclock Oscillator Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) (2) External clock = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V...
Page 886: Pll Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.4.3 PLL characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 887: Dc Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.6 DC Characteristics 31.6.1 Pin characteristics = −40 to +85°C, V = EV = AV = AV...
Page 888 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (2/2)
Page 889: Supply Current Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.6.2 Supply current characteristics = −40 to +85°C, V = EV = AV = AV = EV...
Page 890: Data Retention Characteristics (In Stop Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.6.3 Data retention characteristics (in STOP mode) = −40 to +85°C, V = EV = AV = AV...
Page 891: Ac Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.7 AC Characteristics 31.7.1 Measurement conditions (1) AC test input measurement points Measurement points (2) AC test output measurement points...
Page 892: Power On/Power Off/Reset Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.7.2 Power on/power off/reset timing = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V...
Page 893: Peripheral Function Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.8 Peripheral Function Characteristics 31.8.1 Interrupt timing = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V...
Page 894: Uart Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.8.4 UART timing = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 895 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) (2) Slave mode = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 896: C Bus Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.8.6 I C bus mode = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V...
Page 897: A/D Converter
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) C Bus Timing <68> <69> SCL0n (I/O) <70> <74> <73> <71> <72> <75> <67> <76> <67> SDA0n (I/O) <66>...
Page 898: D/A Converter
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) 31.8.8 D/A converter = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 899: Flash Memory Programming Characteristics
Renesas Electronics self programming 15 years library Used for updating data Retained 10,000 times When using Renesas Electronics EEPROM emulation library (usable ROM size: 12 KB 5 years of 6 consecutive blocks, or 6 KB of 3 consecutive blocks) −40 °C...
Page 900 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 31 ELECTRICAL SPECIFICATIONS (V850ES/JC3-L (48-pin)) (Target) (3) Programming characteristics = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V...
Page 901: Chapter 32 Electrical Specifications (V850Es/Je3-L) (Target)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.1 Absolute Maximum Ratings Absolute Maximum Ratings (T = 25°C) (1/2) Parameter...
Page 902: Capacitance
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low P02 to P06, P30 to P35, P38, P39,...
Page 903: Operating Conditions
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.3 Operating Conditions = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 904: Oscillator Characteristics
= 2.7 to 3.6 V Note 6 in PLL mode Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JE3-L so that the internal operating conditions do not exceed the ratings shown in AC Characteristics, DC Characteristics, and Operating Conditions.
Page 905: Subclock Oscillator Characteristics
Oscillation Note 2 stabilization time Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JE3-L so that the internal operation conditions do not exceed the ratings shown in AC Characteristics, DC Characteristics, and operating conditions. 2. Time required from when V reaches the oscillation voltage range (2.2 V (MIN.)) to when the crystal...
Page 906: Pll Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.4.3 PLL characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 907: Dc Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.6 DC Characteristics 32.6.1 Pin characteristics = −40 to +85°C, V = EV = AV = AV = EV...
Page 908 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (2/2)
Page 909: Supply Current Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.6.2 Supply current characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 910: Data Retention Characteristics (In Stop Mode)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.6.3 Data retention characteristics (in STOP mode) = −40 to +85°C, V = EV = AV = AV...
Page 911: Ac Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.7 AC Characteristics 32.7.1 Measurement conditions (1) AC test input measurement points Measurement points (2) AC test output measurement points...
Page 912: Power On/Power Off/Reset Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.7.2 Power on/power off/reset timing = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V...
Page 913: Peripheral Function Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.8 Peripheral Function Characteristics 32.8.1 Interrupt timing = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V...
Page 914: Uart Timing
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.8.4 UART timing = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 915 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) (2) Slave mode = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 916: C Bus Mode
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.8.6 I C bus mode = −40 to +85°C, V = EV = AV = AV = 2.2 to 3.6 V, V...
Page 917: A/D Converter
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) C Bus Timing <68> <69> SCL0n (I/O) <70> <74> <73> <71> <72> <75> <67> <76> <67> SDA0n (I/O) <66>...
Page 918: D/A Converter
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.8.8 D/A converter = −40 to +85°C, V = EV = AV = AV = EV = AV...
Page 919: Flash Memory Programming Characteristics
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) 32.9 Flash Memory Programming Characteristics (1) Basic characteristics = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V...
Page 920 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 32 ELECTRICAL SPECIFICATIONS (V850ES/JE3-L) (Target) (3) Programming characteristics = −40 to +85°C, V = EV = AV = AV = 2.7 to 3.6 V, V...
Page 921 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 33 PACKAGE DRAWINGS CHAPTER 33 PACKAGE DRAWINGS • V850ES/JC3-L R01UH0018EJ0001 Rev.0.01 Page 921 of 958 Jul 23, 2010...
Page 922 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 33 PACKAGE DRAWINGS • V850ES/JC3-L 48-PIN PLASTIC LQFP (FINE PITCH) (7x7) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 7.00±0.20 7.00±0.20 9.00±0.20 9.00±0.20 1.60 MAX.
Page 923 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 33 PACKAGE DRAWINGS • V850ES/JC3-L ± ± ± ± R01UH0018EJ0001 Rev.0.01 Page 923 of 958 Jul 23, 2010...
Page 924 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L CHAPTER 33 PACKAGE DRAWINGS • V850ES/JE3-L 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) detail of lead end θ (UNIT:mm) ITEM DIMENSIONS 10.00±0.20 10.00±0.20 12.00±0.20 12.00±0.20 1.60 MAX.
Page 925: Appendix A Development Tools
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/JC3-L, V850ES/JE3-L.
Page 926 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Software package Language processing software Debugging software • Integrated debugger • C compiler package • System simulator •...
Page 927: Software Package
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) commonly used with V850 microcontrollers are included Software package for V850 this package.
Page 928: Debugging Tools (Hardware)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) ® A.4.1 When using IECUBE QB-V850ESJX3L, QB-V850ESSX2 The system configuration when connecting the QB-V850ESJX3L, QB-V850ESSX2 to the host machine (PC-9821 series, PC/AT compatible) is shown below.
Page 929 Note 2 <13> Target connector (optional) <14> Target system Notes 1. Download the device file from the Renesas Electronics website. http://www2.renesas.com/micro/en/ods/index.html 2. Under development 3. When using both <9> and <10>, the order between <9> and <10> is not cared.
Page 930 The in-circuit emulator serves to debug hardware and software when developing Note1 QB-V850ESSX2 application systems using the V850ES/JC3-L, V850ES/JE3-L. It supports the In-circuit emulator integrated debugger ID850QB. This emulator should be used in combination with a power supply unit and emulation probe. Use the USB interface cable to connect this emulator to the host machine.
Page 931: When Using Minicube Qb-V850Minil
MINICUBE. The cable length is approximately 2 m. <4> MINICUBE This on-chip debug emulator serves to debug hardware and software when On-chip debug emulator developing application systems using the V850ES/JC3-L, V850ES/JE3-L. It supports integrated debugger ID850QB. <5> OCD cable Cable to connect MINICUBE and the target system.
Page 932: When Using Minicube2 Qb-Mini2
<4> MINICUBE2 This on-chip debug emulator serves to debug hardware and software when On-chip debug emulator developing application systems using the V850ES/JC3-L, V850ES/JE3-L. It supports integrated debugger ID850QB. <5> 16-pin target cable Cable to connect MINICUBE2 and the target system.
Page 933: Embedded Software
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software μ RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to ITRON 3.0 specifications.
Page 934: Appendix B Major Differences Between Products
Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ESJE3-L APPENDIX B MAJOR DIFFERENCES BETWEEN PRODUCTS APPENDIX B MAJOR DIFFERENCES BETWEEN PRODUCTS Table B-1. Major Differences between V850ES/Jx3-L products Major Differences V850ES/JC3-L V850ES/JE3-L V850ES/JF3-L V850ES/JG3-L μ μ μ μ μ...
Page 935: Appendix C Register Index
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX APPENDIX C REGISTER INDEX (1/10) Symbol Name Unit Page ADA0CR0 A/D conversion result register 0 ADA0CR0H A/D conversion result register 0H...
Page 936 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (2/10) Symbol Name Unit Page CB1CTL2 CSIB1 control register 2 CSIB CB1RIC Interrupt control register INTC CB1RX CSIB1 receive data register...
Page 937 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (3/10) Symbol Name Unit Page CTBP CALLT base pointer CTPC CALLT execution status saving register CTPSW CALLT execution status saving register...
Page 938 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (4/10) Symbol Name Unit Page Interrupt source register EIPC Interrupt status saving register EIPSW Interrupt status saving register FEPC NMI status saving register...
Page 939 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (5/10) Symbol Name Unit Page INTR9H External interrupt rising edge specification register 9H INTC ISPR In-service priority register INTC KRIC...
Page 940 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (6/10) Symbol Name Unit Page PFC4 Port 4 function control register Port PFC5 Port 5 function control register Port PFC9...
Page 941 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (7/10) Symbol Name Unit Page PMDL Port DL mode register Port PMDLL Port DL mode register L Port PRCMD Command register...
Page 942 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (8/10) Symbol Name Unit Page SVA0 Slave address register 0 SVA1 Slave address register 1 SVA2 Slave address register 2...
Page 943 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (9/10) Symbol Name Unit Page TP3CCIC1 Interrupt control register INTC TP3CCR0 TMP3 capture/compare register 0 Timer TP3CCR1 TMP3 capture/compare register 1...
Page 944 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX C REGISTER INDEX (10/10) Symbol Name Unit Page TQ0CTL0 TMQ0 control register 0 Timer TQ0CTL1 TMQ0 control register 1 Timer TQ0IOC0 TMQ0 I/O control register 0...
Page 945: Appendix D Instruction Set List
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST APPENDIX D INSTRUCTION SET LIST D.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers.
Page 946 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ]...
Page 947 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results.
Page 948: Instruction Set (In Alphabetical Order)
Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST D.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT ×...
Page 949 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) DBPSW←PSW PSW.NP←1...
Page 950 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword))
Page 951 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] ×...
Page 952 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3))
Page 953 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] ×...
Page 954 Preliminary document Under development Specifications in this document are tentative and subject to change. V850ES/JC3-L, V850ES/JE3-L APPENDIX D INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode.
Page 955 REVISION HISTORY V850ES/JC3-L, V850ES/JE3-L User’s Manual: Hardware Rev. Date Description Page Summary ⎯ 0.01 Jul 23, 2010 First Edition issued C - 1...
Page 956 V850ES/JC3-L, V850ES/JE3-L User’s Manual: Hardware Publication Date: Rev.0.01 Jul 23, 2010 Published by: Renesas Electronics Corporation...
Page 957 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
Page 958 V850ES/JC3-L, V850ES/JE3-L R01UH0018EJ0001...

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