Renesas V853 User Manual
  1. Manuals
  2. Brands
  3. Renesas Manuals
  4. Microcontrollers
  5. V853
  6. User manual
Renesas V853 User Manual

Renesas V853 User Manual

32-bit single-chip
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
To our customers,
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Old Company Name in Catalogs and Other Documents
Renesas Electronics website: http://www.renesas.com
st
April 1
, 2010
Renesas Electronics Corporation

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the V853 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Renesas V853

Summary of Contents for Renesas V853

  • Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
  • Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
  • Page 3 User’s Manual V853 32-Bit Single-Chip Microcontrollers Hardware µ µ µ µ µ PD703003A µ µ µ µ µ PD703003A(A) µ µ µ µ µ PD703004A µ µ µ µ µ PD703025A µ µ µ µ µ PD703025A(A) µ µ µ µ µ PD70F3003A µ...
  • Page 4 [MEMO] User’s Manual U10913EJ6V0UM...
  • Page 5 Reset operation must be executed immediately after power-on for devices having reset function. V853 and V850 Family are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
  • Page 6 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country.
  • Page 7 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 8 Change of description in 14.1 Features p.304 Addition of Figure 14-1 V853 Flash Memory Writing Adapter (FA-100GC-8EU) Wiring Example p.305 Addition of Table 14-1 Wiring Table of V853 Flash Writing Adapter (FA-100GC08EU) p.307 Change of description in 14.4 (1) UART0 p.307...
  • Page 9 INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of the V853 to design application systems using the V853. The target devices are as follows. • Standard version: µ PD703003A, 703004A, 703025A, 70F3003A, 70F3025A •...
  • Page 10 • Documents related to devices Document Name Document No. V850 Family Architecture User’s Manual U10243E µ PD703003A, 703004A, 703025A, 703003A(A), 703025A(A) Data Sheet U13188E µ PD70F3003A, 70F3025A, 70F3003A(A) Data Sheet U13189E V853 Hardware User’s Manual This manual User’s Manual U10913EJ6V0UM...
  • Page 11 • Documents related to development tools (user’s manuals) Document Name Document No. IE-703002-MC (In-Circuit Emulator) U11595E IE-703003-MC-EM1 (In-Circuit Emulator Option Board) U11596E CA850 (Ver. 2.30 or Later) (C Compiler Package) Operation U14568E C Language U14566E Project Manager U14569E Assembly Language U14567E CA850 (Ver.

  • Page 12: Table Of Contents

    CONTENTS CHAPTER 1 INTRODUCTION .......................20 General .............................20 Features ............................21 Applications ..........................22 Ordering Information ......................22 Pin Configuration (Top View) ....................23 Function Block Configuration ....................25 1.6.1 Internal block diagram ........................ 25 1.6.2 Internal units ..........................26 Differences Among Products ....................28 CHAPTER 2 PIN FUNCTIONS ......................29 Pin Function List ........................29 Pin Status ..........................34 Pin Functions ..........................35...
  • Page 13 Memory Block Function ......................81 Wait Function ...........................82 4.5.1 Programmable wait function ....................... 82 4.5.2 External wait function ......................... 83 4.5.3 Relationship between programmable wait and external wait ........... 83 Idle State Insertion Function ....................84 Bus Hold Function ........................85 4.7.1 Outline of function ........................85 4.7.2 Bus hold procedure ........................
  • Page 14 CHAPTER 6 CLOCK GENERATOR FUNCTION ................127 Features ..........................127 Configuration ........................127 Selecting Input Clock ......................128 6.3.1 Direct mode ..........................128 6.3.2 PLL mode ..........................128 6.3.3 Clock control register (CKC) ....................129 PLL Lockup ........................... 131 Power Save Control ......................132 6.5.1 General ............................
  • Page 15 8.3.1 Features ............................ 198 8.3.2 Configuration ..........................198 8.3.3 Control registers ........................200 8.3.4 Basic operation ......................... 202 8.3.5 Transmission in CSI0 to CSI3 ....................205 8.3.6 Reception in CSI0 to CSI3 ....................... 206 8.3.7 Transmission/reception in CSI0 to CSI3 .................. 207 8.3.8 System configuration example ....................
  • Page 16 11.4.1 Basic operations ........................255 11.4.2 Repeating frequency ........................ 257 11.5 Caution ........................... 257 CHAPTER 12 PORT FUNCTION ....................... 258 12.1 Features ..........................258 12.2 Basic Configuration of Port ....................259 12.3 Port Pin Functions ....................... 263 12.3.1 Port 0 ............................263 12.3.2 Port 1 ............................
  • Page 17 APPENDIX A REGISTER INDEX ....................... 317 APPENDIX B INSTRUCTION SET LIST .................... 322 APPENDIX C INDEX ........................... 329 User’s Manual U10913EJ6V0UM...
  • Page 18 LIST OF FIGURES (1/3) Figure No. Title Page Program Counter (PC) ..........................47 Interrupt Source Register (ECR) ......................48 Program Status Word (PSW) ........................49 CPU Address Space ..........................51 Image on Address Space ........................52 External Memory Area (When Expanded to 64 KB, 128 KB, 256 KB, 512 KB, or 1 MB) ....62 Recommended Memory Map ........................
  • Page 19 LIST OF FIGURES (2/3) Figure No. Title Page 7-16 Example of PWM Output Timing ......................175 7-17 Example of Programming Procedure of PWM Output ................. 176 7-18 Example of Interrupt Request Servicing Routine, Modifying Compare Value ........177 7-19 Example of Frequency Measurement Timing ..................178 7-20 Example of Setup Procedure for Frequency Measurement ..............
  • Page 20 Block Diagram of P96 (Port 9) ......................291 12-23 Block Diagram of P110 and P111 (Port 11) ..................294 12-24 Block Diagram of P112 to P117 (Port 11) ..................... 294 14-1 V853 Flash Writing Adapter (FA100GC-8EU) Wiring Example ............304 User’s Manual U10913EJ6V0UM...
  • Page 21 Operating Status of Each Pin During Reset Period ................299 13-2 Initial Values of Each Register After Reset ................... 301 14-1 Wiring Table of V853 Flash Writing Adapter ..................305 14-2 List of Communication Modes ....................... 314 User’s Manual U10913EJ6V0UM...

  • Page 22: Chapter 1 Introduction

    V853. 1.1 General The V853 is a 32-bit single-chip microcontroller that employs the CPU core of the V850 Family of high-performance 32-bit single-chip microcontrollers for real-time control applications, and integrates peripheral functions such as ROM/ RAM, a real-time pulse unit, serial interface, A/D converter, and PWM.

  • Page 23: Features

    CHAPTER 1 INTRODUCTION 1.2 Features Number of instructions: Minimum instruction execution time: 30 ns (at internal 33 MHz) 32 bits × 32 General-purpose registers: Signed multiply (16 bits × 16 bits → 32 bits): 1 to 2 clocks Instruction set: Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock Bit manipulation instructions...

  • Page 24: Applications

    CHAPTER 1 INTRODUCTION Power save function: HALT/IDLE/software STOP mode Clock output stop function 100-pin plastic LQFP (fine pitch) (14 × 14) Package: CMOS technology 1.3 Applications µ PD703003A, 703004A, 703025A, 70F3003A, 70F3025A: Camcorders, VCRs, PPC, LBP, printers, motor control, NC machine tools, portable phones, etc. µ...

  • Page 25: Pin Configuration (Top View)

    CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) • 100 pin plastic LQFP (fine pitch) (14 × 14) µ PD703003AGC-33-×××-8EU µ PD703003AGC(A)-33-×××-8EU µ PD703004AGC-33-×××-8EU µ PD703025AGC(A)-33-×××-8EU µ PD703025AGC-33-×××-8EU µ PD70F3003AGC(A)-33-8EU µ PD70F3003AGC-33-8EU µ PD70F3025AGC-33-8EU P31/TO131 P75/ANI5 P32/TCLR13 P74/ANI4 P33/TI13 P73/ANI3 P34/INTP130 P72/ANI2 P35/INTP131/SO3...
  • Page 26 CHAPTER 1 INTRODUCTION Pin identification A16 to A19: Address bus P30 to P37: Port3 AD0 to AD15: Address/data bus P40 to P47: Port4 ADTRG: AD trigger input P50 to P57: Port5 ANI0 to ANI7: Analog input P60 to P63: Port6 ANO0, ANO1: Analog output P70 to P77:...

  • Page 27: Function Block Configuration

    CHAPTER 1 INTRODUCTION 1.6 Function Block Configuration 1.6.1 Internal block diagram ASTB Instruction DSTB queue INTC INTP110 to INTP113 INTP120 to INTP123 UBEN Note 1 32-bit INTP130 to INTP133 LBEN barrel shifter INTP140 to INTP143 Multiplier WAIT 16 x 16 → 32 A16 to A19 System TO110, TO111...

  • Page 28: Internal Units

    CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU Executes almost all instruction processing such as address calculation, arithmetic/logic operation, and data transfer in 1 clock by using a 5-stage pipeline. Dedicated hardware devices such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) are provided to increase the speed of processing complicated instructions.
  • Page 29 Timer I/O, external interrupt (10) PWM (Pulse Width Modulation) The V853 is provided with two PWM signal output channels for which 8-/9-/10-/12-bit resolution can be selected. The PWM output can be used as a D/A converter output by connecting an external low pass filter. It is suitable for controlling the actuator of motors, etc.

  • Page 30: Differences Among Products

    CHAPTER 1 INTRODUCTION 1.7 Differences Among Products µ PD703003A µ PD703004A µ PD703025A µ PD703003A(A) µ PD703025A(A) µ PD70F3003A µ PD70F3025A µ PD70F3003A(A) Item Internal ROM Mask ROM Flash memory 128 KB 96 KB 256 KB 128 KB 256 KB 128 KB 256 KB 128 KB...

  • Page 31: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS The following table shows the names and functions of the V853’s pins. These pins can be divided by function into port pins and non-port pins. 2.1 Pin Function List (1) Port pins (1/2) Pin Name Function Alternate Function Port 0.
  • Page 32 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Function Alternate Function Port 4. P40 to P47 AD0 to AD7 8-bit I/O port. Input/output can be specified in 1-bit units. P50 to P57 Port 5. AD8 to AD15 8-bit I/O port. Input/output can be specified in 1-bit units. P60 to P63 Port 6.
  • Page 33 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name Function Alternate Function TO110 Output Pulse signal output from timer 11 to 14. TO111 TO120 TO121 TO130 TO131 TO140 P110 TO141 P111 TCLR11 Input External clear signal input to timer 11 to 14. TCLR12 TCLR13 TCLR14...
  • Page 34 Input that specifies clock generator operation mode. WAIT Input Control signal input inserting wait state to bus cycle. – MODE Input Specifies operation mode of the V853. – RESET Input System reset input. – Input System clock oscillator connecting pins. Supply external clock to X1.
  • Page 35 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function – Positive power supply for A/D converter. – – Ground for A/D converter. – – Positive power supply for on-chip clock generator. CKSEL – Ground for on-chip clock generator. – –...

  • Page 36: Pin Status

    CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The operating status of each pin in each operation mode is as follows. Operating Status Reset STOP Mode IDLE Mode Bus Hold Idle State HALT Mode AD0 to AD15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z A16 to A19...

  • Page 37: Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.3 Pin Functions (1) P00 to P07 (Port 0) ... 3-state I/O These pins constitute an 8-bit I/O port, port 0. They also serve as control signal pins. P00 to P07 function not only as I/O port pins, but also as the I/O pins of the real-time pulse unit (RPU) and external interrupt request input pins.
  • Page 38 CHAPTER 2 PIN FUNCTIONS (iii) TI12 (Timer Input) ... input This pin inputs an external count clock to timer 1. (iv) INTP120 to INTP123 (Interrupt Request from Peripherals) ... input These pins are the external interrupt request input pins of timer 1. (v) SO2 (Serial Output 2) ...
  • Page 39 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ... 3-state I/O These pins constitute an 8-bit I/O port, port 3. They also function as control signal pins. P30 to P37 function not only as I/O port pins but also as I/O pins for the RPU, external interrupt request pins, and serial interface (CSI3) I/O pins in the control mode.
  • Page 40 CHAPTER 2 PIN FUNCTIONS AD0 to AD7 (Address/Data 0 to 7) ... 3-state I/O These pins constitute a multiplexed address/data bus when the external memory is accessed. They function as the A0 to A7 output pins of a 20-bit address in the address timing state (T1), and as the lower 8-bit data I/O bus pins of 16-bit data in the data timing state (T2, TW, T3).
  • Page 41 CHAPTER 2 PIN FUNCTIONS (8) P70 to P77 (Port 7) ... input Port 7 is an 8-bit input-only port whose pins are all fixed to input. P70 to P77 function as input ports, as well as A/D converter analog inputs in the control mode. However, the input port and analog input pin cannot be switched.
  • Page 42 (vii) HLDRQ (Hold Request) ... input This input pin is used by an external device to request that the V853 relinquish control of the address bus, data bus, and control bus. This signal can be input asynchronously to CLKOUT. When this signal becomes active, the V853 sets the address bus, data bus, and control bus in the high- impedance state, after the current bus cycle completes.
  • Page 43 CHAPTER 2 PIN FUNCTIONS This pin inputs an external count clock to timer 1. (iv) INTP140 to INTP143 (Interrupt Request from Peripherals) ... input These pins are the external interrupt request input pins of timer 1. (11) CLKOUT (Clock Output) ... output This pin outputs the system clock.
  • Page 44 CHAPTER 2 PIN FUNCTIONS (20) V (Ground) This is a ground pin. Connect all the V pins to ground. (21) AV (Analog Power Supply) Analog power supply pin for A/D converter. (22) AV (Analog Ground) Ground pin for A/D converter. (23) AV to AV (Analog Reference Voltage) ...

  • Page 45: Pin I/O Circuits And Recommended Connection Of Unused Pins

    CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins When connected to V or V via a resistor, it is recommended to use a resistor of 1 to 10 kΩ. I/O Circuit Type Recommended Connection P00/TO110, P01/TO111 Input: Independently connect to V...

  • Page 46: Pin I/O Circuits

    CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 1 Type 8 Data P-ch IN/OUT P-ch Output N-ch disable N-ch Type 2 Type 9 P-ch Comparator – N-ch (threshold voltage) Input enable Schmitt-triggered input with hysteresis characteristics Type 3 Type 10-A Pullup P-ch enable...

  • Page 47: Chapter 3 Cpu Functions

    CHAPTER 3 CPU FUNCTIONS The CPU of the V853 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features Minimum instruction cycle: 30 ns (at 33 MHz operation) Address space: 16 MB linear 32-bit general-purpose registers ×...

  • Page 48: Cpu Register Set

    CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The registers of the V853 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to V850 Family Architecture User’s Manual.

  • Page 49: Program Register Set

    CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.

  • Page 50: System Register Set

    CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Status saving registers during These registers save the PC and PSW when an exception interrupt or interrupt occurs.
  • Page 51 CHAPTER 3 CPU FUNCTIONS Figure 3-3. Program Status Word (PSW) After reset 00000020H Bit position Bit name Function 31 to 8 Reserved field (fixed to 0) Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set when an NMI is acknowledged, and disables multiple interrupts. 0: NMI servicing not under execution.

  • Page 52: Operation Modes

    The operation mode is fixed to single-chip mode. (2) Flash memory programming mode The operation mode of the V853 is specified depending on the MODE pin and V pin. The MODE pin specification should be fixed in the application system and should not be changed during operation.

  • Page 53: Address Space

    3.4.1 CPU address space The CPU of the V853 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, a linear address space (program space) of up to 16 MB is supported.

  • Page 54: Image

    CHAPTER 3 CPU FUNCTIONS 3.4.2 Image The core CPU supports 4 GB of “virtual” addressing space, or 256 memory blocks, each containing 16 MB memory locations. In actuality, the same 16 MB block is accessed regardless of the values of bits 31 to 24 of the CPU address. Figure 3-5 shows the image of the virtual addressing space.

  • Page 55: Wrap-Around Of Cpu Address Space

    CHAPTER 3 CPU FUNCTIONS 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are set to 0, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0.

  • Page 56: Memory Map

    16 MB Note area XX100000H XX0FFFFFH Internal Internal ROM area ROM area 1 MB XX000000H Note Although the program space of the V853 is 16 MB, the space for physical external memory is 1 MB (see Figure 3-6). User’s Manual U10913EJ6V0UM...
  • Page 57 16 MB Note area XX100000H XX0FFFFFH Internal Internal ROM area ROM area 1 MB XX000000H Note Although the program space of the V853 is 16 MB, the space for physical external memory is 1 MB (see Figure 3-6). User’s Manual U10913EJ6V0UM...

  • Page 58: Area

    CHAPTER 3 CPU FUNCTIONS 3.4.5 Area (1) Internal ROM area (a) Memory map <1> µ PD703003A and 70F3003A A 1 MB area in addresses 000000H to 0FFFFFH is reserved for the internal ROM area, and 128 KB area in addresses 000000H to 01FFFFH is provided for physical internal ROM. The image of 000000H to 01FFFFH can be seen in the remaining area (020000H to 0FFFFFH).
  • Page 59 CHAPTER 3 CPU FUNCTIONS <2> µ PD703004A A 1 MB area in addresses 000000H to 0FFFFFH is reserved for the internal ROM area, 96 KB area in addresses 000000H to 017FFFH is provided for physical internal ROM, and 32 KB area in addresses 018000H to 01FFFFH is undefined.
  • Page 60 XX03FFFFH Image XX000000H (b) Interrupt/exception table The V853 increases the interrupt response speed by assigning destination addresses corresponding to interrupts/exceptions. The collection of these destination addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is granted, execution jumps to the corresponding destination address, and the program written at that memory address is executed.
  • Page 61 CHAPTER 3 CPU FUNCTIONS Table 3-3. Interrupt/Exception Table Start Address of Interrupt/Exception Table Interrupt/Exception Source 00000000H RESET 00000010H 00000040H TRAP0n (n = 0 to FH) 00000050H TRAP1n (n = 0 to FH) 00000060H ILGOP 00000080H INTOV11 00000090H INTOV12 000000A0H INTOV13 000000B0H INTOV14 000000C0H...
  • Page 62 CHAPTER 3 CPU FUNCTIONS (2) Internal RAM area (a) µ µ µ µ µ PD703003A, 70F3003A, and 703004A The V853 is provided with 4 KB of addresses FFE000H to FFEFFFH as a physical internal RAM area. XXFFEFFFH Internal RAM XXFFE000H (b) µ...
  • Page 63 (3) Peripheral I/O area A 4 KB area of addresses FFF000H to FFFFFFH is reserved as a peripheral I/O area. The V853 is provided with a 1 KB area of addresses FFF000H to FFF3FFH as a physical peripheral I/O area, and the image of FFF000H to FFF3FFH can be seen on the rest of the area (FFF400H to FFFFFFH).
  • Page 64 CHAPTER 3 CPU FUNCTIONS (4) External memory area The V853 can use an area of up to xx100000H to xxFFDFFFH in the single-chip mode for external memory accesses. In the external memory area, 64 KB, 128 KB, 256 KB, 512 KB, or 1 MB of physical external memory can be allocated when the external expansion mode is specified.

  • Page 65: External Expansion Mode

    CHAPTER 3 CPU FUNCTIONS 3.4.6 External expansion mode The V853 allows external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. The port/control mode alternate-function pins at reset become port mode, and the external devices cannot be used.

  • Page 66: Memory Expansion Mode Register (Mm)

    CHAPTER 3 CPU FUNCTIONS 3.4.7 Memory expansion mode register (MM) This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external device can be connected to the external memory area of up to 1 MB. However, the external device cannot be connected to the internal RAM area, peripheral I/O area, and internal ROM area in the single-chip mode (access is restricted to external locations 100000H through FFE00H).

  • Page 67: Recommended Use Of Address Space

    To enhance the efficiency of using the pointer in connection with the memory map of the V853, the following points are recommended.
  • Page 68 CHAPTER 3 CPU FUNCTIONS Figure 3-7. Recommended Memory Map (1/3) (a) µ µ µ µ µ PD703003A and 70F3003A Program space Data space FFFFFFFFH Peripheral I/O FFFFF3D1H FFFFF3D0H FFFFF000H FFFFEFFFH Internal XXFFFFFFH Peripheral I/O FFFFE000H XXFFF3D1H FFFFDFFFH XXFFF3D0H External XXFFF000H memory XXFFEFFFH FF800000H...
  • Page 69 CHAPTER 3 CPU FUNCTIONS Figure 3-7. Recommended Memory Map (2/3) (b) µ µ µ µ µ PD703004A Program space Data space F F F F F F F F H Peripheral I/O F F F F F 3 D 1 H F F F F F 3 D 0 H F F F F F 0 0 0 H F F F F E F F F H...
  • Page 70 CHAPTER 3 CPU FUNCTIONS Figure 3-7. Recommended Memory Map (3/3) (c) µ µ µ µ µ PD703025A and 70F3025A Program space Data space FFFFFFFFH Peripheral I/O FFFFF3D1H FFFFF3D0H FFFFF000H FFFFEFFFH FFFFE000H Internal RAM FFFFDFFFH FFFFD000H XXFFFFFFH FFFFCFFFH Image Peripheral I/O FFFFC000H XXFFF3D1H FFFFBFFFH...

  • Page 71: Peripheral I/O Registers

    CHAPTER 3 CPU FUNCTIONS 3.4.9 Peripheral I/O registers Address Function Register Name Symbol Bit Units for After Reset Manipulation 1 Bit 8 Bits 16 Bits FFFFF000H Port 0 Undefined FFFFF002H Port 1 FFFFF004H Port 2 FFFFF006H Port 3 FFFFF008H Port 4 FFFFF00AH Port 5 FFFFF00CH...
  • Page 72 CHAPTER 3 CPU FUNCTIONS Address Function Register Name Symbol Bit Units for After Reset Manipulation 1 Bit 8 Bits 16 Bits FFFFF094H Baud rate generator compare register 1 BRGC1 Undefined FFFFF096H Baud rate generator prescaler mode register 1 BPRM1 FFFFF098H Clocked serial interface mode register 1 CSIM1 FFFFF09AH...
  • Page 73 CHAPTER 3 CPU FUNCTIONS Address Function Register Name Symbol Bit Units for After Reset Manipulation 1 Bit 8 Bits 16 Bits FFFFF11CH Interrupt control register P13IC2 FFFFF11EH Interrupt control register P13IC3 FFFFF120H Interrupt control register P14IC0 FFFFF122H Interrupt control register P14IC1 FFFFF124H Interrupt control register...
  • Page 74 CHAPTER 3 CPU FUNCTIONS Address Function Register Name Symbol Bit Units for After Reset Manipulation 1 Bit 8 Bits 16 Bits FFFFF274H Capture compare register 121 CC121 Undefined FFFFF276H Capture compare register 122 CC122 FFFFF278H Capture compare register 123 CC123 FFFFF280H Timer unit mode register 13 TUM13...
  • Page 75 CHAPTER 3 CPU FUNCTIONS Address Function Register Name Symbol Bit Units for After Reset Manipulation 1 Bit 8 Bits 16 Bits FFFFF3A2H A/D conversion result register 4H ADCR4H Undefined FFFFF3A4H A/D conversion result register 5 ADCR5 FFFFF3A6H A/D conversion result register 5H ADCR5H FFFFF3A8H A/D conversion result register 6...

  • Page 76: Specific Registers

    The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is reported by the system status register (SYS). The V853 has two specific registers, the clock control register (CKC) and power save control register (PSC). For details of the CKC register, refer to 6.3.3, and for details of the PSC register, refer to 6.5.2.
  • Page 77 CHAPTER 3 CPU FUNCTIONS When saving the PSW value, it is necessary to transfer the PSW value before setting the NP bit to the rY register. 2. The instruction (<4> interrupt disable release, <5> NOP instruction) after the store instruction for the specific register to be set to the software STOP mode and IDLE mode is executed before each power save mode is set.
  • Page 78 CHAPTER 3 CPU FUNCTIONS (1) Command Register (PRCMD) The command register (PRCMD) is a register used when write-accessing a specific register to prevent incorrect writing to the specific register due to erroneous program execution. This register can be read/written in 8-bit units. It becomes undefined in a read cycle. The occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
  • Page 79 CHAPTER 3 CPU FUNCTIONS (2) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read/written in 8-bit or 1-bit units. Address After reset PRERR UNLOCK FFFFF078H 0000000XB Bit position Bit name...

  • Page 80: Chapter 4 Bus Control Function

    CHAPTER 4 BUS CONTROL FUNCTION The V853 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features 16-bit data bus External devices connected through multiplexed I/O port pins Wait function •...

  • Page 81: Bus Access

    2. n: Number of inserted wait clock 4.3.2 Bus width The V853 carries out peripheral I/O access and external memory access in 8-, 16-, or 32-bit units. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, the access to even address and the access to odd address.
  • Page 82 CHAPTER 4 BUS CONTROL FUNCTION (3) Word access (32 bits) In word access to external memory, the lower halfword is accessed first and then the higher halfword is accessed. First Second Word data External data bus Word data External data bus User’s Manual U10913EJ6V0UM...

  • Page 83: Memory Block Function

    CHAPTER 4 BUS CONTROL FUNCTION 4.4 Memory Block Function The 16 MB memory space is divided into memory blocks of 1 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. FFFFFFH FFFFFFH Block 15...

  • Page 84: Wait Function

    CHAPTER 4 BUS CONTROL FUNCTION 4.5 Wait Function 4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a bus cycle for two memory blocks. The number of wait states can be programmed by using data wait control register (DWC).

  • Page 85: External Wait Function

    CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external WAIT signal does not affect the access times of the internal ROM, internal RAM, and peripheral I/O areas.

  • Page 86: Idle State Insertion Function

    CHAPTER 4 BUS CONTROL FUNCTION 4.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time (t ) on memory read accesses, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle following continuous bus cycles starts after one idle state.

  • Page 87: Bus Hold Function

    When the HLDRQ pin becomes inactive (high) indicating that the request for the bus is cleared, these pins are driven again. During bus hold period, the V853 continues internal operation until external memory access. In the bus hold status, the HLDAK pin becomes active (low).

  • Page 88: Bus Timing

    CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Timing (1) Memory read (0 waits) CLKOUT Address A16 to A19 Address Data AD0 to AD15 ASTB DSTB UBEN LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
  • Page 89 CHAPTER 4 BUS CONTROL FUNCTION (2) Memory read (1 wait) CLKOUT Address A16 to A19 Address Data AD0 to AD15 ASTB DSTB UBEN LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
  • Page 90 CHAPTER 4 BUS CONTROL FUNCTION (3) Memory read (0 waits, idle state) CLKOUT Address A16 to A19 Address Data AD0 to AD15 ASTB DSTB UBEN LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
  • Page 91 CHAPTER 4 BUS CONTROL FUNCTION (4) Memory read (1 wait, idle state) CLKOUT Address A16 to A19 Address Data AD0 to AD15 ASTB DSTB UBEN LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
  • Page 92 CHAPTER 4 BUS CONTROL FUNCTION (5) Memory write (0 waits) CLKOUT Address A16 to A19 Note Address Data AD0 to AD15 ASTB DSTB UBEN LBEN WAIT Note AD0 to AD7 output invalid data when odd address byte data is accessed. AD8 to AD15 output invalid data when even address byte data is accessed.
  • Page 93 CHAPTER 4 BUS CONTROL FUNCTION (6) Memory write (1 wait) CLKOUT Address A16 to A19 Note Address Data AD0 to AD15 ASTB DSTB UBEN LBEN WAIT Note AD0 to AD7 output invalid data when odd address byte data is accessed. AD8 to AD15 output invalid data when even address byte data is accessed.
  • Page 94 CHAPTER 4 BUS CONTROL FUNCTION (7) Bus hold timing CLKOUT HLDRQ HLDAK Undefined A16 to A19 Address Address Undefined AD0 to AD15 Address Data Address ASTB DSTB UBEN Undefined LBEN WAIT Caution If the transition to the bus hold status takes place after a write cycle, a high-level signal may be output momentarily from the R/W pin immediately before the HLDAK signal changes from the high level to the low level.

  • Page 95: Bus Priority

    CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order.

  • Page 96: On-Chip Peripheral I/O Interface

    CHAPTER 4 BUS CONTROL FUNCTION 4.11 On-Chip Peripheral I/O Interface Access to the on-chip peripheral I/O area is not output to the external bus. Therefore, the on-chip peripheral I/O area can be accessed in parallel with instruction fetch access. Accesses to the on-chip peripheral I/O area take, in most cases, three clock cycles. However, accesses to the following timer/counter registers may take from 3 to 4 cycles.

  • Page 97: Chapter 5 Interrupt/Exception Processing Function

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V853 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can service a total of 33 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependent on program execution.
  • Page 98 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt List (1/2) Type Classification Interrupt/Exception Source Default Exception Vector Restored Priority Code Address Name Control Generating Source Generating Register Unit Reset Interrupt RESET – Reset input – – 0000H 00000000H Undefined Non-maskable Interrupt –...
  • Page 99 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt List (2/2) Type Classification Interrupt/Exception Source Default Exception Vector Restored Priority Code Address Name Control Generating Source Generating Register Unit Maskable Interrupt INTP140/ P14IC0 INTP140 pin/CC140 Pin/RPU 0180H 00000180H nextPC INTCC140 match Interrupt INTP141/ P14IC1...

  • Page 100: Non-Maskable Interrupt

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2 Non-Maskable Interrupt The non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (DI states) in the interrupt disabled (DI) status. The NMI is not subject to priority control and takes precedence over all the other interrupts.

  • Page 101: Acknowledgement Operation

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.1 Acknowledgement operation If the non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher halfword (FECC) of ECR.
  • Page 102 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is executing: Main routine (PSW.NP = 1) NMI request → NMI request → NMI request pending because PSW.NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is executing: Main routine...

  • Page 103: Restore Operation

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.2 Restore operation Execution is restored from the non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0 and the NP bit of PSW is 1.

  • Page 104: Non-Maskable Interrupt Status Flag (Np)

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when the NMI interrupt has been acknowledged, and masks all interrupt and exceptions to prohibit multiple interrupts from being acknowledged.

  • Page 105: Maskable Interrupts

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V853 has 32 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.

  • Page 106: Block Diagram

    Internal Bus ISPR XXMKn (Interrupt mask flag) INTOV11 OVIF11 INTOV12 OVIF12 INTOV13 OVIF13 INTOV14 OVIF14 INTP110/INTCC110 P11IF0 INTP111/INTCC111 P11IF1 Handler INTP112/INTCC112 P11IF2 address INTP113/INTCC113 P11IF3 generator INTP120/INTCC120 P12IF0 INTP121/INTCC121 P12IF1 INTP122/INTCC122 P12IF2 INTP123/INTCC123 P12IF3 INTP130/INTCC130 P13IF0 INTP131/INTCC131 INTP110 P13IF1 INTP111 INTP132/INTCC132 INTM1 INTP112...

  • Page 107: Operation

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.2 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower halfword of ECR (EICC). (4) Sets the ID bit of PSW and clears the EP bit.
  • Page 108 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-5. Maskable Interrupt Servicing INT input INTC acknowledged XXIF = 1 Interrupt request? XXMK = 0 Interrupt unmasked? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with same priority?

  • Page 109: Restore

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.3 Restore To restore execution from the maskable interrupt servicing, the RETI instruction is used. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of PC and PSW from EIPC and EIPSW because the EP bit of PSW is 0 and the NP bit of PSW is 0.

  • Page 110: Priorities Of Maskable Interrupts

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.4 Priorities of maskable interrupts The V853 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxPRn) in an interrupt control register (xxICn).
  • Page 111 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Example of Interrupt Nesting Process (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the priority of (level 3) (level 2) b is higher than that of a and interrupts are enabled.
  • Page 112 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Example of Interrupt Nesting Process (2/2) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its priority is Interrupt request k lower than that of i.
  • Page 113 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-8. Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Processing of interrupt request b • Interrupt request b and c are acknowledged Interrupt request c (level 1) first according to their priorities.

  • Page 114: Interrupt Control Register (Xxicn)

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.5 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units. Address After reset xxICn...
  • Page 115 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION The address and bits of each interrupt control register are shown below. Table 5-2. Address and Bits of Interrupt Control Register Address Register FFFFF100H OVIC11 OVIF11 OVMK11 OVPR112 OVPR111 OVPR110 FFFFF102H OVIC12 OVIF12 OVMK12 OVPR122 OVPR121 OVPR120 FFFFF104H...

  • Page 116: Noise Eliminator

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.6 Noise eliminator Pins INTPn0 to INTPn3, TIn, TCLRn, and ADTRG are provided with timing controllers for maintaining the following noise elimination time (n = 11 to 14). A signal input, which changes a level in the time less than the noise elimination time, is not acknowledged internally. Noise Elimination Time TCLR11 to TCLR14 2 to 3 T...

  • Page 117: Edge Detection Function

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.7 Edge detection function External interrupt mode registers 1 to 4 (INTM1 to INTM4) specify the valid edges of external interrupt requests INTP110 to INTP112, INTP113/ADTRG, INTP120 to INTP123, INTP130 to INTP133, and INTP140 to INTP143 that are input from external pins.

  • Page 118: In-Service Priority Register (Ispr)

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.8 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced.

  • Page 119: Software Exception

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4 Software Exception The software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 5.4.1 Operation If the software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.

  • Page 120: Restore

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.

  • Page 121: Exception Status Flag (Ep)

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.3 Exception status flag (EP) The EP flag in the PSW is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset 00000020H Bit position Bit name Function Exception Pending...

  • Page 122: Exception Trap

    The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V853, an illegal op code exception (ILGOP: ILleGal OPcode trap) is considered as an exception trap. Illegal op code exception occurs if the subop code field of an instruction to be executed next is not a valid op code.

  • Page 123: Restore

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of PSW is 1.

  • Page 124: Multiple Interrupts

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.6 Multiple Interrupts Multiple interrupt servicing is a function that allows the nesting of interrupts. If a higher priority interrupt is generated and acknowledged, it will be allowed to stop a current interrupt service routine in progress. Execution of the original routine will resume once the higher priority interrupt routine is completed.
  • Page 125 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) To acknowledge maskable interrupts in service routine Service routine of maskable interrupt or exception • Saves EIPC to memory or register • Saves EIPSW to memory or register • EI instruction (enables interrupt acknowledgement) ←...

  • Page 126: Interrupt Latency Time

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.7 Interrupt Latency Time The following table describes the V853 interrupt latency time. Figure 5-14. Pipeline Operation upon Reception of Interrupt Request (Outline) 7 to 14 system clocks 4 system clocks Internal system clock (CLKOUT output)

  • Page 127: Periods In Which Interrupts Are Not Acknowledged

    CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.8 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction. Interrupt request non sample instructions are as follows. •...
  • Page 128 (1) Acknowledgement of interrupt servicing following EI instruction The V853 requires a minimum of 7 clocks from the occurrence of an interrupt request until the interrupt request is acknowledged as the interrupt request determination period. Since instructions can continue to be executed during this period, executing the DI (Disable Interrupt) instruction results in the interrupt disabled state.

  • Page 129: Chapter 6 Clock Generator Function

    CHAPTER 6 CLOCK GENERATOR FUNCTION The clock generator (CG) generates and controls the internal system clock ( φ ), which is supplied to all the internal hardware units including the CPU. 6.1 Features Multiplication function by PLL (Phase Locked Loop) synthesizer Clock source •...

  • Page 130: Selecting Input Clock

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.3 Selecting Input Clock The clock generator consists of an oscillator and a PLL synthesizer. When a 6.5536 MHz crystal resonator or ceramic resonator is connected across the X1 and X2 pins for example, the clock generator can generate a 32.768 (Max.

  • Page 131: Clock Control Register (Ckc)

    , φ φ φ φ φ = 1 × f φ = 1/2 × fxx, φ = 1 × fxx are used when there is no need to operate the V853 at a high frequency. Power consumption can be reduced by lowering the internal system clock frequency using software.
  • Page 132 CHAPTER 6 CLOCK GENERATOR FUNCTION The sequence of setting data in this register is the same as the power save control register (PSC). However, the limitation items listed in Caution 2 for the 3.4.10 Specific registers do not apply. A setting example is shown below. CKC Register Operation External Clock...

  • Page 133: Pll Lockup

    Following a power-on reset or when releasing the STOP mode, an amount of time will be required for the PLL to stabilize before using any of the V853 hardware functions (PLL lockup time). The state in which the frequency is not stable is called an unlocked state and the state in which it has been stabilized is called a locked status.

  • Page 134: Power Save Control

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5 Power Save Control 6.5.1 General The V853 is provided with the following power save or standby modes to reduce power consumption when CPU operation is not required. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues operation but the operating clock of the CPU stops.
  • Page 135 CHAPTER 6 CLOCK GENERATOR FUNCTION Table 6-1. Operation of Clock Generator by Power Save Control Clock Source Standby Mode Oscillator Clock Supply Clock Supply Circuit Synthesizer to Peripheral to CPU (OSC) PLL mode Oscillation Normal × with resonator HALT × ×...

  • Page 136: Control Registers

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.2 Control registers (1) Power save control register (PSC) This is an 8-bit register that controls the power save mode. This is a specific register, and only access by the specific sequence is valid during write cycles. For details, refer to 3.4.10 Specific registers. Address After reset DCLK1...

  • Page 137: Halt Mode

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.3 HALT mode (1) Entering and operation status In the HALT mode, the clock generator (oscillator and PLL synthesizer) operates, while the operating clock of the CPU stops. Supply of clocks to the other on-chip peripherals continues and they continue to operate. By entering the HALT mode during the idle time of the CPU, the total power consumption of the system can be reduced.
  • Page 138 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) Releasing HALT mode The HALT mode can be released by the non-maskable interrupt request, an unmasked maskable interrupt request, or RESET signal input. (a) Releasing by interrupt request The HALT mode is unconditionally released by the NMI request or an unmasked maskable interrupt request, regardless of the priority.

  • Page 139: Idle Mode

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.4 IDLE mode (1) Entering and operation status In this mode, both the CPU clock and the internal system clock are stopped to further reduce power consumption. However, since the clock generator continues to run, normal operation can resume without having to wait for the oscillator and PLL circuit to stabilize.
  • Page 140 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) Releasing IDLE mode The IDLE mode is released by the NMI signal input or RESET signal input. (a) Releasing by NMI signal input The NMI request is acknowledged and serviced as soon as the IDLE mode has been released. If the IDLE mode is entered in the NMI processing routine, however, only the IDLE mode is released, and the interrupt will not be acknowledged.

  • Page 141: Software Stop Mode

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.5 Software STOP mode (1) Entering and operation status In this mode, the CPU clock, the internal system clock, and the clock generator are stopped, reducing power consumption to only leakage current. In this state, power consumption is minimized. The software STOP mode is entered by setting the PSC register (specific register) using a store (ST/SST) or bit manipulation (SET1/CLR1/NOT1) instruction (refer to 3.4.10 Specific registers).
  • Page 142 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) Releasing software STOP mode The software STOP mode is released by the NMI signal input or RESET signal input. It is necessary to ensure the oscillation stabilization time when releasing from the software STOP mode in the PLL mode and oscillator connection mode (CESEL bit of the PSC register = 0).

  • Page 143: Cautions

    6.5.6 Cautions Note If the V853 is used under the following conditions , a discrepancy occurs between the address indicated by the program counter (PC) and the address at which an instruction is actually read after the power save mode is released.

  • Page 144: Securing Oscillation Stabilization Time

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.6 Securing Oscillation Stabilization Time The time required for the oscillator to become stabilized after the software STOP mode has been released can be secured in the following two ways. (1) By using internal time base counter (NMI signal input) When a valid edge is input to the NMI pin, the software STOP mode is released.
  • Page 145 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) To secure time by signal level width (RESET pin input) The software STOP mode is released when the falling edge is input to the RESET pin. The time required for the clock output from the oscillator to become stabilized is specified by the low-level width of the signal input to the RESET pin.
  • Page 146 CHAPTER 6 CLOCK GENERATOR FUNCTION Table 6-5. Example of Count Time Count Time TBCS Count Clock fxx = 4.0000 MHz fxx = 5.0000 MHz fxx = 6.5536 MHz φ = 20.000 MHz φ = 25.000 MHz φ = 32.768 MHz fxx/2 16.3 ms 13.1 ms...

  • Page 147: Clock Output Control

    CHAPTER 6 CLOCK GENERATOR FUNCTION 6.7 Clock Output Control The operation mode of the CLKOUT pin can be selected by the DCLK0 and DCLK1 bits of the PSC register. By using this operation mode in combination with the HALT, IDLE, or software STOP mode, the power consumption can be effectively reduced (for how to write these bits, refer to 6.5.2 Control registers).

  • Page 148: Chapter 7 Timer/Counter Function (Real-Time Pulse Unit)

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.1 Features Measures pulse intervals and frequency, and outputs programmable pulse • 16-bit measurement possible • Generates pulses of various shapes (interval pulse, one-shot pulse) Timer 1 • 16-bit timer/event counter • Count clock sources: 2 types (divided internal system clock and external pulse input) •...

  • Page 149: Basic Configuration

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2 Basic Configuration Table 7-1. Configuration of Real-Time Pulse Unit (RPU) Generated Capture Timer Output Timer Count Clock Register Read/Write Other Function Interrupt Trigger Signal φ /2 Timer 1 Read INTOV11 – – External clear φ...

  • Page 150: Timer 1

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timer 1 (16-bit timer/event counter) Edge TCLR1n Clear & start detection Clear & start φ φ φ φ Note 1 φ φ INTOV1n TM1n (16 bits) φ m/32 Note 2 Edge TI1n INTCC1n0 detection INTCC1n1...
  • Page 151 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2.1 Timer 1 (1) Timers 11 to 14 (TM11 to TM14) TM1n functions as a 16-bit free-running timer or event counter. Timers 11 to 14 are used to measure cycles and frequency, and also for programmable pulse generation. TM1n is read-only in 16-bit units (n = 1 to 4).
  • Page 152 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Capture/compare registers 1n0 to 1n3 (CC1n0 to CC1n3) (n = 1 to 4) The capture/compare registers are 16-bit registers and are connected to TM1n. These registers can be used as capture or compare registers depending on the specification of timer unit mode register 1n (TUM1n). They can be read/written in 16-bit units.

  • Page 153: Timer 4

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2.2 Timer 4 (1) Timer 4 (TM4) TM4 is a 16-bit timer and is mainly used as an interval timer for software. This timer is read-only in 16-bit units. Address After reset FFFFF350H 0000H TM4 is started or stopped by the CE4 bit of timer control register 4 (TMC4).

  • Page 154: Control Registers

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.3 Control Registers (1) Timer unit mode registers 11 to 14 (TUM11 to TUM14) TUM1n controls the operation of timer 1, and specifies the operation mode of the capture/compare registers (n = 1 to 4). These registers can be read/written in 16-bit units.
  • Page 155 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit position Bit name Function 9, 8 CES1n1, CES1n0 TCLR1n Edge Select Specifies valid edge of external clear input (TCLR1n). CES1n1 CES1n0 Valid edge Falling edge Rising edge RFU (reserved) Both rising and falling edge 7 to 4 CMS1n3 to Capture/Compare Mode Select...
  • Page 156 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Precautions in use of A/D converter (1) When the A/D converter is set to the timer trigger mode The match interrupt of the compare register becomes the A/D conversion start trigger and conversion operations are started.
  • Page 157 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer control registers 11 to 14 (TMC11 to TMC14) TMC11 to TMC14 control operation of TM11 to TM14. These registers can be read/written in 8-bit or 1-bit units. (1/2) Address After reset TMC11 CE11 ETI11...
  • Page 158 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit position Bit name Function PRM1n1 Prescaler Clock Mode Selects intermediate clock ( φ m) of count clock ( φ is internal system clock). 0: φ /2 1: φ /4 Caution Do not change the count clock frequency while the timer is operating. Remark n = 1 to 4 User’s Manual U10913EJ6V0UM...
  • Page 159 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer control register 4 (TMC4) TMC4 controls the operation of TM4. This register can be read/written in 8-bit or 1-bit units. Address After reset TMC4 PRS40 PRM41 PRM40 FFFFF342H Bit position Bit name Function Count Enable Controls operation of timer.
  • Page 160 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Timer output control registers 11 to 14 (TOC11 to TOC14) TOC1n control the timer outputs from the TO1n0 and TO1n1 pins (n = 1 to 4). These registers can be read/written in 8-bit or 1-bit units. Address After reset TOC11...
  • Page 161 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (6) Timer overflow status register (TOVS) This register is assigned flags that indicate the occurrence of an overflow from TM11 to TM14 and TM4. This register can be read/written in 8-bit or 1-bit units. By testing and resetting the TOVS register via software, the occurrence of an overflow can be polled.

  • Page 162: Timer 1 Operation

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4 Timer 1 Operation 7.4.1 Count operation Timer 1 functions as a 16-bit free-running timer or event counter, as specified by timer control register 1n (TMC1n) (n = 1 to 4). When it is used as a free-running timer, and when the count values of TM1n match the value of any of the CC1n0 to CC1n3 registers, an interrupt signal is generated, and the timer output signals (TO1n0 and TO1n1) can be set/ reset.

  • Page 163: Selecting Count Clock Frequency

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.2 Selecting count clock frequency An internal or external count clock can be output to timer 1, selectable by the ETI1n bit of the TMC1n register (n = 1 to 4). Caution Do not change the count clock frequency while the timer is operating. (1) Internal count clock (ETI1n bit = 0) The internal count clock frequency is selected by the PRM1n1, PRS1n0, and PRS1n1 bits of the TMC1n register, from φ...

  • Page 164: Overflow

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.3 Overflow If the TM1n register overflows as a result of counting the count clock frequency up to FFFFH, the OVF1n bit of the TOVS register is set (to 1), and an overflow interrupt (INTOV1n) is generated. After the overflow has occurred, the timer can be stopped by setting the OSTn bit of the TUM1n register to 1.

  • Page 165: Clearing/Starting Timer By Tclr Signal Input

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.4 Clearing/starting timer by TCLR signal input Timer 1 usually starts a count operation when the CE1n bit of the TMC1n register is set to 1. It is also possible to clear TM1n and start a count operation by using the external input TCLR1n (n = 1 to 4). When the valid edge is input to the TCLR1n signal after ECLR1n bit = 1, OSTn bit = 0 is set, and the CE1n bit is set to 1, a count operation is started.

  • Page 166: Capture Operation

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-4. Relationship Between Clear/Start by TCLR1n Signal Input and Overflow (When ECLR1n = 1, OSTn = 1) Overflow FFFFH Count starts TM1n CE1n TCLR1n TCLR1n TCLR1n INTOV1n Remark n = 1 to 4 7.4.5 Capture operation A capture operation that captures and holds the count value of TM1n and loads it to a capture register asynchronously to an external trigger can be performed (n = 1 to 4).
  • Page 167 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) The valid edge of the capture trigger is set by the external interrupt mode register (INTMn). When both the rising and falling edges are specified as the capture trigger, the width of an externally input pulse can be measured.
  • Page 168 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-6. Example of TM11 Capture Operation (When Both Edges Are Specified) FFFFH TM11 count value CE11 ← 1 OVF11 ← 1 (Count start) (overflow) Interrupt request (INTP110) Capture register (CC110) Remark D0 to D2: Count value of TM11 User’s Manual U10913EJ6V0UM...

  • Page 169: Compare Operation

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.6 Compare operation A comparison between the value in a compare register the count value of TM1n can be performed (n = 1 to 4). When the count value of TM1n matches the value of the compare register programmed in advance, a match signal is sent to the output controller (refer to Figure 7-7).
  • Page 170 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Timer 1 has eight timer output pins (TO1n0, TO1n1). The count value of TM1n is compared with the value of CC1n2. If the two values match, the output level of the TO1n1 pin is set. The count value of TM1n is also compared with the value of CC1n3. If the two values match, the output level of the TO1n1 pin is reset.

  • Page 171: Timer 4 Operation

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.5 Timer 4 Operation 7.5.1 Count operation Timer 4 functions as a 16-bit interval timer. The operation is specified by timer control register 4 (TMC4). The operation of timer 4 counts the internal count clocks ( φ /2 to φ /1024) specified by the PRS40, PRM41, and PRM40 bits of the TMC4 register.

  • Page 172: Compare Operation

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.5.4 Compare operation A comparison can be performed between the count value of TM4 and the value of the compare register (CM4). If the count value of TM4 matches the value of the compare register, a match interrupt (INTCM4) is generated. As a result, TM4 is cleared to 0 at the next count timing (refer to Figure 7-10 (a)).
  • Page 173 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-10. Examples of TM4 Compare Operation (2/2) (b) Setting 0 to CM4 Count clock Count up TM4 clear Clear FFFFH Match detected (INTCM4) Overflow Remark Interval time = (FFFFH + 1) × count clock cycle User’s Manual U10913EJ6V0UM...

  • Page 174: Application Examples

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.6 Application Examples (1) Operation as interval timer (timer 4) Timer 4 is used as an interval timer that repeatedly generates an interrupt request at time intervals specified by the count value preset to compare register CM4. Figure 7-11.
  • Page 175 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Pulse width measurement (timer 1) Timer 1 is used to measure the pulse width. In this example, the width of the high or low level of an external pulse input to the INTP112 pins is measured. The value of timer 1 (TM11) is captured to a capture/compare register (CC112) in synchronization with the valid edge of the INTP112 pin (both the rising and falling edges) and is held, as shown in Figure 7-13.
  • Page 176 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-14. Example of Setting Procedure for Pulse Width Measurement Pulse width measurement initial setting Setting of TMC11 register ; Specifies count clock Setting of INTM1 register ; Specifies both edges as valid INTM1.
  • Page 177 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) PWM output (timer 1) Any square wave can be output to the timer output pins (TO1n0, TO1n1) by combining timer 1 and the timer output function and can be used as a PWM output (n = 1 to 4). Eight capture/compare registers, CC1n0 and CC1n1, are used in this example of PWM output.
  • Page 178 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-17. Example of Programming Procedure of PWM Output PWM output initial setting Setting of TOC1n register ; Specifies active level (high level) <- TOC1n. ENTO1n0 Enables timer output <- TOC1n. ALV1n0 Setting of TUM1n register ;...
  • Page 179 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-18. Example of Interrupt Request Servicing Routine, Modifying Compare Value INTCC1n0 interrupt servicing INTCC1n1 interrupt servicing Sets time (number of counts) to set TO1n0 Sets time (number of counts) to reset TO1n0 output to 1 next, to compare register CC1n0 output to 0 next, to compare register CC1n1 RETI...
  • Page 180 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Frequency measurement (timer 1) Timer 1 can be used to measure the cycle or frequency of an external pulse input to the INTP1n0 to INTP1n3 pins (n = 1 to 4). In this example, the frequency of the external pulse input to the INTP110 pin is measured with an accuracy of 16 bits, by combining the use of timer 1 and the capture/compare register CC110.
  • Page 181 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-20. Example of Setup Procedure for Frequency Measurement Cycle measurement initial setting ; Specifies count clock Setting of TMC11 register ; Specifies CC110 register Setting of TUM11 register TUM11. CMS110 <- 0 as capture register Setting of INTM1 register ;...

  • Page 182: Cautions

    CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.7 Cautions A match is detected by the compare register immediately after the timer value matches the compare register value, and does not take place in the following cases. (1) When compare register is rewritten (TM11 to TM14, TM4) Count clock Value of timer n –...
  • Page 183 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) When timer is cleared (TM4) Count clock Value of timer FFFEH FFFFH Internal match clear Compare register value 0000H Match detection Match does not occur Remark When timer 1 is used as a free-running timer, the timer value is cleared to 0 when the timer overflows. Count clock Value of timer FFFEH...

  • Page 184: Chapter 8 Serial Interface Function

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.1 Features The V853 is provided with two types of serial interfaces which operate as 6-channel transmission/reception channels. Four channels can be used simultaneously. There are the following two types of interfaces. (1) Asynchronous serial interface (UART0, UART1): 2 channels...

  • Page 185: Asynchronous Serial Interface 0 And 1 (Uart0 And Uart1)

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2 Asynchronous Serial Interface 0 and 1 (UART0 and UART1) 8.2.1 Features (baud rate generator and φ = 33 MHz operation) Note Transfer rate: 150 bps to 76800 bps (baud rate generator and φ = 20 MHz operation) Note 110 bps to 307200 bps ( φ...

  • Page 186: Configuration Of Asynchronous Serial Interface

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.2 Configuration of asynchronous serial interface The asynchronous serial interface is controlled by the asynchronous serial interface mode register (ASIMn0, ASIMn1) and the asynchronous serial interface status register (ASISn) (n = 0, 1). The receive data is stored in the receive buffer (RXBn), and the transmit data is written to the transmit shift register (TXSn).
  • Page 187 CHAPTER 8 SERIAL INTERFACE FUNCTION (6) Transmit shift registers (TXS0, TXS0L, TXS1, TXS1L) TXSn are 9-bit shift registers used for transmit operation. When data is written to these registers, the transmission operation is started. A transmission complete interrupt request (INTSTn) is generated after each complete data frame is transmitted.

  • Page 188: Control Registers

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.3 Control registers (1) Asynchronous serial interface mode registers 00, 01, 10, and 11 (ASIM00, ASIM01, ASIM10, ASIM11) These registers specify the transfer mode of UART0 and UART1. They can be read/written in 8-bit or 1-bit units. (1/3) Address After reset...
  • Page 189 CHAPTER 8 SERIAL INTERFACE FUNCTION (2/3) Bit position Bit name Function 5, 4 PSn1, PSn0 Parity Select Specifies parity bit. PSn1 PSn0 Operation No parity. Extended bit operation 0 parity Transmission side → Transmits with parity bit 0 Reception side → Does not generate parity error on reception Odd parity Even parity •...
  • Page 190 CHAPTER 8 SERIAL INTERFACE FUNCTION (3/3) Bit position Bit name Function SCLSn Serial Clock Source Specifies serial clock. 0: Specified by BRGCn and BPRMn 1: φ /2 • When SCLSn = 1 φ /2 (system clock) is selected as the serial clock source. In asynchronous mode, the baud rate is expressed as follows because a sampling rate of ×16 is used.
  • Page 191 CHAPTER 8 SERIAL INTERFACE FUNCTION Address After reset ASIM01 EBS0 FFFFF0C2H ASIM11 EBS1 FFFFF0D2H Bit position Bit name Function EBSn Extended Bit Select Specifies extended bit operation of transmit/receive data when no parity is specified (PSn1, PSn0 = 00). 0: Disables extended bit operation 1: Enables extended bit operation When extended bit operation is enabled, 1 data bit is appended as the most significant bit to the 8-bit transmit/receive data, and therefore 9-bit data is communicated.
  • Page 192 CHAPTER 8 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0 and 1 (ASIS0, ASIS1) These registers consist of a 3-bit error flag that indicates error status when UARTn receive is completed and a transmit status flag. The error flags always indicate the status of an error that has occurred most recently. If two or more errors occur before the current received data, only the status of the error that has occurred last is retained.
  • Page 193 CHAPTER 8 SERIAL INTERFACE FUNCTION (3) Receive buffers 0, 0L, 1, and 1L (RXB0, RXB0L, RXB1, RXB1L) RXBn are 9-bit buffer registers that hold the receive data. When 7- or 8-bit character data is received, the higher bit of these registers are 0. When these registers are accessed in 16-bit units, RXB0 and RXB1 are specified.
  • Page 194 CHAPTER 8 SERIAL INTERFACE FUNCTION (4) Transmit shift registers 0, 0L, 1, and 1L (TXS0, TXS0L, TXS1, TXS1L) TXSn are 9-bit shift registers for data transmission. The transmit operation is started when data is written to these registers during transmission enable status. If data is written to the transmit shift register in the transmission disabled status, the values written are ignored.

  • Page 195: Interrupt Request

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.4 Interrupt request UARTn generates the following three interrupt requests (n = 0, 1). • Receive error interrupt (INTSERn) • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) Of these three, the receive error interrupt has the highest default priority, followed by the reception completion interrupt and transmission completion interrupt.

  • Page 196: Operation

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.5 Operation (1) Data format Full-duplex serial data is transmitted/received. One data frame of the transmit/receive data consists of a start bit, character bits, parity bit, and stop bit, as shown in Figure 8-2. The length of the character bit, parity, and the length of the stop bit in one data frame are specified by the asynchronous serial interface mode registers (ASIMn0, ASIMn1) (n = 0, 1).
  • Page 197 CHAPTER 8 SERIAL INTERFACE FUNCTION (c) Transmission interrupt request When one frame of data or character has been completely transferred, a transmission completion interrupt request (INTSTn) occurs. Unless the data to be transmitted next is written to the TXSn or TXSnL registers, the transmission is aborted.
  • Page 198 CHAPTER 8 SERIAL INTERFACE FUNCTION (3) Reception When reception is enabled, sampling of the RXDn pin is started, and reception of data begins when the start bit is detected. Each time one frame of data or character has been received, the reception completion interrupt (INTSRn) occurs.
  • Page 199 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-4. Asynchronous Serial Interface Reception Completion Interrupt Timing Stop Parity/ RXDn (input) extended Start INTSRn interrupt Remark n = 0, 1 (d) Reception error flag Three error flags, parity error, framing error, and overrun error flags, are related to the reception operation. The receive error interrupt request occurs as a result of ORing these three error flags.

  • Page 200: Clocked Serial Interface 0 To 3 (Csi0 To Csi3)

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3 Clocked Serial Interface 0 to 3 (CSI0 to CSI3) 8.3.1 Features Number of channels: 4 channels (CSIn) High transfer speed: 8.25 Mbps max. (@ φ = 33 MHz operation: CSI0 to CSI2) 2 Mbps max. (@ φ = 33 MHz operation: CSI3) Half-duplex communication Character length: 8 bits MSB first/LSB first selectable...
  • Page 201 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-6. Block Diagram of Clocked Serial Interface Internal bus CSIMn CTXEn CRXEn CSOTn MODn CLSn1 CLSn0 SO latch Shift register (SIOn) Note Baud rate generator Serial clock SCKn controller Note Interrupt INTCSIn Serial clock counter controller Note SO0 to SO2, SCK0 to SCK2: CMOS output...

  • Page 202: Control Registers

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.3 Control registers (1) Clocked serial interface mode registers 0 to 3 (CSIM0 to CSIM3) These registers specify the basic operation mode of CSI0 to CSI3. They can be read/written in 8-bit or 1-bit units (note, however, that bit 5 can only be read). (1/2) After reset Address...
  • Page 203 CHAPTER 8 SERIAL INTERFACE FUNCTION (2/2) Bit position Bit name Function 1, 0 CLSn1, CLSn0 Clock Source Specifies serial clock. CLSn1 CLSn0 Specifies Serial Clock SCKn pin External clock Input Note 1 Internal clock Specified by BPRMn register Output φ /4 Note 2 Output φ...

  • Page 204: Basic Operation

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.4 Basic operation (1) Transfer format CSIn transmits/receives data using three lines: one clock line and two data lines (n = 0 to 3). Serial transfer is started by executing an instruction that writes transfer data to the SIOn register. During transmission, the data is output from the SOn pin in synchronization with the falling edge of SCKn.
  • Page 205 CHAPTER 8 SERIAL INTERFACE FUNCTION (2) Enabling transmission/reception CSIn has only one 8-bit shift register and does not have a buffer. Transmission and reception are therefore performed simultaneously. (a) Transmission/reception enabling condition The CTXEn and CRXEn bits of the CSIMn register specify the conditions of CSIn transmission/reception enable.
  • Page 206 CHAPTER 8 SERIAL INTERFACE FUNCTION (b) Starting transmission/reception Transmission/reception is started by reading/writing the SIOn register. Transmission/reception is controlled by setting the transmission enable bit (CTXEn) and reception enable bit (CRXEn) as follows. CTXEn CRXEn Start Condition Does not start Reads SIOn register Writes SIOn register Writes SIOn register...

  • Page 207: Transmission In Csi0 To Csi3

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.5 Transmission in CSI0 to CSI3 Transmission is started when data is written to the SIOn register after transmission has been enabled by clocked serial interface mode register n (CSIMn) (n = 0 to 3). (1) Starting transmission Transmission is started by writing the transmit data to shift register n (SIOn) after the CTXEn bit of clocked serial interface mode register n (CSIMn) has been set (the CRXEn bit is cleared to 0).

  • Page 208: Reception In Csi0 To Csi3

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.6 Reception in CSI0 to CSI3 Reception is started if the status is changed from reception disabled to reception enabled by the clocked serial interface mode register (CSIMn) or if the SIOn register is read by the CPU with reception enabled (n = 0 to 3). (1) Starting reception Reception can be started in the following two ways.

  • Page 209: Transmission/Reception In Csi0 To Csi3

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.7 Transmission/reception in CSI0 to CSI3 Transmission and reception can be executed simultaneously if both transmission and reception are enabled by clocked serial interface mode register n (CSIMn) (n = 0 to 3). (1) Starting transmission/reception Transmission and reception can be performed simultaneously (transmission/reception operation) when both the CTXEn and CRXEn bits of clocked serial interface mode register n (CSIMn) are set to 1.

  • Page 210: System Configuration Example

    CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-9. Timing of 3-Wire Serial I/O Mode (Transmission/Reception) SCKn DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSIn Serial transmission/ reception completion interrupt occurs Transfer starts in synchronization with falling edge of SCKn Execution of SIOn register write instruction Remark n = 0 to 3 8.3.8 System configuration example...

  • Page 211: Baud Rate Generators 0 To 2 (Brg0 To Brg2)

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4 Baud Rate Generators 0 to 2 (BRG0 to BRG2) 8.4.1 Configuration and function The serial clock of the serial interface can be selected for each channel from the baud rate generator output or φ (internal system clock). The serial clock source for UART0 and UART1 is specified by the SCLS0 and SCLS1 bits of the ASIM00 and ASIM10 registers.
  • Page 212 CHAPTER 8 SERIAL INTERFACE FUNCTION (1) Dedicated baud rate generators 0 to 2 (BRG0 to BRG2) Dedicated baud rate generator n (BRGn) consists of an 8-bit timer (TMBRGn) that generates a serial clock for transmission/reception, a compare register (BRGCn), and a prescaler (n = 0 to 2). (a) Input clock The internal system clock ( φ...
  • Page 213 CHAPTER 8 SERIAL INTERFACE FUNCTION Table 8-2. Setting Values of Baud Rate Generators 0 to 2 φ = 33 MHz φ = 25 MHz φ = 16 MHz φ = 12.5 MHz Baud Rate [bps] Error Error Error UART0 , UART1 CSI0 to CSI3 Error —...
  • Page 214 CHAPTER 8 SERIAL INTERFACE FUNCTION (c) Baud rate error The baud rate error is calculated as follows. Actual baud rate (baud rate with error) × 100 Error [%] = – 1 Desired baud rate (normal baud rate) Example: (9520/9600 – 1) × 100 = –0.833 [%] (5000/4800 –...

  • Page 215: Baud Rate Generator Compare Registers 0 To 2 (Brgc0 To Brgc2)

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.2 Baud rate generator compare registers 0 to 2 (BRGC0 to BRGC2) These are 8-bit compare registers that set a timer/count value for the baud rate generator. These registers can be read/written in 8-bit or 1-bit units. Address After reset BRGC0...

  • Page 216: Baud Rate Generator Prescaler Mode Registers 0 To 2 (Bprm0 To Bprm2)

    CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.3 Baud rate generator prescaler mode registers 0 to 2 (BPRM0 to BPRM2) These registers control the timer/count operation of the baud rate generator and select a count clock. They can be read/written in 8-bit or 1-bit units. Address After reset BPRM0...

  • Page 217: Chapter 9 A/D Converter

    CHAPTER 9 A/D CONVERTER 9.1 Features Analog input: 8 channels 10-bit A/D converter On-chip A/D conversion result register (ADCR0 to ADCR7) 10 bits × 8 A/D conversion trigger mode A/D trigger mode Timer trigger mode External trigger mode Sequential conversion 9.2 Configuration The A/D converter of the V850 adopts the sequential conversion method, and uses the A/D converter mode...
  • Page 218 CHAPTER 9 A/D CONVERTER (5) Successive approximation register (SAR) The SAR is a 10-bit register in which series resistor string voltage tap data, which have values that match the analog input voltage values, is set 1 bit at a time beginning with the most significant bit (MSB). If data is set in the SAR all the way to the least significant bit (LSB) (A/D conversion completed), the contents of the SAR (conversion results) are held in the A/D conversion result register (ADCRn).
  • Page 219 CHAPTER 9 A/D CONVERTER Figure 9-1. Block Diagram of A/D Converter Series resistor string ANI0 Sample & hold circuit REF1 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 Voltage comparator ANI7 SAR (10) INTAD ADCR0 INTCC110 INTCC111 ADCR1 Controller INTCC112 ADCR2 INTCC113 ADCR3 ADTRG Noise...

  • Page 220: Control Registers

    CHAPTER 9 A/D CONVERTER 9.3 Control Registers (1) A/D converter mode register 0 (ADM0) ADM0 is an 8-bit register that selects the analog input pin, specifies the operation mode, and executes conversion operations. This register can be read/written in 8-bit or 1-bit units, however, when the data is written to the ADM0 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning.
  • Page 221 CHAPTER 9 A/D CONVERTER (2/2) Bit position Bit name Function 2 to 0 ANIS2 to Analog Input Select ANIS0 Specifies analog input pin to be A/D converted. ANIS2 ANIS1 ANIS0 Select mode Scan mode A/D trigger Timer trigger A/D trigger Timer trigger mode mode...
  • Page 222 CHAPTER 9 A/D CONVERTER (2) A/D converter mode register 1 (ADM1) ADM1 is an 8-bit register that specifies the conversion operation time and trigger mode. This register can be read/written in 8-bit or 1-bit units. However, when the data is written to the ADM1 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning.

  • Page 223: A/D Converter Operation

    CHAPTER 9 A/D CONVERTER (3) A/D conversion result register (ADCR0 to ADCR7, ADCR0H to ADCR7H) ADCRn is a 10-bit register that holds the A/D conversion results. ADCRn consists of eight 10-bit registers (n = 0 to 7). This register is read-only in 16-bit or 8-bit units. During 16-bit access to this register, the ADCRn register is specified, and during higher 8-bit access, the ADCRnH register is specified.

  • Page 224: Input Voltage And Conversion Results

    CHAPTER 9 A/D CONVERTER 9.4.2 Input voltage and conversion results The following relationship exists between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion results (A/D conversion result register (ADCRn)). × 1024 + 0.5) ADCRn = INT ( REF1 REF1...

  • Page 225: Operation Mode And Trigger Mode

    CHAPTER 9 A/D CONVERTER 9.4.3 Operation mode and trigger mode Various conversion operations can be specified for the A/D converter by specifying the operation mode and trigger mode. The operation mode and trigger mode are set by the ADM0 and ADM1 registers. The following shows the relationship between the operation mode and trigger mode.
  • Page 226 CHAPTER 9 A/D CONVERTER (c) External trigger mode Mode in which the conversion timing of the analog input to the ANI0 to ANI3 pins is specified using the ADTRG pin. This mode can be specified only with the ANI0 to ANI3 pins. (2) Operation mode There are two types of operation modes that set the ANI0 to ANI7 pins: the select mode and the scan mode.
  • Page 227 CHAPTER 9 A/D CONVERTER • 1-buffer mode A/D converts one analog input specified by the ADM0 register. The conversion results are stored in the ADCRn register corresponding to the analog input. The analog input and ADCRn register correspond one to one, and an A/D conversion end interrupt (INTAD) is generated each time one A/D conversion ends.
  • Page 228 CHAPTER 9 A/D CONVERTER • 4-buffer mode A/D converts one analog input four times and stores the results in the ADCR0 to ADCR3 registers. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions end. Figure 9-4. Select Mode Operation Timing: 4-Buffer Mode (ANI6) ANI6 Data 4 Data 5...
  • Page 229 CHAPTER 9 A/D CONVERTER (b) Scan mode Selects the analog inputs specified by the ADM0 register sequentially from the ANI0 pin, after which A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input. When the conversion of the specified analog input ends, the INTAD interrupt is generated.

  • Page 230: Operation In A/D Trigger Mode

    CHAPTER 9 A/D CONVERTER 9.5 Operation in A/D Trigger Mode When the CE bit of the ADM0 register is set to 1, A/D conversion is started. 9.5.1 Select mode operations A/D converts the analog input specified by the ADM0 register. The conversion results are stored in the ADCRn register corresponding to the analog input.
  • Page 231 CHAPTER 9 A/D CONVERTER (2) 4-buffer mode (A/D trigger select: 4-buffer) A/D converts one analog input four times and stores the results in four ADCRn registers. When A/D conversion ends four times, an INTAD interrupt is generated and the A/D conversion terminates. When 1 is written to the CE bit of the ADM0 register, A/D conversion can be restarted.

  • Page 232: Scan Mode Operations

    CHAPTER 9 A/D CONVERTER 9.5.2 Scan mode operations Selects the analog inputs specified by the ADM0 register sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input. When the conversion of all the specified analog input ends, the INTAD interrupt is generated, and A/D conversion is terminated.

  • Page 233: Operation In Timer Trigger Mode

    CHAPTER 9 A/D CONVERTER 9.6 Operation in Timer Trigger Mode The A/D converter is the match interrupt signal of the TM11 compare register, and can set conversion timings to a maximum of four channel analog inputs (ANI0 to ANI3). TM11 and four capture/compare registers (CC110 to CC113) are used for the timer for specifying the analog conversion trigger.

  • Page 234: Select Mode Operations

    CHAPTER 9 A/D CONVERTER 9.6.1 Select mode operations A/D converts an analog input (ANI0 to ANI3) specified by the ADM0 register. The conversion results are stored in the ADCRn register corresponding to the analog input. For the select mode, the 1-buffer mode and 4-buffer mode are provided according to the storage method of the A/D conversion results (n = 0 to 7).
  • Page 235 CHAPTER 9 A/D CONVERTER (b) 4-trigger mode (Timer trigger select: 1-buffer, 4-trigger) A/D converts one analog input four times using four match interrupt signals (INTCC110 to INTCC113) as triggers and stores the results in one ADCRn register. The INTAD interrupt is generated with each A/D conversion, and the CS bit of the ADM0 register is reset (0).
  • Page 236 CHAPTER 9 A/D CONVERTER (2) 4-buffer mode operations (Timer trigger select: 4-buffer) A/D conversion of one analog input is executed four times, and the results are stored in the ADCRn register. There are two 4-buffer modes, 1-trigger mode and 4-trigger mode, according to the number of triggers. This mode is suitable for applications that calculate the average of the A/D conversion result.
  • Page 237 CHAPTER 9 A/D CONVERTER (b) 4-trigger mode (Timer trigger select: 4-buffer, 4-trigger) A/D converts one analog input four times using four match interrupt signals (INTCC110 to INTCC113) as triggers and stores the results in four ADCRn registers. The INTAD interrupt is generated when the four A/D conversions end, the CS bit is reset (0), and A/D conversion ends.

  • Page 238: Scan Mode Operations

    CHAPTER 9 A/D CONVERTER 9.6.2 Scan mode operations Selects the analog inputs specified by the ADM0 register sequentially from the ANI0 pin and A/D converts them for the specified number of times using the match interrupt signal as a trigger. In the conversion operation, first the analog input lower channels (ANI0 to ANI3) are A/D converted for the specified number of times.
  • Page 239 CHAPTER 9 A/D CONVERTER Figure 9-13. Example of 1-Trigger Mode (Timer Trigger Scan 1-Trigger) Operation (a) When ANI0 to ANI3 are set for scanning ANI0 ADCR0 ANI1 ADCR1 INTCC110 ANI2 ADCR2 ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7...
  • Page 240 CHAPTER 9 A/D CONVERTER (2) 4-trigger mode (Timer trigger scan: 4-trigger) A/D converts analog inputs for the number of times specified using the match interrupt signal (INTCC110 to INTCC113) as a trigger. The analog input and ADCRn register correspond one to one. When all the A/D specified conversions have ended, the INTAD interrupt is generated and A/D conversion ends.
  • Page 241 CHAPTER 9 A/D CONVERTER Figure 9-14. Example of 4-Trigger Mode (Timer Trigger Scan 4-Trigger) Operation (a) When ANI0 to ANI3 are set for scanning ANI0 ADCR0 ANI1 ADCR1 INTCC110 ANI2 ADCR2 INTCC111 ANI3 ADCR3 A/D converter INTCC112 ANI4 ADCR4 INTCC113 ANI5 ADCR5 ANI6...

  • Page 242: Operation In External Trigger Mode

    CHAPTER 9 A/D CONVERTER 9.7 Operation in External Trigger Mode In the external trigger mode, the analog inputs (ANI0 to ANI3) are A/D converted at the ADTRG pin input timing. The ADTRG pin is also used as the P07 and INTP113 pins. To set the external trigger mode, set the PMC07 bit of the PMC0 register to 1 and the TRG2 to TRG0 bits of the ADM1 register to 110.
  • Page 243 CHAPTER 9 A/D CONVERTER (2) 4-buffer mode (external trigger select: 4-buffer) A/D converts one analog input four times using the ADTRG signal as a trigger and stores the results in four ADCRn registers. The INTAD interrupt is generated and conversion ends when the four A/D conversions end. While the CE bit of the ADM0 register is 1, the A/D conversion is repeated every time a trigger is input from the ADTRG pin.

  • Page 244: Scan Mode Operations (External Trigger Scan)

    CHAPTER 9 A/D CONVERTER 9.7.2 Scan mode operations (external trigger scan) Selects the analog inputs specified by the ADM0 register sequentially from the ANI0 pin using the ADTRG signal as a trigger, and A/D converts them. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7).
  • Page 245 CHAPTER 9 A/D CONVERTER Figure 9-17. Example of Scan Mode (External Trigger Scan) Operation (a) When ANI0 to ANI3 are set for scanning ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ADTRG ANI7 ADCR7 Set CE bit of ADM0 to 1 (enabled)

  • Page 246: Cautions In Use Of A/D Converter

    CHAPTER 9 A/D CONVERTER 9.8 Cautions in Use of A/D Converter (1) When A/D converter is set in the timer trigger mode The match interrupt of the compare register becomes the A/D conversion start trigger and conversion operations are started. At this time, the match interrupt of the compare register also functions as the match interrupt of the compare register for the CPU.

  • Page 247: Cautions

    CHAPTER 9 A/D CONVERTER 9.9 Cautions (1) When 0 is written to the CE bit of the ADM0 register during a conversion operation, the conversion operation stops and the conversion results are not stored in the ADCRn register (n = 0 to 7). (2) Set the interval (input time interval) of the trigger in the external or timer trigger mode to longer than the conversion time specified by the FR2 to FR0 bits of the ADM1 register.

  • Page 248: How To Read A/D Converter Characteristics Table

    CHAPTER 9 A/D CONVERTER 9.10 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
  • Page 249 CHAPTER 9 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0 …… 000 to 0 …… 001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0 ……...
  • Page 250 CHAPTER 9 A/D CONVERTER (7) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (8) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample &...

  • Page 251: Chapter 10 D/A Converter

    CHAPTER 10 D/A CONVERTER 10.1 Features 8-bit resolution D/A converter: 2 channels R-2R mode 10.2 Configuration ANOn REF2 REF3 DACSn DACEn Internal bus Remark n = 0, 1 User’s Manual U10913EJ6V0UM...

  • Page 252: Control Registers

    CHAPTER 10 D/A CONVERTER 10.3 Control Registers (1) D/A converted data coefficient register (DACS0, DACS1) The DACSn register writes the value to be output using the D/A conversion value setting register and outputs the analog value to the ANOn pin (n = 0, 1). This register can be read/written in 8-bit or 1-bit units.

  • Page 253: D/A Converter Operations

    CHAPTER 10 D/A CONVERTER 10.4 D/A Converter Operations When values to be output are written in the DACSn register and analog voltage corresponding to the value written from the ANOn pin is immediately output (n = 0, 1). The output voltage is held until the next time a value is written in the DACSn register.

  • Page 254: Chapter 11 Pwm Unit

    CHAPTER 11 PWM UNIT 11.1 Features PWMn: 2 channels Active level of PWMn output pulse can be selected. Operating clock: Can be selected from φ , φ /2, φ /4, φ /8, and φ /16. ( φ is the internal system clock) PWMn output resolution: Can be selected from 8, 9, 10, and 12 bits Remark n = 0, 1 11.2 Configuration...

  • Page 255: Control Registers

    CHAPTER 11 PWM UNIT 11.3 Control Registers (1) PWM control register (PWMC) Controls PWMn operation, specifies the output active level, and specifies the bit length of the timer counters (TMPn) and compare registers (CMPn) (n = 0, 1). This register can be read/written in 8-bit or 1-bit units. Address After reset PWMC...
  • Page 256 CHAPTER 11 PWM UNIT (2) PWM prescaler register (PWPR) This register selects the operation clock of PWMn, and can be read/written in 8-bit or 1-bit units. However, bit 7 and bit 3 are fixed to 0 by hardware, so writing 1 in these bits will be ignored. Address After reset PWPR...

  • Page 257: Operations

    CHAPTER 11 PWM UNIT (3) PWM buffer registers (PWM0, PWM0L, PWM1, PWM1L) These registers are 12-bit buffer registers that set the control data of the active signal width of the PWMn output. Bits 15 to 12 are fixed to 0 by hardware, so even if 1 is written, it will be ignored. Bits 11 to 8 are not affected by the bit length by the PWMC register, and the written values are read as they are.
  • Page 258 CHAPTER 11 PWM UNIT Figure 11-1. Basic Operation Timing of PWM PWME0, PWME1 TMPn count starts PWM timer overflow PWM0, PWM1 n + 1 n + 2 CMP0, CMP1 n + 1 CMP match PWM output 0, 1 Full count n count n + 1 count Figure 11-2.

  • Page 259: Repeating Frequency

    CHAPTER 11 PWM UNIT 11.4.2 Repeating frequency The repeating frequency of the PWMn is shown below. PWMn Operation Frequency Resolution Repeating Frequency φ φ /2 8 bits φ /2 9 bits φ /2 10 bits φ /2 12 bits φ /2 φ...

  • Page 260: Chapter 12 Port Function

    CHAPTER 12 PORT FUNCTION 12.1 Features The ports of the V853 have the following features. Number of pins: Input: 8 I/O: Multiplexed with I/O pins of other peripheral functions Can be set in input/output mode in 1-bit units Noise elimination Edge detection User’s Manual U10913EJ6V0UM...

  • Page 261: Basic Configuration Of Port

    12.2 Basic Configuration of Port The V853 is provided with a total of 75 input/output port pins (of which eight are input-only port pins) that make up ports 0 to 11. The configuration of the V853’s ports is shown below.
  • Page 262 CHAPTER 12 PORT FUNCTION (1) Function of each port The ports of the V853 have the functions shown in the table below. Each port can be manipulated in 8-bit or 1-bit units and performs various types of control operations. In addition to port functions, the ports also have functions as internal hardware I/O pins, when placed in the control mode.
  • Page 263 CHAPTER 12 PORT FUNCTION (2) Register for setting function after reset and port/control mode of each port pin (1/2) Port Name Pin Name Function After Reset Register for In Single-Chip Mode Setting Mode Port 0 P00/TO110 P00 (Input mode) PMC0 P01/TO111 P01 (Input mode) P02/TCLR11...
  • Page 264 CHAPTER 12 PORT FUNCTION (2/2) Port Name Pin Name Function After Reset Register for In Single-Chip Mode Setting Mode Port 9 P90/LBEN P90 (Input mode) P91/UBEN P91 (Input mode) P92/R/W P92 (Input mode) P93/DSTB P93 (Input mode) P94/ASTB P94 (Input mode) P95/HLDAK P95 (Input mode) P96/HLDRQ...

  • Page 265: Port Pin Functions

    CHAPTER 12 PORT FUNCTION 12.3 Port Pin Functions 12.3.1 Port 0 Port 0 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset FFFFF000H Undefined Bit position Bit name Function 7 to 0 Port 0 (n = 7 to 0)
  • Page 266 CHAPTER 12 PORT FUNCTION (1) Hardware configuration Figure 12-1. Block Diagram of P00 and P01 (Port 0) PMC0n PM0n TO11n PORT Address Remark n = 0, 1 Figure 12-2. Block Diagram of P02 to P07 (Port 0) PMC0n PM0n PORT Address INTP110 to INTP112, Noise elimination...
  • Page 267 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 0 is set by the port 0 mode register (PM0). The control mode is set by the port 0 mode control register (PMC0). Port 0 mode register (PM0) This register can be read/written in 8-bit or 1-bit units.
  • Page 268 CHAPTER 12 PORT FUNCTION Port 0 mode control register (PMC0) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC0 PMC07 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 FFFFF040H Bit position Bit name Function PMC07 Port mode Control Sets operation mode of P07 pin.

  • Page 269: Port 1

    CHAPTER 12 PORT FUNCTION 12.3.2 Port 1 Port 1 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset FFFFF002H Undefined Bit position Bit name Function 7 to 0 Port 1 (n = 7 to 0) I/O port In addition to the function as a general I/O port, this port can also be used to input/output signals of the real-time...
  • Page 270 CHAPTER 12 PORT FUNCTION (1) Hardware configuration Figure 12-3. Block Diagram of P10 and P11 (Port 1) PMC1n PM1n PORT TO12n Address Remark n = 0, 1 Figure 12-4. Block Diagram of P12 to P14 (Port 1) PMC1n PM1n PORT Address TCLR12, TI12 Noise elimination...
  • Page 271 CHAPTER 12 PORT FUNCTION Figure 12-5. Block Diagram of P15 (Port 1) PCM1 PMC15 PM15 PORT Address Noise elimination INTP121 PCM1 Edge detection Figure 12-6. Block Diagram of P16 (Port 1) PMC16 PM16 PORT Address Noise elimination INTP122 Edge detection PCM1 User’s Manual U10913EJ6V0UM...
  • Page 272 CHAPTER 12 PORT FUNCTION Figure 12-7. Block Diagram of P17 (Port 1) SCK2 I/O switch PCM1 PMC17 PM17 PORT SCK2 output Address Noise elimination INTP123 Edge detection SCK2 input PCM1 (2) Setting input/output mode and control mode The input/output mode of port 1 is set by the port 1 mode register (PM1). The control mode is set by the port 1 mode control register (PMC1) and port control mode register (PCM).
  • Page 273 CHAPTER 12 PORT FUNCTION Port 1 mode control register (PMC1) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC1 PMC17 PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10 FFFFF042H PCM3 PCM1 FFFFF05CH Bit position Bit name Function (PMC1) PMC17...

  • Page 274: Port 2

    CHAPTER 12 PORT FUNCTION 12.3.3 Port 2 Port 2 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset FFFFF004H Undefined Bit position Bit name Function 7 to 0 Port 2 (n = 7 to 0) I/O port In addition to the function as a port, this port can also be used to output PWM0 and PWM1 and input/output signals...
  • Page 275 CHAPTER 12 PORT FUNCTION (1) Hardware configuration Figure 12-8. Block Diagram of P20 and P21 (Port 2) PMC2n PM2n PORT PWM0, PWM1 Address Remark n = 0, 1 Figure 12-9. Block Diagram of P22 and P25 (Port 2) SO0, SO1 output enable PMC2n PM2n...
  • Page 276 CHAPTER 12 PORT FUNCTION Figure 12-10. Block Diagram of P23 and P26 (Port 2) PMC2n PM2n PORT Address RXD0/SI0 RXD1/SI1 Remark n = 3, 6 Figure 12-11. Block Diagram of P24 and P27 (Port 2) SCK0, SCK1 I/O switch PMC2n PM2n SCK0 output, PORT...
  • Page 277 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 2 is set by the port 2 mode register (PM2). The control mode is set by the port 2 mode control register (PMC2). Port 2 mode register (PM2) This register can be read/written in 8-bit or 1-bit units.
  • Page 278 CHAPTER 12 PORT FUNCTION Port 2 mode control register (PMC2) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 FFFFF044H Bit position Bit name Function PMC27 Port Mode Control Sets operation mode of P27 pin.

  • Page 279: Port 3

    CHAPTER 12 PORT FUNCTION 12.3.4 Port 3 Port 3 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset FFFFF006H Undefined Bit position Bit name Function 7 to 0 Port 3 (n = 7 to 0) I/O port In addition to the function as a port, this port can also be used to input /output signals of the real-time pulse unit...
  • Page 280 CHAPTER 12 PORT FUNCTION (1) Hardware configuration Figure 12-12. Block Diagram of P30 and P31 (Port 3) PMC3n PM3n TO13n PORT Address Remark n = 0, 1 Figure 12-13. Block Diagram of P32 to P34 (Port 3) PMC3n PM3n PORT Address TCLR13, TI13 Noise elimination...
  • Page 281 CHAPTER 12 PORT FUNCTION Figure 12-14. Block Diagram of P35 (Port 3) SO3 output enable PCM3 PUO3 PMC35 PM35 PORT Address Noise elimination INTP131 PCM3 Edge detection Figure 12-15. Block Diagram of P36 (Port 3) PUO3 PMC36 PM36 PORT Address Noise elimination INTP132 Edge detection...
  • Page 282 CHAPTER 12 PORT FUNCTION Figure 12-16. Block Diagram of P37 (Port 3) PCM3 SCK3 I/O switch PUO3 PMC37 PM37 PORT SCK3 output Address Noise elimination INTP133 Edge detection SCK3 input PCM3 (2) Setting input/output mode and control mode The input/output mode of port 3 is set by the port 3 mode register (PM3). The control mode is set by the port 3 mode control register (PMC3) and port control mode register (PCM).
  • Page 283 CHAPTER 12 PORT FUNCTION Port 3 mode control register (PMC3) This register can be read/written in 8-bit or 1-bit units. (1/2) Address After reset PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF046H PCM3 PCM1 FFFFF05CH Bit position Bit name Function (PMC1) PMC37...
  • Page 284 CHAPTER 12 PORT FUNCTION (2/2) Bit position Bit name Function (PMC1) PMC32 Port Mode Control Sets operation mode of P32 pin. 0: I/O port mode 1: TCLR13 input mode PMC31 Port Mode Control Sets operation mode of P31 pin. 0: I/O port mode 1: TO131 output mode PMC30 Port Mode Control...

  • Page 285: Port 4

    CHAPTER 12 PORT FUNCTION 12.3.5 Port 4 Port 4 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset FFFFF008H Undefined Bit position Bit name Function 7 to 0 Port 4 (n = 7 to 0) I/O port In addition to the function as a general I/O port, this port also serves as an external address/data bus for external...
  • Page 286 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 4 is set by the port 4 mode register (PM4). The control mode (external expansion mode) is set by the memory expansion mode register (MM: refer to 3.4.7). Port 4 mode register (PM4) This register can be read/written in 8-bit or 1-bit units.

  • Page 287: Port 5

    CHAPTER 12 PORT FUNCTION 12.3.6 Port 5 Port 5 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset FFFFF00AH Undefined Bit position Bit name Function 7 to 0 Port 5 (n = 7 to 0) I/O port In addition to the function as a general I/O port, this port also serves as an external address/data bus for external...
  • Page 288 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 5 is set by the port 5 mode register (PM5). The control mode (external expansion mode) is set by the memory expansion mode register (MM: refer to 3.4.7). Port 5 mode register (PM5) This register can be read/written in 8-bit or 1-bit units.

  • Page 289: Port 6

    CHAPTER 12 PORT FUNCTION 12.3.7 Port 6 Port 6 is a 4-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset — — — — FFFFF00CH Undefined Bit position Bit name Function 3 to 0 Port 6 (n = 3 to 0)
  • Page 290 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 6 is set by the port 6 mode register (PM6). To enable the external address/ data bus function, the control mode (external expansion mode) is set by the memory expansion mode register (MM: refer to 3.4.7).

  • Page 291: Port 7

    CHAPTER 12 PORT FUNCTION 12.3.8 Port 7 Port 7 is an 8-bit input-only port and all the pins of port 7 are fixed to the input mode. Address After reset FFFFF0EH Undefined Bit position Bit name Function 7 to 0 Port 7 (n = 7 to 0) Input-only port...

  • Page 292: Port 9

    CHAPTER 12 PORT FUNCTION 12.3.9 Port 9 Port 9 is a 7-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset – FFFFF012H Undefined Bit position Bit name Function 6 to 0 Port 9 (n = 6 to 0) I/O port...
  • Page 293 CHAPTER 12 PORT FUNCTION (1) Hardware configuration Figure 12-21. Block Diagram of P90 to P95 (Port 9) MM0 to MM3 I/O controller PM9n LBEN, UBEN, R/W, PORT DSTB, ASTB, HLDAK Address Remark n = 0 to 5 Figure 12-22. Block Diagram of P96 (Port 9) I/O controller PM96 PORT...
  • Page 294 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 9 is set by the port 9 mode register (PM9). The control mode (external expansion mode) is set by the memory expansion mode register (MM: refer to 3.4.7). Port 9 mode register (PM9) This register can be read/written in 8- or 1-bit units.

  • Page 295: Port 11

    CHAPTER 12 PORT FUNCTION 12.3.10 Port 11 Port 11 is an 8-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset P117 P116 P115 P114 P113 P112 P111 P110 FFFFF016H Undefined Bit position Bit name Function 7 to 0...
  • Page 296 CHAPTER 12 PORT FUNCTION (1) Hardware configuration Figure 12-23. Block Diagram of P110 and P111 (Port 11) PMC11n PM11n TO14n PORT P11n P11n Address Remark n = 0, 1 Figure 12-24. Block Diagram of P112 to P117 (Port 11) PMC11n PM11n PORT P11n...
  • Page 297 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 11 is set by the port 11 mode register (PM11). The control mode is set by the port 11 mode control register (PMC11). Port 11 mode register (PM11) This register can be read/written in 8-bit or 1-bit units.

  • Page 298: Switching Between External Maskable Interrupt Request Input/Timer External Capture Trigger Input And Csi Pins

    Trigger Input and CSI Pins The higher 3 bits of port 1 of the V853 are used by the external maskable interrupt request input/timer external capture trigger input (INTP121 to INTP123) as well as the CSI2 output (S02, SI2, SCK2) together in the control mode.
  • Page 299 CHAPTER 12 PORT FUNCTION Unselected functions operate as follows. (1) CSI operations when the INTP signal input mode is selected Even when the INTP signal is selected, the CSI2, CSI3, and BRG3 registers can be accessed. However, serial data input and serial clock input from the pins, and serial data output and serial clock output to the pins can not be performed.

  • Page 300: Specifying Pull-Up Resistors

    CHAPTER 12 PORT FUNCTION 12.5 Specifying Pull-up Resistors The V853 has on-chip pull-up resistors, which can be specified for use at the higher three bits (P35 to P37) of port 3 by means of software. Whether to use an internal pull-up resistor can be specified for each pin using the pull-up resistor option register (PUO) and port mode register (PM).

  • Page 301: Chapter 13 Reset Function

    CHAPTER 13 RESET FUNCTION When a low level is input to the RESET pin, the system is reset and each on-chip hardware is initialized to its initial state. When the RESET pin changes from low level to high level, the reset state is released and the CPU starts executing the program.

  • Page 302: Initialize

    CHAPTER 13 RESET FUNCTION (1) Acknowledging reset signal RESET pin Analog Analog Analog delay delay delay Eliminated as noise Internal system Note reset signal Reset Reset acknowledged released Note The internal system reset signal remains active for the duration of at least 4 system clocks after the reset condition is removed from the RESET pin.
  • Page 303 CHAPTER 13 RESET FUNCTION Table 13-2. Initial Values of Each Register After Reset (1/2) Register Initial Value After Reset 00000000H r1 to r31 Undefined 00000000H 00000020H EIPC Undefined EIPSW Undefined FEPC Undefined FEPSW Undefined 00000000H Internal RAM Undefined Port I/O latch (P0 to P6, P9, P11) Undefined Input latch (P7) Undefined...
  • Page 304 CHAPTER 13 RESET FUNCTION Table 13-2. Initial Values of Each Register After Reset (2/2) Register Initial Value After Reset Serial interface Asynchronous serial interface mode register (ASIM00, ASIM10) Asynchronous serial interface mode register (ASIM01, ASIM11) Asynchronous serial interface status register (ASIS0, ASIS1) Receive buffer (RXB0, RXB0L, RXB1, RXB1L) Undefined...

  • Page 305: Chapter 14 Flash Memory ( Μ Μ Μ Μ Μ Pd70F3003A And 70F3025A)

    Writing can be performed either on-board or off-board using the dedicated flash programmer. (1) On-board programming The contents of the flash memory is rewritten after the V853 is mounted on the target system. Mount connectors, etc., on the target system to connect the dedicated flash programmer.
  • Page 306 CHAPTER 14 FLASH MEMORY ( µ µ µ µ µ PD70F3003A AND 70F3025A) Figure 14-1. V853 Flash Writing Adapter (FA100GC-8EU) Wiring Example µ PD70F3003A, µ PD70F3025A, µ PD70F3003A(A) Connected to GND Connected to VDD /RESET RESERVE/HS Remarks 1. Pins not described above should be handled according to the recommended connection of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of Unused...
  • Page 307 CHAPTER 14 FLASH MEMORY ( µ µ µ µ µ PD70F3003A AND 70F3025A) Table 14-1. Wiring Table of V853 Flash Writing Adapter Flash Programmer (PG-FP3) When Using CSI + HS When Using CSI0 When Using UART0 Connection Pins Signal Pin Function Pin Name Pin No.

  • Page 308: Programming Environment

    A host machine is required for controlling the dedicated flash programmer. UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V853 to perform writing, erasing, etc. A dedicated program adapter (FA series) is required for off-board writing.

  • Page 309: Communication Mode

    RESET Dedicated flash V853 programmer SCK0 HS (V When PG-FP3 is used as the dedicated flash programmer, it generates the following signals to the V853. For the details, refer to PG-FP3 Flash Memory Programmer User’s Manual (U13502E). User’s Manual U10913EJ6V0UM...
  • Page 310 Pin Function Pin Name Note 1 CSI0 UART0 Output Writing voltage voltage generation/ voltage monitoring – Ground Note 2 Output Clock output to V853 RESET Output Reset signal RESET SI/RxD Input Receive signal SO0/TXD0 SO/TxD Output Transmit signal SI0/RXD0 ×...

  • Page 311: Pin Handling

    In the flash memory programming mode, a 10.3 V writing voltage is supplied to the V pin. The following shows an example of the connection of the V pin. V853 Dedicated flash programmer connection pin Pull-down resistor (R User’s Manual U10913EJ6V0UM...

  • Page 312: Serial Interface Pin

    When connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the high-impedance status. V853 Conflict of signals Dedicated flash programmer connection pin...
  • Page 313 Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V853 outputs affects the other device, isolate the signal on the other device side. V853 Dedicated flash programmer connection pin Other device...

  • Page 314: Reset Pin

    When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. V853 Conflict of signals Dedicated flash programmer connection pin...

  • Page 315: Programming Method

    CHAPTER 14 FLASH MEMORY ( µ µ µ µ µ PD70F3003A AND 70F3025A) 14.6 Programming Method 14.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Start Switch to flash memory programming mode Supply RESET pulse Select communication mode Manipulate flash memory End ?

  • Page 316: Flash Memory Programming Mode

    CHAPTER 14 FLASH MEMORY ( µ µ µ µ µ PD70F3003A AND 70F3025A) 14.6.2 Flash memory programming mode When rewriting the contents of a flash memory using the dedicated flash programmer, set the V853 in the flash memory programming mode. When switching modes, set the MODE, V , and WAIT pins as follows before releasing reset.

  • Page 317: Communication Commands

    The V853 communicates with the dedicated flash programmer by means of commands. The command sent from the dedicated flash programmer to the V853 is called a “command”. The response signal sent from the V853 to the dedicated flash programmer is called a “response command”.

  • Page 318: Resources Used

    CHAPTER 14 FLASH MEMORY ( µ µ µ µ µ PD70F3003A AND 70F3025A) The V853 sends back response commands to the commands issued from the dedicated flash programmer. The following shows the response commands the V853 sends out. Response Command Name...
  • Page 319 APPENDIX A REGISTER INDEX (1/5) Symbol Name Unit Page ADCR0 A/D conversion result register 0 ADCR0H A/D conversion result register 0H ADCR1 A/D conversion result register 1 ADCR1H A/D conversion result register 1H ADCR2 A/D conversion result register 2 ADCR2H A/D conversion result register 2H ADCR3 A/D conversion result register 3...
  • Page 320 APPENDIX A REGISTER INDEX (2/5) Symbol Name Unit Page CC122 Capture/compare register 122 CC123 Capture/compare register 123 CC130 Capture/compare register 130 CC131 Capture/compare register 131 CC132 Capture/compare register 132 CC133 Capture/compare register 133 CC140 Capture/compare register 140 CC141 Capture/compare register 141 CC142 Capture/compare register 142 CC143...
  • Page 321 APPENDIX A REGISTER INDEX (3/5) Symbol Name Unit Page OVIC14 Interrupt control register INTC Port 0 Port Port 1 Port Port 2 Port Port 3 Port Port 4 Port Port 5 Port Port 6 Port Port 7 Port Port 9 Port Port 11 Port...
  • Page 322 APPENDIX A REGISTER INDEX (4/5) Symbol Name Unit Page PMC3 Port 3 mode control register Port PMC11 Port 11 mode control register Port PRCMD Command register Power save control register Program status word Pull-up resistor option register Port PWM0 PWM buffer register 0 (12 bits) PWM0L PWM buffer register 0L (lower 8 bits) PWM1...
  • Page 323 APPENDIX A REGISTER INDEX (5/5) Symbol Name Unit Page TOC14 Timer output control register 14 TOVS Timer overflow status register TUM11 Timer unit mode register 11 TUM12 Timer unit mode register 12 TUM13 Timer unit mode register 13 TUM14 Timer unit mode register 14 TXS0 Transmit shift register 0 UART...
  • Page 324 APPENDIX B INSTRUCTION SET LIST Conventions (1) Symbols used for operand description Symbol Description reg1 General-purpose register (r0 to r31): Used as source register reg2 General-purpose register (r0 to r31): Mainly used as destination register immx x-bit immediate dispx x-bit displacement reglD System register number bit#3...
  • Page 325 APPENDIX B INSTRUCTION SET LIST (3) Symbols used for operation description (2/2) Symbol Description Halfword Halfword (16 bits) Word Word (32 bits) – Subtract Bit concatenation Multiply ÷ Divide Logical product Logical sum Exclusive logical sum Logical negate logically shift left by Logical left shift logically shift right by Logical right shift...
  • Page 326 APPENDIX B INSTRUCTION SET LIST Condition Code Condition Condition Name Conditional Expression Description Code (cccc) (cond) 0 0 0 0 OV = 1 Overflow 1 0 0 0 OV = 0 No overflow 0 0 0 1 CY = 1 Carry Lower (Less than) NC/NL...
  • Page 327 APPENDIX B INSTRUCTION SET LIST Instruction Set (Alphabetical Order) (1/4) Operand Op Code Operation Execution Mnemonic Flag Clock l CY OV S Z SAT r r r r r 0 0 1 1 1 0RRRRR reg1, reg2 GR[reg2]←GR[reg2]+GR[reg1] r r r r r 0 1 0 0 1 0 i i i i i imm5, reg2 GR[reg2]←GR[reg2]+sign-extend(imm5) r r r r r 1 1 0 0 0 0RRRRR...
  • Page 328 APPENDIX B INSTRUCTION SET LIST Instruction Set (Alphabetical Order) (2/4) Operand Op Code Operation Execution Mnemonic Flag Clock l CY OV S Z SAT r r r r r 1 1 1 1 1 1RRRRR LDSR reg2, regID SR[regID]←GR[reg2] regID = EIPC, FEPC 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 regID = EIPSW, FEPSW Note 1...
  • Page 329 APPENDIX B INSTRUCTION SET LIST Instruction Set (Alphabetical Order) (3/4) Operand Op Code Operation Flag Mnemonic Execution Clock l CY OV S Z SAT SATADD reg1, reg2 r r r r r 0 0 0 1 1 0RRRRR GR[reg2]←saturated(GR[reg2]+GR[reg1]) r r r r r 0 1 0 0 0 1 i i i i i imm5, reg2 GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)) SATSUB...
  • Page 330 APPENDIX B INSTRUCTION SET LIST Instruction Set (Alphabetical Order) (4/4) Mnemonic Operand Op Code Operation Execution Flag Clock l CY OV S Z SAT r r r r r 1 1 1 0 1 1RRRRR ST.H reg2, disp16[reg1] adr←GR[reg1]+sign-extend(disp16) d d d d d d d d d d d d d d d 0 Store-memory(adr, GR[reg2], Halfword) Note ST.W...
  • Page 331 APPENDIX C INDEX compare registers 0 to 2 ......213 1-buffer mode ............225 prescaler mode registers 0 to 2 ....214 4-buffer mode ............226 setting value ..........211 100-pin plastic LQFP ..........22 BCC ................. 84 BCn1 (n = 0 to 7) ............ 84 BCU .................
  • Page 332 APPENDIX C INDEX CLKOUT ..............41 DAM ..............250 Clock DAn0 to DAn7 (n = 0, 1) ........250 control register ..........129 Data space ..........53, 65, 93 generator ............26 Data wait control register ........82 generator function ........127 DCLK0, DCLK1 .............
  • Page 333 APPENDIX C INDEX INTP1mn/INTCC1mn General-purpose registers ........47 (m = 1 to 4, n = 0 to 3) .......... 96 Global pointer ............47 INTSER0, INTSER1 ........96, 193 INTSR0, INTSR1 ........... 96, 193 INTST0, INTST1 ..........96, 193 Halfword access ............. 79 ISPR ..............
  • Page 334 APPENDIX C INDEX OVE0, OVE1 ............190 PCM ..............296 Overall error ............246 PCM1, PCM3 ............296 Overflow (timer 1) ..........162 PE0, PE1 .............. 190 Overflow (timer 4) ..........169 Periods where interrupt is not acknowledged ..125 OVFn (n = 4, 11 to 14) .........
  • Page 335 APPENDIX C INDEX port 9 ............290 PWM0, PWM0L, PWM1, PWM1L ....255 port 11 ............293 PWM0, PWM1 ..........36 Port control mode register ........296 PWMC ............253 Port function ............258 PWME0, PWME1 ........253 Port mode control register PWPn0 to PWPn2 (n = 0, 1) ........
  • Page 336 APPENDIX C INDEX SEPRmn (m = 0, 1, n = 0 to 2) ....112, 113 TI13 ................. 37 Serial I/O shift register 0 to 3 ....... 201 TI14 ................. 40 Serial interface ............26 Time base counter ..........143 Serial interface function ........
  • Page 337 APPENDIX C INDEX WAIT ............... 41 Wait function ............82 Word access ............80 Wrap-around ............ 53, 65 X1, X2 ..............41 Z ................49 Zero register ............47 Zero scale error ............ 247 User’s Manual U10913EJ6V0UM...
  • Page 338 [MEMO] User’s Manual U10913EJ6V0UM...
  • Page 339 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we’ve taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

Mpd703003aMpd703004aMpd703025aMpd70f3003aMpd70f3025aMpd703003aa ... Show all

Table of Contents