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Renesas V850ES/F 3-L Series User Manual

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Hardware

V850ES/Fx3-L

32

32-bit Single-Chip Microcontroller

V850ES/FE3-L: V850ES/FF3-L: V850ES/FG3-L:

µPD70F3610

µPD70F3611

µPD70F3612

µPD70F3613

µPD70F3614

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

µPD70F3615

µPD70F3616

µPD70F3617

µPD70F3618

µPD70F3619

µPD70F3620

µPD70F3621

µPD70F3622

R01UH0469ED0201, Rev. 2.01

January 14, 2014

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Summary of Contents for Renesas V850ES/F 3-L Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 R01UH0469ED0201 Rev. 2.01 User Manual...
Page 3 You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
Page 4 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.
Page 5 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on theproducts covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 6 Block diagrams do not necessarily show the exact wiring in hardware but the functional structure. Timing diagrams are for functional explanation purposes only, without any relevance to the real hardware implementation. Further Information For further information see http://www.renesas.eu/. R01UH0469ED0201 Rev. 2.01 User Manual...
Page 7: Table Of Contents
Table of Contents Chapter 1 Introduction ..........17 General .
Page 8 2.4.24 Port type F100x-U ..........67 2.4.25 Port type F1010-U.
Page 9 Chapter 3 CPU System Functions ....... 125 Overview............125 3.1.1 Description .
Page 10 Non-Maskable Interrupts ..........213 5.2.1 Operation .
Page 11 Device Information ..........279 7.6.1 PRDSELH register - Product selection code register .
Page 12 13.3 Control Registers ..........369 13.4 Operation .
Page 13 Chapter 17 I C Bus (IIC) ..........448 17.1 Features .
Page 14 18.3.5 CAN sleep mode/CAN stop mode function ......529 18.3.6 Error control function......... . 529 18.3.7 Baud rate control function .
Page 15 19.3 ADC Registers ........... . . 657 19.4 Operation .
Page 16 Appendix B Registers Access Times ......734 Timer AA............735 Timer M.
Page 17: Chapter 1 Introduction
Chapter 1 Introduction Chapter 1 Introduction The V850ES/Fx3-L is a product line in NEC Electronics’ V850 family of single- chip microcontrollers designed for automotive applications. 1.1 General The V850ES/Fx3-L single-chip microcontroller devices make the performance gains attainable with 32-bit RISC-based controllers available for embedded control applications.
Page 18: Features Summary
Chapter 1 Introduction A full range of software development tools A development system is available that includes an optimized C compiler, debugger, in-circuit emulator, simulator, system performance analyzer, and other elements. 1.2 Features Summary The V850ES/Fx3-L series includes the following microcontrollers: •...
Page 19 Chapter 1 Introduction R01UH0469ED0201 Rev. 2.01 User Manual...
Page 20 Chapter 1 Introduction R01UH0469ED0201 Rev. 2.01 User Manual...
Page 21: Description
Chapter 1 Introduction 1.3 Description The following figure provides a functional block diagram of the V850ES/FE3-L, V850ES/FF3-L, and V850ES/FG3-L microcontrollers. Power and Reset Interrupt INTP0 to INTP7 Controller INTP8 to INTP11 Note 1 Reset Low Voltage Detector Power supply KR0 to KR7 Key Interrupt Memory Access Note 4...
Page 22 Chapter 1 Introduction Table 1-2 V850ES/FE3-L, V850ES/FF3-L, V850ES/FG3-L feature set differences Note Feature V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L √ INTP8,INTP9, – – INTP10, UARTD2 √ √ ANI10 to – ANI11 √ ANI12 to – – ANI15 Code flash refer to “Memory” on page 141 refer to “Memory”...
Page 23: Internal Units
Chapter 1 Introduction 1.3.1 Internal units The CPU can execute almost all instruction processing, such as address calculation, arithmetic and logic operations, and data transfer, in one clock under control of a five-stage pipeline. Dedicated hardware units such as a multiplier and a 32-bit barrel shifter are provided to speed up complicated instruction processing.
Page 24: Structure Of The Manual
Chapter 1 Introduction 1.3.2 Structure of the manual This manual explains how to use the V850ES/Fx3-L microcontroller devices. It provides comprehensive information about the building blocks, their features, and how to set registers in order to enable or disable specific functions. The manual provides individual chapters for the building blocks.
Page 25: Ordering Information
Chapter 1 Introduction 1.4 Ordering Information 1.4.1 V850ES/FE3-L ordering information On-chip Quality Part number Package flash Remark grade memory UPD70F3610M1GBA-GAH-AX 64-pin plastic LQFP 64 KB without Power-On- (0.5 mm, 10 x 10 mm Clear circuit UPD70F3610M1GBA1-GAH-AX UPD70F3610M1GBA2-GAH-AX UPD70F3610M2GBA-GAH-AX with Power-On- Clear circuit UPD70F3610AM2GBA1-GAH-AX UPD70F3610AM2GBA2-GAH-AX...
Page 26 Chapter 1 Introduction On-chip Quality Part number Package flash Remark grade memory UPD70F3613M1GBA-GAH-AX 64-pin plastic LQFP 192 KB without Power-On- (0.5 mm, 10 x 10 mm Clear circuit UPD70F3613M1GBA1-GAH-AX UPD70F3613M1GBA2-GAH-AX UPD70F3613M2GBA-GAH-AX with Power-On- Clear circuit UPD70F3613AM2GBA1-GAH-AX UPD70F3613AM2GBA2-GAH-AX UPD70F3614M1GBA-GAH-AX 256 KB without Power-On- Clear circuit UPD70F3614M1GBA1-GAH-AX...
Page 27: V850Es/Ff3-L Ordering Information
Chapter 1 Introduction 1.4.2 V850ES/FF3-L ordering information On-chip Quality Part number Package flash Remark grade memory UPD70F3615M1GKA-GAK-AX 80-pin plastic LQFP 64 KB without Power-On- (0.5 mm, 12 x 12 mm Clear circuit UPD70F3615M1GKA1-GAK-AX UPD70F3615M1GKA2-GAK-AX UPD70F3615M2GKA-GAK-AX with Power-On- Clear circuit UPD70F3615M2GKA1-GAK-AX UPD70F3615M2GKA2-GAK-AX UPD70F3616M1GKA-GAK-AX 96 KB...
Page 28: V850Es/Fg3-L Ordering Information
Chapter 1 Introduction 1.4.3 V850ES/FG3-L ordering information On-chip Quality Part number Package flash Remark grade memory UPD70F3620M1GCA-UEU-AX 100-pin plastic LQFP 128 KB without Power-On- (0.5 mm, 14 x 14 mm Clear circuit UPD70F3620M1GCA1-UEU-AX UPD70F3620M1GCA2-UEU-AX UPD70F3620M2GCA-UEU-AX with Power-On- Clear circuit UPD70F3620M2GCA1-UEU-AX UPD70F3620M2GCA2-UEU-AX UPD70F3621M1GCA-UEU-AX 192 KB...
Page 29: Chapter 2 Pin Functions
Chapter 2 Pin Functions This chapter lists the ports of the microcontroller. It presents the configuration of the ports for alternative functions. Noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter.
Page 30: Description
Chapter 2 Pin Functions 2.1.1 Description The V850ES/FE3-L, V850ES/FF3-L, and V850ES/FG3-L microcontrollers have the port groups shown below. Port group 0 P913 Port group 9 FG3-L Port group 1 P915 only FG3-L only P910 P912 FG3-L Port group 3 only PCM0 FF3-L/ PCM1...
Page 31 Chapter 2 Pin Functions Port group overview Table 2-1 gives an overview of the port groups. For each port group it shows the supported functions in port mode and in alternative mode. Any port group can operate in 8-bit or 1-bit units. Port groups 3, 6, 9, and DL can additionally operate in 16-bit units.
Page 32: Terms
Chapter 2 Pin Functions Pin configuration To define the function and the electrical characteristics of a pin, several control registers are provided. • For a general description of the registers, see “Port Group Configuration Registers” on page 33. • For every port, detailed information on the configuration registers is given in “Port Type Diagrams”...
Page 33: Port Group Configuration Registers
Chapter 2 Pin Functions 2.2 Port Group Configuration Registers This section starts with an overview of all configuration registers and then presents all registers in detail. The configuration registers are classified in the following groups: • “Pin function configuration” on page 34 •...
Page 34: Pin Function Configuration
Chapter 2 Pin Functions 2.2.2 Pin function configuration The registers for pin function configuration define the general function of a pin: • port mode or alternative mode • in port mode: input mode or output mode • in alternative mode: selection of one of the alternative functions in alternative mode •...
Page 35 Chapter 2 Pin Functions PMCn - Port mode control register The PMCn register specifies whether the individual pins of port group n are in port mode or in alternative mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 36 Chapter 2 Pin Functions PMn - Port mode register The PMn register specifies whether the individual pins of the port group n are in input mode or in output mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 37 Chapter 2 Pin Functions PFCn - Port function control register If a pin is in alternative mode (PMCn.PMCnm = 1) some pins offer up to four alternative functions. The PFCn register together with the PFCEn register specifie which function of a pin is to be used.
Page 38 Chapter 2 Pin Functions PFCEn - Port function control expansion register If a pin is in alternative mode (PMCn.PMCnm = 1) some pins offer up to four alternative functions. The PFCEn together with the PFCn register specifies which function of a pin is to be used.
Page 39 Chapter 2 Pin Functions OCDM - On-chip debug mode register The 8-bit OCDM register specifies whether dedicated pins of the microcontroller operate in normal operation mode or can be used for on-chip debugging (N-Wire interface). The setting of this register concerns only those pins that can be used for the N-Wire interface: P05/DRST, P52/DDI, P53/DDO, P54/DCK, and P55/DMS.
Page 40: Pin Data Input/Output
Chapter 2 Pin Functions 2.2.3 Pin data input/output If a pin is in port mode, the registers for pin data input/output specify the input and output data. Pn - Port register If a pin is in port mode (PMCn.PMCnm = 0), data is input from or output to an external device by writing or reading the Pn register.
Page 41 Chapter 2 Pin Functions Alternative mode In alternative mode (PMCn.PMCnm = 1), the corresponding port type defines whether a pin is in input or output mode. However, register PMn influences the writing/reading of register Pn. In alternative mode, data is written to or read from the Pn register as follows: Table 2-11 Writing/reading register Pn in alternative mode (PMCn.PMCnm = 1) Function...
Page 42: Configuration Of Pull-Up Resistors
Chapter 2 Pin Functions 2.2.4 Configuration of pull-up resistors PUn - Port pull-up resistor option register The PUn register specifies whether a pull-up resistor is connected to the pin. Access This register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units.
Page 43: Open Drain Configuration
Chapter 2 Pin Functions 2.2.5 Open drain configuration PFn - Port function register If a pin is in alternative mode (PMCn.PMCnm = 1), the PFn register specifies normal output or open-drain output. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 44: Port Buffers Diagrams
Chapter 2 Pin Functions 2.3 Port Buffers Diagrams This chapter presents the block diagrams of all buffer types. The tables in “Port group configuration lists” on page 93 informs also about the buffer type, used for each port. Buffer type 2 Figure 2-2 Block diagram: buffer type 2 Buffer type 5...
Page 45 Chapter 2 Pin Functions Buffer type 5-K Figure 2-5 Block diagram: buffer type 5-K Buffer type 5-W Figure 2-6 Block diagram: buffer type 5-W R01UH0469ED0201 Rev. 2.01 User Manual...
Page 46 Chapter 2 Pin Functions Buffer type 11-G Figure 2-7 Block diagram: buffer type 11-G Buffer type 16 Figure 2-8 Block diagram: buffer type 16 R01UH0469ED0201 Rev. 2.01 User Manual...
Page 47: Port Type Diagrams
Chapter 2 Pin Functions 2.4 Port Type Diagrams This chapter presents the block diagrams of all port types. The tables in the detailed descriptions of each port group from “Port group 0” on page 100 onwards informs also about the port type, used for each port. 2.4.1 Port type C PMmn (a) Output buffer control...
Page 48: Port Type D0
Chapter 2 Pin Functions 2.4.3 Port type D0 PMCmn (a) Output buffer control PMmn 1st alternate function PORT (d) Output data Selection Address (b) Input buffer control Figure 2-11 Port type D0 block diagram 2.4.4 Port type D0-U EVDD PUmn (c) Pull-up control PMCmn (a) Output buffer control...
Page 49: Port Type D1
Chapter 2 Pin Functions 2.4.5 Port type D1 PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input control 1st alternate f unction Figure 2-13 Port type D1 block diagram 2.4.6 Port type D1-U EVDD PUmn (c) Pull-up control...
Page 50: Port Type D1-Ui
Chapter 2 Pin Functions 2.4.7 Port type D1-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 1st alternate f unction detector remov al Figure 2-15...
Page 51: Port Type D3-Ui
Chapter 2 Pin Functions 2.4.8 Port type D3-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 1st alternate f unction detector remov al (INTPx)
Page 52: Port Type D1A
Chapter 2 Pin Functions 2.4.9 Port type D1A PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control 1st alternate function Figure 2-17 Port type D1A block diagram R01UH0469ED0201 Rev. 2.01 User Manual...
Page 53: Port Type D1O1-Ui
Chapter 2 Pin Functions 2.4.10 Port type D1O1-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn OCDM OCDM0 PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 1st alternate f unction detector remov al (f) On-chip debug...
Page 54: Port Type D2
Chapter 2 Pin Functions 2.4.11 Port type D2 Output enable signal 1 in alternative mode PM C PMCmn (a) Output buffer control PMmn 1st alternate f unction PORT (d) Output data Selection Address (b) Input buffer control Input enable signal 1 (e) A lternate function input in alternative mode control...
Page 55: Port Type E01-U
Chapter 2 Pin Functions 2.4.12 Port type E01-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn 1st alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 2nd alternate f unction Figure 2-20 Port type E01-U block diagram R01UH0469ED0201 Rev.
Page 56: Port Type E10-U
Chapter 2 Pin Functions 2.4.13 Port type E10-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 1st alternate f unction Figure 2-21 Port type E10-U block diagram R01UH0469ED0201 Rev.
Page 57: Port Type E10-Ui
Chapter 2 Pin Functions 2.4.14 Port type E10-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input Edge Noise control...
Page 58: Port Type E11-U
Chapter 2 Pin Functions 2.4.15 Port type E11-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control 2nd alternate function Figure 2-23 Port type E11-U block diagram R01UH0469ED0201 Rev.
Page 59: Port Type E11-Ui
Chapter 2 Pin Functions 2.4.16 Port type E11-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control Edge Noise (e) Alternate function input 1st alternate function detector removal control 2nd alternate function...
Page 60: Port Type E21-U
Chapter 2 Pin Functions 2.4.17 Port type E21-U EVDD PUmn (c) Pull - up control P ch Output enable signal 1 in alternative mode P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 1st alternate function PORT (d) Output data Selection Address (b) Input buffer control (e) A lternate function input...
Page 61: Port Type Ex0-U
Chapter 2 Pin Functions 2.4.18 Port type Ex0-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate function PORT (d) Output data Selection Address (b) Input buffer control Figure 2-26 Port type Ex0-U block diagram R01UH0469ED0201 Rev.
Page 62: Port Type Ex1-U
Chapter 2 Pin Functions 2.4.19 Port type Ex1-U EVDD PUmn (c) Pull-up control PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input control 2nd alternate f unction Figure 2-27 Port type Ex1-U block diagram R01UH0469ED0201 Rev.
Page 63: Port Type Ex1-Ui
Chapter 2 Pin Functions 2.4.20 Port type Ex1-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Edge Noise control 2nd alternate f unction detector remov al Figure 2-28...
Page 64: Port Type Ex2-U
Chapter 2 Pin Functions 2.4.21 Port type Ex2-U EVDD PUmn (c) Pull - up control P ch Output enable signal 2 in alternative mode P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control...
Page 65: Port Type F010X-U
Chapter 2 Pin Functions 2.4.22 Port type F010x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 1st alternate f unction 3rd alternate f unction (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input control 2nd alternate f unction...
Page 66: Port Type F010X-Ui
Chapter 2 Pin Functions 2.4.23 Port type F010x-UI EVDD PUmn (c) Pull-up control PFCE INTRmn INTFmn PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 1st alternate f unction 3rd alternate f unction (d) Output data Selection PORT Address (b) Input buffer control...
Page 67: Port Type F100X-U
Chapter 2 Pin Functions 2.4.24 Port type F100x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction 3rd alternate f unction (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input control 1st alternate f unction...
Page 68: Port Type F1010-U
Chapter 2 Pin Functions 2.4.25 Port type F1010-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate function 4th alternate function (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control 3rd alternate function...
Page 69: Port Type F101X-U
Chapter 2 Pin Functions 2.4.26 Port type F101x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input 1st alternate f unction control 3rd alternate f unction...
Page 70: Port Type F1100O0-U
Chapter 2 Pin Functions 2.4.27 Port type F1100O0-U EVDD PUmn (c) Pull-up control OCDM signal PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function 4th alternate function On-chip debug function (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control...
Page 71: Port Type F1100O1-U
Chapter 2 Pin Functions 2.4.28 Port type F1100O1-U EVDD PUmn (c) Pull-up control OCDM signal PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function 4th alternate function (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input 1st alternate function control...
Page 72: Port Type F1100-U
Chapter 2 Pin Functions 2.4.29 Port type F1100-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate function 4th alternate function (d) Output data Selection PORT Address (b) Input buffer control (e) 1st alternate function input 1st alternate function control 2nd alternate function...
Page 73: Port Type F1110-Ui
Chapter 2 Pin Functions 2.4.30 Port type F1110-UI EVDD PUmn (c) Pull - up control P ch INTR INTRmn INTF INTFmn P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 4th alternate function PORT (d) Output data Selection Address (b) In put buffer control Edge...
Page 74: Port Type F113X-Ui
Chapter 2 Pin Functions 2.4.31 Port type F113x-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control 1st alternate function (e) Alternate function input 2nd alternate function control Edge Noise...
Page 75: Port Type F1X10-Ui
Chapter 2 Pin Functions 2.4.32 Port type F1x10-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate f unction PORT (d) Output data Selection Address (b) Input buffer control Edge Noise (e) Alternate function input...
Page 76: Port Type F3X1X-Ui
Chapter 2 Pin Functions 2.4.33 Port type F3x1x-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control Edge Noise 1st alternate f unction detector remov al (INTPx) (e) Alternate function input control...
Page 77: Port Type F1Xx0O1-U
Chapter 2 Pin Functions 2.4.34 Port type F1xx0O1-U EVDD PUmn (c) Pull-up control OCDM signal PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate function PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 1st alternate function On-chip debug function...
Page 78: Port Type Fx010-U
Chapter 2 Pin Functions 2.4.35 Port type Fx010-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 2nd alternate f unction 4th alternate f unction (d) Output data Selection PORT Address (b) Input buffer control (e) Alternate function input control 3rd alternate f unction...
Page 79: Port Type Fx01X-U
Chapter 2 Pin Functions 2.4.36 Port type Fx01x-U EVDD PUmn (c) Pull - up control P ch P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) A lternate function input...
Page 80: Port Type Fx103-Ui
Chapter 2 Pin Functions 2.4.37 Port type Fx103-UI EVDD PUmn (c) Pull - up control P ch INTR INTRmn INTF INTFmn P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 3rd alternate function PORT (d) Output data Selection Address (b) Input buffer control (e) A lternate function input...
Page 81: Port Type Fx10X-U
Chapter 2 Pin Functions 2.4.38 Port type Fx10x-U EVDD PUmn (c) Pull - up control P ch P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) A lternate function input...
Page 82: Port Type Fx10X-Ui
Chapter 2 Pin Functions 2.4.39 Port type Fx10x-UI EVDD PUmn (c) Pull-up control INTR INTRmn INTF INTFmn PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 3rd alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input Edge Noise...
Page 83: Port Type Fx110-U
Chapter 2 Pin Functions 2.4.40 Port type Fx110-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input 2nd alternate f unction control 3rd alternate f unction...
Page 84: Port Type Fx120-Ufi
Chapter 2 Pin Functions 2.4.41 Port type Fx120-UFI EVDD PUmn (c) Pull - up control P ch INTR INTRmn INTF INTFmn PFmn P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 3rd alternate f unction 4th alternate f unction (d) Output data Select ion PORT...
Page 85: Port Type Fx123-Ufi
Chapter 2 Pin Functions 2.4.42 Port type Fx123-UFI EVDD PUmn (c) Pull - up control P ch INTR INTRmn INTF INTFmn PFmn P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 3rd alternate function PORT (d) Output data Selection Address (b) Input buffer control...
Page 86: Port Type Fx12X-Ufi
Chapter 2 Pin Functions 2.4.43 Port type Fx12x-UFI EVDD PUmn (c) Pull - up control P ch INTR INTRmn INTF INTFmn PFmn P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 3rd alternate function PORT (d) Output data Selection Address (b) Input buffer control...
Page 87: Port Type Fx13X-U
Chapter 2 Pin Functions 2.4.44 Port type Fx13x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input Share 2nd & 3rd alternate function control control (KRx) 3rd alternate function (RXDDy)
Page 88: Port Type Fx210-U
Chapter 2 Pin Functions 2.4.45 Port type Fx210-U EVDD PUmn (c) Pull - up control P ch Output enable signale 2 in alternative mode P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate function 4th alternate function (d) Output data Selection PORT...
Page 89: Port Type Fx2X0-U
Chapter 2 Pin Functions 2.4.46 Port type Fx2x0-U EVDD PUmn (c) Pull - up control P ch Output enable signale 2 in alternative mode P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 2nd alternate f unction 4th alternate f unction (d) Output data Selection PORT...
Page 90: Port Type Fxx10-U
Chapter 2 Pin Functions 2.4.47 Port type Fxx10-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn 4th alternate f unction PORT (d) Output data Selection Address (b) Input buffer control (e) Alternate function input control 3rd alternate f unction Figure 2-55...
Page 91: Port Type Fxx1X-U
Chapter 2 Pin Functions 2.4.48 Port type Fxx1x-U EVDD PUmn (c) Pull-up control PFCE PFCEmn PFCmn PMCmn (a) Output buffer control PMmn PORT Address (b) Input buffer control (e) Alternate function input control 3rd alternate f unction Figure 2-56 Port type Fxx1x-U block diagram R01UH0469ED0201 Rev.
Page 92: Port Type Fxx2X-U
Chapter 2 Pin Functions 2.4.49 Port type Fxx2x-U EVDD PU mn (c) Pull - up control P ch Output enable signale 3 in alternative mode P FCE PFCEmn P FC PFCmn PM C PMCmn (a) Output buffer control PMmn 3rd alternate f unction PORT (d) Output data Selection Address...
Page 93: Port Group Configuration
Chapter 2 Pin Functions 2.5 Port Group Configuration This section provides an overview of the port groups (Table 2-14) and of the pin functions (Table 2-14 on page 93). In Table 2-40 on page 120 it is listed how the pin functions change if the microcontroller is reset. In the subsections, for every port group the settings of the configuration registers is listed.
Page 94 Chapter 2 Pin Functions Table 2-14 V850ES/FE3, V850ES/FF3, V850ES/FG3 port group list (2/3) Port group Port Buffer Alternative outputs Alternative inputs name name type – ANI0 11-G – ANI1 11-G – ANI2 11-G – ANI3 11-G – ANI4 11-G – ANI5 11-G –...
Page 95 Chapter 2 Pin Functions Table 2-14 V850ES/FE3, V850ES/FF3, V850ES/FG3 port group list (3/3) Port group Port Buffer Alternative outputs Alternative inputs name name type PCT0 – – PCT1 – – PCT4 – – PCT6 – – PDL0 – – PDL1 –...
Page 96: Alphabetic Pin Function List
Chapter 2 Pin Functions 2.5.2 Alphabetic pin function list Table 2-15 provides a list of all pin function names in alphabetic order. The table does not list differences between the various devices of the V850ES/ Fx3-L. These are listed in Table 2-14 on page 93 . Table 2-15 Alphabetic pin functions list (1/3) Pin number...
Page 97 Chapter 2 Pin Functions Table 2-15 Alphabetic pin functions list (2/3) Pin number Pin name Pin function Port V850ES/ V850ES/ V850ES/ FE3-L FF3-L FG3-L FLMD0 – Flash programming mode setting pin – FLMD1 Flash programming mode setting pin PDL5 INTP0 External interrupts INTP0 - INTP10 INTP1 INTP2...
Page 98 Chapter 2 Pin Functions Table 2-15 Alphabetic pin functions list (3/3) Pin number Pin name Pin function Port V850ES/ V850ES/ V850ES/ FE3-L FF3-L FG3-L TIAA00 Timer TAA channel 0 capture trigger input TIAA10 TIAA20 TIAA30 TIAA40 TIAA01 Timer TAA channel 1 capture trigger input TIAA11 TIAA21 TIAA31...
Page 99 Chapter 2 Pin Functions Note The following alternative functions are provided on two pins each: Unit Alternative function Port 1 Port 2 Timer TOAA01 CTXD0 CRXD0 Key interrupt Thus you can select on which pin the alternative function should appear. Refer to “Pin function configuration”...
Page 100: Port Group 0
Chapter 2 Pin Functions 2.5.3 Port group 0 Port group 0 is a 7-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP0 to INTP3) • Non-maskable interrupt (NMI) • N-Wire debug interface reset (DRST) •...
Page 101 Chapter 2 Pin Functions Table 2-17 Port group 0: configuration registers Initial Register Address Used bits value PMC0 FFFF F440 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 FFFF F420 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PFC0 FFFF F460 PFC06 PFC04 PFC03 PFC02...
Page 102: Port Group 1 (V850Es/Fg3, V850Es/Fj3, V850Es/Fk3)
Chapter 2 Pin Functions 2.5.4 Port group 1 (V850ES/FG3, V850ES/FJ3, V850ES/FK3) Note Port group 1 is available only for V850ES/FG3-L. Port group 1 is a 2-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP9 and INTP10) Port group 1 includes the following pins: Table 2-18 Port group 1: pin functions and port types...
Page 103: Port Group 3
Chapter 2 Pin Functions 2.5.5 Port group 3 Port group 3 is a 10-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP7 and INTP8) • Timer TAA0 channels (TIAA00, TIAA01 and TOAA00, TOAA01) •...
Page 104 Chapter 2 Pin Functions Table 2-21 Port group 3: configuration registers Initial Register Address Used bits value V850ES/FE3-L PMC3L FFFF F446 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PM3L FFFF F426 PM35 PM34 PM33 PM32 PM31 PM30 PFC3L FFFF F466 PFC35 PFC34 PFC33 PFC32...
Page 105: Port Group 4
Chapter 2 Pin Functions 2.5.6 Port group 4 Port group 4 is a 3-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP14) • Key interrupt input (KR0 to KR2) • Clocked Serial Interface CSIB0 data/clock line (SIB0, SOB0, SCKB0) Port group 4 includes the following pins: Table 2-22 Port group 4: pin functions and buffer...
Page 106: Port Group 5
Chapter 2 Pin Functions 2.5.7 Port group 5 Port group 5 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Key interrupt input 0 to 5 (KR0 to KR5) • N-Wire debug interface signals (DDI, DDO, DCK, DMS) Port group 5 includes the following pins: Table 2-24 Port group 5: pin functions and port types...
Page 107: Port Group 7
Chapter 2 Pin Functions 2.5.8 Port group 7 Port group 7 is a 16-bit port group. It includes pins for the following functions: • A/D Converter 0 inputs Port group 7 includes the following pins: Table 2-26 Port group 7: pin functions and port types Pin functions in different modes Port Noise...
Page 108 Chapter 2 Pin Functions Table 2-27 Port group 7: configuration registers Initial Register Address Used bits value PMC7L FFFF F44E PMC77 PMC76 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 PMC7H FFFF F44F PMC715 PMC714 PMC713 PMC712 PMC711 PMC710 PMC79 PMC78 PM7L FFFF F42E PM77 PM76...
Page 109: Port Group 9
Chapter 2 Pin Functions 2.5.9 Port group 9 Port group 9 is an 16-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP4 to INTP6) • Key interrupt input 6 to 7 (KR6 to KR7) •...
Page 110 Chapter 2 Pin Functions Table 2-29 Port group 9: V850ES/FE3-L, V850ES/FF3-L configuration registers Initial Register Address Used bits value PMC9L FFFF F452 PMC97 PMC96 PMC91 PMC90 PMC9H FFFF F453 PMC915 PMC914 PMC913 PMC99 PMC98 PMC9 (16 bit) FFFF F452 0000 PMC915 to PMC98 (PMC9H) PMC97 to PMC90 (PMC9L) PM9L...
Page 111 Chapter 2 Pin Functions Table 2-30 Port group 9: V850ES/FG3-L configuration registers Initial Register Address Used bits value PMC9L FFFF F452 PMC97 PMC96 PMC91 PMC90 PMC9H FFFF F453 PMC915 PMC914 PMC913 PMC99 PMC98 PMC9 (16 bit) FFFF F452 0000 PMC915 to PMC98 (PMC9H) PMC97 to PMC90 (PMC9L) PM9L FFFF F432...
Page 112: Port Group Cm
Chapter 2 Pin Functions 2.5.10 Port group CM Port group CM is a 6-bit port group. In alternative mode, it comprises pins for the following functions: • CPU system clock output (CLKOUT) Port group CM includes the following pins: Table 2-31 Port group CM: pin functions and port types Pin functions in different modes Port...
Page 113: Port Group Cs (V850Es/Ff3-L, V850Es/Fg3-L)
Chapter 2 Pin Functions 2.5.11 Port group CS (V850ES/FF3-L, V850ES/FG3-L) Note Port group CS is available only for V850ES/FF3-L and V850ES/FG3-L. Port group CS is an 8-bit port group. Port group CS includes the following pins: Table 2-33 Port group CS: pin functions and port types Pin functions in different modes Port Noise...
Page 114: Port Group Ct (V850Es/Ff3-L, V850Es/Fg3-L)
Chapter 2 Pin Functions 2.5.12 Port group CT (V850ES/FF3-L, V850ES/FG3-L) Note Port group CT is available only for V850ES/FF3-L and V850ES/FG3-L. Port group CT is an 8-bit port group. Port group CT includes the following pins: Table 2-35 Port group CT: pin functions and port types Pin functions in different modes Port Noise...
Page 115: Port Group Dl
Chapter 2 Pin Functions 2.5.13 Port group DL Port group DL is an 16-bit input/output port group. Port group DL includes the following pins: Table 2-37 Port group DL: pin functions and port types Pin functions in different modes Port Noise Input function...
Page 116: Noise Elimination
Chapter 2 Pin Functions 2.6 Noise Elimination The input signals at some pins are passing a filter to remove noise and glitches. The microcontroller supports both analog and digital filters. In Table 2-16 on page 100 and in the following tables it is listed whether a pin is equipped with an analog filter, a digital filter, both analog and digital filter, or no filter at all.
Page 117: Digitally Filtered Inputs
Chapter 2 Pin Functions 2.6.2 Digitally filtered inputs The input signal INTP3 is passed through both an analog and a digital filter. The digital filter operates in all modes, in which f is available. Thus, it does not operate in standby modes (if f is used as the sampling clock, it can operate in standby modes).
Page 118 Chapter 2 Pin Functions NFC - Digital noise filter control register The 8-bit NFC register specifies the noise elimination circuit for signal INTP3. Access This register can be read/written in 8-bit and 1-bit units. Address FFFF F318 Initial Value . This register is cleared by any reset. NFEN NFSTS NFC2...
Page 119 Chapter 2 Pin Functions When using the interrupt function, after the N sampling clocks (selected sampling frequency N = 3 or 2) have elapsed, enable interrupts after the interrupt request flag (PIC3.PIF3 bit) has been cleared. When using the DMA function (started by INTP3), enable DMA after the N sampling clocks have elapsed.
Page 120: Pin Functions In Reset And Power Save Modes
Chapter 2 Pin Functions 2.7 Pin Functions in Reset and Power Save Modes The following table summarizes the status of the pins during reset and power save modes and after release of these operating states in normal operation mode. The reset source makes a difference concerning the N-Wire debugger interface pins DRST, DDI, DDO, DCK and DMS after reset release.
Page 121: Recommended Connection Of Unused Pins
Chapter 2 Pin Functions 2.8 Recommended Connection of unused Pins If a pin is not used, it is recommended to connect it as follows: Table 2-41 Recommended connection of unused pins Recommended connection Port pins pins of port groups 0, 1, 3 to 5, 9 •...
Page 122: Package Pins Assignment
Chapter 2 Pin Functions 2.9 Package Pins Assignment The following figures shows the location of pins in top view. Every pin is labelled with its pin number and all possible pin names. 2.9.1 V850ES/FE3-L package pins assignment AVREF0 ○ 48 ←→○ PDL1 AVSS ○...
Page 123: V850Es/Ff3-L Package Pins Assignment
Chapter 2 Pin Functions 2.9.2 V850ES/FF3-L package pins assignment AVREF0 60 ←→○ PDL3 ○ AVSS ○ 59 ←→○ PDL2 P00/TIAA31/TOAA31 ○←→ 58 ←→○ PDL1 P01/TIAA30/TOAA30 ○←→ 57 ←→○ PDL0 P02/NMI/TIAA40/TOAA40 ○←→ 56 ←→○ PCT6 P03/INTP0/ADTRG/TIAA41/TOAA41 ○←→ 55 ←→○ PCT4 μPD70F3615GK-GAK P04/INTP1/CRXD0 ○←→...
Page 124: V850Es/Fg3 Package Pins Assignment
Chapter 2 Pin Functions 2.9.3 V850ES/FG3 package pins assignment AVREF0 75 ←→○ PDL4 ○ AVSS 74 ←→○ PDL3 ○ P10/INTP9 ○←→ 73 ←→○ PDL2 P11/INTP10 ○←→ 72 ←→○ PDL1 EVDD ○ 71 ←→○ PDL0 P00/TIAA31/TOAA31 ○←→ ○ BVDD P01/TIAA30/TOAA30 ○←→ ○...
Page 125: Cpu System Functions
Chapter 3 CPU System Functions This chapter describes the registers of the CPU, the operation modes, the address space and the memory areas. 3.1 Overview The CPU is founded on Harvard architecture and it supports a RISC instruction set. Basic instructions can be executed in one clock period. Optimized five- stage pipelining is supported.
Page 126: Description
Chapter 3 CPU System Functions 3.1.1 Description The figure below shows a block diagram of the microcontroller, focusing on the CPU and modules that interact with the CPU directly. Table 3-1 lists the bus types. RCU interface System controller Instruction queue Multiplier (16 x 16 →...
Page 127: Cpu Register Set
Chapter 3 CPU System Functions 3.2 CPU Register Set There are two categories of registers: • General purpose registers • System registers All registers are 32-bit registers. An overview is given in the figure below. For details, refer to V850ES User’s Manual Architecture. (Zero Register) EIPC (Status Saving Register during interrupt)
Page 128: General Purpose Registers (R0 To R31)
Chapter 3 CPU System Functions 3.2.1 General purpose registers (r0 to r31) Each of the 32 general purpose registers can be used as a data variable or address variable. However, the registers r0, r1, r3 to r5, r30, and r31 may implicitly be used by the assembler/compiler (see table Table 3-2).
Page 129: System Register Set
Chapter 3 CPU System Functions 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Additionally, the program counter holds the instruction address during program execution. To read/write the system registers, use instructions LDSR (load to system register) or STSR (store contents of system register), respectively, with a specific system register number (regID) indicated below.
Page 130 Chapter 3 CPU System Functions PC - Program counter The program counter holds the instruction address during program execution. The lower 26 bits are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to 26, it is ignored. Branching to an odd address cannot be performed.
Page 131 Chapter 3 CPU System Functions PSW - Program status word The 32-bit program status word is a collection of flags that indicates the status of the program (result of instruction execution) and the status of the CPU. If the bits in the register are modified by the LDSR instruction, the PSW will take on the new value immediately after the LDSR instruction has been executed.
Page 132 Chapter 3 CPU System Functions Table 3-5 PSW register contents (2/2) Bit position Flag Function Overflow flag. Indicates whether an overflow occurred as a result of the operation. 0: Overflow did not occur. 1: Overflow occurred. Sign flag. Indicates whether the result of the operation is negative. 0: Result is positive or zero.
Page 133 Chapter 3 CPU System Functions EIPSW, FEPSW, DBPSW, CTPSW saving registers The PSW saving registers save the contents of the program status word for different occasions, see Table 3-4. When one of the occasions listed in Table 3-4 occurs, the current value of the PSW is saved to the saving registers.
Page 134 Chapter 3 CPU System Functions ECR - Interrupt/exception source register The 32-bit ECR register displays the exception codes if an exception or an interrupt has occurred. With the exception code, the interrupt/exception source can be identified. For a list of interrupts/exceptions and corresponding exception codes, see Table 3-9 on page 134.
Page 135 Chapter 3 CPU System Functions If an interrupt (maskable or non-maskable) is acknowledged during instruction execution, generally, the address of the instruction following the one being executed is saved to the saving registers, except when an interrupt is acknowledged during execution of one of the following instructions: •...
Page 136: Operation Modes
Chapter 3 CPU System Functions 3.3 Operation Modes This section describes the operation modes of the CPU and how the modes are specified. The following operation modes are available: • Normal operation mode • Flash programming mode • On-chip debug mode After reset release, the microcontroller starts to fetch instructions from an internal boot ROM which contains the internal firmware.
Page 137: Address Space
Chapter 3 CPU System Functions For more information see Chapter 23 on page 711. 3.4 Address Space In the following sections, the address space of the CPU is explained. Size and addresses of CPU address space and physical address space are explained. The address range of data space and program space together with their wrap- around properties are presented.
Page 138 Chapter 3 CPU System Functions The 64 MB physical address space is seen as 64 images in the 4 GB CPU address space: CPU address space FFFF FFFFH Image FC00 0000H FBFF FFFFH Physical address space x3FF FFFFH Fixed peripheral I/O x3FF F000H Image note...
Page 139: Program And Data Space
Chapter 3 CPU System Functions 3.4.2 Program and data space The CPU allows the following assignment of data and instructions to the CPU address space: • 4 GB as data space The entire CPU address space can be used for operand addresses. •...
Page 140 Chapter 3 CPU System Functions Wrap-around of data space If an operand address calculation exceeds 32 bits, only the lower 32 bits of the result are considered. Therefore, the addresses 0000 0000 and FFFF FFFF are contiguous addresses. This results in a wrap-around of the data space: Data space FFFF FFFEH FFFF FFFFH...
Page 141: Memory
Chapter 3 CPU System Functions 3.5 Memory In the following sections, the memory of the CPU is introduced. Specific memory areas are described and a recommendation for the usage of the address space is given. 3.5.1 Memory areas The internal memory of the CPU provides several areas: •...
Page 142 Chapter 3 CPU System Functions Table 3-12 Internal RAM areas V850ES/Fx3-L Product Device RAM size Address range V850ES/FE3-L µPD70F3610 6 KB 03FF D800 – 03FF EFFF µPD70F3611 6 KB 03FF D800 – 03FF EFFF µPD70F3612 8 KB 03FF D000 – 03FF EFFF µPD70F3613 12 KB 03FF C000...
Page 143 Chapter 3 CPU System Functions For registers in which byte access is possible, if half word access is executed: • During read operation: The higher 8 bits become undefined. • During write operation: The lower 8 bits of data are written to the register.
Page 144: Recommended Use Of Data Address Space
Chapter 3 CPU System Functions 3.5.2 Recommended use of data address space When accessing operand data in the data space, one register has to be used for address generation. This register is called pointer register. With relative addressing, an instruction can access operand data at all addresses that lie in the range of ±32 KB relative to the address in the pointer register.
Page 145: Write Protected Registers
Chapter 3 CPU System Functions 3.6 Write Protected Registers Write protected registers are protected from inadvertent write access due to erroneous program execution, etc. Write access to a write protected register is only given immediately after writing to a corresponding write enable register. For a write access to the write protected registers you have to use the following instructions: 1.
Page 146 Chapter 3 CPU System Functions Since any action between writing to a write enable register and writing to a protected register destroys this sequence, the effects of interrupts have to be considered: • In order to prevent any maskable interrupt to be acknowledged between the two write instructions in question, shield this sequence by DI-EI (disable interrupt—enableinterrupt).
Page 147: Write Protection Control Registers
Chapter 3 CPU System Functions 3.6.1 Write protection control registers The following section describes the registers that control access to write protected registers. PRCMD - Command register The 8-bit PRCMD register protects other registers from inadvertent write access, so that the system does not stop in case of a program hang-up. After writing to the PRCMD register, you are permitted to write once to one of the protected registers.
Page 148: Chapter 4 Clock Generator
Chapter 4 Clock Generator The Clock Generator provides the clock signals needed by the CPU and the on-chip peripherals. 4.1 Overview The Clock Generator can generate the required clock signals from the following sources: • Main oscillator—a built-in oscillator that requires an external crystal with a frequency between 4 MHz and 16 MHz •...
Page 149: Description
Chapter 4 Clock Generator 4.1.1 Description The Clock Generator is built up as illustrated in the following figure. OB_7A.STOPXTAL OB_7A.STOPRCZ PCC.FRC Xtal SubOSC WT, TMM0, TAA1, TAA3 240 KHz WDT2, TMM0 RingOSC IDLE control RCM.RSTOP OB_7B.SUBCLK Clock Monitor PCC.MFRC IDLE1,2 mode OB_7B.PLLI[1:0] OB_7B.PLLO PLLCTL.PLLON...
Page 150 Chapter 4 Clock Generator 8 MHz internal OSC The high speed internal oscillator generates a clock f with a frequency of typically 8 MHz. After reset release, the 8 MHz internal oscillator is activated. The high speed internal oscillator is equipped with a stop control. The oscillation can be stopped by means of the RCM register.
Page 151 Chapter 4 Clock Generator Prescaler2, the SubOSC, or the 240 KHz internal OSC can generate the CPU core clock (f ) and the CPU system clock (f ). The only difference VBCLK between f and f is that the latter can be stopped in HALT mode. VBCLK is the clock supplied to the DMA, INTC, ROM, and RAM blocks.
Page 152: Clock Monitor
Chapter 4 Clock Generator Stand-by control In the block diagram, you find also boxes labelled “IDLE Control” or “HALT control”. These boxes symbolize the switches that are used to disable circuits when the microcontroller enters one of the various power save modes. For an introduction, see “Power save modes overview“...
Page 153: Power Save Modes Overview
Chapter 4 Clock Generator 4.1.3 Power save modes overview The power consumption of the system can be effectively reduced by using the stand-by modes and selecting the appropriate mode for the application. The available stand-by modes are listed below. The following explanations provide a general overview. For details, please refer to “Power save modes description“...
Page 154: Start Conditions
Chapter 4 Clock Generator 4.1.4 Start conditions After securing the setup time of the 8 MHz internal OSC, the CPU begins program execution. The oscillation stabilization time for the internal oscillator is ensured by hardware. The table below shows the state during reset and after reset release. Table 4-2 Oscillation during reset period or after reset release Item...
Page 155: Clock Generator Registers
Chapter 4 Clock Generator 4.2 Clock Generator Registers The Clock Generator is controlled and operated by means of the following registers (the list is sorted according to memory allocation): Table 4-3 Clock Generator register overview Write- Register name Shortcut Address protected by register Power save control register...
Page 156 Chapter 4 Clock Generator The subsequent register descriptions are grouped as follows: • General clock generator registers: – “CCLS - CPU operation clock status register“ on page 157 – “MCM - Main system clock mode register“ on page 158 – “OSTC - Oscillation stabilization timer status register“ on page 159 –...
Page 157: General Clock Generator Registers
Chapter 4 Clock Generator 4.2.1 General Clock Generator registers The general clock generator registers control and reflect the operation of the clock generator. CCLS - CPU operation clock status register The CCLS register indicates the CPU operation clock status.. Access This register can be read in 1-bit or 8-bit units.
Page 158 Chapter 4 Clock Generator MCM - Main system clock mode register The 8-bit MCM register specifies the main system clock (f ) source in clock- through mode and informs about its status. Access This register can be read/written in 1-bit or 8-bit units. Writing to this register is protected by a special sequence of instructions.
Page 159 Chapter 4 Clock Generator OSTC - Oscillation stabilization timer status register The 8-bit OSTC register indicates the status of the main oscillator. Access This register is read-only. This register can be read in 1-bit and 8-bit units Address FFFF F6C2 Initial Value .
Page 160 Chapter 4 Clock Generator OSTS - Oscillation stabilization time select register The 8-bit OSTS register specifies the oscillation stabilization time following reset release or release of the STOP mode. The oscillation stabilization time and setup time are required when the STOP mode and IDLE mode are released, respectively.
Page 161 Chapter 4 Clock Generator Note When IDLE2 mode is released, set the stabilization time to the following requirements: – In case of PLL mode: PLL lockup time requirements – In case of clock-through mode: flash set up time requirement For the exact timing values, refer to the Datasheet. When STOP mode is released, set the stabilization time to the following requirements: –...
Page 162 Chapter 4 Clock Generator PCC - Processor clock control register The 8-bit PCC register controls the CPU system clock f VBCLK Access This register can be read/written in 1-bit and 8-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “CPU System Functions“...
Page 163 Chapter 4 Clock Generator Table 4-8 PCC register contents (2/2) Bit name Function position 3 to 0 CK[3:0] Clock selection: Clock selection × Setting prohibited × × × Subclock f or f Note: 1. Do not change the CPU clock (by using the CK[3:0] bits) while CLKOUT is being output.
Page 164 Chapter 4 Clock Generator subclock to main 1. Setting the MCK bit to "0": Enables main clock oscillation. 2. Software wait: Insert wait status via program to wait until the oscillation stabilization time of the main clock oscillator (OSTC.MSTS = 1) is elapsed. 3.
Page 165 Chapter 4 Clock Generator PCLM - Programmable clock mode register The 8-bit PCLM register specifies the setting the programmable clock output PCL. Access This register can be read/written in 1-bit or 8-bit units. Address FFFF F82F Initial Value . The register is initialized by any reset. PCLM PCLE PCK1...
Page 166 Chapter 4 Clock Generator RCM - Internal oscillator mode register The 8-bit RCM register specifies the operation and informs about the status of the low-speed and high-speed internal oscillators. Access This register can be read/written in 1-bit or 8-bit units. Address FFFF F80C Initial Value...
Page 167: Pll Control Registers
Chapter 4 Clock Generator 4.2.2 PLL control registers The PLL registers control and reflect the operation of the PLL. LOCKR - PLL lock status register Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time).
Page 168 Chapter 4 Clock Generator PLLCTL - PLL control register The 8-bit PLLCTL register controls the PLL function. Access This register can be read or written in 8-bit or 1-bit units. Address FFFF F82C Initial Value . The register is initialized by any reset. PLLCTL SELPLL PLLON...
Page 169 Chapter 4 Clock Generator PLLS - PLL lockup time specification register The 8-bit PLLS register specifies the settling time of the PLL. Access This register can be read/written in 8-bit units. Address FFFF F6C1 Initial Value . The register is initialized by any reset. PLLS PLLS2 PLLS1...
Page 170: Stand-By Control Registers
Chapter 4 Clock Generator 4.2.3 Stand-by control registers These registers control and reflect the various stand-by modes that can be entered for saving power. PSC - Power save control register The 8-bit PSC register controls the stand-by function. The STP bit of this register specifies the stand-by mode.
Page 171 Chapter 4 Clock Generator PSMR - Power save mode control register The 8-bit PSMR register is used to specify one of the power save modes. The setting becomes effective when the mode is entered by setting PSC.STP to 1. Access This register can be read/written in 1-bit or 8-bit units.
Page 172: Prescaler3 Control Registers
Chapter 4 Clock Generator 4.2.4 Prescaler3 control registers These registers control the Prescaler3 that generates f which can be applied to the Watch Timer and the Clocked Serial Interface CSIB0. Prescaler3 includes a clock divider, a counter, and a comparator. For details see “Operation of Prescaler3“...
Page 173: Clock Monitor Control Registers
Chapter 4 Clock Generator PRSCM0 - Prescaler3 compare register The PRSCM0 register specifies the compare value and hence the output frequency of f Access This register can be read/written in 8-bit units. Address FFFF F8B1 Initial Value . This register is cleared by any reset. PRSCM0 PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 Note...
Page 174: Selector Control Registers
Chapter 4 Clock Generator 4.2.6 Selector control registers These registers are used to select the clocks and functions of timers TAAn, TMM0 and serial interfaces UARTDn, CANn. Note In this section, only the bits that refer to clock generation and distribution are described.
Page 175 Chapter 4 Clock Generator SELCNT2 - Selector control register 2 The 8-bit SELCNT2 register is used to specify the clock for UARTD0, UARTD1, CAN0 and TAAn. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F30C Initial Value .
Page 176 Chapter 4 Clock Generator SELCNT3 - Selector control register 3 The 8-bit SELCNT3 register is used to specify the clocks for UARTD2. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F30E Initial Value . The register is initialized by any reset. •...
Page 177: Option Bytes
Chapter 4 Clock Generator 4.3 Option Bytes The code flash memory versions in this product series have an option data area where a block subject to mask options is specified. When writing a program to a code flash memory version, be sure to set the option data area corresponding to the following option bytes.
Page 178: Option Byte 0000 007A H
Chapter 4 Clock Generator 4.3.1 Option byte 0000 007A Address 0000 007A STOPXTAL STOPRCZ WDTMD1 RMOPIN Note Bits marked with “0” must not be changed from their value “0”. Table 4-21 Setting of option byte 0000 007A Bit name Function position 7 to 6 STOPXTAL,...
Page 179: Option Byte 0000 007B H
Chapter 4 Clock Generator 4.3.2 Option byte 0000 007B Address 0000 007B SUBCLK LATENCY PLLO PRSI PLLI1 PLLI0 Note Bits marked with “0” must not be changed from their value “0”. Table 4-22 Setting of option byte 0000 007B Bit name Function position SUBCLK...
Page 180: Clock Generator Operation
Chapter 4 Clock Generator 4.4 Clock Generator Operation This chapter describes the specific features of the Clock Generator. For details see: • “Overview of clock operation control settings“ on page 180 • “Operation state transitions“ on page 181 • “Power save modes description“ on page 184 •...
Page 181: Operation State Transitions
Chapter 4 Clock Generator 4.4.2 Operation state transitions The following figure illustrates the various state transitions. RESET 8 MHz internal Each STBY oscillator operation (HALT/IDLE1/IDLE2/ Software STOP) Oscillation stabilization wait Each STBY (HALT/IDLE1/IDLE2/ Software STOP) X1 main clock-through PLL operation (PLL = ON) Note 1 (PLL = ON)
Page 182 Chapter 4 Clock Generator Status transition from PLL operation Note 2 PLL operation (PLL = ON) Note 1 HALT mode Software STOP mode X1 = ON, PLL = ON X1 = OFF, PLL = OFF IDLE1 mode IDLE2 mode X1 = ON, PLL = ON X1 = ON, PLL = OFF Figure 4-3 Stand-by transition from PLL operation (PLL = ON)
Page 183 Chapter 4 Clock Generator Status transition from clock-through operation (with PLL off) Note 2 X1 main clock-through mode (PLL = OFF) Note 1 HALT mode Software STOP mode X1 = ON, PLL = OFF X1 = OFF, PLL = OFF IDLE1 mode IDLE2 mode X1 = ON, PLL = OFF...
Page 184: Power Save Modes Description
Chapter 4 Clock Generator 4.4.3 Power save modes description This section explains the various power save modes in detail. Table 4-24 Stand-by modes Mode Functional Outline HALT mode Mode in which only the operating clock of the CPU is stopped IDLE1 mode Mode in which all the internal operations of the chip except the oscillator, PLL/SSCG, and flash memory are stopped...
Page 185 Chapter 4 Clock Generator Note In the following tables the clock status “operates” does not necessarily mean that the functions that use this clock source are operating as well. HALT mode In this mode, the clock oscillators continue operating, but clock supply to the CPU is stopped.
Page 186 Chapter 4 Clock Generator Table 4-25 Controller status in HALT mode (2/2) Working condition Without Subclock With Subclock Clock Monitor Operable Power-On-Clear circuit Operable Low-Voltage Detector Operable Voltage Regulator Operation continues Internal data The CPU registers, states, data and all other internal data such as the contents of the internal RAM are retained as they were before HALT mode was set Leaving HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI...
Page 187 Chapter 4 Clock Generator IDLE1 mode In the IDLE1 mode, the main oscillator, PLL, and flash memory continue operating, but clock supply to the CPU and the other on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the IDLE1 mode was set are retained.
Page 188 Chapter 4 Clock Generator Table 4-27 Controller status in IDLE1 mode (2/2) Working condition Without Subclock With Subclock Power-On-Clear circuit Operable Low-Voltage Detector Operable Voltage Regulator Operation continues Internal data The CPU registers, states, data and all other internal data such as the contents of the internal RAM are retained as they were before IDLE1 mode was set Only when setting the ISELxx bit =1 (f ), the count operation by f...
Page 189 Chapter 4 Clock Generator IDLE2 mode In the IDLE2 mode, the main clock oscillator continues operating, but clock supply to the CPU, PLL, flash memory, and the other on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the IDLE2 mode was set are retained.
Page 190 Chapter 4 Clock Generator Table 4-29 Controller status in IDLE2 mode (2/2) Working condition Without Subclock With Subclock Low-Voltage Detector Operable Voltage Regulator Operation continuous Internal data The CPU registers, states, data and all other internal data such as the contents of the internal RAM are retained as they were before IDLE2 mode was set To achieve low power consumption, stop the A/D Converter before shifting to the IDLE2 mode.
Page 191 Chapter 4 Clock Generator (c) Securing setup time after release of IDLE2 mode Secure the setup time of ROM (flash memory) after releasing the IDLE2 mode. • Releasing by non-maskable interrupt request signal or unmasked maskable interrupt request signal: The setup time is secured by setting the OSTS register. When a source that releases the IDLE2 mode occurs, an internal dedicated timer starts counting in accordance with the setting of the OSTS register.
Page 192 Chapter 4 Clock Generator STOP mode In the STOP mode, the subclock oscillator continues operating, but the main clock oscillator stops operating. Moreover, clock supply to the CPU and the other on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set are retained.
Page 193 Chapter 4 Clock Generator Table 4-31 Controller status in STOP mode (2/2) Working condition Without Subclock With Subclock Power-On-Clear circuit Operable Low-Voltage Detector Operable Voltage Regulator Operation continuous Internal data The CPU registers, states, data and all other internal data such as the contents of the internal RAM are retained as they were before STOP mode was set Note If the STOP mode is set while the A/D Converter is operating, the A/D...
Page 194 Chapter 4 Clock Generator Table 4-32 Operation after STOP mode is released by interrupt request signal Releasing Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address after the specified signal oscillation stabilization time has elapsed. Maskable interrupt request signal Execution branches to the handler The next instruction is executed...
Page 195 Chapter 4 Clock Generator Subclock operation mode When the subclock operation mode is set, the CPU system clock f VBCLK changed from the main system clock to the subclock. Subclock can be f . The selection is made by the SUBCLK bit of the option byte 007B Check that the CPU system clock has been changed by using the CLS bit of the PCC register.
Page 196 Chapter 4 Clock Generator Table 4-33 Controller status in subclock mode (2/2) Working condition With MainOSC operating With MainOSC stopped Serial Interface UARTD0-2 Operable UARTD0: Operable if ASCKD0 is selected input clock UARTD1-2: Operation stops CSIB0-1 Operable Operable if SCKBn input clock is selected as operation clock.
Page 197 Chapter 4 Clock Generator Sub-IDLE mode In the sub-IDLE mode, the clock oscillator continues operating, but clock supply to the CPU, flash memory, and the other on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the sub-IDLE mode was set is retained.
Page 198 Chapter 4 Clock Generator Table 4-34 Controller status in sub-IDLE mode (2/2) Working condition When main clock oscillator When main clock oscillator stops oscillates Power-On-Clear circuit Operable Low-Voltage Detector Operable Voltage Regulator Operation continuous Internal data The CPU registers, statuses, data and all other internal data such as the contents of the internal RAM are retained as they were before Sub IDLE mode was set Stop the PLL (PLLCTL.PLLON = 0) when you stop the main clock oscillation circuit.
Page 199 Chapter 4 Clock Generator Table 4-35 Operation after sub-IDLE mode is released by interrupt request signal Releasing Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt Execution branches to the handler address. request signal Maskable interrupt Execution branches to the handler address, The next instruction is executed.
Page 200: Available Clocks In Power Save Modes
Chapter 4 Clock Generator 4.4.4 Available clocks in power save modes The following table gives an overview of the clock signals available in the various stand-by modes. Table 4-36 Clock operation in power save modes PLLI Operation status VBCLK Note2 Note2 Note2 Note2...
Page 201 Chapter 4 Clock Generator O: Operating x: Stopped Enable: Operation enable (by control register and option bytes setting) Note The working conditions are the following: - 8 MHz internal oscillator: 8 MHz internal oscillator clock operation - MainOSC: MainOSC clock operation - PLL: PLL clock operation - SubOSC:...
Page 202: Power Save Mode Activation
Chapter 4 Clock Generator 4.4.5 Power save mode activation In the following procedures are described how to securely entering a power save mode. Caution Before entering any power save mode make sure that any access to the data flash is completed. HALT mode For entering the HALT mode proceed as follows: 1.
Page 203 Chapter 4 Clock Generator In this example, maskable interrupts are permitted to leave the power save mode. // xxIC.xxMK = 0 // mask all none wake-up interrupts // xxIC.xxMK = 1 // unmask all wake-up interrupts 0x02,r10 st.b 10,PSMR[r0] // PSMR.PSM[1:0] = 10B: IDLE2 mode 0x62,r10 st.b r10,PRCMD[r0]...
Page 204: Controlling The Pll
Chapter 4 Clock Generator 4.4.6 Controlling the PLL Using the PLL After the RESET signal has been released, the PLL has to be started by PLLCTL.PLLON = 1, after the main oscillator has stabilized (OSTC.MSTS = 1). Since the default mode is the clock-through mode (PLLCTL.SELPLL = 0), select the PLL mode (PLLCTL.SELPLL = 1).
Page 205: Operation Of Prescaler3
Chapter 4 Clock Generator 4.4.9 Operation of Prescaler3 Prescaler3 generates the clock f by dividing the main oscillator output signal f Description Prescaler3 consists of a clock divider, a counter, and a comparator. Figure 4-9 Prescaler3 Block Diagram Calculation The relation between the main oscillator clock (f ), prescaler clock divider selection PRSM0.BGCS0[1:2], PRSCM0 compare register value, and output clock f...
Page 206: Operation Of The Clock Monitor
Chapter 4 Clock Generator 4.4.10 Operation of the Clock Monitor The Clock Monitor samples the main clock by using the internal 240 KHz internal oscillator. It generates a reset request signal when the oscillation of the main clock has stopped. Description The functional block diagram is shown below.
Page 207 Chapter 4 Clock Generator The Clock Monitor automatically stops under the following conditions: • While oscillation stabilization time is being counted after STOP mode is released • When the main clock is stopped (PCC.MCK bit = 1 during subclock operation, or PCC.CLS bit = 0 during main clock operation) •...
Page 208 Chapter 4 Clock Generator Operation when main clock is stopped During subclock operation (CLS bit of the PCC register = 1) or when the main clock is stopped by setting the MCK bit of the PCC register to 1, the monitor operation is stopped until the main clock operation is started (CLS bit of PCC register = 0).
Page 209: Chapter 5 Interrupt Controller (Intc)
Chapter 5 Interrupt Controller (INTC) This controller is provided with a dedicated Interrupt Controller (INTC) for interrupt servicing and can process a large amount of maskable and two non- maskable interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 210 Chapter 5 Interrupt Controller (INTC) Table 5-1 Interrupt/exception source list (1/3) Interrupt/Exception Source Default Exception Handler Restored Type Control Generating Priority Code Address Name Generating Source Register Unit Reset RESET – Reset input by internal source RESET – 0000 00000000 undef.
Page 211 Chapter 5 Interrupt Controller (INTC) Table 5-1 Interrupt/exception source list (2/3) Interrupt/Exception Source Default Exception Handler Restored Type Control Generating Priority Code Address Name Generating Source Register Unit Maskable INTTAA4CC0 TAA4CCIC0 TAA4 capture 0 / compare 0 match TAA4 0240 00000240 nextPC INTTAA4CC1...
Page 212 Chapter 5 Interrupt Controller (INTC) Table 5-1 Interrupt/exception source list (3/3) Interrupt/Exception Source Default Exception Handler Restored Type Control Generating Priority Code Address Name Generating Source Register Unit Maskable Reserved – – – 0460 00000460 nextPC Reserved – – – 0470 00000470 nextPC...
Page 213: Non-Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. Non-maskable interrupts of this microcontroller are available for the following requests: • NMI: NMI pin input •...
Page 214 Chapter 5 Interrupt Controller (INTC) NMI and INTWDT2 requests generated simultaneously Main routine INTWDT2 servicing NMI and INTWDT2 requests System reset (generated simultaneously) Figure 5-1 Example of non-maskable interrupt request acknowledgement operation: multiple NMI requests generated at the same time R01UH0469ED0201 Rev.
Page 215 Chapter 5 Interrupt Controller (INTC) NMI being NMI request generated during NMI servicing serviced INTWDT2 NMI request generated during INTWDT2 request generated NMI servicing during NMI servicing (NP = 1 retained before NMI1 request) Main routine Main routine NMI servicing NMI servicing INTWDT2 request (Held pending)
Page 216: Operation
Chapter 5 Interrupt Controller (INTC) 5.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: 1. Saves the restored PC to FEPC. 2. Saves the current PSW to FEPSW. 3.
Page 217: Restore
Chapter 5 Interrupt Controller (INTC) 5.2.2 Restore Execution is restored from the non-maskable interrupt (NMI) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. 1.
Page 218: Non-Maskable Interrupt Status Flag (Np)
Chapter 5 Interrupt Controller (INTC) 5.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 219: Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. This microcontroller has up to 52 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 220 Chapter 5 Interrupt Controller (INTC) INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request Interrupt request pending...
Page 221: Restore
Chapter 5 Interrupt Controller (INTC) 5.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. 1.
Page 222: Priorities Of Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.3.3 Priorities of maskable interrupts This microcontroller provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 223 Chapter 5 Interrupt Controller (INTC) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are enabled.
Page 224 Chapter 5 Interrupt Controller (INTC) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i. (level 1) k that occurs after j is acknowledged because it has the higher priority.
Page 225 Chapter 5 Interrupt Controller (INTC) Main routine Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request b and c are Processing of interrupt request b NMI request Interrupt request c (level 1) acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first Default priority...
Page 226: Xxicn - Maskable Interrupt Control Registers
Chapter 5 Interrupt Controller (INTC) 5.3.4 xxICn - Maskable interrupt control registers An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. Access This register can be read/written in 1-bit or 8-bit units. Address FFFF F110 to FFFF F1F8...
Page 227 Chapter 5 Interrupt Controller (INTC) The address and the availability of each interrupt control register for each device is shown in the following table. Note The symbols used in the table mean: √ : register available for the device –: register not available for the device Table 5-2 V850ES/Fx3-L addresses of interrupt control registers (1/2) V850ES/FE3-L...
Page 228 Chapter 5 Interrupt Controller (INTC) Table 5-2 V850ES/Fx3-L addresses of interrupt control registers (2/2) V850ES/FE3-L Address Register V850ES/FG3-L V850ES/FF3-L √ √ FFFFF160 UD1TIC √ √ FFFFF162 IIC0IC √ √ FFFFF164 ADIC √ √ FFFFF166 C0ERRIC √ √ FFFFF168 C0WUPIC √ √...
Page 229: Imrm - Interrupt Mask Registers
Chapter 5 Interrupt Controller (INTC) 5.3.5 IMRm - Interrupt mask registers These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMRm registers is equivalent to the xxMKn bit of the xxICn register. • 16 bit IMRm registers are accessible through –...
Page 230 Chapter 5 Interrupt Controller (INTC) IMR1 - Interrupt mask register 1 Address FFFF F102 Initial Value FFFF . The register is initialized by any reset IMR1 CB0RMK TM0EQMK0 TAA4CCMK1 TAA4CCMK0 TAA4OVMK TAA3CCMK1 TAA3CCMK0 TAA3OVMK TAA2CCMK1 TAA2CCMK0 TAA2OVMK TAA1CCMK1 TAA1CCMK0 TAA1OVMK TAA0CCMK1 TAA0CCMK0 IMR2 - Interrupt mask register 2 Address FFFF F104...
Page 231 Chapter 5 Interrupt Controller (INTC) IMR4 - Interrupt mask register 4 Address FFFF F108 Initial Value FFFF . The register is initialized by any reset • V850ES/FG3-L only IMR4 UD2TMK UD2RMK UD2SMK R01UH0469ED0201 Rev. 2.01 User Manual...
Page 232: Ispr - In-Service Priority Register
Chapter 5 Interrupt Controller (INTC) 5.3.6 ISPR - In-service priority register This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 233: Maskable Interrupt Status Flag (Id)
Chapter 5 Interrupt Controller (INTC) 5.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and this controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. Initial Value 00000020 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Bit position...
Page 234 Chapter 5 Interrupt Controller (INTC) Bit position Bit name Function Specifies the edge detection for external interrupt signals 15 to 0 INTRm[15:0] 0: no detection at rising edge 1: detection at rising edge INTFm The INTFm registers specify the falling edge for edge detection of corresponding external interrupt signals.
Page 235 Chapter 5 Interrupt Controller (INTC) INTR1/INTF1 - External interrupt edge specification register 1 Address FFFFFC22 Initial Value . The register is initialized by any reset. INTR1 INTR11 INTR10 INTP10 INTP9 Address FFFFFC02 Initial Value . The register is initialized by any reset. INTF1 INTF11 INTF10...
Page 236 Chapter 5 Interrupt Controller (INTC) • V850ES/FG3 • V850ES/FJ3 • V850ES/FK3 Address FFFFFC26 Initial Value 0000 . The register is initialized by any reset. INTR39 INTR3 INTP8 INTR31 INTP7 Both bytes of this 16-bit register can also be accessed bytewise with –...
Page 237 Chapter 5 Interrupt Controller (INTC) INTR6/INTF6 - External interrupt edge specification register 6 • V850ES/FJ3 Address FFFFFC2C Initial Value . The register is initialized by any reset. INTR6L INTR62 INTR61 INTR60 INTP13 INTP12 INTP11 Address FFFFFC0C Initial Value . The register is initialized by any reset. INTF6L INTF62 INTF61...
Page 238 Chapter 5 Interrupt Controller (INTC) INTR8/INTF8 - External interrupt edge specification register 8 • V850ES/FJ3 • V850ES/FK3 Address FFFFFC30 Initial Value . The register is initialized by any reset. INTR8 INTR80 INTP14 Address FFFFFC10 Initial Value . The register is initialized by any reset. INTF8 INTF80 INTP14...
Page 239: Software Exception
Chapter 5 Interrupt Controller (INTC) 5.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 5.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: 1.
Page 240: Restore
Chapter 5 Interrupt Controller (INTC) 5.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. 1. Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1.
Page 241: Exception Status Flag (Ep)
Chapter 5 Interrupt Controller (INTC) 5.5.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Initial Value 00000020 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Bit position...
Page 242: Exception Trap
Chapter 5 Interrupt Controller (INTC) 5.6 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. For this microcontroller, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 5.6.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111 , a sub-opcode...
Page 243: Debug Trap
Chapter 5 Interrupt Controller (INTC) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. 1. Loads the restored PC and PSW from DBPC and DBPSW. 2.
Page 244 Chapter 5 Interrupt Controller (INTC) DBTRAP instruction DBPC restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing Figure 5-14 Debug trap processing Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 245: Multiple Interrupt Processing Control
Chapter 5 Interrupt Controller (INTC) 5.7 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first.
Page 246 Chapter 5 Interrupt Controller (INTC) Generation of exception in service program Service program of maskable interrupt or exception •EIPC saved to memory or register •EIPSW saved to memory or register •TRAP instruction ¨ Exception such as TRAP instruction acknowledged. •Saved value restored to EIPSW •Saved value restored to EIPC •RETI instruction The priority order for multiple interrupt processing control has 8 levels, from 0...
Page 247: Interrupt Response Time
Chapter 5 Interrupt Controller (INTC) 5.8 Interrupt Response Time The following table describes the interrupt response time (from interrupt generation to start of interrupt processing). Except in the following cases, the interrupt response time is a minimum of 5 clocks. •...
Page 248: Periods In Which Interrupts Are Not Acknowledged
Chapter 5 Interrupt Controller (INTC) 5.9 Periods in which interrupts are not acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction. The interrupt request non-sampling instructions are as follows: •...
Page 249: Chapter 6 Key Interrupt Function
Chapter 6 Key Interrupt Function 6.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the key return mode register (KRM). Table 6-1 Assignment of Key Return Detection Pins Flag Pin Description...
Page 250: Control Register
Chapter 6 Key Interrupt Function 6.2 Control Register KRM - Key return mode register The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F300 Initial Value...
Page 251: Chapter 7 Flash Memory
Chapter 7 Flash Memory The following V850ES/Fx3-L devices are equipped with internal flash memory: Product Product name Code flash V850ES/FE3-L µPD70F3610 64 KB µPD70F3611 96 KB µPD70F3612 128 KB µPD70F3613 192 KB µPD70F3614 256 KB V850ES/FF3-L µPD70F3615 64 KB µPD70F3616 96 KB µPD70F3617 128 KB...
Page 252: Code Flash Memory Overview
Chapter 7 Flash Memory 7.1 Code Flash Memory Overview 7.1.1 Code flash memory features • 4-byte/1 CPU clock access during instruction fetch • All-blocks or multiple blocks batch erase or single block erase • Erase/write with single power supply • Communication with dedicated flash programmer via various serial interfaces •...
Page 253: Code Flash Memory Mapping
Chapter 7 Flash Memory 7.1.2 Code flash memory mapping The microcontroller’s internal code flash memory area is divided into blocks of 2 KB respectively 4 KB blocks and can be programmed/erased in block units. All or some of the blocks can also be erased at once. Following figures list the block structures and address assignments for all V850ES/Fx3-L devices with code flash memory.
Page 254 Chapter 7 Flash Memory 0003 FFFF Block 127 (2 KB) 0003 F800 0003 07FF Block 96 (2 KB) 0003 0000 0002 FFFF Block 95 (2 KB) Block 95 (2 KB) 0002 F800 0002 07FF Block 64 (2 KB) 0002 0000 0001 FFFF Block 63 (2 KB) Block 63 (2 KB)
Page 255: Code Flash Memory Functional Outline
Chapter 7 Flash Memory 7.1.3 Code flash memory functional outline Serial programming The internal flash memory of the microcontroller can be rewritten by using the rewrite function of a dedicated flash programmer, regardless of whether the microcontroller has already been mounted on the target system or the device is not mounted (off-board/on-board programming).
Page 256 Chapter 7 Flash Memory Table 7-1 Flash memory write methods Environment Interface Outline Operation Mode Serial Serial I/F (UART, Flash memory programming is done by an external Flash memory programming CSI) flash programmer. programming The device may be mounted on the target system (on- mode board) or unmounted (off-board) by using a suitable programming adapter board.
Page 257 Chapter 7 Flash Memory Table 7-2 Basic functions for flash memory modifications Support (√: Supported, ×: Not supported) Function Functional outline Serial Self-programming programming √ √ Block erasure The contents of specified memory blocks are erased. Multiple block The contents of the specified successive multiple √...
Page 258: Code Flash Memory Erasure And Rewrite
Chapter 7 Flash Memory The boot cluster protection flag is not erased. 7.1.4 Code flash memory erasure and rewrite Erasure According to its block structure the flash memory can be erased in two different modes. • All-blocks batch erasure (chip erase) All blocks are erased all together.
Page 259: Flash Programming With Flash Programmer
Chapter 7 Flash Memory 7.2 Flash Programming with Flash Programmer A dedicated flash programmer can be used for external writing of the flash memory. • On-board programming The contents of the flash memory can be rewritten with the microcontroller mounted on the target system. Mount a connector that connects the flash programmer on the target system.
Page 260: Communication Mode
Chapter 7 Flash Memory 7.2.2 Communication mode The communication between the flash programmer and the microcontroller utilizes the asynchronous serial interface UART or optionally the synchronous serial interface CSI. For programming via the synchronous serial interface CSI without handshake and with handshake modes are supported. In the latter mode the port pin HSPORT is used for the programmer’s handshake signal HS.
Page 261 Chapter 7 Flash Memory CSI with handshake (CSI + HS) The external flash programmer offers various choices of available clock rates. Note Note FLMD0 (FLMD1 FLMD0 (FLMD1 RESET RESET V850 microcontroller flash programmer HSPORT Note: FLMD1 connection may be replaced by a pull-down resistor on the board Figure 7-6 Communication with flash programmer via CSI with handshake The flash programmer outputs a transfer clock and the microcontroller...
Page 262: Pin Connection With Flash Programmer Pg-Fp5
Chapter 7 Flash Memory 7.2.3 Pin connection with flash programmer PG-FP5 A connector must be mounted on the target system to connect the flash programmer for on-board writing. In addition, functions to switch between the normal operation mode and flash memory programming mode and to control the microcontroller’s reset pin must be provided on the board.
Page 263 Chapter 7 Flash Memory Table 7-5 Wiring of V850ES/Fx3 flash writing adapters Flash programmer (FG-FP5) connection Name of Name of Serial I/F pin FA board Signal name Pin function UARTD0 CSIB0 + HS CSIB0 SI/RxD Receive signal TXDD0 SOB0 SO/TxD Transmit signal RXDD0 SIB0...
Page 264: Flash Memory Programming Control
Chapter 7 Flash Memory 7.2.4 Flash memory programming control The procedure to program the flash memory is illustrated below. Reset/FLMD0 pulse supply Note: A reset pulse is required to initiate the selection of the flash programming mode. Figure 7-7 Flash memory programming procedure Operation mode control To rewrite the contents of the flash memory by using the flash programmer, set the microcontroller in the flash memory programming mode.
Page 265 Chapter 7 Flash Memory PG-FP5 V850 FLMD0 FLMD0 FLMD1 FLMD1 PG-FP5 V850 FLMD0 FLMD0 FLMD1 FLMD1 Figure 7-8 Example of connection to flash programmer PG-FP5 Once started in normal operation mode (FLMD0 = 0), FLMD0 pin is used for enabling self-programming. Refer also to 7.3 on page 269. Potential conflicts with on-board signal connections Serial I/O signals If other devices are connected to the serial interface pins in use for flash...
Page 266 Chapter 7 Flash Memory RESET Pay attention in particular if the flash programmer’s RESET signal is connected also to an on-board reset generation circuit. The reset output of the reset generator may ruin the flash programming process and may need to be isolated or disabled.
Page 267 Chapter 7 Flash Memory Selection of the communication mode The communication interface is chosen by applying a specified number of pulses to the FLMD0 pin after reset release. Note that this is handled by the flash programmer. Figure 7-11 on page 267 gives an example how the UART is established for the communication between the flash programmer and the microcontroller.
Page 268 Chapter 7 Flash Memory Communication commands The flash programmer sends commands to the microcontroller. Depending on the commands, the microcontroller returns status information or the requested data. Command Status V850 Data microcontroller flash programmer Figure 7-12 Communication commands exchange The following table lists the flash memory control commands of the microcontroller.
Page 269: Code Flash Self-Programming
By using this flash macro service and a self-programming library, provided by Renesas, the user’s program is able to rewrite the flash memory with data, transferred in advance to the internal RAM or the external memory.
Page 270: Self-Programming Enable
Detailed information how to use the library functions is given in the Application Note: “Self-Programming Library for embedded Single Voltage FLASH” (document no. U16929EE). The up-to-date version of the self-programming library and the above mentioned Application Note can be obtained from http://www.renesas.eu/updates R01UH0469ED0201 Rev. 2.01 User Manual...
Page 271: Secure Self-Programming (Boot Cluster Swapping)
Chapter 7 Flash Memory 7.3.3 Secure self-programming (boot cluster swapping) The V850 flash microcontrollers support a mechanism to swap a cluster of code flash memory blocks, starting from address 0000 0000 , with another cluster of the same size, located immediately above the first one. Caution Boot cluster swapping is only supported, if the variable reset vector remains in its default state 0000 0000...
Page 272 Chapter 7 Flash Memory Secure self- The boot cluster swapping function enables secure self-programming. In case programming the boot code shall be rewritten, the new code can be written to the inactive boot cluster, while the boot_flag remains in its previous state. If rewriting of the boot cluster has been completed successfully, the boot_flag can be inverted, making the new boot code active.
Page 273 Chapter 7 Flash Memory Table 7-10 Relation between boot block and boot swap cluster Number of Boot swap Boot cluster cluster Boot blocks 0000 0000 - 0000 07FF 0000 0000 (2 KB) 0000 1FFF RESV - 0000 0FFF (8 KB) (4 KB) RESV - 0000 17FF (6 KB)
Page 274 Chapter 7 Flash Memory Figure 7-16 on page 274 illustrates an example with following settings: • number of boot blocks: 2 (boot cluster contains 2 blocks), thus the active boot cluster comprises – if boot_flag: blocks 0and 1 – if not(boot_flag): blocks 4 and 5 •...
Page 275: Interrupt Handling During Flash Self-Programming
It is recommended to refer to the application note “Self-Programming” (document nr. U16929EE) for comprehensive information concerning flash self-programming. This document explains also the functions of the self- programming library. The latest version of this document can be loaded via the http://www.renesas.eu/updates R01UH0469ED0201 Rev. 2.01 User Manual...
Page 276: Variable Reset Vector
Chapter 7 Flash Memory 7.4 Variable Reset Vector This microcontroller provides a facility to specify the address of the first user software instruction to be executed after reset release. By default the first user’s instruction to be executed after reset, i.e. the reset vector, is the one stored at address 0000 0000 .
Page 277: Flash Mask Options
Chapter 7 Flash Memory 7.5 Flash Mask Options In the option data area, a block subject to mask options is specified. Make sure to set the option data area corresponding to the following option bytes in the program at address 0000 007A /0000 007B as default data.
Page 278 Chapter 7 Flash Memory Option Byte 0000 0007B 0000 007B SUBCLK PLLO PRSI PLLI1 PLLI0 Table 7-12 Option byte 0000 0007B contents Bit name Function position SUBCLK Clock source at subclock operating mode. 0: SubOSC selection 1: 240 KHz internal oscillator selection PLLO PLL output clock selection.
Page 279: Device Information
Chapter 7 Flash Memory 7.6 Device Information 7.6.1 PRDSELH register - Product selection code register The 16-bit PRDSELH register specifies the RAM start address of the device. Access The register can be read in 16-bit units. Address FFFFFCCA Initial Value Device depending (for details refer to Table 7-13) ×...
Page 280: Chapter 8 Data Protection And Security
Chapter 8 Data Protection and Security 8.1 Overview The microcontroller supports various methods for securing safe (re-)programming of the internal flash memory and protecting of the flash memory data against undesired access, such as illegal read-out or illegal reprogramming. Security functions Security functions provide countermeasures against unexpected failures during reprogramming processes.
Page 281 Chapter 8 Data Protection and Security You can specify your own 10-byte ID code and program it to the internal flash memory by an external flash writer or with the self-programming feature. The ID code is located in the address range 0000 0070 to 0000 0079 The protection levels are summarized in Table 8-1 Table 8-1...
Page 282: Flash Programmer And Self-Programming Protection
Chapter 8 Data Protection and Security 8.3 Flash Programmer and Self-Programming Protection In general, illegal read-out and re-programming of the flash memory contents is possible via the flash writer interface and the self-programming feature. The available flash memory protection methods are as follows. Serial programming It is possible to prohibit any access from external via the serial programming interface,e.g.
Page 283 Chapter 8 Data Protection and Security Read-out protection flag Set this flag to disable the feature that allows reading back the flash memory via external flash programmer interfaces. No flash content can be read out. This flag does not affect the self-programming interface. In self-programming mode read-out of flash memory content is further on possible.
Page 284 Chapter 8 Data Protection and Security Table 8-3 Rewriting operation when erasing/writing is enabled/prohibited Block erasure Write Chip None None Prohibition state Programming mode Boot Boot erasure boot boot area area area area Rewriting All enabled Self-programming – boot area Serial programming enabled Block erase...
Page 285: Chapter 9 Bus Control Unit (Bcu)
Chapter 9 Bus Control Unit (BCU) The Bus Control Unit controls the access to on-chip peripheral I/Os. 9.1 Description The figure below shows a block diagram of the modules that are necessary for accessing on-chip peripherals, external memory, external I/O, or data flash. Control Unit Bridge...
Page 286: Peripheral I/O Area
Chapter 9 Bus Control Unit (BCU) 9.1.1 Peripheral I/O area Two areas of the address range are reserved for the registers of the on-chip peripheral functions. These areas are called “peripheral I/O areas”: Table 9-1 Peripheral I/O areas Name Address range Size Fixed peripheral I/O area 03FF F000...
Page 287 Chapter 9 Bus Control Unit (BCU) Programmable peripheral I/O area (PPA) With this microcontroller, usage and address range of the PPA are not configurable. The PPA extends the fixed peripheral I/O area and assigns an additional 12 KB address space for accessing on-chip peripherals. The figure below illustrates the programmable peripheral I/O area (PPA).
Page 288: Npb Access Timing
Chapter 9 Bus Control Unit (BCU) 9.1.2 NPB access timing All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register (refer to “Registers Access Times”...
Page 289: Bus Properties
Chapter 9 Bus Control Unit (BCU) 9.1.3 Bus properties This section summarizes the properties of the internal bus. Bus access The number of CPU clocks necessary for accessing each resource is as follows: Table 9-2 Number of bus access clocks Internal ROM Internal (32 bits)
Page 290 Chapter 9 Bus Control Unit (BCU) Data space The microcontroller device is provided with an address misalign function. By this function, data of any format (word: 32 bit, halfword: 16 bit, byte: 8 bit) can be placed to any address in memory, even though the address is not aligned to the data format (that means address 4n for words, address 2n for halfwords).
Page 291: Registers
Chapter 9 Bus Control Unit (BCU) 9.2 Registers Access to on-chip peripherals is controlled and operated by registers of the Bus Control Unit (BCU): Table 9-3 Bus and memory control register overview Module Register name Shortcut Address Bus Control Unit (BCU) Peripheral area selection control register FFFF F064 Internal peripheral function wait control register...
Page 292 Chapter 9 Bus Control Unit (BCU) The base address PBA is calculated by PBA = BPC.PA[13:0] x 2 Table 9-5 shows how the addresses of the programmable peripheral area are assembled. The base address PBA is highlighted. Table 9-5 Address range of programmable peripheral area (12 KB) …...
Page 293 Chapter 9 Bus Control Unit (BCU) Table 9-6 VSWC register contents (2/2) Bit name Function position Data wait for internal bus: VSWL2 VSWL1 VSWL0 Number of data wait states 1 CPU system clock (VBCLK) 2 CPU system clock (VBCLK) 2 to 0 VSWL[2:0] 3 CPU system clock (VBCLK) 4 CPU system clock (VBCLK)
Page 294: Chapter 10 16-Bit Timer/Event Counter Aa
Chapter 10 16-Bit Timer/Event Counter AA The V850ES/Fx3-L microcontrollers have following instances of the 16-bit timer/event counter AA: V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names TAA0 to TAA4 Throughout this chapter, the individual instances of Timer AA are identified by “n”, for example, TAAnCTL0 for the TAAn control register 0. The timer is upward compatible to Timer P used in various other devices of the V850E and the V850ES family.
Page 295: Function Outline
Chapter 10 16-Bit Timer/Event Counter AA 10.2 Function Outline • Capture trigger input signal × 2 • External trigger input signal × 1 • Clock select × 8 • External event count input × 1 • Readable counter × 1 •...
Page 296 Chapter 10 16-Bit Timer/Event Counter AA Inter nal b us TAAnCTL0 TAAnIOC2 TAAnOPT1 TAAnCE TAAnCKS2-0 TAAnESS1-0 TAAnETS1-0 TAAnCE TAAnCSE or f /2 or f TAAnCCR0 /4 or f CCR0 b uff er TAAnCNT0 Load INTTAAnCC0 register /128 or f /256 or f Clear TAAnCE Edge...
Page 297 Chapter 10 16-Bit Timer/Event Counter AA TIAA00 TIAA10 Edge Edge TSOUT detector detector RXDD0 from CAN0 TIAA01 TIAA11 Edge Edge detector detector RXDD1 INTTM0EQ0 SELCNT0 SELCNT0 Inter nal bu s Internal bus Figure 10-2 Input circuit of TAA0 (left) and TAA1 (right) TIAA30 Edge detector...
Page 298 Chapter 10 16-Bit Timer/Event Counter AA TAAnCCR0 - TAA capture/compare register 0 The TAAnCCR0 register is a 16-bit register that operates either as capture register or as a compare register. In free-running mode, this register can be used as a capture register or as a compare register specified by bit TAAnOPT0.TAAnCCS0.
Page 299 Chapter 10 16-Bit Timer/Event Counter AA TAAnCCR1 - TAA capture/compare register 1 The TAAnCCR1 register is a 16-bit register that operates either both as a capture register or as a compare register. In free-running mode, this register can be used as a capture register or as a compare register specified by bit TAAnOPT0.TAAnCCS1.
Page 300 Chapter 10 16-Bit Timer/Event Counter AA TAAnCNT - TAA counter read buffer register TAAnCNT register is a read buffer register that can read 16-bit counter values. Access This register can be read only in 16-bit units. Address TAA0CNT: FFFFF59A TAA1CNT: FFFFF5AA TAA2CNT: FFFFF5BA TAA3CNT: FFFFF5CA TAA4CNT: FFFFF5DA...
Page 301: Input Selection Registers
Chapter 10 16-Bit Timer/Event Counter AA 10.4 Input Selection Registers These registers are used to select the inputs to timers. Note In this section, only the bits that refer to Timer AA input selections are described. For further information concerning the other bits please refer to “Clock Generator”...
Page 302 Chapter 10 16-Bit Timer/Event Counter AA SELCNT3 - Selector control register 3 Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F30E Initial Value . This register is initialized by any reset. • V850ES/FG3-L SELCNT3 ISEL32 Note “R”...
Page 303: Control Registers
Chapter 10 16-Bit Timer/Event Counter AA 10.5 Control Registers TAAnCTL0 - TAA control register 0 TAAn control register 0 is an 8-bit register that controls the operation of timer AA. Access This register can be read/written in 8-bit or 1-bit units. Address TAA0CTL0: FFFFF590 TAA1CTL0: FFFFF5A0...
Page 304 Chapter 10 16-Bit Timer/Event Counter AA Table 10-4 TAAnCTL0 register contents (2/2) Bit name Function position 2 to 0 TAAnCKS Selects the count clock of timer TAAn. [2:0] Selection of internal count clock SELCNT2. n = 0, 2, 4, 6 n = 1, 3, 5, 7 ISEL2[4:0] Input...
Page 305 Chapter 10 16-Bit Timer/Event Counter AA TAAnCTL1 - TAA timer control register 1 TAAn control register 1 is an 8-bit register that controls the operation of timer AA. This register can be read and written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 306 Chapter 10 16-Bit Timer/Event Counter AA Table 10-5 TAAnCTL1 register contents (2/2) Bit name Function position 2 to 0 TAAnMD Selects the operation mode of timer TAAn. [2:0] TAAnMD2 TAAnMD1 TAAnMD0 Timer mode selection Interval timer mode External event counter mode External trigger pulse output mode One-shot pulse mode PWM mode...
Page 307 Chapter 10 16-Bit Timer/Event Counter AA TAAnIOC0 - TAA dedicated I/O control register 0 The TAAnIOC0 register is an 8-bit register that controls the timer output. Access This register can be read/written in 8-bit or 1-bit units. Address TAA0IOC0: FFFFF592 TAA1IOC0: FFFFF5A2 TAA2IOC0: FFFFF5B2 TAA3IOC0: FFFFFC2...
Page 308 Chapter 10 16-Bit Timer/Event Counter AA TAAnIOC1 - TAA dedicated I/O control register 1 The TAAnIOC1 register is an 8-bit register that controls the valid edge for the external input signals (TIAAn0 and TIAAn1). Access This register can be read/written in 8-bit or 1-bit units. Address TAA0IOC1: FFFFF593 TAA1IOC1: FFFFF5A3...
Page 309 Chapter 10 16-Bit Timer/Event Counter AA edge specification bits TAAnIOC1.TAAnIS[k:i] of a dedicated capture input may be changed with a single write operation. Consequently proceed as follows (TIAAn0 is used exemplarily): • Change from rising edge to falling edge: – current status is TAAnIOC1.TAAnIS[1:0] = 01 : “rising edge”...
Page 310 Chapter 10 16-Bit Timer/Event Counter AA TAAnIOC2 - TAA I/O control register 2 The TAAnIOC2 register is an 8-bit register that controls the valid edge for external event count input signals (TIAAn0) and external trigger input signal (TIAAn0). Access This register can be read/written in 8-bit or 1-bit units. Address TAA0IOC2: FFFFF594 TAA1IOC2: FFFFF5A4...
Page 311 Chapter 10 16-Bit Timer/Event Counter AA Rewrite during If the edge specification for the external event count input and external trigger timer operation input shall be changed, while the timer remains in operation (TAAnCTL0.TAAnCE = 1), only a single bit of the edge specification bits TAAnIOC2.TAAnEES[k:i] / TAAnIOC2.TAAnETS[k:i] of a dedicated capture input may be changed with a single write operation.
Page 312 Chapter 10 16-Bit Timer/Event Counter AA TAAnIOC4 - TAA I/O control register 4 The TAAnIOC4 register is an 8-bit register that controls the output function of Timer AA. Access This register can be read/written in 8-bit or 1-bit units. Address TAA0IOC4: FFFFF59C TAA1IOC4 FFFFF5AC TAA2IOC4: FFFFF5BC...
Page 313 Chapter 10 16-Bit Timer/Event Counter AA Table 10-9 TAAnIOC4 register contents (2/2) Bit name Function position 1, 0 TAAnOS0 Controls toggling of the timer output TOAAn0. TAAnOR0 TAAnOS0 TAAnOR0 Toggle Control of TOAAn0 Standard operation. Force output level to inactive at next toggle event Force output level to active at next toggle event Freeze current output level.
Page 314 Chapter 10 16-Bit Timer/Event Counter AA TAAnOPT0 - TAA option register 0 The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. Access This register can be read/written in 8-bit or 1-bit units. Address TAA0OPT0: FFFFF595 TAA1OPT0: FFFFF5A5 TAA2OPT0: FFFFF5B5...
Page 315 Chapter 10 16-Bit Timer/Event Counter AA TAAnOPT1 - TAA option register 1 The TAAnOPT1 register is an 8-bit register used to set the 32-bit capture mode by cascading two Timer AA. Access This register can be read/written in 8-bit or 1-bit units. Address TAA1OPT1: FFFFF5AD TAA3OPT1: FFFFF5CD...
Page 316: Operation
Chapter 10 16-Bit Timer/Event Counter AA 10.6 Operation Timer AA can perform the following operations when not in cascade mode: TAAnEST TIAAn0 TAAnEEE Capture/ Compare Operation Software External Count clock Compare Write trigger bit trigger input selection Selection Interval timer mode Invalid Invalid Internal/TIAAn0...
Page 317: Anytime Write And Reload
Chapter 10 16-Bit Timer/Event Counter AA 10.6.1 Anytime write and reload TAAnCCR0 and TAAnCCR1 register rewrite is possible for timer AA during timer operation (TAAnCE = 1), but the write method (any time write, reload) differs depending on the mode. Anytime write When data is written to the TAAnCCRm register during timer operation, it is transferred at any time to CCRm buffer register and used as the 16-bit counter...
Page 318 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 16-bit counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 Figure 10-5 Timing diagram for anytime write D01, D02: Setting values of TAAnCCR0 register (0000 to FFFF D11, D12: Setting values of TAAnCCR1 register (0000 to FFFF The above timing chart illustrates an example of the operation in the interval...
Page 319 Chapter 10 16-Bit Timer/Event Counter AA Reload When data is written to the TAAnCCR0 and TAAnCCR1 registers during timer operation, it is compared with the value of the 16-bit counter via the CCRm buffer register. The values of the TAAnCCR0 and TAAnCCR1 registers can be rewritten when TAAnCE = 1.
Page 320 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 16-bit counter TAAnCCR0 CCR0 buff er 0000H register Note Same value write TAAnCCR1 CCR1 buff er 0000H register Note INTTAAnCC0 INTTAAnCC1 Figure 10-7 Timing chart for reload Note Reload is not performed because TAAnCCR1 register is not written. D01, D02, D03: Setting value of TAAnCCR0 register (0000 to FFFF D11, D12: Setting value of TAAnCCR1 register (0000...
Page 321: Interval Timer Mode (Taanmd2 To Taanmd0 = 000 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.2 Interval timer mode (TAAnMD2 to TAAnMD0 = 000 In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated upon a match between the setting value of the TAAnCCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. The TAAnCCR0 register can be rewritten when TAAnCE = 1, and when a value is set to TAAnCCR0 with a write instruction from the CPU, it is transferred to the CCR0 buffer register through any time write mode, and is compared with the...
Page 322 Chapter 10 16-Bit Timer/Event Counter AA Note The 16-bit counter is not cleared when its value matches the value of TAAnCCR1. TAAnCE = 1 FFFFH 16-bit Note counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn0 TOAAn1 Figure 10-9...
Page 323 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn0 TOAAn1 Figure 10-10 Basic operation timing in interval timer mode when D1 = D2; TAAnCCR0 and TAAnCCR1 are not rewritten, and TOAAn0 and TOAAn1 are output (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 1) D1: Setting value of TAAnCCR0 register (0000...
Page 324 Chapter 10 16-Bit Timer/Event Counter AA When a new value is written to the TAAnCCR0 register that is smaller than the TAAn counter value at that moment, the counter will run to up to FFFF restart counting at 0000 . When the value of the counter then matches the TAAnCCR0 register a compare event will occur..
Page 325: External Event Counter Mode (Taanmd2 To Taanmd0 = 001 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.3 External event counter mode (TAAnMD2 to TAAnMD0 = 001 In the external event count mode, the external event count input (TIAAn0 pin input) is used as a count-up signal. Regardless of the setting of the TAAnCTL1.TAAnEEE bit, 16-bit timer/event counter AA counts up the external event count input (TIAAn0 pin input) when it is set in the external event count mode.
Page 326 Chapter 10 16-Bit Timer/Event Counter AA START Initial setting • Clock selection (TAAnCTL0: TAAnCKS[2:0]) • Set external event count mode Note 1 (TAAnCTL1: TAAnMD[2:0] = 001B) • Set valid edge (TAAnIOC2: TAAnEES[1:0]) • Compare register setting (TAAnCCR0 and TAAnCCR1) (TAAnOPT0: TAAnCCS[1:0]=00) Timer operation enable (TAAnCE = 1) →...
Page 327 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buff er 0000H register TAAnCCR1 CCR1 buff er 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn1 Figure 10-13 Basic Operation Timing in External Event Counter Mode When D1 > D2 > D3; rewrite TAAnCCR0 only; TOAAn1 is not output (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 1) D1, D2: Setting values of TAAnCCR0 register (0000 to FFFF...
Page 328 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buff er 0000H register TAAnCCR1 CCR1 buff er 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn1 Figure 10-14 Basic Operation Timing in External Event Counter Mode When D1 = D2; TAAnCCR0 and TAAnCCR1 are not rewritten, TOAAn1 is output (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 1) D1: Setting value of TAAnCCR0 register (0000...
Page 329: External Trigger Pulse Mode (Taanmd2 To Taanmd0 = 010 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.4 External trigger pulse mode (TAAnMD2 to TAAnMD0 = 010 When TAAnCE = 1 in the external trigger pulse mode, the 16-bit counter stops at FFFF and waits for a trigger condition (input of an external trigger (TIAAn0 pin input) or SW trigger by setting of TAAnEST bit)).
Page 330 Chapter 10 16-Bit Timer/Event Counter AA START • Clock selection (TAAnCTL0: TAAnCKS[2:0], Initial settings TAAnCTL1: TAAnEEE=0) • External trigger pulse output mode setting Note 1 (TAAnCTL1: TAAnMD[2:0] = 010B) • Compare register setting (TAAnCCR0, TAA,CCR1) (TAAnOPT0: TAAnCCS[1:0] = 00) Timer operation enable (TAAnCE = 1) External trigger →...
Page 331 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit Note counter External trigger (TIAAn0 pin) TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register TOAAn1 TOAAn0 Figure 10-16 Basic Operation Timing in External Trigger Pulse Output Mode (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) Note The 16-bit counter is not cleared when it matches the CCR1 buffer register.
Page 332: One-Shot Pulse Mode (Taanmd2 To Taanmd0 = 011 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.5 One-shot pulse mode (TAAnMD2 to TAAnMD0 = 011 When TAAnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the TAAnEST bit (to 1) or a trigger that is input when the edge of the TIAAn0 pin is detected, while holding FFFF .
Page 333 Chapter 10 16-Bit Timer/Event Counter AA STAR T Initial settings • Clock selection (TAAnCTL1: TAAnEEE = 0) (TAAnCTL0: TAAnCKS[2:0]) • One-shot pulse mode setting (TAAnCTL1: TAAnMD[2:0]=011) • Compare register setting (TAAnCCR0, TAAnCCR1) Timer operation enable (TAAnCE = 1) → Transfer of TAAnCCR0, TAAnCCR1 values to CCR0 buffer register and CCR1 buffer register Trigger wait status, 16-bit counter in...
Page 334 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 TAAnEST = 1 FFFFH Note 16-bit counter External trigger (TIAAn0 pin) TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CC1 buffer 0000H register INTTAAnCC0 INTTAAnCC1 TOAAn1 TOAAn0 Figure 10-18 Timing of Basic Operation in One-Shot Pulse Mode (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) Note The 16-bit counter starts counting up when either TAAnEST = 1 is set or the...
Page 335: Pwm Mode (Taanmd2 To Taanmd0 = 100 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.6 PWM mode (TAAnMD2 to TAAnMD0 = 100 In the PWM mode, TAAn capture/compare register 1 (TAAnCCR1) is used to set the duty factor and TAAn capture/compare register 0 (TAAnCCR0) is used to set the cycle. By using these two registers and operating the timer, variable- duty PWM is output.
Page 336 Chapter 10 16-Bit Timer/Event Counter AA START Initial setting • Select clock. (TAAnCTL0: TAAnCKS[2:0]) • Set PWM mode. (TAAnCTL1: TAAnMD[2:0] = 100B) • Set compare register. (TAAnCCR0, TAAnCCR1) Enable timer operation (TAAnCE = 1) → Transfer value of TAAnCCRm register to CCRm buffer register 16-bit counter matches TAAnCCR1.
Page 337 Chapter 10 16-Bit Timer/Event Counter AA START Initial setting • Select clock. (TAAnCTL0: TAAnCKS[2:0]) • Set PWM mode. (TAAnCTL1: TAAnMD[2:0] = 100B) • Set compare register. (TAAnCCR0, TAAnCCR1) Enable timer operation (TAAnCE = 1) → Transfer value of TAAnCCRm register to CCRm buffer register 16-bit counter matches TAAnCCR1.
Page 338 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 CCR0 buffer 0000H register TAAnCCR1 CCR1 buffer 0000H register TOAAn1 TOAAn0 Figure 10-21 Basic Operation Timing in PWM Mode When rewriting TAAnCCR1 value (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) D00: Set value of TAAnCCR0 register (0000 to FFFF D10, D11, D12, D13: Set value of TAAnCCR1 register (0000...
Page 339 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH 16-bit counter TAAnCCR0 Note CCR0 buffer 0000H register Same value write TAAnCCR1 CCR1 buffer 0000H register TOAAn1 TOAAn0 Figure 10-22 Basic Operation Timing in PWM Mode When TAAnCCR0, TAAnCCR1 values are rewritten (TAAnOE0 = 1, TAAnOE1 = 1, TAAnOL0 = 0, TAAnOL1 = 0) Note Reload is not performed because the TAAnCCR1 register was not rewritten.
Page 340: Free-Running Mode (Taanmd2 To Taanmd0 = 101 B )
Chapter 10 16-Bit Timer/Event Counter AA 10.6.7 Free-running mode (TAAnMD2 to TAAnMD0 = 101 In the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the TAAnOPT0.TAAnCCS[1:0] bits. The settings of the TAAnOPT0.TAAnCCS[1:0] bits are valid only in the free- running mode.
Page 341 Chapter 10 16-Bit Timer/Event Counter AA START Initial settings • Clock selection (TAAnCTL0: TAAnCKS[2:0]) Free-running mode setting • (TAAnCTL1: TAAnMD[2:0] = 101B) TAAnCCS[1:0] setting TAAnCCS[1:0] = 11 TAAnCCS[1:0] = 10 TAAnCCS[1:0] = 00 TAAnCCS[1:0] = 01 TIAAn1 edge detection Timer operation enable TIAAn0 edge detection TIAAn0, TIAAn1 edge det.
Page 342 Chapter 10 16-Bit Timer/Event Counter AA When TAAnCCS1 = 0, and TAAnCCS0 = 0 settings (interval function description, compare function) When TAAnCE = 1 is set, the 16-bit counter counts from 0000 to FFFF the free-running count-up operation continues until TAAnCE = 0 is set. In this mode, when a value is written to the TAAnCCR0 and TAAnCCR1 registers, they are transferred to the CCR0 buffer register and the CCR1 buffer register (any time write mode).
Page 343 Chapter 10 16-Bit Timer/Event Counter AA When TAAnCCS1 = 1 and TAAnCCS0 = 1 settings (capture function description) When TAAnCE = 1, the 16-bit counter counts from 0000H to FFFFH and free- running count-up operation continues until TAAnCE = 0 is set. During this time, values are captured by capture trigger operation and are written to the TAAnCCR0 and TAAnCCR1 registers.
Page 344 Chapter 10 16-Bit Timer/Event Counter AA When TAAnCCS1 = 1 and TAAnCCS0 = 0 When TAAnCE = 1 is set, the counter counts from 0000 to FFFF and free- running count-up operation continues until TAAnCE = 0 is set. The TAAnCCR0 register is used as a compare register.
Page 345 Chapter 10 16-Bit Timer/Event Counter AA When TAAnCCS1 = 0 and TAAnCS0 = 1 When TAAnCE is set to 1, the 16-bit counter counts from 0000 to FFFF free-running count-up operation continues until TAAnCE = 0 is set. The TAAnCCR1 register is used as a compare register. An interrupt signal is output upon a match between the value of the 16-bit counter and the setting value of the TAAnCCR1 register as an interval function.
Page 346: Pulse Width Measurement Mode (Taanmd2 To Taanmd0 = 110B)346
Chapter 10 16-Bit Timer/Event Counter AA 10.6.8 Pulse width measurement mode (TAAnMD2 to TAAnMD0 = 110B) In the pulse width measurement mode, free-running count is performed. The value of the 16-bit counter is saved to capture register 0 (TAAnCCR0), or capture register 1 (TAAnCCR1) respectively, and the 16-bit counter is cleared upon edge detection of the TIAAn0 pin, or TIAAn1 respectively.
Page 347 Chapter 10 16-Bit Timer/Event Counter AA Pulse period measurement The pulse period of a signal can be measured in the pulse width measurement mode, when the edge detection of one of the inputs TIAAn0 and TIAAn1 is set either to “rising edge” or “falling edge”. The detection of the other input should be set to “no edge detection”.
Page 348 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH FFFFH 16-bit counter TIAAn0 TAAnCC0 0000H INTTAAnCCR0 cleared by writing 0 from CPU TAAnOVF INTTAAnOV Figure 10-29 Basic Operation Timing of Pulse Period Measurement (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 0) : Values captured to TAAnCCR0 register (0000 to FFFF TIAAn0: Set to detection of rising edge (TAAnIS[1:0] = 01...
Page 349 Chapter 10 16-Bit Timer/Event Counter AA Alternating pulse width and pulse space measurement The pulse width and space of a signal can be measured in the pulse width measurement mode alternating in one capture register, when the edge detection of one of the inputs TIAAn0 and TIAAn1 is set to “both rising and falling edges”.
Page 350 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH FFFFH 16-bit counter TIAAn0 TAAnCCR0 0000H INTTAAnCC0 cleared by writing 0 from CPU TAAnOVF INTTAAnOV Figure 10-31 Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 0) Values captured to TAAnCCR0 register (0000 to FFFF TIAAn0: Set to detection of both rising and falling edges (TAAnIS[1:0] = 11...
Page 351 Chapter 10 16-Bit Timer/Event Counter AA Simultaneous pulse width and pulse space measurement Pulse width and pulse space can be measure simultaneously in the pulse width measurement mode, when the signal is input to both inputs TIAAn0 and TIAAn1, where both inputs detect opposite edges. By detection of the specified edge the resulting values of pulse width or pulse space are captured in the corresponding capture registers (TAAnCCR0, TAAnCCR1), and the timer is cleared and restarts counting.
Page 352 Chapter 10 16-Bit Timer/Event Counter AA TAAnCE = 1 FFFFH FFFFH 16-bit counter Note TIAAn0, TIAAn1 TAAnCCR0 0000H TAAnCCR1 0000H INTTAAnCC0 INTTAAnCC1 cleared by writing 0 TAAnOVF from CPU INTTAAnOV Figure 10-33 Basic Operation Timing of Simultaneous Pulse Width and Pulse Space Measurement (TAAnOE0 = 0, TAAnOE1 = 0, TAAnOL0 = 0, TAAnOL1 = 0) Note...
Page 353: 32-Bit Capture In Free-Running Cascade Mode
Chapter 10 16-Bit Timer/Event Counter AA 10.6.9 32-bit Capture in Free-Running Cascade Mode Two Timer AA (TAA0 in combination with TAA1, or TAA2 in combination with TAA3) can be cascaded to operate as a 32-bit capture timer. In cascade mode, the timer with the lower number (TAA0 or TAA2) is used to control the operation (master timer).
Page 354 Chapter 10 16-Bit Timer/Event Counter AA Note m = 0, 2 n = 1, 3 The 32-bit capture in cascade free-running mode is not available for TAA4. Explanation of signals can be found in Figure 10-1 on page 296. Block diagrams of the input circuits can be found in Figure 10-2 on page 297 and Figure 10-3 on page 297.
Page 355 Chapter 10 16-Bit Timer/Event Counter AA START Initial settings for upper 16-bit Timer (TMAAn) Free-running mode setting • (TAAnCTL1: TAAnMD[2:0] = 101B) Set Capture operation • (TAAnOPT0: TAAnCCS[1:0] = 11B) • Set Cascade operation (TAAnOPT1: TAAnCSE = 1) Initial settings for lower 16-bit Timer (TMAAm) •...
Page 356 Chapter 10 16-Bit Timer/Event Counter AA TAAmCE = 1 FFFFH 16-bit counter TMAAm FFFFH 16-bit counter TMAAn 0002H 0001H 0000H TIAAm0 0000H TAAmCCR0 0000H 0000H 0001H 0002H 0001H TAAnCCR0 TIAAm1 0000H TAAmCCR1 0000H TAAnCCR1 0000H 0002H 0002H INTTAAmCC0 INTTAAmCC1 INTTAAmOV INTTAAnOV TOAAm0 TOAAn0...
Page 357 Chapter 10 16-Bit Timer/Event Counter AA START Disable INTTAAmCCR0/1 Clear INTTAAmCCR0/1 pending flag Read TMAAnCCR0/1 and store as upper 16-bit capture value Read TMAAmCCR0/1 and store as lower 16-bit capture value. INTTAAmCCR0/1 pending? Enable INTTAAmCCR0/1 Figure 10-37 Flow of 32-bit Read (Capture or Counter Value) Disabling the capture interrupt (INTTAAmCCR0/1) is not required if the read sequence is done in the interrupt service routine, as nesting of the same interrupt is not possible.
Page 358: Capture Operation On Delayed Input Clock
Chapter 10 16-Bit Timer/Event Counter AA 10.6.10 Capture operation on delayed input clock If during capture operation the first capture event triggers before the first edge of the count clock occurs a value of FFFF and not a value of 0000 may be stored in the TAAnCCRm registers.
Page 359: Chapter 11 16-Bit Interval Timer M
Chapter 11 16-Bit Interval Timer M The microcontroller includes a 16-bit interval Timer M (TMM0). 11.1 Features Timer M (TMM) supports only a clear & start mode. It does not support a free- running mode. To use Timer M in a manner equivalent to in the free-running mode, set the compare register to FFFF and start the 16-bit counter.
Page 360: Configuration
Chapter 11 16-Bit Interval Timer M 11.2 Configuration TMM consists of the following hardware. Table 11-1 Configuration of TMM Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 control register 0 (TM0CTL0) Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1 TM0CKS0 TM0CMP0...
Page 361: Timer M Registers
Chapter 11 16-Bit Interval Timer M 11.3 Timer M Registers TM0CMP0 - TMM0 compare register 0 The TM0CMP0 register is a 16-bit compare register. Access This register can be read/written in 16-bit units. Address FFFFF694 Initial Value 0000 . This registers is cleared by any reset, or if the internal operation clock is disabled by TM0CTL0.TM0nCE = 0.
Page 362 Chapter 11 16-Bit Interval Timer M Table 11-2 TM0CTL0 register contents (2/2) Bit name Function position 2 to 0 TM0CKS Selects the count clock of timer TM0. [2:0] Selection of internal count clock SELCNT0. TM0CKS2 TM0CKS1 TM0CKS0 PRSI = SEL07 Input ×...
Page 363: Operation
Chapter 11 16-Bit Interval Timer M 11.4 Operation 11.4.1 Interval timer mode In the interval timer mode, a match interrupt signal (INTTM0EQ0) is output when the value of the 16-bit counter matches the value of TMM0 compare register 0 (TM0CMP0). At the same time, the counter is cleared to 0000 starts counting up.
Page 364: Cautions
Chapter 11 16-Bit Interval Timer M 11.4.2 Cautions Clock Generator and clock enable timing Because the second clock is the first pulse of the timer count-up signal when the TM0CE bit is changed from 0 to 1, the timer counts one clock less. Clock for counting TM0CE bit Clock enable signal...
Page 365: Chapter 12 Timer Aa Synchronous Operation
Chapter 12 Timer AA Synchronous Operation Timers AA have a timer synchronized operation function, also named tuned operation mode. Master timer and incorporated slave timers of the corresponding timer group (listed in Table 12-1) start and clock synchronously. When the master timer is cleared, the slave timers are cleared synchronously, too.
Page 366 Chapter 12 Timer AA Synchronous Operation Table 12-4 Timer output functions Free-running mode PWM mode (compare function) Synch Timer channel Synch Synch Synch Synch TOAA00 Toggle Toggle Toggle Toggle TAA0 (master) TOAA01 Toggle Toggle TOAA10 Toggle Toggle Toggle TAA1 (slave) TOAA11 Toggle Toggle...
Page 367: Chapter 13 Watch Timer Functions
Chapter 13 Watch Timer Functions 13.1 Functions The Watch Timer has the following functions. • Watch Timer • Interval timer The Watch Timer and interval timer functions can be used at the same time. Reset Clear 5-bit counter INTWT Note 1 11-bit prescaler Clear INTWTI...
Page 368: Configuration
Chapter 13 Watch Timer Functions Watch Timer The Watch Timer generates interrupt requests (INTWT) at time intervals of 0.5 or 0.25 seconds by using the Sub oscillator (nominal f = 32.768 KHz). Caution When using a clock f obtained by dividing the main clock f by Prescaler3 as the Watch Timer count clock f , set the PRSM0 and PRSCM0 registers...
Page 369: Control Registers
Chapter 13 Watch Timer Functions 13.3 Control Registers The Watch Timer operation mode register (WTM) controls the Watch Timer. Before operating the Watch Timer, set the count clock and the interval time. WTM - Watch Timer operation mode register The WTM register enables or disables the count clock and operation of the Watch Timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 370 Chapter 13 Watch Timer Functions Table 13-3 TAAnCTL1 register contents (2/2) Bit name Function position 7, 3, 2 WTM7, Selects the set time of watch flag. WTM[3:2] WTM7 WTM3 WTM3 Set time of watch flag (0.5 s: f (0.25 s: f (977µs: f (488 µs: f (0.5 s: f...
Page 371: Operation
Chapter 13 Watch Timer Functions 13.4 Operation 13.4.1 Operation as Watch Timer The Watch Timer generates an interrupt request at fixed time intervals. The Watch Timer operates using time intervals of 0.5 or 0.25 seconds with the Sub oscillator (32.768 KHz). The count operation starts when the WTM[1:0] bits are set to 11 .
Page 372: Cautions
Chapter 13 Watch Timer Functions 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) Interval time (T) Figure 13-2 Operation Timing of Watch Timer/Interval Timer Note...
Page 373: Chapter 14 Watchdog Timer 2
Chapter 14 Watchdog Timer 2 14.1 Functions Watchdog Timer 2 has the following functions. • Default-start Watchdog Timer • Reset mode: Reset operation upon overflow of Watchdog Timer 2 (generation of WDT2RES signal) • Non-maskable interrupt request mode: NMI operation upon overflow of Watchdog Timer 2 (generation of INTWDT2 signal) •...
Page 374: Configuration
Chapter 14 Watchdog Timer 2 to f to f INTWDT2 /128 Clock 16-bit Output Selector input counter controller WDT2RES controller (internal reset signal) Clear WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 RUN2 Watchdog timer mode Watchdog timer enable register 2 (WDTM2) register (WDTE) Internal bus Figure 14-1...
Page 375: Control Registers
Chapter 14 Watchdog Timer 2 14.3 Control Registers WDTM2 - Watchdog Timer 2 mode register The WDTM2 register sets the operation mode, operation clock and overflow time of Watchdog Timer 2. Access The register can be read/written in 1-bit and 8-bit units. This register can be read any number of times, but it can be written only once following reset release.
Page 376 Chapter 14 Watchdog Timer 2 Table 14-2 WDTM2 register contents (2/2) Bit name Function position 4 to 0 WDCS2 Selects the count clock of watchdog timer 2. [4:0] Selected clock 240 KHz (typ.) period 17.1 ms 34.1 ms 68.3 ms 136.5 ms 273.1 ms 546.1 ms...
Page 377 Chapter 14 Watchdog Timer 2 WDTE - Watchdog Timer enable register The counter of Watchdog Timer 2 is cleared and counting restarted by writing to the WDTE register. Access The register can be read/written in 8-bit units. Address FFFF F6D1 Initial Value .
Page 378: Watchdog Timer Operation
Chapter 14 Watchdog Timer 2 14.4 Watchdog Timer Operation Watchdog Timer 2 automatically starts in the reset mode after reset is released. The WDTM2 register can be written only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction.
Page 379: Chapter 15 Asynchronous Serial Interface (Uartd)
Chapter 15 Asynchronous Serial Interface (UARTD) The V850ES/Fx3-L microcontrollers have following instances of the Universal Asynchronous Serial Interface UARTD: UARTD V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names UARTD0 to UART1 UARTD0 to UART2 Throughout this chapter, the individual instances of UARTD are identified by “n”, for example, UDnCTL0 for the UARTDn control register 0.
Page 380: Features
Chapter 15 Asynchronous Serial Interface (UARTD) 15.1 Features • Transfer rate: 300 bps to 1500 kbps (using dedicated baud rate generator) • Full-duplex communication: – Internal UARTD receive data register n (UDnRX) – Internal UARTD transmit data register n (UDnTX) •...
Page 381: Configuration
Chapter 15 Asynchronous Serial Interface (UARTD) 15.2 Configuration The block diagram of the UARTDn is shown below. Internal bus INTUDnT INTUDnR INTUDnS Reception unit Transmission unit UDnRX UDnTX Reception Transmit Receive shift controller Transmission shift register register controller Send and receive data comparison Filter Baud rate...
Page 382 Chapter 15 Asynchronous Serial Interface (UARTD) UARTDn control register 0 (UDnCTL0) The UDnCTL0 register is an 8-bit register used to specify the UARTDn operation. UARTDn control register 1 (UDnCTL1) The UDnCTL1 register is an 8-bit register used to select the input clock for the UARTDn.
Page 383 Chapter 15 Asynchronous Serial Interface (UARTD) UARTDn transmit shift register The transmit shift register is a shift register used to convert the parallel data transferred from the UDnTX register into serial data. When 1 byte of data is transferred from the UDnTX register, the shift register data is output from the TXDDn pin.
Page 384: Uartd Registers
Chapter 15 Asynchronous Serial Interface (UARTD) 15.3 UARTD Registers UDnCTL0 - UARTDn control register 0 The UDnCTL0 register is an 8-bit register that controls the UARTDn serial transfer operation. Access This register can be read/written in 8-bit or 1-bit units. Address UD0CTL0: FFFFFA00 UD1CTL0: FFFFFA10...
Page 385 Chapter 15 Asynchronous Serial Interface (UARTD) Table 15-2 UCnCTL0 register contents (2/2) Bit name Function position 3, 2 UDnPS[1:0] Selects the parity function. Parity Selection UCnPS1 UCnPS0 During Transmission During Reception No parity output Reception with no parity 0 parity output Reception with 0 parity Odd parity output Odd parity check...
Page 386 Chapter 15 Asynchronous Serial Interface (UARTD) UDnOPT0 - UARTDn option control register 0 The UDnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTDn register. Access This register can be read/written in 8-bit or 1-bit units. Address UD0OPT0: FFFFFA03 UD1OPT0: FFFFFA13...
Page 387 Chapter 15 Asynchronous Serial Interface (UARTD) Table 15-3 UDnOPT0 register contents (2/3) Bit name Function position UDnSTT SBF Transmission Trigger 0: – 1: SBF transmission trigger • This is the SBF transmittion trigger bit during LIN communication. Note: 1. When this bit is read, always “0” is returned. 2.
Page 388 Chapter 15 Asynchronous Serial Interface (UARTD) Table 15-3 UDnOPT0 register contents (3/3) Bit name Function position UDnRDL Receive Data Level 0: Normal input of transfer data 1: Inverted input of transfer data • The value of the RXDDn pin can be inverted using the UDnRDL bit. Note: Setting of the UDnRDL bit is permitted only when UDnCTL0.UDnPWR = 0 ,or UDnCTL0.UDnRXE = 0.
Page 389 Chapter 15 Asynchronous Serial Interface (UARTD) UDnOPT1 - UARTDn option control register 1 The UDnOPT1 register is an 8-bit register that controls the serial transfer operation of the UARTDn register. Access This register can be read/written in 8-bit or 1-bit units. Address UD0OPT1: FFFFFA05 UD1OPT1: FFFFFA15...
Page 390 Chapter 15 Asynchronous Serial Interface (UARTD) UDnSTR - UARTDn status register The UDnSTR register is an 8-bit register that displays the UARTDn transfer status and reception error contents. Access This register can be read/written in 8-bit or 1-bit units. Though the UDnTSF bit is a read-only bit, the UCnPE, UCnFE, and UCnOVE bits can be read and written.
Page 391 Chapter 15 Asynchronous Serial Interface (UARTD) Table 15-5 UDnSTR register contents (2/3) Bit name Function position UDnSSF SBF receive successful flag 0: When the UDnPWR bit = 1, or when the UDnRXE bit = 0, or when the UDnSRS bit = 0, or when the UDnSSF bit = 0 has been set.
Page 392 Chapter 15 Asynchronous Serial Interface (UARTD) Table 15-5 UDnSTR register contents (3/3) Bit name Function position UDnOVE Overrun Error Flag 0: When UDnCTL0.UDnPWR = 0, or when UDnCTL0.UDnRXE = 0 has been set (reception disabled), or when 0 has been written 1: When data has been received into the UDnRX register and the next receive operation is completed before that receive data has been read.
Page 393 Chapter 15 Asynchronous Serial Interface (UARTD) UDnRX - UARTDn receive data register The UDnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UDnRX register upon completion of reception of 1 byte of data.
Page 394: Interrupt Request Signals
Chapter 15 Asynchronous Serial Interface (UARTD) 15.4 Interrupt Request Signals The following three interrupt request signals are generated from UARTDn. • Reception complete interrupt request signal (INTUDnR) • Transmission enable interrupt request signal (INTUDnT) • Status interrupt request signal (INTUDnS) Reception complete interrupt request signal (INTUDnR) A reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the UDnRX register in the reception...
Page 395: Operation
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5 Operation 15.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in the figures below, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UDnCTL0 register.
Page 396 Chapter 15 Asynchronous Serial Interface (UARTD) (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start Parity Stop Stop (e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H 1 data frame Start Stop...
Page 397: Sbf Transmission/Reception Format
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.2 SBF transmission/reception format The UARTD has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. About LIN LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
Page 398 Chapter 15 Asynchronous Serial Interface (UARTD) Wake-up Synch Check signal break Synch DATA DATA Ident frame field field field field field field LIN-bus Note 2 Data Data Note 5 SF reception ID reception 13 bits transmission transmission Data transmission RXDDn (input) Disable Enable reception...
Page 399: Sbf Transmission
Chapter 15 Asynchronous Serial Interface (UARTD) Check-sum field distinctions are made by software. UARTDn is initialized following CSF reception, and the processing for setting the SBF reception mode again is performed by software. When the UDnSRS bit = 1, the SBF reception can be performed automatically without setting to the SBF reception mode again.
Page 400 Chapter 15 Asynchronous Serial Interface (UARTD) performed. Moreover, data transfer of the UARTDn reception shift register and UDnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to.
Page 401: Data Consistency Check
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.5 Data consistency check The UARTD incorporates a data consistency check function to detect a mismatch between the transmit data written to transmit register (UDnTX) and the data on the bus when the device operates in master mode. The data consistency is checked by comparing the transmit data in the transmit register (UDnTX) and the receive data in the receive register (UDnRX).
Page 402 Chapter 15 Asynchronous Serial Interface (UARTD) (b) Timing example of data consistency error when there is a delay between transmit and receive operation Communication stops UDnTX signal Start Stop 0xD5 UDnRX signal Start Stop 0xAA UDnSTR. Reception UDnTSF internal error detection UDnSTR.
Page 403: Uart Transmission
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.6 UART transmission First, set the transmission enabled status by performing the following procedures. • Specify the operation clock by the UARTD control register 1 (UDnCTL1) • Specify the baud rate by the UARTD control register 2 (UDnCTL2) •...
Page 404: Continuous Transmission Procedure
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.7 Continuous transmission procedure A continuous transmissions becomes enabled by writing the next transmit data after the transmission request interrupt (INTUDnT) is generated . Caution If the value is written to the UDnTX register before the INTUDnT is generated, the transmit data set before is overwritten by the new transmit data.
Page 405 Chapter 15 Asynchronous Serial Interface (UARTD) Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDDn UDnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUDnT UDnTSF Figure 15-6 Continuous transmission operation timing —transmission start Stop UDTTXD Parity...
Page 406: Uart Reception
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.8 UART reception First, set the reception enabled status by the next operations to monitor the RXDDn input and perform the start bit detection. • Specify the operation clock by the UARTD control register 1 (UDnCTL1) •...
Page 407: Reception Errors
Chapter 15 Asynchronous Serial Interface (UARTD) stop bit. A second stop bit is ignored. When reception is completed, read the UDnRX register after the reception complete interrupt request signal (INTUDnR) has been generated, and clear the UDnPWR or UDnRXE bit to 0. If the UDnPWR or UDnRXE bit is cleared to 0 before the INTUDnR signal is generated, the read value of the UDnRX register cannot be guaranteed.
Page 408: Parity Types And Operations
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.10 Parity types and operations Caution When using the LIN function, fix the UDnPS1 and UDnPS0 bits of the UDnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 409: Receive Data Noise Filter
Chapter 15 Asynchronous Serial Interface (UARTD) 15.5.11 Receive data noise filter This filter samples the RXDDn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDDn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 15-10).
Page 410: Baud Rate Generator
Chapter 15 Asynchronous Serial Interface (UARTD) 15.6 Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTDn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 411 Chapter 15 Asynchronous Serial Interface (UARTD) UDnCTL1 - UARTDn control register 1 The UDnCTL1 register is an 8-bit register that selects the UARTDn base clock. Access This register can be read/written in 8-bit units. Address UD0CTL1: FFFFFA01 UD1CTL1: FFFFFA11 UD2CTL1: FFFFFA21 Initial Value .
Page 412 Chapter 15 Asynchronous Serial Interface (UARTD) UDnCTL2 - UARTDn control register 2 The UDnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTDn. Access This register can be read/written in 8-bit units. Address UD0CTL2: FFFFFA02 UD1CTL2: FFFFFA12 UD2CTL2: FFFFFA22...
Page 413 Chapter 15 Asynchronous Serial Interface (UARTD) Baud rate error The baud rate error is obtained by the following equation. Actual baud rate (baud rate with error) --------------------------------------------------------------------------- - × – Error (%) 100 [%] Target baud rate (correct baud rate) Caution The baud rate error during transmission must be within the error tolerance on the receiving side.
Page 414 Chapter 15 Asynchronous Serial Interface (UARTD) Table 15-10 Baud rate generator setting data (normal operation, f = 16 MHz, PRSI = 0) Target Actual UDnCTL1 UDnCTL2 Baud rate error baud rate baud rate [bps] [bps] Selector Divider Divider k 300.48 0.16 600.96 0.16...
Page 415 Chapter 15 Asynchronous Serial Interface (UARTD) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 416 Chapter 15 Asynchronous Serial Interface (UARTD) 21k 2 – × × × × ----- - ----------- - ------------------ - 11 FL – 21k 2 – × × ------------------ - FL 11 Therefore, the minimum baud rate that can be received by the destination is as follows.
Page 417: Cautions
Chapter 15 Asynchronous Serial Interface (UARTD) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 418: Chapter 16 Clocked Serial Interface (Csib)
Chapter 16 Clocked Serial Interface (CSIB) The V850ES/Fx3-L microcontrollers have following instances of the Clocked Serial Interface CSIB: CSIB V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names CSIB0 to CSIB1 Throughout this chapter, the individual instances of CSIB are identified by “n”, for example, CBnCTL0 for the CSIBn control register 0. 16.1 Features •...
Page 419: Configuration
Chapter 16 Clocked Serial Interface (CSIB) 16.2 Configuration The following shows the block diagram of CSIBn. Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR Phase control (n=0) or TOAA01(n=1) or /128(n=2,3) CBnTX SCKBn Phase SO latch SOBn control SIBn Shif t register CBnRX Figure 16-1...
Page 420 Chapter 16 Clocked Serial Interface (CSIB) CBnRX - CSIBn receive data register The CBnRX register is a 16-bit buffer register that holds receive data.The receive operation is started by reading the CBnRX register in the reception enabled status. Access This register can be read-only in 16-bit units. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register.
Page 421: Csib Control Registers
Chapter 16 Clocked Serial Interface (CSIB) 16.3 CSIB Control Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) CBnCTL0 - CSIBn control register 0 CBnCTL0 is a register that controls the CSIBn serial transfer operation.
Page 422 Chapter 16 Clocked Serial Interface (CSIB) Table 16-2 CBnCTL0 register contents (2/2) Bit name Function position CBnSCE Specification of start transfer disable/enable: 0: Communication start trigger invalid 1: Communication start trigger valid This bit controls the behaviour upon a communication start trigger in master/slave single/continuous reception mode.
Page 423 Chapter 16 Clocked Serial Interface (CSIB) CBnCTL1 - CSIBn control register 1 CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. Access This register can be read/written in 8-bit or 1-bit units. Address CB0CTL1: FFFFFD01 CB1CTL1: FFFFFD11 Initial Value .
Page 424 Chapter 16 Clocked Serial Interface (CSIB) Table 16-4 Communication clock setting Input clock Input n = 0 n = 1 n = 2, 3 Mode CKS2 CKS1 CKS0 PRSI = 0 PRSI = 1 PRSI = 0 PRSI = 1 PRSI = 0 PRSI = 1 /128 /128 /128...
Page 425 Chapter 16 Clocked Serial Interface (CSIB) CBnCTL2 - CSIBn control register 2 CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. Access This register can be read/written in 8-bit units. Address CB0CTL2: FFFFFD02 CB1CTL2: FFFFFD12 Initial Value .
Page 426 Chapter 16 Clocked Serial Interface (CSIB) SOBn SIBn Insertion of 0 Figure 16-2 (i) Transfer bit length = 10 bits, MSB first SIBn SOBn Insertion of 0 Figure 16-3 (ii) Transfer bit length = 12 bits, LSB first R01UH0469ED0201 Rev. 2.01 User Manual...
Page 427 Chapter 16 Clocked Serial Interface (CSIB) CBnSTR - CSIBn status register CBnSTR is an 8-bit register that displays the CSIBn status. Access This register can be read/written in 8-bit or 1-bit units. Bit CBnTSF is read-only. Address CB0CTL2: FFFFFD03 CB1CTL2: FFFFFD13 Initial Value .
Page 428: Operation
Chapter 16 Clocked Serial Interface (CSIB) 16.4 Operation 16.4.1 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL[3:0] bits = 0000 CBnTX write (55H) CBnRX read (AAH)
Page 429 Chapter 16 Clocked Serial Interface (CSIB) Note In single transmission mode the INTCBnT signal is generated. When communication is complete, the INTCBnR signal is generated. The processing of steps (3) and (4) can be set simultaneously. Caution In case the CSIB interface is operating in •...
Page 430: Single Transfer Mode (Master Mode, Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) 16.4.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL[3:0] bits = 0000 CBnRX read (55H) CBnRX read (AAH) SCKBn...
Page 431: Continuous Mode (Master Mode, Transmission/Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) 16.4.3 Continuous mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 3 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL[3:0] bits = 0000 CBnTX SCKBn SOBn...
Page 432 Chapter 16 Clocked Serial Interface (CSIB) (7) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception).
Page 433: Continuous Mode (Master Mode, Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) 16.4.4 Continuous mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL[3:0] bits = 0000 SCKBn CBnSCE SIBn...
Page 434: Continuous Reception Mode (Error)
Chapter 16 Clocked Serial Interface (CSIB) 16.4.5 Continuous reception mode (error) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL[3:0] bits = 0000 SCKBn SIBn SOBn INTCBnR...
Page 435: Continuous Mode (Slave Mode, Transmission/Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) 16.4.6 Continuous mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL[3:0] bits = 0000 CBnTX SCKBn SOBn...
Page 436 Chapter 16 Clocked Serial Interface (CSIB) (7) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception). To continue transfer, repeat steps (5) to (7) before (8).
Page 437: Continuous Mode (Slave Mode, Reception Mode)
Chapter 16 Clocked Serial Interface (CSIB) 16.4.7 Continuous mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.3 (2) CBnCTL1 - CSIBn control register 1), transfer data length = 8 bits (CBnCTL2.CBnCL[3:0] bits = 0000 SCKBn SIBn INTCBn R...
Page 438: Clock Timing
Chapter 16 Clocked Serial Interface (CSIB) 16.4.8 Clock timing SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt Note INTCBnR interrupt Note CBnTSF Figure 16-5 (i) Communication type 1 (CBnCKP = 0, CBnDAP = 0) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2...
Page 439 Chapter 16 Clocked Serial Interface (CSIB) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF Figure 16-8 (iv) Communication type 4 (CBnCKP = 1, CBnDAP = 1) Note The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes.
Page 440: Output Pins
Chapter 16 Clocked Serial Interface (CSIB) 16.5 Output Pins SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn pin output Don’t care Don’t care Don’t care Fixed to high level High impedance Other than above...
Page 441: Operation Flow
Chapter 16 Clocked Serial Interface (CSIB) 16.6 Operation Flow Single transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR interrupt request? Transfer data exists? CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting. Caution In the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the CBnTX register is written.
Page 442 Chapter 16 Clocked Serial Interface (CSIB) Single reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR interrupt request? Last data? CBnRX register read CBnSCE bit = 0 (CBnCTL0) CBnRX register read CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 443 Chapter 16 Clocked Serial Interface (CSIB) Single transmission/reception START Note 1 Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR interrupt request? Transmission/reception Reception Transmission Read CBnRX register. Read CBnRX register. Transfer end? Transfer end? Transfer end? Note 2 Note 2 Note 2...
Page 444 Chapter 16 Clocked Serial Interface (CSIB) Continuous transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT interrupt request? Exists data to be transferred next? CBnTSF bit = 0? (CBnSTR) CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 445 Chapter 16 Clocked Serial Interface (CSIB) Continuous reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnRE interrupt INTCBnR interrupt CBnRX register read request? request? Is data being CBnSCE bit = 0 received last data? (CBnCTL0) CBnRX register read CBnSCE bit = 0...
Page 446 Chapter 16 Clocked Serial Interface (CSIB) Continuous transmission/reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register. INTCBnT interrupt request? Last data transferred? Write CBnTX register. INTCBnR interrupt request? CBnRX register read INTCBnRE interrupt request? Data received completely? CBnRX register read CBnOVE bit clear (CBnSTR)
Page 447 Chapter 16 Clocked Serial Interface (CSIB) Caution When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed.
Page 448: Chapter 17 I 2 C Bus (Iic)
Chapter 17 I C Bus (IIC) This microcontroller has one instance of this I C Bus interface. Note Throughout this chapter, the individual instances of this I C Bus interface identified by “n” (IICn, n = 0). 17.1 Features The I C Bus interface provides a synchronous serial interface with the following features: •...
Page 449: Configuration
Chapter 17 C Bus (IIC) 17.3 Configuration The block diagram of the IICn is shown below. Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELnSPIEn WTIMn ACKEn STTn SPTn Slave address Clear Start condition...
Page 450 Chapter 17 C Bus (IIC) A serial bus configuration example is shown below. Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC Address 4 Slave IC Address N Figure 17-2 Serial bus configuration example using I...
Page 451 Chapter 17 C Bus (IIC) IIC shift register n (IICn) The IICn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both transmission and reception. Write and read operations to the IICn register are used to control the actual transmit and receive operations.
Page 452 Chapter 17 C Bus (IIC) (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the SCL0n pin. (12) Start condition generator A start condition is issued when the IICCn.STTn bit is set. However, in the communication reservation disabled status (IICFn.IICRSVn = 1), this request is ignored and the IICFn.STCFn bit is set if the bus is not released (IICFn.IICBSYn = 1).
Page 453: Iic Registers
Chapter 17 C Bus (IIC) 17.4 IIC Registers The I C interfaces are controlled by the following registers. • IIC control register IICCn • IIC status register IICSn • IIC flag register IICFn • IIC clock select register IICCLn • IIC function expansion register IICXn •...
Page 454 Chapter 17 C Bus (IIC) IICCn - IICn control registers The IICCn register enables/stops IICn operations, sets the wait timing, and sets other I C operations. Access This register can be read/written in 8-bit or 1-bit units. Address FFFFD82 Initial Value .
Page 455 Chapter 17 C Bus (IIC) Table 17-2 IICCn register contents (2/4) Bit name Function position WRELn Wait cancellation control: 0: Wait not cancelled 1: Wait cancelled. Caution: When TRCn bit = 1, the WRELn bit is set during the ninth clock and wait is cancelled, after which the TRCn bit is cleared and the SDA0n line is set to high impedance.
Page 456 Chapter 17 C Bus (IIC) Table 17-2 IICCn register contents (3/4) Bit name Function position STTn Start condition trigger: 0: Single transfer mode 1: When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level and then the start condition is generated.
Page 457 Chapter 17 C Bus (IIC) Table 17-2 IICCn register contents (4/4) Bit name Function position SPTn Stop condition trigger: 0: Stop condition is not generated. 1: Stop condition is generated (termination of master device’s transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until it goes to high level.
Page 458 Chapter 17 C Bus (IIC) IICSn - IICn status registers The IICSn register indicates the status of the I Cn bus. Access This register can be read/written in 8-bit or 1-bit units. Address FFFFD86 Initial Value . This register is cleared by any reset. IICSn MSTSn ALDn...
Page 459 Chapter 17 C Bus (IIC) Table 17-3 IICSn register contents (2/3) Bit name Function position EXCn Detection of extension code reception: 0: Extension code was not received. 1: Extension code was received: when the higher four bits of the received address data are either 0000 or 1111 (set at the rising edge of the eighth clock).
Page 460 Chapter 17 C Bus (IIC) Table 17-3 IICSn register contents (3/3) Bit name Function position ACKDn ACK detection: 0: ACK was not detected. 1: ACK was detected: after the SDA0n line is set to low level at the rising edge of the SCL0n pin’s ninth clock Note: The ACKDn bit is cleared •...
Page 461 Chapter 17 C Bus (IIC) IICFn - IICn flag registers The IICFn register sets the I Cn operation mode and indicates the I C bus status. Access This register can be read/written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read-only.
Page 462 Chapter 17 C Bus (IIC) Table 17-4 IICFn register contents (2/2) Bit name Function position IICRSVn Communication reservation function disable bit: 0: Communication reservation enabled. 1: Communication reservation disabled. Caution: Write the IICRSVn bit only when operation is stopped (IICEn = 0). R01UH0469ED0201 Rev.
Page 463 Chapter 17 C Bus (IIC) IICCLn - IICn clock select registers The IICCLn register sets the transfer clock for the I Cn bus. Access This register can be read/written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Address FFFFD84 Initial Value...
Page 464 Chapter 17 C Bus (IIC) IICXn - IICn function expansion registers The IICXn register provides additional transfer data rate configuration in fast- speed mode. Access This register can be read/written in 8-bit or 1-bit units. Address FFFFD85 Initial Value . This register is cleared by any reset. IICXn CLXn Table 17-6...
Page 465 Chapter 17 C Bus (IIC) Transfer rate setting The nominal transfer rate of the I C interface is determined by the root clock source f . The frequency of f can be set to f or f /2 by the PRSI bit of the option byte (007BH).
Page 466 Chapter 17 C Bus (IIC) Table 17-9 PRSI = 0: Transfer rate settings in fast-speed mode (IICCLn.SMCn = 1) Possible Main System IICXn. IICCLn. IICCLn. Selected Transfer (Reference) Clock Range (fxx) OCKSn CLXn CLn1 CLn0 Clock Clock Transfer speed from fxx/2 fxx/48 8 MHz...
Page 467 Chapter 17 C Bus (IIC) Table 17-11 PRSI = 1: Transfer rate settings in fast-speed mode (IICCLn.SMCn = 1) Possible Main System IICXn. IICCLn. IICCLn. Selected Transfer (Reference) Clock Range (fxx) OCKSn CLXn CLn1 CLn0 Clock Clock Transfer speed from fxx/4 fxx/96 16 MHz...
Page 468 Chapter 17 C Bus (IIC) The effective clock frequency appearing at the SCL0n pin calculates to = 1 / (T SCL_eff SCL_nom With a nominal frequency of f = 355.6 KHz (T = 2.812 µs and a SCL_nom SCL_nom rise time of t = 135 ns the effective frequency is f = 339.31 KHz.
Page 469 Chapter 17 C Bus (IIC) IICn - IICn shift registers The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. A wait state is released by writing the IICn register during the wait period, and data transfer is started.
Page 470: I 2 C Bus Mode Functions
Chapter 17 C Bus (IIC) 17.5 I C Bus Mode Functions 17.5.1 Pin functions The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows. SCL0n The SCL0n pin is used for serial clock input and output. It is equipped with an N-ch open-drain output for both master and slave devices.
Page 471: I 2 C Bus Definitions And Control Methods
Chapter 17 C Bus (IIC) 17.6 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. The transfer timing for the “start condition”, "address", "transfer direction specification", "data"...
Page 472: Addresses
Chapter 17 C Bus (IIC) Caution When the IICC0.IICE0 bit of the microcontroller is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICC0.IICE0 bit to 1 when the SCL00 and SDA00 lines are high level.
Page 473: Transfer Direction Specification
Chapter 17 C Bus (IIC) 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 474: Stop Condition
Chapter 17 C Bus (IIC) Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the ACKEn bit to 0 will prevent the ACK signal from being returned.
Page 475: Wait Signal (Wait)
Chapter 17 C Bus (IIC) 17.6.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait status.
Page 476 Chapter 17 C Bus (IIC) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master after output of ninth clock. IICn data write (cancel wait) IICn SCL0n Slave...
Page 477: C Interrupt Request Signals (Intiicn)
Chapter 17 C Bus (IIC) 17.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing. 17.7.1 Master device operation Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 478 Chapter 17 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 479 Chapter 17 C Bus (IIC) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ♦ AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ♦...
Page 480: Slave Device Operation
Chapter 17 C Bus (IIC) 17.7.2 Slave device operation Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ♦ 1: IICSn register = 0001X110B ♦...
Page 481 Chapter 17 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 482 Chapter 17 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 483 Chapter 17 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 484: Slave Device Operation (When Receiving Extension Code)
Chapter 17 C Bus (IIC) 17.7.3 Slave device operation (when receiving extension code) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ♦...
Page 485 Chapter 17 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 486 Chapter 17 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 487 Chapter 17 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦...
Page 488: Operation Without Communication
Chapter 17 C Bus (IIC) 17.7.4 Operation without communication Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 1: IICSn register = 00000001B Remarks 1. : Generated only when SPIEn bit = 1 2.
Page 489 Chapter 17 C Bus (IIC) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ ♦ 1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) ♦...
Page 490: Operation When Arbitration Loss Occurs
Chapter 17 C Bus (IIC) 17.7.6 Operation when arbitration loss occurs When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ 1: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) 2: IICSn register = 00000001B ♦...
Page 491 Chapter 17 C Bus (IIC) When arbitration loss occurs during data transfer <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ♦ ♦ ♦ 1: IICSn register = 10001110B ♦ 2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) 3: IICSn register = 00000001B ♦...
Page 492 Chapter 17 C Bus (IIC) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ♦ ♦ ♦ 1: IICSn register = 1000X110B ♦...
Page 493 Chapter 17 C Bus (IIC) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition When WTIMn bit = 1 STTn bit = 1 ♦ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ♦...
Page 494 Chapter 17 C Bus (IIC) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition When WTIMn bit = 1 SPTn bit = 1 ♦ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ♦...
Page 495: Interrupt Request Signal (Intiicn)
Chapter 17 C Bus (IIC) 17.8 Interrupt Request Signal (INTIICn) The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below. Table 17-12 INTIICn generation timing and wait control WTIMn Bit During Slave Device Operation During Master Device Operation...
Page 496: Address Match Detection Method
Chapter 17 C Bus (IIC) Wait cancellation method The four wait cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • Note By start condition setting (IICCn.STTn bit = 1) •...
Page 497: Extension Code
Chapter 17 C Bus (IIC) 17.11 Extension Code • When the higher 4 bits of the receive address are either 0000 or 1111 , the extension code flag (IICSn.EXCn bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock.
Page 498: Arbitration
Chapter 17 C Bus (IIC) 17.12 Arbitration When several master devices simultaneously output a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs.
Page 499: Wakeup Function
Chapter 17 C Bus (IIC) Table 17-14 Status during arbitration and interrupt request signal generation timing Status During Arbitration Interrupt Request Generation Timing Transmitting address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data...
Page 500: Cautions
Chapter 17 C Bus (IIC) 17.14 Cautions When IICFn.STCENn bit = 0 Immediately after the I Cn operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication.
Page 501: Communication Operations
Chapter 17 C Bus (IIC) 17.15 Communication Operations 17.15.1 Master operation 1 The following flowchart shows the master communication when the communi- cation reservation function is enabled (IICFn.IICRSVn = 0) and the master operation is started after detecting a stop condition (IICFn.STCENn = 0). START IICCLn ←...
Page 502: Master Operation 2
Chapter 17 C Bus (IIC) 17.15.2 Master operation 2 The following flowchart showas the master communication when the communication reservation function is disabled (IICRSVn = 1) and the master operation is started without detecting a stop condition (STCENn = 1). START IICCLn ←...
Page 503: Slave Operation
Chapter 17 C Bus (IIC) 17.15.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 504 Chapter 17 C Bus (IIC) Communication direction flag This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit. The following shows the operation of the main processing block during slave operation. Start I Cn and wait for the communication enabled status.
Page 505 Chapter 17 C Bus (IIC) START IICCLn ← XXH Selection of transfer flag IICFn ← XXH IICFn register setting IICCn ← XXH IICEn = 1 Communication mode? ACKEn = WTIMn = 1 Communication direction flag = 1? WRELn = 1 WTIMn = 1 Communication mode? Data processing...
Page 506 Chapter 17 C Bus (IIC) The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are executed.
Page 507: Timing Of Data Communication
Chapter 17 C Bus (IIC) 17.16 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 508 Chapter 17 C Bus (IIC) Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device ←...
Page 509 Chapter 17 C Bus (IIC) Processing by master device ← ← IICn data IICn data IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n SDA0n Processing by slave device ← ← IICn IICn FFH Note IICn FFH Note...
Page 510 Chapter 17 C Bus (IIC) Processing by master device ← ← IICn data IICn address IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transmit Transfer lines SCL0n SDA0n Stop Start condition condition Processing by slave device ←...
Page 511 Chapter 17 C Bus (IIC) Processing by master device IICn ← address IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn Note INTIICn TRCn Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device IICn ←...
Page 512 Chapter 17 C Bus (IIC) Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note Note WRELn INTIICn TRCn Receive Transfer lines SCL0n SDA0n Processing by slave device IICn ←...
Page 513 Chapter 17 C Bus (IIC) Processing by master device IICn ← FFH Note IICn ← address IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCL0n SDA0n N-ACK Stop Start condition condition Processing by slave device...
Page 514: Chapter 18 Can Controller (Can)
Chapter 18 CAN Controller (CAN) These microcontrollers feature an on-chip n-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The number of CAN channels is given in the table below: V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names CAN0...
Page 515: Features
Chapter 18 CAN Controller (CAN) 18.1 Features • Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) • Standard frame and extended frame transmission/reception enabled • Transfer rate: 1 Mbps max. (if CAN clock input ≥ 8 MHz, for 32 channels) •...
Page 516: Overview Of Functions
Chapter 18 CAN Controller (CAN) 18.1.1 Overview of functions Table 18-1 presents an overview of the CAN Controller functions. Table 18-1 Overview of functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz) Baud rate Data storage Storing messages in the CAN RAM...
Page 517: Configuration
Chapter 18 CAN Controller (CAN) 18.1.2 Configuration The CAN Controller is composed of the following four blocks. • NPB interface This functional block provides an NPB (Peripheral I/O Bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU.
Page 518: Can Protocol
Chapter 18 CAN Controller (CAN) 18.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer.
Page 519: Frame Types
Chapter 18 CAN Controller (CAN) 18.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 18-2 Frame types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 520 Chapter 18 CAN Controller (CAN) Remote frame A remote frame is composed of six fields. Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Figure 18-4 Remote frame Note...
Page 521 Chapter 18 CAN Controller (CAN) (b) Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 522 Chapter 18 CAN Controller (CAN) (c) Control field The control field sets “DLC” as the number of data bytes in the data field (DLC = 0 to 8). (Arbitration field) Control field (Data field) DLC3 DLC2 DLC1 DLC0 (IDE) Figure 18-8 Control field Note D: Dominant = 0...
Page 523 Chapter 18 CAN Controller (CAN) (d) Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. (Control field) Data field (CRC field) Data 0 Data 7 (8 bits) (8 bits)
Page 524 Chapter 18 CAN Controller (CAN) (f) ACK field The ACK field is used to acknowledge normal reception. (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Figure 18-11 ACK field Note D: Dominant = 0 R: Recessive = 1 •...
Page 525 Chapter 18 CAN Controller (CAN) Note Bus idle: State in which the bus is not used by any node. D: Dominant = 0 R: Recessive = 1 – Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field.
Page 526: Error Frame
Chapter 18 CAN Controller (CAN) 18.2.4 Error frame An error frame is output by a node that has detected an error. Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter Error flag 2 Error flag 1...
Page 527: Overload Frame
Chapter 18 CAN Controller (CAN) 18.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node has not completed the reception operation • If a dominant level is detected at the first two bits during intermission •...
Page 528: Functions
Chapter 18 CAN Controller (CAN) 18.3 Functions 18.3.1 Determining bus priority When a node starts transmission: • During bus idle, the node that output data first transmits the data. When more than one node starts transmission: • The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value).
Page 529: Multi Masters
Chapter 18 CAN Controller (CAN) 18.3.3 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 18.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes.
Page 530 Chapter 18 CAN Controller (CAN) Output timing of error frame Table 18-12 Output timing of error frame Type Output timing Bit error, stuff error, Error frame output is started at the timing of the bit following form error, ACK error the detected error.
Page 531 Chapter 18 CAN Controller (CAN) Table 18-13 Types of error states Value of error Indication of Type Operation Operation specific to error state counter CnINFO register Error active Transmission 0 to 95 TECS1, TECS0 = 00 Outputs an active error flag (6 consecutive dominant-level bits) on detection of the error.
Page 532 Chapter 18 CAN Controller (CAN) (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated immediately after error detection. Table 18-14 Error counter Transmission error counter Reception error counter State (TEC7 to TEC0 bits)
Page 533 Chapter 18 CAN Controller (CAN) Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTXDn) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
Page 534 Chapter 18 CAN Controller (CAN) (REC [6:0]) is cleared. In this case, it is required to detect 11 consecutive recessive-level bits 128 times again on the bus. TEC > FFH »bus-off« »bus-off-recovery-sequence« »error-active« »error-passive« BOFF bit in CnINFO register <1> <2>...
Page 535 Chapter 18 CAN Controller (CAN) Initializing CAN module error counter register (CnERC) in initialization mode If it is necessary to initialize the CAN module error counter register (CnERC) and CAN module information register (CnINFO) for debugging or evaluating a program, they can be initialized to the default value by setting the CCERC bit of the CnCTRL register in the initialization mode.
Page 536: Baud Rate Control Function
Chapter 18 CAN Controller (CAN) 18.3.7 Baud rate control function Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer basic system clock (f derived from the CAN module system clock (f ), and divided by 1 to 256 CANMOD (“CnBRP - CANn module bit rate prescaler register”...
Page 537 Chapter 18 CAN Controller (CAN) Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point (SPT) Figure 18-19 Configuration of data bit time defined by CAN specification Table 18-16 Configuration of data bit time defined by CAN specification Notes on setting to conform to CAN Segment name Settable range...
Page 538 Chapter 18 CAN Controller (CAN) Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
Page 539: Connection With Target System
Chapter 18 CAN Controller (CAN) If phase error is positive CAN bus Prop Sync Phase Bit timing Phase segment 1 segment segment segment 2 Sample point If phase error is negative CAN bus Prop Sync Phase Bit timing Phase segment 1 segment segment segment 2...
Page 540: Internal Registers Of Can Controller
Chapter 18 CAN Controller (CAN) 18.5 Internal Registers of CAN Controller 18.5.1 CAN module register and message buffer addresses In this chapter all register and message buffer addresses are defined as address offsets to different base addresses. Since all registers are accessed via the programmable peripheral area the bottom address is defined by the BPC register (refer to “Programmable peripheral I/O area”...
Page 541: Can Controller Configuration
Chapter 18 CAN Controller (CAN) 18.5.2 CAN Controller configuration Table 18-18 List of CAN Controller registers Item Register Name CAN global registers CANn global control register (CnGMCTRL) CANn global clock selection register (CnGMCS) CANn global automatic block transmission control register (CnGMABT) CANn global automatic block transmission delay setting register (CnGMABTD) CAN module registers CANn module mask 1 register (CnMASK1L, CnMASK1H)
Page 542: Can Registers Overview
Chapter 18 CAN Controller (CAN) 18.5.3 CAN registers overview CAN0 module registers The following table lists the address offsets to the CAN0 register base address: C0RBaseAddr = PBA Table 18-19 CAN0 global and module registers Access Address Register name Symbol After reset offset 1-bit...
Page 543 Chapter 18 CAN Controller (CAN) The addresses in the following table denote the address offsets to the CAN #n message buffer base address: CnMBaseAddr, with m being the message buffer number. Example CAN0, message buffer m = 14 = E , byte 6 C0MDATA614 has the address E x 20 + C0MBaseAddr...
Page 544 Chapter 18 CAN Controller (CAN) CAN1 module registers The following table lists the address offsets to the CAN1 register base address: C1RBaseAddr = PBA + 600 Table 18-21 CAN1 global and module registers Access Address Register name Symbol After reset offset 1-bit 8-bit...
Page 545 Chapter 18 CAN Controller (CAN) The addresses in the following table denote the address offsets to the CAN1 message buffer base address: C1MBaseAddr = PBA + 700 Example CAN1, message buffer register m = 23 = 17 , byte 3 C1MDATA323 has the address 17 x 20 + C1MBaseAddr...
Page 546 Chapter 18 CAN Controller (CAN) CAN2 module registers The following table lists the address offsets to the CAN2 register base address: C2RBaseAddr = PBA + C00 Table 18-23 CAN2 global and module registers Access Address Register name Symbol After reset offset 1-bit 8-bit...
Page 547 Chapter 18 CAN Controller (CAN) The addresses in the following table denote the address offsets to the CAN2 message buffer base address: C2MBaseAddr = PBA + D00 Example CAN2, message buffer register m = 30= 1E , byte 6, C2MDATA630 has the address 1E x 20 + C2MBaseAddr...
Page 548: Can3 Register Bit Configuration
Chapter 18 CAN Controller (CAN) 18.5.4 Register bit configuration CAN3 Table 18-25 CAN global register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnGMCTRL (W) Clear GOM Set EFSD Set GOM CnGMCTRL (R)
Page 549 Chapter 18 CAN Controller (CAN) Table 18-26 CAN module register bit configuration (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnLEC (W) CnLEC (R) LEC2 LEC1 LEC0 CnINFO BOFF TECS1 TECS0...
Page 550 Chapter 18 CAN Controller (CAN) Table 18-27 Message buffer register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnMDATA01m Message data (byte 0) Message data (byte 1) CnMDATA0m Message data (byte 0) CnMDATA1m...
Page 551: Bit Set/Clear Function
Chapter 18 CAN Controller (CAN) 18.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 552 Chapter 18 CAN Controller (CAN) Bit status after bit setting/clearing operations Clear Clear Clear Clear Clear Clear Clear Clear Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Set 0 ... 7 Clear 0 ... 7 Status of bit n after bit set/clear operation No change No change...
Page 553: Control Registers
Chapter 18 CAN Controller (CAN) 18.7 Control Registers CnGMCTRL - CANn global control register The CnGMCTRL register is used to control the operation of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 000 Initial Value 0000 .
Page 554 Chapter 18 CAN Controller (CAN) Caution To request forced shut down, the GOM bit must be cleared to 0 in a subsequent, immediately following access after the EFSD bit has been set to 1. If access to another register (including reading the CnGMCTRL register) is executed without clearing the GOM bit immediately after the EFSD bit has been set to 1, the EFSD bit is forcibly cleared to 0, and the forced shut down request is invalid.
Page 555 Chapter 18 CAN Controller (CAN) CnGMCS - CANn global clock selection register The CnGMCS register is used to select the CAN module system clock. Access This register can be read/written in 8-bit units. Address <CnRBaseAddr> + 002 Initial Value . The register is initialized by any reset. CCP3 CCP2 CCP1...
Page 556 Chapter 18 CAN Controller (CAN) CnGMABT - CANn global automatic block transmission control register The CnGMABT register is used to control the automatic block transmission (ABT) operation. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 006 Initial Value 0000 .
Page 557 Chapter 18 CAN Controller (CAN) (b) CnGMABT write ABTCLR ABTTRG Clear ABTTRG Caution Before changing the normal operation mode with ABT to the initialization mode, be sure to set the CnGMABT register to the default value (0000 ) and confirm the CnGMABT register is surely initialized to the default value (0000 Set ABTCLR Automatic block transmission engine clear request bit The automatic block transmission engine is in idle status or under...
Page 558 Chapter 18 CAN Controller (CAN) CnGMABTD - CANn global automatic block transmission delay register The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT.
Page 559 Chapter 18 CAN Controller (CAN) CnMASKaL, CnMASKaH - CANn module mask control register (a = 1 to 4) The CnMASKaL and CnMASKaH registers are used to extend the number of receivable messages into the same message buffer by masking part of the identifier (ID) comparison of a message and invalidating the ID of the masked part.
Page 560 Chapter 18 CAN Controller (CAN) (c) CANn module mask 3 register (CnMASK3L, CnMASK3H) Access These registers can be read/written in 16-bit units. Address CnMASK3L: <CnRBaseAddr> + 048 CnMASK3H: <CnRBaseAddr> + 04A Initial Value Undefined. CnMASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8...
Page 561 Chapter 18 CAN Controller (CAN) CnCTRL - CANn module control register The CnCTRL register is used to control the operation mode of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 050 Initial Value 0000 .
Page 562 Chapter 18 CAN Controller (CAN) CCERC Error counter clear bit The CnERC and CnINFO registers are not cleared in the initialization mode. The CnERC and CnINFO registers are cleared in the initialization mode. Note The CCERC bit is used to clear the CnERC and CnINFO registers for re-initialization or forced recovery from the bus-off state.
Page 563 Chapter 18 CAN Controller (CAN) PSMODE1 PSMODE0 Power save mode No power save mode is selected. CAN sleep mode Setting prohibited CAN stop mode Caution Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored.
Page 564 Chapter 18 CAN Controller (CAN) Set AL Clear AL Setting of AL bit AL bit is cleared to 0. AL bit is set to 1. Other than above AL bit is not changed. Clear VALID Setting of VALID bit VALID bit is not changed. VALID bit is cleared to 0.
Page 565 Chapter 18 CAN Controller (CAN) Access This register can be read/written in 8-bit units. Address <CnRBaseAddr> + 052 Initial Value . The register is initialized by any reset. LEC2 LEC1 LEC0 Note The contents of the CnLEC register are not cleared when the CAN module changes from an operation mode to the initialization mode.
Page 566 Chapter 18 CAN Controller (CAN) CnINFO - CANn module information register The CnINFO register indicates the status of the CAN module. Access This register is read-only in 8-bit units. Address <CnRBaseAddr> + 053 Initial Value . The register is initialized by any reset. BOFF TECS1 TECS0...
Page 567 Chapter 18 CAN Controller (CAN) CnERC - CANn module error counter register The CnERC register indicates the count value of the transmission/reception error counter. Access This register is read-only in 16-bit units. Address <CnRBaseAddr> + 054 Initial Value 0000 . The register is initialized by any reset. REPS REC6 REC5...
Page 568 Chapter 18 CAN Controller (CAN) (10) CnIE - CANn module interrupt enable register The CnIE register is used to enable or disable the interrupts of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 056 Initial Value 0000 .
Page 569 Chapter 18 CAN Controller (CAN) Set CIE2 Clear CIE2 Setting of CIE2 bit CIE2 bit is cleared to 0. CIE2 bit is set to 1. Other than above CIE2 bit is not changed. Set CIE1 Clear CIE1 Setting of CIE1 bit CIE1 bit is cleared to 0.
Page 570 Chapter 18 CAN Controller (CAN) (11) CnINTS - CANn module interrupt status register The CnINTS register indicates the interrupt status of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 058 Initial Value 0000 .
Page 571 Chapter 18 CAN Controller (CAN) (12) CnBRP - CANn module bit rate prescaler register The CnBRP register is used to select the CAN protocol layer basic system clock (f ). The communication baud rate is set to the CnBTR register. Access This register can be read/written in 8-bit units.
Page 572 Chapter 18 CAN Controller (CAN) (13) CnBTR - CANn module bit rate register The CnBTR register is used to control the data bit time of the communication baud rate. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 05C Initial Value 370F .
Page 573 Chapter 18 CAN Controller (CAN) TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited (default value) This setting must not be made when the CnBRP register = 00 Note = 1/f : CAN protocol layer basic system clock) (14) CnLIPT - CANn module last in-pointer register The CnLIPT register indicates the number of the message buffer in which a...
Page 574 Chapter 18 CAN Controller (CAN) (15) CnRGPT - CANn module receive history list register The CnRGPT register is used to read the receive history list. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 060 Initial Value xx02 .
Page 575 Chapter 18 CAN Controller (CAN) (b) CnRGPT write Clear ROVF Clear ROVF Setting of ROVF bit ROVF bit is not changed. ROVF bit is cleared to 0. (16) CnLOPT - CANn module last out-pointer register The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
Page 576 Chapter 18 CAN Controller (CAN) (17) CnTGPT - CANn module transmit history list register The CnTGPT register is used to read the transmit history list. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 064 Initial Value xx02 .
Page 577 Chapter 18 CAN Controller (CAN) (b) CnTGPT write Clear TOVF Clear Setting of TOVF bit TOVF TOVF bit is not changed. TOVF bit is cleared to 0. R01UH0469ED0201 Rev. 2.01 User Manual...
Page 578 Chapter 18 CAN Controller (CAN) (18) CnTS - CANn module time stamp register The CnTS register is used to control the time stamp function. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 066 Initial Value 0000 .
Page 579 Chapter 18 CAN Controller (CAN) (b) CnTS write TSLOCK TSSEL TSEN Clear Clear Clear TSLOCK TSSEL TSEN Clear Setting of TSLOCK bit TSLOCK TSLOCK TSLOCK bit is cleared to 0. TSLOCK bit is set to 1. Other than above TSLOCK bit is not changed. Clear Setting of TSSEL bit TSSEL...
Page 580 Chapter 18 CAN Controller (CAN) (19) CnMDATAxm, CnMDATAzm - CANn message data byte register (x = 0 to 7, z = 01, 23, 45, 67) The CnMDATAxm, CnMDATAzm registers are used to store the data of a transmit/receive message. Access The CnMDATAzm registers can be read/written in 16-bit units.
Page 581 Chapter 18 CAN Controller (CAN) CnMDATA45m MDATA4515 MDATA4514 MDATA4513 MDATA4512 MDATA4511 MDATA4510 MDATA459 MDATA458 MDATA457 MDATA456 MDATA455 MDATA454 MDATA453 MDATA452 MDATA451 MDATA450 CnMDATA4m MDATA47 MDATA46 MDATA45 MDATA44 MDATA43 MDATA42 MDATA41 MDATA40 CnMDATA5m MDATA57 MDATA56 MDATA55 MDATA54 MDATA53 MDATA52 MDATA51 MDATA50 CnMDATA67m MDATA6715 MDATA6714 MDATA6713 MDATA6712 MDATA6711 MDATA6710 MDATA679...
Page 582 Chapter 18 CAN Controller (CAN) (20) CnMDLCm - CANn message data length register m The CnMDLCm register is used to set the number of bytes of the data field of a message buffer. Access This register can be read/written in 8-bit units. Address Refer to “CAN registers overview”...
Page 583 Chapter 18 CAN Controller (CAN) (21) CnMCONFm - CANn message configuration register m The CnMCONFm register is used to specify the type of the message buffer and to set a mask. Access This register can be read/written in 8-bit units. Address Refer to “CAN registers overview”...
Page 584 Chapter 18 CAN Controller (CAN) Message buffer assignment bit Message buffer not used. Message buffer used. Caution Be sure to write 0 to bits 2 and 1. R01UH0469ED0201 Rev. 2.01 User Manual...
Page 585 Chapter 18 CAN Controller (CAN) (22) CnMIDLm, CnMIDHm - CANn message ID register m The CnMIDLm and CnMIDHm registers are used to set an identifier (ID). Access These registers can be read/written in 16-bit units. Address Refer to “CAN registers overview” on page 542. Initial Value Undefined.
Page 586 Chapter 18 CAN Controller (CAN) (23) CnMCTRLm - CANn message control register m The CnMCTRLm register is used to control the operation of the message buffer. Access This register can be read/written in 16-bit units. Address Refer to “CAN registers overview” on page 542. Initial Value 00x0 0000 0000 0000 .
Page 587 Chapter 18 CAN Controller (CAN) Message buffer transmission request bit No message frame transmitting request that is pending or being transmitted is in the message buffer. The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Message buffer ready bit The message buffer can be written by software.
Page 588 Chapter 18 CAN Controller (CAN) Set RDY Clear RDY Setting of RDY bit RDY bit is cleared to 0. RDY bit is set to 1. Other than above RDY bit is not changed. Caution Set IE bit and RDY bit always separately. Do not set the DN bit to 1 by software.
Page 589: Can Controller Initialization
Chapter 18 CAN Controller (CAN) 18.8 CAN Controller Initialization 18.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the CnGMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 590 Chapter 18 CAN Controller (CAN) the transmit message buffer, set a transmission request using the procedure described below. When setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. Redefinition completed Execute transmission?
Page 591: Transition From Initialization Mode To Operation Mode
Chapter 18 CAN Controller (CAN) 18.8.4 Transition from initialization mode to operation mode The CAN module can be switched to the following operation modes. • Normal operation mode • Normal operation mode with ABT • Receive-only mode • Single-shot mode •...
Page 592: Resetting Error Counter Cnerc Of Can Module
Chapter 18 CAN Controller (CAN) 18.8.5 Resetting error counter CnERC of CAN module If it is necessary to reset the CAN module error counter CnERC and CAN module information register CnINFO when re-initialization or forced recovery from the bus-off status is made, set the CCERC bit of the CnCTRL register to 1 in the initialization mode.
Page 593: Message Reception
Chapter 18 CAN Controller (CAN) 18.9 Message Reception 18.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process).
Page 594: Receive Data Read
Chapter 18 CAN Controller (CAN) 18.9.2 Receive data read To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 18-49 on page 641 to Figure 18-52 on page 644. During message reception, the CAN module sets DN of the CnMCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process.
Page 595: Receive History List Function
Chapter 18 CAN Controller (CAN) 18.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding CnLIPT register and the receive history list get pointer (RGPT) with the corresponding CnRGPT register.
Page 596 Chapter 18 CAN Controller (CAN) As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without reading the RHL by the host processor, complete sequence of receptions can not be recovered. Figure 18-29 Receive history list R01UH0469ED0201 Rev.
Page 597: Mask Function
Chapter 18 CAN Controller (CAN) 18.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer.
Page 598: Multi Buffer Receive Block Function
Chapter 18 CAN Controller (CAN) 18.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.
Page 599: Remote Frame Reception
Chapter 18 CAN Controller (CAN) 18.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. •...
Page 600: Message Transmission
Chapter 18 CAN Controller (CAN) 18.10 Message Transmission 18.10.1 Message transmission A message buffer with its TRQ bit set to 1 participates in the search for the most high-prioritized message when the following conditions are fulfilled. This behavior is valid for all operational modes. •...
Page 601 Chapter 18 CAN Controller (CAN) Priority Conditions Description 1 (high) Value of first 11 bits of ID The message frame with the lowest value represented by the first 11 [ID28 to ID18]: bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11-bit standard ID has a higher priority than a message frame with a 29-bit extended ID.
Page 602: Transmit History List Function
Chapter 18 CAN Controller (CAN) 18.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding CnLOPT register, and the transmit history list get pointer (TGPT) with the corresponding CnTGPT register.
Page 603 Chapter 18 CAN Controller (CAN) Caution If the history list is in the overflow condition (TOVF is set), reading the history list contents is still possible, until the history list is empty (indicated by THPM flag set). Nevertheless, the history list remains in the overflow condition, until TOVF is cleared by software.
Page 604: Automatic Block Transmission (Abt)
Chapter 18 CAN Controller (CAN) 18.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).
Page 605 Chapter 18 CAN Controller (CAN) held pending and the transmission ID of the message buffers other than those used by the ABT function. Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL). Caution Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT operation at buffer No.0.
Page 606: Transmission Abort Process
Chapter 18 CAN Controller (CAN) 18.10.4 Transmission abort process Transmission abort process except for in normal operation mode with automatic block transmission (ABT) The user can clear the TRQ bit of the CnMCTRLm register to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful.
Page 607: Remote Frame Transmission
Chapter 18 CAN Controller (CAN) Status of TRQ of Abort after successful transmission Abort after erroneous transmission ABT message buffer Set (1) Next message buffer in the ABT area Same message buffer in the ABT area Cleared (0) Next message buffer in the ABT area Next message buffer in the ABT area The above resumption operation can be performed only if a message buffer ready for ABT exists in the ABT area.
Page 608: Power Saving Modes
Chapter 18 CAN Controller (CAN) 18.11 Power Saving Modes 18.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN Controller to stand-by mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes.
Page 609 Chapter 18 CAN Controller (CAN) transmitting or receiving) when the CAN sleep mode is requested in one of the operation modes, immediate transition to the CAN sleep mode is not possible. In this case, the CAN sleep mode transition request has to be held pending until the CAN bus state becomes bus idle (the 4th bit in the interframe space is recessive).
Page 610 Chapter 18 CAN Controller (CAN) Releasing CAN sleep mode The CAN sleep mode is released by the following events: • When the CPU writes 00 to the PSMODE[1:0] bits of the CnCTRL register • A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to dominant) Caution Even if the falling edge belongs to the SOF of a receive message, this...
Page 611: Can Stop Mode
Chapter 18 CAN Controller (CAN) 18.11.2 CAN stop mode The CAN stop mode can be used to set the CAN Controller to stand-by mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.
Page 612: Example Of Using Power Saving Modes
Chapter 18 CAN Controller (CAN) 18.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.
Page 613: Interrupt Function
Chapter 18 CAN Controller (CAN) 18.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 614: Diagnosis Functions And Special Operational Modes
Chapter 18 CAN Controller (CAN) 18.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 18.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
Page 615: Single-Shot Mode
Chapter 18 CAN Controller (CAN) node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus. Caution If only two CAN nodes are connected to the CAN bus and one of them is operating in the receive-only mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will transmit an active error flag, and repeat transmitting a message frame.
Page 616: Self-Test Mode
Chapter 18 CAN Controller (CAN) The single-shot mode can be used when emulating time-triggered communication methods (e.g., TTCAN level 1). Caution The AL bit is only valid in single-shot mode. It does not influence the operation of re-transmission upon arbitration loss in the other operation modes. 18.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or...
Page 617: Receive/Transmit Operation In Each Operation Mode
Chapter 18 CAN Controller (CAN) 18.13.4 Receive/transmit operation in each operation mode The following table shows outline of the receive/transmit operation in each operation mode. Table 18-30 Outline of the receive/transmit in each operation mode Transmis- Transmis- Automatic sion of Transmis- sion of Store data to...
Page 618: Time Stamp Function
Chapter 18 CAN Controller (CAN) 18.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies).
Page 619: Baud Rate Settings
Chapter 18 CAN Controller (CAN) Caution The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame.
Page 620 Chapter 18 CAN Controller (CAN) Table 18-31 shows the combinations of bit rates that satisfy the above conditions. Table 18-31 Settable bit rate combinations (1/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length...
Page 621 Chapter 18 CAN Controller (CAN) Table 18-31 Settable bit rate combinations (2/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1001 64.7 1010 70.6 1011...
Page 622 Chapter 18 CAN Controller (CAN) Table 18-31 Settable bit rate combinations (3/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1000 83.3 1001 91.7 0101...
Page 623: Representative Examples Of Baud Rate Settings
Chapter 18 CAN Controller (CAN) 18.15.2 Representative examples of baud rate settings Table 18-32 and Table 18-33 show representative examples of baud rate settings. Table 18-32 Representative examples of baud rate settings = 8 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud...
Page 624 Chapter 18 CAN Controller (CAN) Table 18-32 Representative examples of baud rate settings = 8 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 625 Chapter 18 CAN Controller (CAN) Table 18-33 Representative examples of baud rate settings = 16 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 626 Chapter 18 CAN Controller (CAN) Table 18-33 Representative examples of baud rate settings = 16 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 627: Operation Of Can Controller
Chapter 18 CAN Controller (CAN) 18.16 Operation of CAN Controller The processing procedure for showing in this chapter is recommended processing procedure to operate CAN controller. Develop the program referring to recommended processing procedure in this chapter. START CnGMCS register. CnGMCTRL register (set GOM bit = 1) CnBRP register,...
Page 628 Chapter 18 CAN Controller (CAN) START START Clear Clear OPMODE OPMODE INIT mode? INIT mode? CnBRP register, CnBRP register, CnBTR register CnBTR register CnIE register CnIE register CnMASK register CnMASK register Initialize message buffers Initialize message buffers CnERC and CnINFO CnERC and CnINFO register clear? register clear?
Page 629 Chapter 18 CAN Controller (CAN) START START RDY = 1? RDY = 1? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? CnMCONFm register CnMCONFm register CnMIDHm register, CnMIDHm register, CnMIDLm register CnMIDLm register Transmit message buffer? Transmit message buffer? CnMDLCm register CnMDLCm register...
Page 630 Chapter 18 CAN Controller (CAN) Figure 18-38 shows the processing for a receive message buffer (MT[2:0] bits of CnMCONFm register = 001 to 101 START Clear VALID bit RDY = 1? Clear RDY bit RDY = 0? RSTAT = 0 or VALID = 1? Note1 Wait for 4 CAN data bits...
Page 631 Chapter 18 CAN Controller (CAN) Figure 18-39 shows the processing for a transmit message buffer during transmission (MT[2:0] bits of CnMCONFm register = 000 START START Transmit abort process Transmit abort process Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame...
Page 632 Chapter 18 CAN Controller (CAN) Figure 18-40 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000 START START TRQ = 0? TRQ = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame Remote frame...
Page 633 Chapter 18 CAN Controller (CAN) Figure 18-41 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000 START START ABTTRG = 0? ABTTRG = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Set CnMDATAxm register Set CnMDATAxm register Set CnMDLCm register...
Page 634 Chapter 18 CAN Controller (CAN) START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnLOPT register Read CnLOPT register Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame Remote frame Remote frame Data frame or remote frame?
Page 635 Chapter 18 CAN Controller (CAN) START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnTGPT register Read CnTGPT register TOVF = 1? TOVF = 1? Clear TOVF bit Clear TOVF bit Clear RDY bit Clear RDY bit RDY = 0? RDY = 0?
Page 636 Chapter 18 CAN Controller (CAN) START START CINTS0 = 1? CINTS0 = 1? Clear CINTS0 bit Clear CINTS0 bit Read CnTGPT register Read CnTGPT register TOVF = 1? TOVF = 1? Clear TOVF bit Clear TOVF bit Clear RDY bit Clear RDY bit RDY = 0? RDY = 0?
Page 637 Chapter 18 CAN Controller (CAN) START START Clear TRQ bit Clear TRQ bit Wait for 11 CAN data bits Wait for 11 CAN data bits Note Note TSTAT = 0? TSTAT = 0? Read CnLOPT register Read CnLOPT register Message buffer to Message buffer to be aborted matches CnLOPT be aborted matches CnLOPT...
Page 638 Chapter 18 CAN Controller (CAN) START START Clear ABTTRG bit Clear ABTTRG bit ABTTRG = 0? ABTTRG = 0? Clear TRQ bit Clear TRQ bit Wait for 11 CAN data bits Wait for 11 CAN data bits TSTAT = 0? TSTAT = 0? Read CnLOPT register Read CnLOPT register...
Page 639 Chapter 18 CAN Controller (CAN) Figure 18-47 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START START TSTAT = 0? TSTAT = 0? Clear ABTTRG bit Clear ABTTRG bit ABTTRG = 0? ABTTRG = 0?
Page 640 Chapter 18 CAN Controller (CAN) Figure 18-48 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START START Clear TRQ bit of message buffer Clear TRQ bit of message buffer undergoing transmission undergoing transmission Clear ABTTRG bit...
Page 641 Chapter 18 CAN Controller (CAN) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnLIPT register Read CnLIPT register Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm, Read CnMDATAxm, CnMDLCm, CnMIDLm, and CnMIDHm CnMIDLm, and CnMIDHm registers registers DN = 0...
Page 642 Chapter 18 CAN Controller (CAN) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? RHPM = 1? Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm,...
Page 643 Chapter 18 CAN Controller (CAN) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? RHPM = 1? Read CnMDATAxm, CnMDLCm, Read CnMDATAxm, CnMDLCm, CnMIDLm, CnMIDHm registers...
Page 644 Chapter 18 CAN Controller (CAN) START START CINTS1 = 1? CINTS1 = 1? Clear CINTS1 bit Clear CINTS1 bit Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm,...
Page 645 Chapter 18 CAN Controller (CAN) START (when PSMODE[1:0] = 00B) START (when PSMODE[1:0] = 00B) Set PSMODE0 bit Set PSMODE0 bit PSMODE0 = 1? PSMODE0 = 1? CAN sleep mode CAN sleep mode CAN sleep mode Set PSMODE1 bit Set PSMODE1 bit PSMODE1 = 1? PSMODE1 = 1? Request CAN sleep...
Page 646 Chapter 18 CAN Controller (CAN) START CAN stop mode Clear PSMODE1 bit CAN sleep mode Releasing CAN sleep mode by CAN bus activity Releasing CAN sleep mode by user Dominant edge on CAN detected Clear PSMODE0 bit Clear PSMODE0 bit Clear PSMODE0 bit Clear CINTS5 bit Figure 18-54...
Page 647 Chapter 18 CAN Controller (CAN) START BOFF = 1? Note Clear all TRQ bits Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? Set CnCTRL register Set CCERC bit (Set OPMODE) Set CnCTRL register Wait for recovery (Set OPMODE)
Page 648 Chapter 18 CAN Controller (CAN) START BOFF = 1? Clear ABTTRG bit Note Clear all TRQ bits Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? Set CnCTRL register Set CnCTRL register Set CCERC bit (Set OPMODE) (Set OPMODE)
Page 649 Chapter 18 CAN Controller (CAN) START START INIT mode Clear GOM bit GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Figure 18-57 Normal shutdown process START Set EFSD bit Must be a subsequent write Clear GOM bit Clear GOM bit GOM = 0? GOM = 0?
Page 650 Chapter 18 CAN Controller (CAN) START Error interrupt CINTS2 = 1? Check CAN module state (read CnINFO register) Clear CINTS2 bit CINTS3 = 1? CINTS3 = 1? Check CAN protocol error state (read CnLEC register) Clear CINTS3 bit CINTS4 = 1? Clear CINTS4 bit Figure 18-59 Error handling...
Page 651 Chapter 18 CAN Controller (CAN) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode CINTS5 bit = 1? MBON bit = 0? Set CPU standby mode.
Page 652 Chapter 18 CAN Controller (CAN) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 PSMODE1 bit = 1? CAN stop mode...
Page 653: Chapter 19 A/D Converter (Adc)
Chapter 19 A/D Converter (ADC) The V850ES/Fx3-L microcontrollers have following instances of the A/D Converter ADC: V850ES/FE3-L V850ES/FF3-L V850ES/FG3-L Instances Names ADA0 ADA0 ADA0 Channels Throughout this chapter, the individual instances of ADC are identified by “n”, for example, ADAnM0 for the ADAn mode register 0. Throughout this chapter, the individual channels of each ADC instance are identified by “m”, for example, ADAnCRm for the conversion result register m of ADAn.
Page 654 Chapter 19 A/D Converter (ADC) The block diagram of the A/D Converter is shown below. REFn ADAnPS bit Sample & hold circuit Analog input pins ADAnCE bit Voltage comparator INTAD ADAnPFE bit ADAnPFC bit Control Circuit INTTAA2CC0 INTTAA2CC1 ADAnCR0 Controller ADAnCR1 Edge ADTRG...
Page 655: Configuration
Chapter 19 A/D Converter (ADC) 19.2 Configuration The A/D Converter includes the following hardware. Table 19-1 Configuration of A/D Converter Item Configuration Analog inputs ANI0 to ANIm / ANI100 to ANI1m pins Registers Successive approximation register (SAR) A/D conversion result registers ADAnCRm, ADAnCRmH AVREF A/D conversion diagnostic registers ADAnCRDD, ADAnCRDDH AVSS A/D conversion diagnostic registers ADAnCRSS, ADAnCRSSH ADC power-fail compare mode register ADAnPFM...
Page 656 Chapter 19 A/D Converter (ADC) Sample & hold circuit The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the Voltage Comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion.
Page 657: Adc Registers
Chapter 19 A/D Converter (ADC) 19.3 ADC Registers The A/D Converter is controlled by the following registers: • A/D Converter mode registers 0, 1, 2 (ADAnM0, ADAnM1, ADAnM2) • A/D Converter channel specification register 0 (ADAnS) • Power-fail compare mode register (ADAnPFM) The following registers are also used: •...
Page 658 Chapter 19 A/D Converter (ADC) Table 19-2 ADAnM0 register contents (2/2) Bit name Function position 3, 2 ADAnETS1, Specifies the valid edege of external trigger input (ADTRG pin). ADAnETS0 ADAnETS1 ADAnETS0 External trigger nput (ADTRG pin) ivalid edge Continuous select mode Continuous scan mode One-shot select mode One-shot scan mode...
Page 659 Chapter 19 A/D Converter (ADC) ADAnM1 - ADC mode register 1 The ADAnM1 register is an 8-bit register that controls the conversion time specification. Access This register can be read/written in 8-bit or 1-bit units. Address FFFFF201 Initial Value . This register is cleared by any reset. ADA0M1 ADAnFR3 ADAnFR2...
Page 660 Chapter 19 A/D Converter (ADC) Table 19-4 Conversion time settings conversion 20 MHz 16 MHz 10 MHz 4 MHz time 32/f prohibited prohibited 3.20 µs 8.00 µs 64/f 3.20 µs 4.00 µs 6.40 µs 16.00 µs 96/f 4.80 µs 6.00 µs 9.60 µs prohibited 128/f...
Page 661 Chapter 19 A/D Converter (ADC) ADAnM2 - ADC mode register 2 The ADAnM2 register specifies the hardware trigger mode. Access This register can be read/written in 8-bit or 1-bit units. Address FFFFF203 Initial Value . This register is cleared by any reset. ADA0M2 ADAnDIAG ADAnDISC ADAnTMD1 ADAnTMD0...
Page 662 Chapter 19 A/D Converter (ADC) ADAnS - ADC channel specification register The ADAnS register specifies the pin that inputs the analog voltage to be converted into a digital signal. Access This register can be read/written in 8-bit or 1-bit units. Address FFFFF202 Initial Value...
Page 663 Chapter 19 A/D Converter (ADC) ADAnCRm, ADAnCRmH - ADC conversion result registers The ADAnCRm and ADAnCRmH registers store the A/D conversion results. Access These registers are read-only in 16-bit or 8-bit units. When 16-bit access is performed, the ADAnCRm register is specified, and when 8 bit access is performed, the ADAnCRmH register holding the upper 8 bits of the conversion result is specified When reading the 10-bit data of the A/D conversion results from the...
Page 664 Chapter 19 A/D Converter (ADC) The relationship between the analog voltage input to the analog input pins ANInmm and the A/D conversion result (of A/D conversion result register n ADAnCRm is as follows: ⋅ ------------------- - 1024 ADnCRm REFn REF0 REFn ⋅...
Page 665 Chapter 19 A/D Converter (ADC) ADAnCRDD, ADAnCRDDH - AV A/D conversion diagnostic registers The ADAnCRDD and ADAnCRDDH registers store the result of the AV REFn conversion if the ADC diagnostic function is enabled (ADAnM2.ADAnDIAG = 1). Access These registers are read-only in 16-bit or 8-bit units. When 16-bit access is performed, the ADAnCRDD register is specified, and when 8 bit access is performed, the ADAnCRDDH register holding the upper 8 bits of the conversion result is specified...
Page 666 Chapter 19 A/D Converter (ADC) ADAnCRSS, ADAnCRSSH - AV A/D conversion diagnostic registers The ADAnCRSS and ADAnCRSSH registers store the result of the AV conversion if the ADC diagnostic function is enabled (ADAnM2.ADAnDIAG = 1). Access These registers are read-only in 16-bit or 8-bit units. When 16-bit access is performed, the ADAnCRSS register is specified, and when 8 bit access is performed, the ADAnCRSSH register holding the upper 8 bits of the conversion result is specified...
Page 667 Chapter 19 A/D Converter (ADC) ADAnPFM - ADC power-fail compare mode register The ADAnPFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Access This register can be read/written in 8-bit or 1-bit units.
Page 668 Chapter 19 A/D Converter (ADC) ADAnPFT - ADC power-fail compare threshold value register The ADAnPFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Address FFFFF205 Initial value...
Page 669: Operation
Chapter 19 A/D Converter (ADC) 19.4 Operation 19.4.1 Basic operation 1. Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADAnM0, ADAnM1, ADAnM2, and ADAnS registers. Set the ADAnM0.ADAnPS bit to supply power to the analog circuitry of the ADC.
Page 670: Trigger Mode
Chapter 19 A/D Converter (ADC) 19.4.2 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
Page 671 Chapter 19 A/D Converter (ADC) Timer trigger mode In this mode, converting the signal of the analog input pin ANInmm, specified by the ADAnS register, is started by any of the timer output signals INTTAA2CC0, INTTAA2CC1 or TQTADT0. The timer output signal is selected by the ADAnM2.ADAnTMD[1:0] bits, and conversion is started at the rising edge of the timer output signal.
Page 672: Operation Modes
Chapter 19 A/D Converter (ADC) 19.4.3 Operation modes Four operation modes are available as the modes in which to set the ANInmm pins: continuous select mode, continuous scan mode, one-shot select mode and one-shot scan mode. The operation mode is selected by the ADAnM0.ADAnMD[1:0] bits. Continuous select mode In this mode, the voltage of one analog input pin selected by the ADAnS register is continuously converted into a digital value.
Page 673 Chapter 19 A/D Converter (ADC) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion ANI0) (ANI1) (ANI2) (ANI3) (ANI0) ANI1) (ANI2) Data 1...
Page 674 Chapter 19 A/D Converter (ADC) One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
Page 675 Chapter 19 A/D Converter (ADC) One-shot scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADAnS register, and their values are converted into digital values. The result of each conversion is stored in the ADAnCRm register corresponding to the analog input pin.
Page 676 Chapter 19 A/D Converter (ADC) Diagnostic mode When activating the diagnostic mode (ADAnM2.ADADIAG = 1) the voltage at the AV pin and the AV pin are sampled after conversion of the specified REFn ANInm range is finished. The resulting values can be found in the ADAnCRDD, ADAnCRDDH, ADAnCRSS and ADAnCRSSH registers.
Page 677: Power-Fail Compare Mode
Chapter 19 A/D Converter (ADC) 19.4.4 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD/INTAD1) can be controlled as follows by the ADAnPFM and ADAnPFT registers. • When the ADAnPFE bit = 0, the INTAD/INTAD1 signal is generated each time conversion is completed (normal use of the A/D Converter).
Page 678 Chapter 19 A/D Converter (ADC) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADAnS register is compared with the set value of the ADAnPFT register. If the result of power-fail comparison matches the condition set by the ADAnPFC bit, the conversion result is stored in the ADAnCRm register, and the INTAD/INTAD1 signal is generated.
Page 679 Chapter 19 A/D Converter (ADC) (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion ANI0) ANI1) ANI2) ANI3) ANI0) ANI1) ANI2) Data 1 Data 2...
Page 680 Chapter 19 A/D Converter (ADC) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 681 Chapter 19 A/D Converter (ADC) One-shot scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADAnS register are stored, and the set value of the ADAnCR0H register of channel 0 is compared with the value of the ADAnPFT register.
Page 682 Chapter 19 A/D Converter (ADC) (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion ANI0) ANI1) ANI2) ANI3) Data 1 Data 2 Data 3 Data 4 ADA0CRn ANI0) (ANI1)
Page 683: Cautions
Chapter 19 A/D Converter (ADC) 19.5 Cautions When A/D Converter is not used When the A/D Converter is not used, the power consumption can be reduced by clearing the ADAnCE bit and the ADAnPS bit of the ADAnM0 register to 0. Input range of ANInm pins Input the voltage within the specified range to the ANInm pins.
Page 684 Chapter 19 A/D Converter (ADC) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADAnS register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADAnS register is rewritten.
Page 685: How To Read A/D Converter Characteristics Table
Chapter 19 A/D Converter (ADC) 19.6 How to read A/D Converter characteristics table This section describes the terms related to the A/D Converter. For detailed specifications refer to the Datasheet Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 686 Chapter 19 A/D Converter (ADC) Overall error This is the maximum value of the difference between an actually measured value and a theoretical value. It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. The overall error in the characteristics table does not include the quantization error.
Page 687 Chapter 19 A/D Converter (ADC) Zero-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0…000 to 0…001 (1/2 LSB). Ideal line Zero-scale error −1 REFn Analog input (LSB) Figure 19-16 Zero-scale error Full-scale error...
Page 688 Chapter 19 A/D Converter (ADC) Differential linearity error Ideally, the width to output a specific code is 1 LSB. This error indicates the difference between the actually measured value and its theoretical value when a specific code is output. 1 ..1 Ideal width of 1 LSB Differential linearity error...
Page 689 Chapter 19 A/D Converter (ADC) Conversion time This is the time required to obtain a digital output after an analog input voltage has been assigned. The conversion time in the characteristics table includes the sampling time. Sampling time This is the time for which the analog switch is ON to load an analog voltage to the sample &...
Page 690: Chapter 20 Power Supply Scheme
Chapter 20 Power Supply Scheme The microcontroller has general power supply pins for its core, internal memory and peripherals. These pins are connected to internal voltage regulators. The microcontroller also has dedicated power supply pins for certain I/O modules. These pins provide the power for the I/O operations. 20.1 Overview The following table gives the naming convention of the pins: Table 20-1...
Page 691: Description
Chapter 20 Power Supply Scheme 20.2 Description Following figures give an overview of the allocation of power supply pins on the chip. Note The diagrams do not show the exact pin location. V850ES/FE3-L, V850ES/FF3-L power supply pins assignment AVREF0 A/D converter Regulator Flash memory...
Page 692: On-Chip Voltage Regulators
Chapter 20 Power Supply Scheme V850ES/FG3-L power supply pins assignment AVREF0 A/D converter BVDD I/O buffer Regulator Flash memory BVDD/VDD1 REGC Main and Sub oscillators Internal circuit EVDD EVDD I/O buffer Bidirectional level shifter Figure 20-2 V850ES/FG3-L power supply pins assignment 20.3 On-chip voltage regulators The on-chip voltage regulators generate the voltages for the internal circuitry, refer to Figure 20-1 and following.
Page 693: Chapter 21 Reset
Chapter 21 Reset Several reset functions are provided in order to initialize hardware and registers. 21.1 Overview Features summary An internal system reset SYSRES can be generated by the following sources: • External reset signal RESET • Power-On-Clear (RESPOC) • Watchdog Timer 2 (RESWDT2) •...
Page 694 Chapter 21 Reset Hardware status With each reset function the hardware is initialized. When the reset status is released, program execution is started. The following table describes the status of the clocks and on-chip modules during reset and after reset release. Table 21-1 Hardware status during and after reset Item...
Page 695 Chapter 21 Reset Register status With each reset function the registers of the CPU, internal RAM, and on-chip peripheral I/Os are initialized. After a reset, make sure to set the registers to the values needed within your program. Table 21-2 Initial values of CPU and internal RAM after reset Initial value On-chip hardware...
Page 696: Reset At Power-On
Chapter 21 Reset 21.1.2 Reset at power-on The Power-On-Clear circuit (POC) permanently compares the power supply voltage V with an internal reference voltage (V ). It ensures that the microcontroller only operates as long as the power supply exceeds a well- defined limit.
Page 697 Chapter 21 Reset Figure 21-3 on page 697 outlines the start up of the CPU system after Power- On-Clear. MainOSC Stop MainOSC start possible 8 MHz internal oscillator f Stop PLL output PLLO Stop PLL enable possible CPU system clock f VBCLK CPU system f operation...
Page 698: External Reset
Chapter 21 Reset 21.1.3 External RESET Reset is performed when a low level signal is applied to the RESET pin. The reset status is released when the signal applied to the RESET pin changes from low to high. After the external RESET is released, the RESF register is cleared and the internal system reset signal SYSRES is generated.
Page 699: Reset By Watchdog Timer 2
Chapter 21 Reset 21.1.4 Reset by Watchdog Timer 2 The Watchdog Timer can be configured to generate a reset if the watchdog time overflows. After watchdog reset, the RESF.WDT2RF bit is set. The system reset signal SYSRES is generated and the system resets. 21.1.5 Reset by Clock Monitor The Clock Monitor generates a reset when the main oscillator fails.
Page 700: Reset Registers
Chapter 21 Reset 21.2 Reset Registers The reset functions are controlled and operated by means of the following registers: Table 21-3 Reset function register overview Register name Shortcut Address Reset source flag register RESF FFFF F888 RESF - Reset source flag register The 8-bit RESF register contains information about which type of resets occurred since the last Power-On-Clear or external RESET.
Page 701: Chapter 22 Low-Voltage Detector
Chapter 22 Low-Voltage Detector This chapter describes the Low-Voltage Detector and the RAM data rentention function. 22.1 Functions The Low-Voltage Detector (LVI) has the following functions. • Compares the supply voltage (V ) with a reference voltage (V ) and generates –...
Page 702: Configuration
Chapter 22 Low-Voltage Detector 22.2 Configuration Figure 22-1 shows the block diagram of the Low-Voltage Detector. N-ch voltage Internal reset signal detection level selector − INTLVIH INTLVIL Reference voltage source (V Low voltage detection level Low voltage detection selection register (LVIS) register (LVIM) Internal bus Figure 22-1...
Page 703: Registers
Chapter 22 Low-Voltage Detector 22.3 Registers The Low-Voltage Detector is controlled by the following registers. • Low voltage detection register (LVIM) • Low voltage detection level selection register (LVIS) LVIM - Low voltage detection register This register is a special register and can be written only in a combination of specific sequences (refer to “Write Protected Registers”...
Page 704 Chapter 22 Low-Voltage Detector LVIS - Low voltage detection level selection register The LVIS register is used to select the level of low voltage to be detected. Access This register can be read/written in 8-bit or 1-bit units. Address FFFFF891 Initial Value .
Page 705 Chapter 22 Low-Voltage Detector RAMS - Internal RAM data status register The RAMS register is a flag register that indicates that the supply voltage has dropped below a specific data retention voltage. If so, the contents of the RAM may have changed and has to be considered as invalid. Access This register can be read/written in 8-bit or 1-bit units.
Page 706 Chapter 22 Low-Voltage Detector PEMU1 - Peripheral emulation register 1 When an in-circuit emulator is used, the operation of the RAM retention flag (RAMF bit: bit 0 of RAMS register) can be pseudo-controlled and emulated by manipulating this register on the debugger. This register can be read or written in 8-bit or 1-bit units.
Page 707: Operation
Chapter 22 Low-Voltage Detector 22.4 Operation Depending on the setting of the LVIMD bit, the interrupt signals (INTLVIL, INTLVIH) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 22.4.1 Reset generation from LVI (LVIM.LVIMD = 1) Operation start 1.
Page 708: Interrupt Generation From Lvi (Lvim.lvimd = 0)
Chapter 22 Low-Voltage Detector 22.4.2 Interrupt generation from LVI (LVIM.LVIMD = 0) Operation start 1. Mask the interrupts of LVI. 2. Select the voltage to be detected by using the LVIS.LVIS0 bit. 3. Set the LVIM.LVION bit to 1 (to enable operation). 4.
Page 709: Disabling The Lvi Operation
Chapter 22 Low-Voltage Detector servicing is performed at the last, even though VDD > VLVI, software detects VDD < VLVI by mistake. Therefore when LVI detection interrupt servicing is performed, program the software code as to complete interrupt servicing before the next LVI detection is generated, at the same time as controlling the VDD, or monitoring the LVIF flag.
Page 710: Ram Retention Voltage Detection Operation
Chapter 22 Low-Voltage Detector 22.4.4 RAM retention voltage detection operation The supply voltage and the data retention voltage are compared. When the supply voltage drops below the data retention voltage (including power on application), the RAMS.RAMF bit is set. For the specification of the data retention voltage, consult the Datasheet. The RAMS.RAMF flag behaves as follows: •...
Page 711: Chapter 23 On-Chip Debug Unit
Chapter 23 On-Chip Debug Unit The microcontroller includes an on-chip debug unit. By connecting an N-Wire emulator, on-chip debugging can be executed. 23.1 Functional Outline 23.1.1 Debug functions Debug interface Communication with the host machine is established by using the DRST, DCK, DMS, DDI, and DDO signals via an on-chip debug emulator.
Page 712 Chapter 23 On-Chip Debug Unit Debug monitor function A memory space for debugging that is different from the user memory space is used during debugging (background monitor mode). The user program can be executed starting from any address. While execution of the user program is aborted, the user resources (such as memory and I/O) can be read and written, and the user program can be downloaded.
Page 713 Chapter 23 On-Chip Debug Unit The on-chip debug emulator interface is still accessible during power saving modes: • The on-chip debug emulator can get status information from the on-chip debug unit. • Stop mode can be released by the on-chip debug emulator. (13) Security function This microcontroller has a N-Wire security function, that demands the user to...
Page 714: Controlling The N-Wire Interface
Chapter 23 On-Chip Debug Unit 23.2 Controlling the N-Wire Interface The N-Wire interface pins DRST, DDI, DDO, DCK, DMS are shared with port functions, see Table 23-1. During debugging the respective device pins are forced into the N-Wire interface mode and port functions are not available. Note that N-Wire debugging must be generally permitted by the security bit in the ID code region (*0x0000 0079[bit7] = 1) of the code flash memory.
Page 715 Chapter 23 On-Chip Debug Unit Power-On-Clear RESPOC RESPOC (Power-On-Clear) reset sets OCDM.OCDM0 = 0, i.e. the pins are defined as port pins. The debugger can not communicate with the controller and the N-Wire debug circuit is disabled. The first CPU instructions after RESPOC can not be controlled by the debugger.
Page 716: N-Wire Enabling Methods
Chapter 23 On-Chip Debug Unit 23.3 N-Wire Enabling Methods The current operation mode of the microcontroller is determined by OCDM.OCDM0 and DRST: Table 23-3 Normal operation and debug mode control DRST OCDM.OCDM0 Mode × normal operation on-chip debug 23.3.1 Starting normal operation after RESET and RESPOC For “normal operation”...
Page 717: N-Wire Activation By Reset Pin
Chapter 23 On-Chip Debug Unit Figure 23-2. This will cause the program to restart. However the status of the controller might not be the same as immediately after RESPOC, since the internal RAM may have already been initialized, when the external RESET is applied.
Page 718: Connection To N-Wire Emulator
Chapter 23 On-Chip Debug Unit 23.4 Connection to N-Wire Emulator To connect the N-Wire emulator, a connector for emulator connection and a connection circuit must be mounted on the target system. As a connector example the KEL connector is described in more detail. Other connectors, like for instance MICTOR connector (product name: 2-767004-2, Tyco Electronics AMP K.K.), are available as well.
Page 719 Chapter 23 On-Chip Debug Unit Pin configuration Figure 23-5 shows the pin configuration of the connector for emulator connection (target system side), and Table 23-4 on page 720 shows the pin functions. Figure 23-5 Pin configuration of connector for emulator connection (target system side) Caution Evaluate the dimensions of the connector when actually mounting the...
Page 720 Chapter 23 On-Chip Debug Unit Pin functions The following table shows the pin functions of the connector for emulator connection (target system side). “I/O” indicates the direction viewed from the device. Table 23-4 Pin functions of connector for emulator connection (target system side) Pin no.
Page 721 Chapter 23 On-Chip Debug Unit Example of recommended circuit An example of the recommended circuit of the connector for emulator connection (target system side) is shown below. V850 KEL connector 8830E-026-170S Note 3 (Reserved 1) (Reserved 2) (Reserved 3) (Reserved 4) (Reserved 5) (Reserved 6) Note 1...
Page 722: Restrictions And Cautions On On-Chip Debug Function
Chapter 23 On-Chip Debug Unit 23.5 Restrictions and Cautions on On-Chip Debug Function • Do not mount a device that was used for debugging on a mass-produced product (this is because the code flash memory was rewritten during debugging and the number of rewrites of the code flash memory cannot be guaranteed).
Page 723: Appendix A Special Function Registers
Appendix A Special Function Registers The following tables list all registers that are accessed via the NPB (peripheral bus). The registers are called “special function registers” (SFR). Table A-1 lists all CAN special function registers. The addresses are given as offsets to the programmable peripheral base address (refer to “CAN module register and message buffer addresses”...
Page 724 Appendix A Special Function Registers Table A-1 CAN special function registers (2/2) Address offset Register name Shortcut 0x064 CAN0 module transmit history list register C0TGPT 0x066 CAN0 module time stamp register C0TS 0x100 to 0x4EF CAN0 Message Buffer registers, see Table 18-20 on page 543 R01UH0469ED0201 Rev.
Page 725: Other Special Function Registers
Appendix A Special Function Registers A.2 Other Special Function Registers Table A-2 Other special function registers (1/9) Address Register name Shortcut 0xFFFFF004 PortDL 0xFFFFF004 PortDL low byte PDLL R/W R/W 0xFFFFF005 PortDL high byte PDLH R/W R/W 0xFFFFF008 PortCS R/W R/W 0xFFFFF00A PortCT R/W R/W...
Page 726 Appendix A Special Function Registers Table A-2 Other special function registers (2/9) Address Register name Shortcut 0xFFFFF10C Interrupt mask control register 6L IMR6L R/W R/W 0xFFFFF10D Interrupt mask control register 6H IMR6H R/W R/W 0xFFFFF10E Interrupt mask control register 7 IMR7 0xFFFFF10E Interrupt mask control register 7L...
Page 727 Appendix A Special Function Registers Table A-2 Other special function registers (3/9) Address Register name Shortcut 0xFFFFF164 Interrupt control register ADIC R/W R/W 0xFFFFF166 Interrupt control register C0ERRIC R/W R/W 0xFFFFF168 Interrupt control register C0WUPIC R/W R/W 0xFFFFF16A Interrupt control register C0RECIC R/W R/W 0xFFFFF16C...
Page 728 Appendix A Special Function Registers Table A-2 Other special function registers (4/9) Address Register name Shortcut 0xFFFFF21D ADC0 conversion result register 6H ADA0CR6H 0xFFFFF21E ADC0 conversion result register 7 ADA0CR7 0xFFFFF21F ADC0 conversion result register 7H ADA0CR7H 0xFFFFF220 ADC0 conversion result register 8 ADA0CR8 0xFFFFF221 ADC0 conversion result register 8H...
Page 729 Appendix A Special Function Registers Table A-2 Other special function registers (5/9) Address Register name Shortcut 0xFFFFF426 Port mode register 3L PM3L R/W R/W 0xFFFFF427 Port mode register3H PM3H R/W R/W 0xFFFFF428 Port mode register4 R/W R/W 0xFFFFF42A Port mode register5 R/W R/W 0xFFFFF42E Port mode register7L...
Page 730 Appendix A Special Function Registers Table A-2 Other special function registers (6/9) Address Register name Shortcut 0xFFFFF5A3 TAA1 I/O control register 1 TAA1IOC1 R/W R/W 0xFFFFF5A4 TAA1 I/O control register 2 TAA1IOC2 R/W R/W 0xFFFFF5A5 TAA1 option register 0 TAA1OPT0 R/W R/W 0xFFFFF5A6 TAA1 capture/compare register 0...
Page 731 Appendix A Special Function Registers Table A-2 Other special function registers (7/9) Address Register name Shortcut 0xFFFFF694 TMM0 compare register 0 TM0CMP0 0xFFFFF6C0 Oscillation stabilization time select register OSTS 0xFFFFF6C1 PLL lockup time specification register PLLS 0xFFFFF6C2 Oscillation stabilization timer status register OSTC 0xFFFFF6D0 Watchdog Timer mode register 2...
Page 732 Appendix A Special Function Registers Table A-2 Other special function registers (8/9) Address Register name Shortcut 0xFFFFFA12 UARTD1 control register 2 UD1CTL2 0xFFFFFA13 UARTD1 option control register 0 UD1OPT0 R/W R/W 0xFFFFFA14 UARTD1 status register UD1STR R/W R/W 0xFFFFFA15 UARTD1 option control register 1 UD1OPT1 0xFFFFFA16 UARTD1 receive data register...
Page 733 Appendix A Special Function Registers Table A-2 Other special function registers (9/9) Address Register name Shortcut 0xFFFFFC48 Pull-up resistor option register 4 R/W R/W 0xFFFFFC4A Pull-up resistor option register 5 R/W R/W 0xFFFFFC4C Pull-up resistor option register 6 0xFFFFFC50 Pull-up resistor option register 8 R/W R/W 0xFFFFFC52 Pull-up resistor option register 9...
Page 734: Appendix B Registers Access Times
Appendix B Registers Access Times This chapter provides formulas to calculate the access time to registers, which are accessed via the peripheral I/O areas. All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register, the system clock VBCLK and the setting of the VSWC register.
Page 735: Timer Aa
Appendix B Registers Access Times B.1 Timer AA Register TAAnCCRm Access Formula • if TAAnCTL0.TAAnCE = 0: ⋅ ----------------- - SUWL VSWL VBCLK • if TAAnCTL0.TAAnCE = 1: ⋅ ⋅ ----------------- - SUWL 2 VSWL VBCLK Access Formula • if TAAnCTL0.TAAnCE = 0: ⋅...
Page 736: Timer M
Appendix B Registers Access Times Register TAAnCNT Access Formula • if TAAnCTL0.TAAnCE = 0: ⋅ ----------------- - SUWL VSWL VBCLK • if TAAnCTL0.TAAnCE = 1: ⋅ ⋅ ----------------- - SUWL 2 VSWL VBCLK Register all other Access ⋅ ----------------- - SUWL VSWL Formula...
Page 737: Watchdog Timer 2
Appendix B Registers Access Times B.3 Watchdog Timer 2 Register WDTM2 Access Formula • if Watchdog Timer operating: ⋅ ⋅ ----------------- - SUWL 4 VSWL VBCLK • if Watchdog Timer stopped: ⋅ ----------------- - SUWL VSWL VBCLK Access ⋅ ----------------- - SUWL VSWL Formula...
Page 738: I2C Bus
Appendix B Registers Access Times B.5 I C Bus Register IICSn Access ⋅ ⋅ ----------------- - SUWL 3 VSWL Formula VBCLK Register all other Access ⋅ ----------------- - SUWL VSWL Formula VBCLK B.6 Asynchronous Serial Interface (UARTD) Register Access ⋅ ----------------- - SUWL VSWL...
Page 739: Can Controller
Appendix B Registers Access Times B.8 CAN Controller Register CnMDATA[7:0]m Access ⋅ ⎧ ⎫ ⎛ ⎞ VBCLK ÷ ⋅ ----------------- - SUWL VSWL ------------------------- - VSWL ⎨ ⎬ Formula ⎝ ⎠ ⎩ ⎭ VBCLK CANMOD Access 8-bit Write ⋅ ⎧ ⎫...
Page 740: Appendix C Differences Between Fx3-L Andfx3
Appendix C Differences between Fx3-L andFx3 The following table gives a short overview of the main differences between the devices of V850ES/Fx3-L series and the devices of Fx3 series. Table C-1 Differences of features between V850ES/Fx3L and V850ES/Fx3 Feature V850ES/Fx3-L V850ES/Fx3 max.
Page 741: Revision History
U18743EE1V2UM00 (date published June 2008). Chapter Page Description disclaimer changed for Renesas Electronics product order codes of V850ES/FF3-L devices corrected product order codes of V850ES/FG3-L devices corrected PMnm bit condition in caution corrected note added for PU05 setting...
Page 742 Chapter Page Description identifier of asynchronous clock input corrected to ASCKD0 addresses of unavailable registers removed register name corrected to CBnCTL0 flow chart of CSIB single transmission corrected: - checking of CBnTSF bit removed flow chart of CSIB continuous transmission corrected: - "CBnTSF bit = 1?"...
Page 743: Index
Index AVREF A/D conversion diagnostic registers (ADAnCRDDH) 665 AVSS A/D conversion diagnostic registers (ADAnCRSS) 666 A/D Converter 653 AVSS A/D conversion diagnostic registers Basic operation 669 (ADAnCRSSH) 666 Cautions 683 Configuration 655 Control registers 657 Baud rate generator How to read A/D Converter characteristics UARTD 410 table 685 BCU registers 291...
Page 744 register (CnGMABTD) 558 CLKOUT Function 204 CANn global clock selection register Clock Generator 148 (CnGMCS) 555 General registers 157 CANn global control register (CnGMCTRL) 553 Operation 180 CANn message configuration register m PLL related registers 167 (CnMCONFm) 583 Registers 155 CANn message control register m Start conditions 154 (CnMCTRLm) 586...
Page 745 Memory 141 External interrupt rising edge specification regis- ter (INTRm) 233 Operation modes 136 External memory area 144 Register set 127 External reset 698 Write protected registers 145 CPU operation clock status register (CCLS) 157 CSIB FEPC 130 Configuration 419 FEPSW 133 Control registers 421 Fixed peripheral I/O area 142, 286...
Page 746 Wakeup function 499 Idle pins Key Interrupt Function 249 Recommended connection 121 Cautions 250 IDLE1 mode 187 Control register 250 IDLE2 mode 189 Key return mode register (KRM) 250 IIC clock select registers (IICCLn) 463 KRIC 211, 226 IIC control registers (IICCn) 454 KRM 250 IIC division clock select registers (OCKSn) 464 IIC flag registers (IICFn) 461...
Page 747 Open drain configuration 43 Control 204 Operation modes PLL control register (PLLCTL) 168 Flash programming mode 136 PLL lock status register (LOCKR) 167 Normal operation mode 136 PLL lockup time specification register (PLLS) 169 Option Bytes 177 PLLCTL 168 Oscillation stabilization time select register (OSTS) 160 PLLS 169 Oscillation stabilization timer status register...
Page 748 PSMR 171 PSW 131 TAA capture/compare register 0 PSW saving registers 133 (TAAnCCR0) 298 PUn 42 TAA capture/compare register 1 (TAAnCCR1) 299 TAA control register 0 (TAAnCTL0) 303 RAM area 141 TAA counter read buffer register RAMS 705 (TAAnCNT) 300 RCM 166 TAA dedicated I/O control register 0 (TAAnIOC0) 307...
Page 749 TM0CTL0 361 Watchdog Timer 2 373 TM0EQIC0 211, 226 Configuration 374 Control Registers 375 Watchdog timer 2 mode register (WDTM2) 375 UARTD Watchdog timer enable register (WDTE) 377 Cautions 417 WDTE 377 Dedicated baud rate generator 410 WDTM2 375 Interrupt request signals 394 Write protected registers 145 Operation 395 WTIC 211, 226...
Page 750 R01UH0469ED0201 Rev. 2.01 User Manual...
Page 751 V850ES/Fx3-L User Manual Publication Date: Rev. 2.01 January 14, 2014 Published by: Renesas Electronics Corporation...
Page 752 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
Page 753 V850ES/Fx3-L R01UH0469ED0201, Rev. 2.01...

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