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3.4.2
Input Timing Diagram
3.5
Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown
in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
Power Supply VDD
LVDS Signal
Backlight On
Power Sequence Timing
Parameter
T1
T2
T3
T4
T5
T1
90%
10%
T2
T3
Value
Min.
Typ.
0.5
-
0
40
200
-
200
-
0
16
13
90%
T6
T5
VALID
DATA
T4
Unit
Max.
10
[ms]
50
[ms]
-
[ms]
-
[ms]
50
[ms]
IDK-2115 User Manual
10%
T7
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