BC68F2130/BC68F2140/BC68F2150
Sub-1GHz RF Transmitter Flash MCU with OCDS
• RF_FIFO_CTRL4 Register – RF FIFO Control Register 4
Bit
7
Name
DTXD
R/W
R/W
POR
0
Bit 7
DTXD: Direct mode TX data setting
Bit 6~4
Unimplemented, read as "0"
Bit 3
TXFFLT: TX FIFO length less than the threshold length specified by FFMG[1:0] (read
only)
0: TX FIFO length is greater than the threshold length specified by FFMG[1:0]
1: TX FIFO length is less than or equal to threshold length specified by FFMG[1:0]
If the FFMG_EN bit equals to 0, the TXFFLT bit always keeps at 0. If the FFMG_EN
bit equals to 1, the TXFFLT bit indicates the TX FIFO length status. When this bit is
set high by hardware, it indicates that the TX FIFO length is less than or equal to the
threshold length specified by FFMG[1:0], in which case, an FFMGF interrupt request
will be generated.
Bit 2
FFMG_EN: TX FIFO length margin detect enable
0: Disable
1: Enable
Bit 1~0
FFMG1~FFMG0: TX FIFO length margin - indicates the remained number of data
bytes in the FIFO
00: 4 bytes
01: 8 bytes
10: 16 bytes
11: 32 bytes
RF Channel Setup
The RF channel setup is implemented using four registers, the RF_SX1 ~ RF_SX4 registers.
• RF_SX1 Register – RF Fractional-N Synthesizer Control Register 1
Bit
7
Name
—
R/W
—
POR
—
Bit 7
Unimplemented, read as "0"
Bit 6~0
DN6~DN0: Integer of dividend for MMD, supports 32 to 127
Since the MMD data is generated from a delta-sigma modulator, the DN support range
will be affected. The real range will be (32+3) ~ (127-4), i.e. 35~123.
Set initial value to XO=16MHz and TX band=433.92MHz:
For example, if Crystal=XO=16MHz, XODIV2=0, and RF_OD1=04H;
VCO frequency=TX frequency×4=433.92MHz×4=1735.68MHz;
XO×(DN+DK/2
=867.84MHz;
(DN+DK/2
Rev. 1.50
6
5
4
—
—
—
—
—
—
—
—
—
6
5
4
DN6
DN5
DN4
R/W
R/W
R/W
0
1
1
)=16MHz×(DN+DK/2
)=VCO frequency/2=1735.68MHz/2
20
20
)=54.24, so DN[6:0]=36H=54, DK[19:0]=3D70AH=251658.
20
105
3
2
1
TXFFLT
FFMG_EN
FFMG1
R
R/W
R/W
0
0
0
3
2
1
DN3
DN2
DN1
R/W
R/W
R/W
0
1
1
January, 22, 2021
0
FFMG0
R/W
1
0
DN0
R/W
0
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