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4
Board Layout
This section provides a description of the EVM, board layout, and layer illustrations.
4.1
Layout
The board layout for the EVM is shown in
copper.
The top layer contains the main power traces for V
components to allow the user to easily view, probe, and evaluate the TPS43061 control IC. The remaining
area is filled with ground. The remaining three layers have additional copper for VIN, VOUT, AGND, and
PGND connected with multiple vias. Additional copper is also connected to the sense resistor to aid with
thermal dissipation. The second internal layer and bottom layer contain signal routes. Five vias directly
under the TPS43061 device provide a thermal path from the top-side ground plane to the bottom-side and
internal AGND plane. Lastly, the layout guidelines should be followed for the CSD86330Q3D which
includes 12 vias beneath the device to the internal and bottom PGND planes to aid with thermal
dissipation.
All noise-sensitive analog circuitry are placed as close as possible to the IC. The voltage divider network
ties to the output voltage at the point of regulation on the bottom layer, near the output capacitors. Q1 is
also placed as close as possible to the IC to keep the gate-drive traces as short as possible. The output
capacitors are placed next to Q1 to limit the length of the high frequency switching current path. The SW
copper is kept as small as possible to limit radiated noise from the high-frequency switching voltage node.
The power pad is connected to the AGND pin and all noise-sensitive circuitry must use this as the ground
return path. The ground return for the power components are connected to the PGND pin. The AGND and
PGND are connected at one point near the PGND pin. The bypass capacitors for VIN and VCC are placed
next to their respective pins. The filter capacitor between ISNS+ and ISNS- is located next to the pins to
help filter out switching noise. An additional input bulk capacitor may be required (C13) depending on the
connection to the EVM from the input supply. See the product datasheet for all layout recommendations.
J5
VIN =
J5
6V-12.6V
J6
J6
GND
J3
J3
PWR198 Rev. A
TPS43061EVM-198
Figure 18. TPS43061EVM-198 Top Assembly and Silkscreen
SLVU799A – November 2012 – Revised March 2013
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Figure 18
JP1
J4
JP1
J4
VBIAS
ON
EN
OFF
(OPTIONAL)
R3
C13
TP8
TP8
R7
R7
C12
C12
TP9
R12
R6
R6
TP6
R12
TP6
LOOP
R13
TP9
R13
Copyright © 2012–2013, Texas Instruments Incorporated
through
Figure
22. This design has 4 layers of 2-oz
, V
, and SW. Also on the top layer are all other
IN
OUT
TP1
TP1
PGOOD
TP5
TP5
SW
TP2
TP2
R3
HDRV
R4
R4
R1
R2
R1
R2
Q1
U1
C1
C1
U1
Q1
C6
C11
R10
C11
TP7
TP7
R15
R15
L1
R14
L1
R14
R17
R16
R17
R16
Using the TPS43061 Boost Evaluation Module (EVM)
Board Layout
J1
VOUT =
J1
15V @ 2A
TP3
VOUT
J2
TP3
J2
TP4
TP4
PGND
C16
GND
J7
J7
13
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