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5
Board Layout
This section provides a description of the EVM board layout and layer illustrations.
5.1
Layout
The board layout for the EVM is shown in
laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.
The top layer contains the main power traces for V
for the remaining pins of the TPS55330 and a large area filled with ground. The internal layers and bottom
are primarily ground with additional fill areas for V
bottom and internal ground planes with multiple vias placed around the board. Nine vias directly under the
TPS55330 device provide a thermal path from the top-side ground plane to the bottom-side ground plane.
Place the output decoupling capacitors (C8–C11) as close to the IC as possible. The copper area of the
SW node is kept small, minimizing noise. The vias near the diode, D1, on the V
dissipation. Additionally, keep the voltage setpoint resistor divider components close to the IC. The voltage
divider network ties to the output voltage at the point of regulation, the copper V
connector. For the TPS55330, an additional input bulk capacitor may be necessary, depending on the
EVM connection to the input supply. Critical analog circuits such as the voltage setpoint divider, frequency
set resistor, slow-start capacitor, and compensation components terminate to ground using a separate
ground trace on the top and bottom connected power ground, pour only at one point directly under the IC.
SLVU930 – July 2013
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Figure 15
Figure 15. TPS55330EVM-017 Top-Side Assembly
TPS55330EVM-017 2.9-V to 4.2-V Input, 5.0-V Output Boost Evaluation
Copyright © 2013, Texas Instruments Incorporated
through
Figure
19. The top-side layer of the EVM is
, V
, and SW. Also on the top layer are connections
IN
OUT
and V
. The top-side ground traces connect to the
IN
OUT
Board Layout
plane aid with thermal
OUT
trace at the J7 output
OUT
Module
11
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