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Board Layout
5 Board Layout
This section provides a description of the TPS51386EVM, board layout, and layer illustrations.
5.1 Layout
The following figures show the board layout for the TPS51386EVM. TPS51386EVM is with four layers. The top
layer contains the main power traces for VIN, VOUT, and GND. Also on the top layer are connections for the pins
of the TPS51386 and a large area filled with ground. Most of the signal traces are also located on the top side.
The input decoupling capacitors, C3, C4, C5, and C6 are located as close to VIN pins and PGND pins of the IC
as possible. The input and output connectors, test points, and all of the components are located on the top side.
The bottom layer is a ground plane along with signal ground copper fill and the feedback trace from the point of
regulation to the top of the resistor divider network. Two inner layers are ground plane.
8
TPS51386 Step-Down Converter Evaluation Module
Figure 5-1. Top Assembly
Figure 5-2. Top Layer
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SLUUCN0B – JUNE 2022 – REVISED AUGUST 2023
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